include/mpc5xxx.h

   1 /*
   2  * include/asm-ppc/mpc5xxx.h
   3  *
   4  * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
   5  * embedded cpu chips
   6  *
   7  * 2003 (c) MontaVista, Software, Inc.
   8  * Author: Dale Farnsworth <dfarnsworth@mvista.com>
   9  *
  10  * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30 #ifndef __ASMPPC_MPC5XXX_H
  31 #define __ASMPPC_MPC5XXX_H
  32
  33 /* Processor name */
  34 #if defined(CONFIG_MPC5200)
  35 #define CPU_ID_STR      "MPC5200"
  36 #elif defined(CONFIG_MGT5100)
  37 #define CPU_ID_STR      "MGT5100"
  38 #endif
  39
  40 /* Exception offsets (PowerPC standard) */
  41 #define EXC_OFF_SYS_RESET       0x0100
  42
  43 /* useful macros for manipulating CSx_START/STOP */
  44 #if defined(CONFIG_MGT5100)
  45 #define START_REG(start)        ((start) >> 15)
  46 #define STOP_REG(start, size)   (((start) + (size) - 1) >> 15)
  47 #elif defined(CONFIG_MPC5200)
  48 #define START_REG(start)        ((start) >> 16)
  49 #define STOP_REG(start, size)   (((start) + (size) - 1) >> 16)
  50 #endif
  51
  52 /* Internal memory map */
  53
  54 #define MPC5XXX_CS0_START       (CFG_MBAR + 0x0004)
  55 #define MPC5XXX_CS0_STOP        (CFG_MBAR + 0x0008)
  56 #define MPC5XXX_CS1_START       (CFG_MBAR + 0x000c)
  57 #define MPC5XXX_CS1_STOP        (CFG_MBAR + 0x0010)
  58 #define MPC5XXX_CS2_START       (CFG_MBAR + 0x0014)
  59 #define MPC5XXX_CS2_STOP        (CFG_MBAR + 0x0018)
  60 #define MPC5XXX_CS3_START       (CFG_MBAR + 0x001c)
  61 #define MPC5XXX_CS3_STOP        (CFG_MBAR + 0x0020)
  62 #define MPC5XXX_CS4_START       (CFG_MBAR + 0x0024)
  63 #define MPC5XXX_CS4_STOP        (CFG_MBAR + 0x0028)
  64 #define MPC5XXX_CS5_START       (CFG_MBAR + 0x002c)
  65 #define MPC5XXX_CS5_STOP        (CFG_MBAR + 0x0030)
  66 #define MPC5XXX_BOOTCS_START    (CFG_MBAR + 0x004c)
  67 #define MPC5XXX_BOOTCS_STOP     (CFG_MBAR + 0x0050)
  68 #define MPC5XXX_ADDECR          (CFG_MBAR + 0x0054)
  69
  70 #if defined(CONFIG_MGT5100)
  71 #define MPC5XXX_SDRAM_START     (CFG_MBAR + 0x0034)
  72 #define MPC5XXX_SDRAM_STOP      (CFG_MBAR + 0x0038)
  73 #define MPC5XXX_PCI1_START      (CFG_MBAR + 0x003c)
  74 #define MPC5XXX_PCI1_STOP       (CFG_MBAR + 0x0040)
  75 #define MPC5XXX_PCI2_START      (CFG_MBAR + 0x0044)
  76 #define MPC5XXX_PCI2_STOP       (CFG_MBAR + 0x0048)
  77 #elif defined(CONFIG_MPC5200)
  78 #define MPC5XXX_CS6_START       (CFG_MBAR + 0x0058)
  79 #define MPC5XXX_CS6_STOP        (CFG_MBAR + 0x005c)
  80 #define MPC5XXX_CS7_START       (CFG_MBAR + 0x0060)
  81 #define MPC5XXX_CS7_STOP        (CFG_MBAR + 0x0064)
  82 #define MPC5XXX_SDRAM_CS0CFG    (CFG_MBAR + 0x0034)
  83 #define MPC5XXX_SDRAM_CS1CFG    (CFG_MBAR + 0x0038)
  84 #endif
  85
  86 #define MPC5XXX_SDRAM           (CFG_MBAR + 0x0100)
  87 #define MPC5XXX_CDM             (CFG_MBAR + 0x0200)
  88 #define MPC5XXX_LPB             (CFG_MBAR + 0x0300)
  89 #define MPC5XXX_ICTL            (CFG_MBAR + 0x0500)
  90 #define MPC5XXX_GPT             (CFG_MBAR + 0x0600)
  91 #define MPC5XXX_GPIO            (CFG_MBAR + 0x0b00)
  92 #define MPC5XXX_PCI             (CFG_MBAR + 0x0d00)
  93 #define MPC5XXX_USB             (CFG_MBAR + 0x1000)
  94 #define MPC5XXX_SDMA            (CFG_MBAR + 0x1200)
  95 #define MPC5XXX_XLBARB          (CFG_MBAR + 0x1f00)
  96
  97 #if defined(CONFIG_MGT5100)
  98 #define MPC5XXX_PSC1            (CFG_MBAR + 0x2000)
  99 #define MPC5XXX_PSC2            (CFG_MBAR + 0x2400)
 100 #define MPC5XXX_PSC3            (CFG_MBAR + 0x2800)
 101 #elif defined(CONFIG_MPC5200)
 102 #define MPC5XXX_PSC1            (CFG_MBAR + 0x2000)
 103 #define MPC5XXX_PSC2            (CFG_MBAR + 0x2200)
 104 #define MPC5XXX_PSC3            (CFG_MBAR + 0x2400)
 105 #define MPC5XXX_PSC4            (CFG_MBAR + 0x2600)
 106 #define MPC5XXX_PSC5            (CFG_MBAR + 0x2800)
 107 #define MPC5XXX_PSC6            (CFG_MBAR + 0x2c00)
 108 #endif
 109
 110 #define MPC5XXX_FEC             (CFG_MBAR + 0x3000)
 111
 112 #define MPC5XXX_I2C1            (CFG_MBAR + 0x3D00)
 113 #define MPC5XXX_I2C2            (CFG_MBAR + 0x3D40)
 114
 115 #if defined(CONFIG_MGT5100)
 116 #define MPC5XXX_SRAM            (CFG_MBAR + 0x4000)
 117 #define MPC5XXX_SRAM_SIZE       (8*1024)
 118 #elif defined(CONFIG_MPC5200)
 119 #define MPC5XXX_SRAM            (CFG_MBAR + 0x8000)
 120 #define MPC5XXX_SRAM_SIZE       (16*1024)
 121 #endif
 122
 123 /* SDRAM Controller */
 124 #define MPC5XXX_SDRAM_MODE      (MPC5XXX_SDRAM + 0x0000)
 125 #define MPC5XXX_SDRAM_CTRL      (MPC5XXX_SDRAM + 0x0004)
 126 #define MPC5XXX_SDRAM_CONFIG1   (MPC5XXX_SDRAM + 0x0008)
 127 #define MPC5XXX_SDRAM_CONFIG2   (MPC5XXX_SDRAM + 0x000c)
 128 #if defined(CONFIG_MGT5100)
 129 #define MPC5XXX_SDRAM_XLBSEL    (MPC5XXX_SDRAM + 0x0010)
 130 #endif
 131
 132 /* Clock Distribution Module */
 133 #define MPC5XXX_CDM_JTAGID      (MPC5XXX_CDM + 0x0000)
 134 #define MPC5XXX_CDM_PORCFG      (MPC5XXX_CDM + 0x0004)
 135 #define MPC5XXX_CDM_CFG         (MPC5XXX_CDM + 0x000c)
 136 #define MPC5XXX_CDM_48_FDC      (MPC5XXX_CDM + 0x0010)
 137 #define MPC5XXX_CDM_SRESET      (MPC5XXX_CDM + 0x0020)
 138
 139 /* Local Plus Bus interface */
 140 #define MPC5XXX_CS0_CFG         (MPC5XXX_LPB + 0x0000)
 141 #define MPC5XXX_CS1_CFG         (MPC5XXX_LPB + 0x0004)
 142 #define MPC5XXX_CS2_CFG         (MPC5XXX_LPB + 0x0008)
 143 #define MPC5XXX_CS3_CFG         (MPC5XXX_LPB + 0x000c)
 144 #define MPC5XXX_CS4_CFG         (MPC5XXX_LPB + 0x0010)
 145 #define MPC5XXX_CS5_CFG         (MPC5XXX_LPB + 0x0014)
 146 #define MPC5XXX_BOOTCS_CFG      MPC5XXX_CS0_CFG
 147 #define MPC5XXX_CS_CTRL         (MPC5XXX_LPB + 0x0018)
 148 #define MPC5XXX_CS_STATUS       (MPC5XXX_LPB + 0x001c)
 149 #if defined(CONFIG_MPC5200)
 150 #define MPC5XXX_CS6_CFG         (MPC5XXX_LPB + 0x0020)
 151 #define MPC5XXX_CS7_CFG         (MPC5XXX_LPB + 0x0024)
 152 #define MPC5XXX_CS_BURST        (MPC5XXX_LPB + 0x0028)
 153 #define MPC5XXX_CS_DEADCYCLE    (MPC5XXX_LPB + 0x002c)
 154 #endif
 155
 156 #if defined(CONFIG_MPC5200)
 157 /* XLB Arbiter registers */
 158 #define MPC5XXX_XLBARB_CFG              (MPC5XXX_XLBARB + 0x40)
 159 #define MPC5XXX_XLBARB_MPRIEN   (MPC5XXX_XLBARB + 0x64)
 160 #define MPC5XXX_XLBARB_MPRIVAL  (MPC5XXX_XLBARB + 0x68)
 161 #endif
 162
 163 /* GPIO registers */
 164 #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
 165
 166 /* PCI registers */
 167 #define MPC5XXX_PCI_CMD         (MPC5XXX_PCI + 0x04)
 168 #define MPC5XXX_PCI_CFG         (MPC5XXX_PCI + 0x0c)
 169 #define MPC5XXX_PCI_BAR0        (MPC5XXX_PCI + 0x10)
 170 #define MPC5XXX_PCI_BAR1        (MPC5XXX_PCI + 0x14)
 171 #if defined(CONFIG_MGT5100)
 172 #define MPC5XXX_PCI_CTRL        (MPC5XXX_PCI + 0x68)
 173 #define MPC5XXX_PCI_VALMSKR     (MPC5XXX_PCI + 0x6c)
 174 #define MPC5XXX_PCI_VALMSKW     (MPC5XXX_PCI + 0x70)
 175 #define MPC5XXX_PCI_SUBW1       (MPC5XXX_PCI + 0x74)
 176 #define MPC5XXX_PCI_SUBW2       (MPC5XXX_PCI + 0x78)
 177 #define MPC5XXX_PCI_WINCOMMAND  (MPC5XXX_PCI + 0x7c)
 178 #elif defined(CONFIG_MPC5200)
 179 #define MPC5XXX_PCI_GSCR        (MPC5XXX_PCI + 0x60)
 180 #define MPC5XXX_PCI_TBATR0      (MPC5XXX_PCI + 0x64)
 181 #define MPC5XXX_PCI_TBATR1      (MPC5XXX_PCI + 0x68)
 182 #define MPC5XXX_PCI_TCR         (MPC5XXX_PCI + 0x6c)
 183 #define MPC5XXX_PCI_IW0BTAR     (MPC5XXX_PCI + 0x70)
 184 #define MPC5XXX_PCI_IW1BTAR     (MPC5XXX_PCI + 0x74)
 185 #define MPC5XXX_PCI_IW2BTAR     (MPC5XXX_PCI + 0x78)
 186 #define MPC5XXX_PCI_IWCR        (MPC5XXX_PCI + 0x80)
 187 #define MPC5XXX_PCI_ICR         (MPC5XXX_PCI + 0x84)
 188 #define MPC5XXX_PCI_ISR         (MPC5XXX_PCI + 0x88)
 189 #define MPC5XXX_PCI_ARB         (MPC5XXX_PCI + 0x8c)
 190 #define MPC5XXX_PCI_CAR         (MPC5XXX_PCI + 0xf8)
 191 #endif
 192
 193 /* Interrupt Controller registers */
 194 #define MPC5XXX_ICTL_PER_MASK   (MPC5XXX_ICTL + 0x0000)
 195 #define MPC5XXX_ICTL_PER_PRIO1  (MPC5XXX_ICTL + 0x0004)
 196 #define MPC5XXX_ICTL_PER_PRIO2  (MPC5XXX_ICTL + 0x0008)
 197 #define MPC5XXX_ICTL_PER_PRIO3  (MPC5XXX_ICTL + 0x000c)
 198 #define MPC5XXX_ICTL_EXT        (MPC5XXX_ICTL + 0x0010)
 199 #define MPC5XXX_ICTL_CRIT       (MPC5XXX_ICTL + 0x0014)
 200 #define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
 201 #define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
 202 #define MPC5XXX_ICTL_STS        (MPC5XXX_ICTL + 0x0024)
 203 #define MPC5XXX_ICTL_CRIT_STS   (MPC5XXX_ICTL + 0x0028)
 204 #define MPC5XXX_ICTL_MAIN_STS   (MPC5XXX_ICTL + 0x002c)
 205 #define MPC5XXX_ICTL_PER_STS    (MPC5XXX_ICTL + 0x0030)
 206 #define MPC5XXX_ICTL_BUS_STS    (MPC5XXX_ICTL + 0x0038)
 207
 208 /* General Purpose Timers registers */
 209 #define MPC5XXX_GPT0_ENABLE             (MPC5XXX_GPT + 0x0)
 210 #define MPC5XXX_GPT0_COUNTER            (MPC5XXX_GPT + 0x4)
 211
 212 /* I2Cn control register bits */
 213 #define I2C_EN          0x80
 214 #define I2C_IEN         0x40
 215 #define I2C_STA         0x20
 216 #define I2C_TX          0x10
 217 #define I2C_TXAK        0x08
 218 #define I2C_RSTA        0x04
 219 #define I2C_INIT_MASK   (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
 220
 221 /* I2Cn status register bits */
 222 #define I2C_CF          0x80
 223 #define I2C_AAS         0x40
 224 #define I2C_BB          0x20
 225 #define I2C_AL          0x10
 226 #define I2C_SRW         0x04
 227 #define I2C_IF          0x02
 228 #define I2C_RXAK        0x01
 229
 230 /* Programmable Serial Controller (PSC) status register bits */
 231 #define PSC_SR_CDE              0x0080
 232 #define PSC_SR_RXRDY            0x0100
 233 #define PSC_SR_RXFULL           0x0200
 234 #define PSC_SR_TXRDY            0x0400
 235 #define PSC_SR_TXEMP            0x0800
 236 #define PSC_SR_OE               0x1000
 237 #define PSC_SR_PE               0x2000
 238 #define PSC_SR_FE               0x4000
 239 #define PSC_SR_RB               0x8000
 240
 241 /* PSC Command values */
 242 #define PSC_RX_ENABLE           0x0001
 243 #define PSC_RX_DISABLE          0x0002
 244 #define PSC_TX_ENABLE           0x0004
 245 #define PSC_TX_DISABLE          0x0008
 246 #define PSC_SEL_MODE_REG_1      0x0010
 247 #define PSC_RST_RX              0x0020
 248 #define PSC_RST_TX              0x0030
 249 #define PSC_RST_ERR_STAT        0x0040
 250 #define PSC_RST_BRK_CHG_INT     0x0050
 251 #define PSC_START_BRK           0x0060
 252 #define PSC_STOP_BRK            0x0070
 253
 254 /* PSC Rx FIFO status bits */
 255 #define PSC_RX_FIFO_ERR         0x0040
 256 #define PSC_RX_FIFO_UF          0x0020
 257 #define PSC_RX_FIFO_OF          0x0010
 258 #define PSC_RX_FIFO_FR          0x0008
 259 #define PSC_RX_FIFO_FULL        0x0004
 260 #define PSC_RX_FIFO_ALARM       0x0002
 261 #define PSC_RX_FIFO_EMPTY       0x0001
 262
 263 /* PSC interrupt mask bits */
 264 #define PSC_IMR_TXRDY           0x0100
 265 #define PSC_IMR_RXRDY           0x0200
 266 #define PSC_IMR_DB              0x0400
 267 #define PSC_IMR_IPC             0x8000
 268
 269 /* PSC input port change bits */
 270 #define PSC_IPCR_CTS            0x01
 271 #define PSC_IPCR_DCD            0x02
 272
 273 /* PSC mode fields */
 274 #define PSC_MODE_5_BITS         0x00
 275 #define PSC_MODE_6_BITS         0x01
 276 #define PSC_MODE_7_BITS         0x02
 277 #define PSC_MODE_8_BITS         0x03
 278 #define PSC_MODE_PAREVEN        0x00
 279 #define PSC_MODE_PARODD         0x04
 280 #define PSC_MODE_PARFORCE       0x08
 281 #define PSC_MODE_PARNONE        0x10
 282 #define PSC_MODE_ERR            0x20
 283 #define PSC_MODE_FFULL          0x40
 284 #define PSC_MODE_RXRTS          0x80
 285
 286 #define PSC_MODE_ONE_STOP_5_BITS        0x00
 287 #define PSC_MODE_ONE_STOP               0x07
 288 #define PSC_MODE_TWO_STOP               0x0f
 289
 290 #ifndef __ASSEMBLY__
 291 struct mpc5xxx_psc {
 292         volatile u8     mode;           /* PSC + 0x00 */
 293         volatile u8     reserved0[3];
 294         union {                         /* PSC + 0x04 */
 295                 volatile u16    status;
 296                 volatile u16    clock_select;
 297         } sr_csr;
 298 #define psc_status      sr_csr.status
 299 #define psc_clock_select sr_csr.clock_select
 300         volatile u16    reserved1;
 301         volatile u8     command;        /* PSC + 0x08 */
 302         volatile u8     reserved2[3];
 303         union {                         /* PSC + 0x0c */
 304                 volatile u8     buffer_8;
 305                 volatile u16    buffer_16;
 306                 volatile u32    buffer_32;
 307         } buffer;
 308 #define psc_buffer_8    buffer.buffer_8
 309 #define psc_buffer_16   buffer.buffer_16
 310 #define psc_buffer_32   buffer.buffer_32
 311         union {                         /* PSC + 0x10 */
 312                 volatile u8     ipcr;
 313                 volatile u8     acr;
 314         } ipcr_acr;
 315 #define psc_ipcr        ipcr_acr.ipcr
 316 #define psc_acr         ipcr_acr.acr
 317         volatile u8     reserved3[3];
 318         union {                         /* PSC + 0x14 */
 319                 volatile u16    isr;
 320                 volatile u16    imr;
 321         } isr_imr;
 322 #define psc_isr         isr_imr.isr
 323 #define psc_imr         isr_imr.imr
 324         volatile u16    reserved4;
 325         volatile u8     ctur;           /* PSC + 0x18 */
 326         volatile u8     reserved5[3];
 327         volatile u8     ctlr;           /* PSC + 0x1c */
 328         volatile u8     reserved6[19];
 329         volatile u8     ivr;            /* PSC + 0x30 */
 330         volatile u8     reserved7[3];
 331         volatile u8     ip;             /* PSC + 0x34 */
 332         volatile u8     reserved8[3];
 333         volatile u8     op1;            /* PSC + 0x38 */
 334         volatile u8     reserved9[3];
 335         volatile u8     op0;            /* PSC + 0x3c */
 336         volatile u8     reserved10[3];
 337         volatile u8     sicr;           /* PSC + 0x40 */
 338         volatile u8     reserved11[3];
 339         volatile u8     ircr1;          /* PSC + 0x44 */
 340         volatile u8     reserved12[3];
 341         volatile u8     ircr2;          /* PSC + 0x44 */
 342         volatile u8     reserved13[3];
 343         volatile u8     irsdr;          /* PSC + 0x4c */
 344         volatile u8     reserved14[3];
 345         volatile u8     irmdr;          /* PSC + 0x50 */
 346         volatile u8     reserved15[3];
 347         volatile u8     irfdr;          /* PSC + 0x54 */
 348         volatile u8     reserved16[3];
 349         volatile u16    rfnum;          /* PSC + 0x58 */
 350         volatile u16    reserved17;
 351         volatile u16    tfnum;          /* PSC + 0x5c */
 352         volatile u16    reserved18;
 353         volatile u32    rfdata;         /* PSC + 0x60 */
 354         volatile u16    rfstat;         /* PSC + 0x64 */
 355         volatile u16    reserved20;
 356         volatile u8     rfcntl;         /* PSC + 0x68 */
 357         volatile u8     reserved21[5];
 358         volatile u16    rfalarm;        /* PSC + 0x6e */
 359         volatile u16    reserved22;
 360         volatile u16    rfrptr;         /* PSC + 0x72 */
 361         volatile u16    reserved23;
 362         volatile u16    rfwptr;         /* PSC + 0x76 */
 363         volatile u16    reserved24;
 364         volatile u16    rflrfptr;       /* PSC + 0x7a */
 365         volatile u16    reserved25;
 366         volatile u16    rflwfptr;       /* PSC + 0x7e */
 367         volatile u32    tfdata;         /* PSC + 0x80 */
 368         volatile u16    tfstat;         /* PSC + 0x84 */
 369         volatile u16    reserved26;
 370         volatile u8     tfcntl;         /* PSC + 0x88 */
 371         volatile u8     reserved27[5];
 372         volatile u16    tfalarm;        /* PSC + 0x8e */
 373         volatile u16    reserved28;
 374         volatile u16    tfrptr;         /* PSC + 0x92 */
 375         volatile u16    reserved29;
 376         volatile u16    tfwptr;         /* PSC + 0x96 */
 377         volatile u16    reserved30;
 378         volatile u16    tflrfptr;       /* PSC + 0x9a */
 379         volatile u16    reserved31;
 380         volatile u16    tflwfptr;       /* PSC + 0x9e */
 381 };
 382
 383 struct mpc5xxx_intr {
 384         volatile u32    per_mask;       /* INTR + 0x00 */
 385         volatile u32    per_pri1;       /* INTR + 0x04 */
 386         volatile u32    per_pri2;       /* INTR + 0x08 */
 387         volatile u32    per_pri3;       /* INTR + 0x0c */
 388         volatile u32    ctrl;           /* INTR + 0x10 */
 389         volatile u32    main_mask;      /* INTR + 0x14 */
 390         volatile u32    main_pri1;      /* INTR + 0x18 */
 391         volatile u32    main_pri2;      /* INTR + 0x1c */
 392         volatile u32    reserved1;      /* INTR + 0x20 */
 393         volatile u32    enc_status;     /* INTR + 0x24 */
 394         volatile u32    crit_status;    /* INTR + 0x28 */
 395         volatile u32    main_status;    /* INTR + 0x2c */
 396         volatile u32    per_status;     /* INTR + 0x30 */
 397         volatile u32    reserved2;      /* INTR + 0x34 */
 398         volatile u32    per_error;      /* INTR + 0x38 */
 399 };
 400
 401 struct mpc5xxx_gpio {
 402         volatile u32 port_config;       /* GPIO + 0x00 */
 403         volatile u32 simple_gpioe;      /* GPIO + 0x04 */
 404         volatile u32 simple_ode;        /* GPIO + 0x08 */
 405         volatile u32 simple_ddr;        /* GPIO + 0x0c */
 406         volatile u32 simple_dvo;        /* GPIO + 0x10 */
 407         volatile u32 simple_ival;       /* GPIO + 0x14 */
 408         volatile u8 outo_gpioe;         /* GPIO + 0x18 */
 409         volatile u8 reserved1[3];       /* GPIO + 0x19 */
 410         volatile u8 outo_dvo;           /* GPIO + 0x1c */
 411         volatile u8 reserved2[3];       /* GPIO + 0x1d */
 412         volatile u8 sint_gpioe;         /* GPIO + 0x20 */
 413         volatile u8 reserved3[3];       /* GPIO + 0x21 */
 414         volatile u8 sint_ode;           /* GPIO + 0x24 */
 415         volatile u8 reserved4[3];       /* GPIO + 0x25 */
 416         volatile u8 sint_ddr;           /* GPIO + 0x28 */
 417         volatile u8 reserved5[3];       /* GPIO + 0x29 */
 418         volatile u8 sint_dvo;           /* GPIO + 0x2c */
 419         volatile u8 reserved6[3];       /* GPIO + 0x2d */
 420         volatile u8 sint_inten;         /* GPIO + 0x30 */
 421         volatile u8 reserved7[3];       /* GPIO + 0x31 */
 422         volatile u16 sint_itype;        /* GPIO + 0x34 */
 423         volatile u16 reserved8;         /* GPIO + 0x36 */
 424         volatile u8 gpio_control;       /* GPIO + 0x38 */
 425         volatile u8 reserved9[3];       /* GPIO + 0x39 */
 426         volatile u8 sint_istat;         /* GPIO + 0x3c */
 427         volatile u8 sint_ival;          /* GPIO + 0x3d */
 428         volatile u8 bus_errs;           /* GPIO + 0x3e */
 429         volatile u8 reserved10;         /* GPIO + 0x3f */
 430 };
 431
 432 struct mpc5xxx_sdma {
 433         volatile u32 taskBar;           /* SDMA + 0x00 */
 434         volatile u32 currentPointer;    /* SDMA + 0x04 */
 435         volatile u32 endPointer;        /* SDMA + 0x08 */
 436         volatile u32 variablePointer;   /* SDMA + 0x0c */
 437
 438         volatile u8 IntVect1;           /* SDMA + 0x10 */
 439         volatile u8 IntVect2;           /* SDMA + 0x11 */
 440         volatile u16 PtdCntrl;          /* SDMA + 0x12 */
 441
 442         volatile u32 IntPend;           /* SDMA + 0x14 */
 443         volatile u32 IntMask;           /* SDMA + 0x18 */
 444
 445         volatile u16 tcr_0;             /* SDMA + 0x1c */
 446         volatile u16 tcr_1;             /* SDMA + 0x1e */
 447         volatile u16 tcr_2;             /* SDMA + 0x20 */
 448         volatile u16 tcr_3;             /* SDMA + 0x22 */
 449         volatile u16 tcr_4;             /* SDMA + 0x24 */
 450         volatile u16 tcr_5;             /* SDMA + 0x26 */
 451         volatile u16 tcr_6;             /* SDMA + 0x28 */
 452         volatile u16 tcr_7;             /* SDMA + 0x2a */
 453         volatile u16 tcr_8;             /* SDMA + 0x2c */
 454         volatile u16 tcr_9;             /* SDMA + 0x2e */
 455         volatile u16 tcr_a;             /* SDMA + 0x30 */
 456         volatile u16 tcr_b;             /* SDMA + 0x32 */
 457         volatile u16 tcr_c;             /* SDMA + 0x34 */
 458         volatile u16 tcr_d;             /* SDMA + 0x36 */
 459         volatile u16 tcr_e;             /* SDMA + 0x38 */
 460         volatile u16 tcr_f;             /* SDMA + 0x3a */
 461
 462         volatile u8 IPR0;               /* SDMA + 0x3c */
 463         volatile u8 IPR1;               /* SDMA + 0x3d */
 464         volatile u8 IPR2;               /* SDMA + 0x3e */
 465         volatile u8 IPR3;               /* SDMA + 0x3f */
 466         volatile u8 IPR4;               /* SDMA + 0x40 */
 467         volatile u8 IPR5;               /* SDMA + 0x41 */
 468         volatile u8 IPR6;               /* SDMA + 0x42 */
 469         volatile u8 IPR7;               /* SDMA + 0x43 */
 470         volatile u8 IPR8;               /* SDMA + 0x44 */
 471         volatile u8 IPR9;               /* SDMA + 0x45 */
 472         volatile u8 IPR10;              /* SDMA + 0x46 */
 473         volatile u8 IPR11;              /* SDMA + 0x47 */
 474         volatile u8 IPR12;              /* SDMA + 0x48 */
 475         volatile u8 IPR13;              /* SDMA + 0x49 */
 476         volatile u8 IPR14;              /* SDMA + 0x4a */
 477         volatile u8 IPR15;              /* SDMA + 0x4b */
 478         volatile u8 IPR16;              /* SDMA + 0x4c */
 479         volatile u8 IPR17;              /* SDMA + 0x4d */
 480         volatile u8 IPR18;              /* SDMA + 0x4e */
 481         volatile u8 IPR19;              /* SDMA + 0x4f */
 482         volatile u8 IPR20;              /* SDMA + 0x50 */
 483         volatile u8 IPR21;              /* SDMA + 0x51 */
 484         volatile u8 IPR22;              /* SDMA + 0x52 */
 485         volatile u8 IPR23;              /* SDMA + 0x53 */
 486         volatile u8 IPR24;              /* SDMA + 0x54 */
 487         volatile u8 IPR25;              /* SDMA + 0x55 */
 488         volatile u8 IPR26;              /* SDMA + 0x56 */
 489         volatile u8 IPR27;              /* SDMA + 0x57 */
 490         volatile u8 IPR28;              /* SDMA + 0x58 */
 491         volatile u8 IPR29;              /* SDMA + 0x59 */
 492         volatile u8 IPR30;              /* SDMA + 0x5a */
 493         volatile u8 IPR31;              /* SDMA + 0x5b */
 494
 495         volatile u32 res1;              /* SDMA + 0x5c */
 496         volatile u32 res2;              /* SDMA + 0x60 */
 497         volatile u32 res3;              /* SDMA + 0x64 */
 498         volatile u32 MDEDebug;          /* SDMA + 0x68 */
 499         volatile u32 ADSDebug;          /* SDMA + 0x6c */
 500         volatile u32 Value1;            /* SDMA + 0x70 */
 501         volatile u32 Value2;            /* SDMA + 0x74 */
 502         volatile u32 Control;           /* SDMA + 0x78 */
 503         volatile u32 Status;            /* SDMA + 0x7c */
 504         volatile u32 EU00;              /* SDMA + 0x80 */
 505         volatile u32 EU01;              /* SDMA + 0x84 */
 506         volatile u32 EU02;              /* SDMA + 0x88 */
 507         volatile u32 EU03;              /* SDMA + 0x8c */
 508         volatile u32 EU04;              /* SDMA + 0x90 */
 509         volatile u32 EU05;              /* SDMA + 0x94 */
 510         volatile u32 EU06;              /* SDMA + 0x98 */
 511         volatile u32 EU07;              /* SDMA + 0x9c */
 512         volatile u32 EU10;              /* SDMA + 0xa0 */
 513         volatile u32 EU11;              /* SDMA + 0xa4 */
 514         volatile u32 EU12;              /* SDMA + 0xa8 */
 515         volatile u32 EU13;              /* SDMA + 0xac */
 516         volatile u32 EU14;              /* SDMA + 0xb0 */
 517         volatile u32 EU15;              /* SDMA + 0xb4 */
 518         volatile u32 EU16;              /* SDMA + 0xb8 */
 519         volatile u32 EU17;              /* SDMA + 0xbc */
 520         volatile u32 EU20;              /* SDMA + 0xc0 */
 521         volatile u32 EU21;              /* SDMA + 0xc4 */
 522         volatile u32 EU22;              /* SDMA + 0xc8 */
 523         volatile u32 EU23;              /* SDMA + 0xcc */
 524         volatile u32 EU24;              /* SDMA + 0xd0 */
 525         volatile u32 EU25;              /* SDMA + 0xd4 */
 526         volatile u32 EU26;              /* SDMA + 0xd8 */
 527         volatile u32 EU27;              /* SDMA + 0xdc */
 528         volatile u32 EU30;              /* SDMA + 0xe0 */
 529         volatile u32 EU31;              /* SDMA + 0xe4 */
 530         volatile u32 EU32;              /* SDMA + 0xe8 */
 531         volatile u32 EU33;              /* SDMA + 0xec */
 532         volatile u32 EU34;              /* SDMA + 0xf0 */
 533         volatile u32 EU35;              /* SDMA + 0xf4 */
 534         volatile u32 EU36;              /* SDMA + 0xf8 */
 535         volatile u32 EU37;              /* SDMA + 0xfc */
 536 };
 537
 538 struct mpc5xxx_i2c {
 539         volatile u32 madr;              /* I2Cn + 0x00 */
 540         volatile u32 mfdr;              /* I2Cn + 0x04 */
 541         volatile u32 mcr;               /* I2Cn + 0x08 */
 542         volatile u32 msr;               /* I2Cn + 0x0C */
 543         volatile u32 mdr;               /* I2Cn + 0x10 */
 544 };
 545
 546 /* function prototypes */
 547 void loadtask(int basetask, int tasks);
 548
 549 #endif /* __ASSEMBLY__ */
 550
 551 #endif /* __ASMPPC_MPC5XXX_H */