include/mpc824x.h

   1 /*
   2  * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000.
   3  * Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __MPC824X_H__
  25 #define __MPC824X_H__
  26
  27 #include <config.h>
  28
  29 /* CPU Types */
  30 #define CPU_TYPE_601            0x01            /* PPC 601       CPU */
  31 #define CPU_TYPE_602            0x02            /* PPC 602       CPU */
  32 #define CPU_TYPE_603            0x03            /* PPC 603       CPU */
  33 #define CPU_TYPE_603E           0x06            /* PPC 603e      CPU */
  34 #define CPU_TYPE_603P           0x07            /* PPC 603p      CPU */
  35 #define CPU_TYPE_604            0x04            /* PPC 604       CPU */
  36 #define CPU_TYPE_604E           0x09            /* PPC 604e      CPU */
  37 #define CPU_TYPE_604R           0x0a            /* PPC 604r      CPU */
  38 #define CPU_TYPE_750            0x08            /* PPC 750       CPU */
  39 #define CPU_TYPE_8240           0x81            /* PPC 8240      CPU */
  40 #define CPU_TYPE_8245           0x8081          /* PPC 8245/8241 CPU */
  41 #define _CACHE_ALIGN_SIZE       32              /* cache line size */
  42
  43 /* spr976 - DMISS data tlb miss address register
  44  * spr977 - DCMP data tlb miss compare register
  45  * spr978 - HASH1 PTEG1 address register
  46  * spr980 - HASH2 PTEG2 address register
  47  * IMISS  - instruction tlb miss address register
  48  * ICMP   - instruction TLB mis compare register
  49  * RPA    - real page address register
  50  * HID0   - hardware implemntation register
  51  * HID2   - instruction address breakpoint register
  52  */
  53
  54 /* Kahlua/MPC8240 defines */
  55 #define VEN_DEV_ID              0x00021057      /* Vendor and Dev. ID for MPC106 */
  56 #define KAHLUA_ID               0x00031057      /* Vendor & Dev Id for Kahlua's PCI */
  57 #define KAHLUA2_ID              0x00061057      /* 8245 is aka Kahlua-2 */
  58 #define BMC_BASE                0x80000000      /* Kahlua ID in PCI Memory space */
  59 #define CHRP_REG_ADDR           0xfec00000      /* MPC107 Config, Map B */
  60 #define CHRP_REG_DATA           0xfee00000      /* MPC107 Config, Map B */
  61 #define CHRP_ISA_MEM_PHYS       0xfd000000
  62 #define CHRP_ISA_MEM_BUS        0x00000000
  63 #define CHRP_ISA_MEM_SIZE       0x01000000
  64 #define CHRP_ISA_IO_PHYS        0xfe000000
  65 #define CHRP_ISA_IO_BUS         0x00000000
  66 #define CHRP_ISA_IO_SIZE        0x00800000
  67 #define CHRP_PCI_IO_PHYS        0xfe800000
  68 #define CHRP_PCI_IO_BUS         0x00800000
  69 #define CHRP_PCI_IO_SIZE        0x00400000
  70 #define CHRP_PCI_MEM_PHYS       0x80000000
  71 #define CHRP_PCI_MEM_BUS        0x80000000
  72 #define CHRP_PCI_MEM_SIZE       0x7d000000
  73 #define CHRP_PCI_MEMORY_PHYS    0x00000000
  74 #define CHRP_PCI_MEMORY_BUS     0x00000000
  75 #define CHRP_PCI_MEMORY_SIZE    0x40000000
  76 #define PREP_REG_ADDR           0x80000cf8      /* MPC107 Config, Map A */
  77 #define PREP_REG_DATA           0x80000cfc      /* MPC107 Config, Map A */
  78 #define PREP_ISA_IO_PHYS        0x80000000
  79 #define PREP_ISA_IO_BUS         0x00000000
  80 #define PREP_ISA_IO_SIZE        0x00800000
  81 #define PREP_PCI_IO_PHYS        0x81000000
  82 #define PREP_PCI_IO_BUS         0x01000000
  83 #define PREP_PCI_IO_SIZE        0x3e800000
  84 #define PREP_PCI_MEM_PHYS       0xc0000000
  85 #define PREP_PCI_MEM_BUS        0x00000000
  86 #define PREP_PCI_MEM_SIZE       0x3f000000
  87 #define PREP_PCI_MEMORY_PHYS    0x00000000
  88 #define PREP_PCI_MEMORY_BUS     0x80000000
  89 #define PREP_PCI_MEMORY_SIZE    0x80000000
  90 #define MPC107_PCI_CMD          0x80000004      /* MPC107 PCI cmd reg */
  91 #define MPC107_PCI_STAT         0x80000006      /* MPC107 PCI status reg */
  92 #define PROC_INT1_ADR           0x800000a8      /* MPC107 Processor i/f cfg1 */
  93 #define PROC_INT2_ADR           0x800000ac      /* MPC107 Processor i/f cfg2 */
  94 #define MEM_CONT1_ADR           0x800000f0      /* MPC107 Memory control config. 1 */
  95 #define MEM_CONT2_ADR           0x800000f4      /* MPC107 Memory control config. 2 */
  96 #define MEM_CONT3_ADR           0x800000f8      /* MPC107 Memory control config. 3 */
  97 #define MEM_CONT4_ADR           0x800000fc      /* MPC107 Memory control config. 4 */
  98 #define MEM_ERREN1_ADR          0x800000c0      /* MPC107 Memory error enable 1 */
  99 #define MEM_START1_ADR          0x80000080      /* MPC107 Memory starting addr */
 100 #define MEM_START2_ADR          0x80000084      /* MPC107 Memory starting addr-lo */
 101 #define XMEM_START1_ADR         0x80000088      /* MPC107 Extended mem. start addr-hi*/
 102 #define XMEM_START2_ADR         0x8000008c      /* MPC107 Extended mem. start addr-lo*/
 103 #define MEM_END1_ADR            0x80000090      /* MPC107 Memory ending address */
 104 #define MEM_END2_ADR            0x80000094      /* MPC107 Memory ending addr-lo */
 105 #define XMEM_END1_ADR           0x80000098      /* MPC107 Extended mem. end addrs-hi */
 106 #define XMEM_END2_ADR           0x8000009c      /* MPC107 Extended mem. end addrs-lo*/
 107 #define OUT_DRV_CONT            0x80000073      /* MPC107 Output Driver Control reg */
 108 #define MEM_EN_ADR              0x800000a0      /* Memory bank enable */
 109 #define PAGE_MODE               0x800000a3      /* MPC107 Page Mode Counter/Timer */
 110
 111 /*-----------------------------------------------------------------------
 112  * Exception offsets (PowerPC standard)
 113  */
 114 #define EXC_OFF_RESERVED0       0x0000  /* Reserved */
 115 #define EXC_OFF_SYS_RESET       0x0100  /* System reset */
 116 #define EXC_OFF_MACH_CHCK       0x0200  /* Machine Check */
 117 #define EXC_OFF_DATA_STOR       0x0300  /* Data Storage */
 118 #define EXC_OFF_INS_STOR        0x0400  /* Instruction Storage */
 119 #define EXC_OFF_EXTERNAL        0x0500  /* External */
 120 #define EXC_OFF_ALIGN           0x0600  /* Alignment */
 121 #define EXC_OFF_PROGRAM         0x0700  /* Program */
 122 #define EXC_OFF_FPUNAVAIL       0x0800  /* Floating-point Unavailable */
 123 #define EXC_OFF_DECR            0x0900  /* Decrementer */
 124 #define EXC_OFF_RESERVED1       0x0A00  /* Reserved */
 125 #define EXC_OFF_RESERVED2       0x0B00  /* Reserved */
 126 #define EXC_OFF_SYS_CALL        0x0C00  /* System Call */
 127 #define EXC_OFF_TRACE           0x0D00  /* Trace */
 128 #define EXC_OFF_FPUNASSIST      0x0E00  /* Floating-point Assist */
 129
 130         /* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */
 131         /* these found in DINK code  - may not apply to 8240*/
 132 #define EXC_OFF_PMI             0x0F00  /* Performance Monitoring Interrupt */
 133 #define EXC_OFF_VMXUI           0x0F20  /* VMX (AltiVec) Unavailable Interrupt */
 134
 135         /* 0x1000 - 0x2FFF are implementation specific */
 136         /* these found in DINK code  - may not apply to 8240 */
 137 #define EXC_OFF_ITME            0x1000  /* Instruction Translation Miss Exception */
 138 #define EXC_OFF_DLTME           0x1100  /* Data Load Translation Miss Exception */
 139 #define EXC_OFF_DSTME           0x1200  /* Data Store Translation Miss Exception */
 140 #define EXC_OFF_IABE            0x1300  /* Instruction Addr Breakpoint Exception */
 141 #define EXC_OFF_SMIE            0x1400  /* System Management Interrupt Exception */
 142 #define EXC_OFF_JMDDI           0x1600  /* Java Mode denorm detect Interr -- WTF??*/
 143 #define EXC_OFF_RMTE            0x2000  /* Run Mode or Trace Exception */
 144
 145 #define MAP_A_CONFIG_ADDR_HIGH  0x8000  /* Upper half of CONFIG_ADDR for Map A */
 146 #define MAP_A_CONFIG_ADDR_LOW   0x0CF8  /* Lower half of CONFIG_ADDR for Map A */
 147 #define MAP_A_CONFIG_DATA_HIGH  0x8000  /* Upper half of CONFIG_DAT for Map A */
 148 #define MAP_A_CONFIG_DATA_LOW   0x0CFC  /* Lower half of CONFIG_DAT for Map A */
 149 #define MAP_B_CONFIG_ADDR_HIGH  0xfec0  /* Upper half of CONFIG_ADDR for Map B */
 150 #define MAP_B_CONFIG_ADDR_LOW   0x0000  /* Lower half of CONFIG_ADDR for Map B */
 151 #define MAP_B_CONFIG_DATA_HIGH  0xfee0  /* Upper half of CONFIG_DAT for Map B */
 152 #define MAP_B_CONFIG_DATA_LOW   0x0000  /* Lower half of CONFIG_DAT for Map B */
 153
 154
 155 #if defined(CFG_ADDR_MAP_A)
 156 #define CONFIG_ADDR_HIGH    MAP_A_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
 157 #define CONFIG_ADDR_LOW     MAP_A_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
 158 #define CONFIG_DATA_HIGH    MAP_A_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
 159 #define CONFIG_DATA_LOW     MAP_A_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
 160 #else /* Assume Map B, default */
 161 #define CONFIG_ADDR_HIGH    MAP_B_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
 162 #define CONFIG_ADDR_LOW     MAP_B_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
 163 #define CONFIG_DATA_HIGH    MAP_B_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
 164 #define CONFIG_DATA_LOW     MAP_B_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
 165 #endif
 166
 167 #define CONFIG_ADDR     (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
 168
 169 #define CONFIG_DATA     (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW)
 170
 171 /* Macros to write to config registers. addr should be a constant in all cases */
 172
 173 #define CONFIG_WRITE_BYTE( addr, data ) \
 174   __asm__ __volatile__( \
 175   " stwbrx %1, 0, %0\n \
 176     sync\n \
 177     stb %3, %4(%2)\n \
 178     sync " \
 179   : /* no output */ \
 180   : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
 181     "b" (CONFIG_DATA), "r" (data), \
 182     "n" ((addr) & 3));
 183
 184 #define CONFIG_WRITE_HALFWORD( addr, data ) \
 185   __asm__ __volatile__( \
 186   " stwbrx %1, 0, %0\n \
 187     sync\n \
 188     sthbrx %3, %4, %2\n \
 189     sync " \
 190   : /* no output */ \
 191   : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
 192     "r" (CONFIG_DATA), "r" (data), \
 193     "b" ((addr) & 3));
 194
 195 /* this assumes it's writeing on word boundaries*/
 196 #define CONFIG_WRITE_WORD( addr, data ) \
 197   __asm__ __volatile__( \
 198   " stwbrx %1, 0, %0\n \
 199     sync\n \
 200     stwbrx %3, 0, %2\n \
 201     sync " \
 202   : /* no output */ \
 203   : "r" (CONFIG_ADDR), "r" (addr), \
 204     "r" (CONFIG_DATA), "r" (data));
 205
 206 /* Configuration register reads*/
 207
 208 #define CONFIG_READ_BYTE( addr, reg ) \
 209   __asm__ ( \
 210   " stwbrx %1, 0, %2\n \
 211     sync\n \
 212     lbz   %0, %4(%3)\n \
 213     sync " \
 214   : "=r" (reg) \
 215   : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
 216     "b" (CONFIG_DATA), "n" ((addr) & 3));
 217
 218
 219 #define CONFIG_READ_HALFWORD( addr, reg ) \
 220   __asm__ ( \
 221   " stwbrx %1, 0, %2\n \
 222     sync\n \
 223     lhbrx %0, %4, %3\n \
 224     sync " \
 225   : "=r" (reg) \
 226   : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
 227     "r" (CONFIG_DATA), \
 228     "b" ((addr) & 3));
 229
 230 /* this assumes it's reading on word boundaries*/
 231 #define CONFIG_READ_WORD( addr, reg ) \
 232   __asm__ ( \
 233   " stwbrx %1, 0, %2\n \
 234     sync\n \
 235     lwbrx %0, 0, %3\n \
 236     sync " \
 237   : "=r" (reg) \
 238   : "r" (addr), "r" (CONFIG_ADDR),\
 239     "r" (CONFIG_DATA));
 240
 241 /*
 242  *  configuration register 'addresses'.
 243  *  These are described in chaper 5 of the 8240 users manual.
 244  *  Where the register has an abreviation in the manual, this has
 245  *  been usaed here, otherwise a name in keeping with the norm has
 246  *  been invented.
 247  *  Note that some of these registers aren't documented in the manual.
 248  */
 249
 250 #define PCICR           0x80000004  /* PCI Command Register */
 251 #define PCISR           0x80000006  /* PCI Status Register */
 252 #define REVID           0x80000008  /* CPU revision id */
 253 #define PIR             0x80000009  /* PCI Programming Interface Register */
 254 #define PBCCR           0x8000000b  /* PCI Base Class Code Register */
 255 #define PCLSR           0x8000000c  /* Processor Cache Line Size Register */
 256 #define PLTR            0x8000000d  /* PCI Latancy Timer Register */
 257 #define PHTR            0x8000000e  /* PCI Header Type Register */
 258 #define BISTCTRL        0x8000000f  /* BIST Control */
 259 #define LMBAR           0x80000010  /* Local Base Addres Register */
 260 #define PCSRBAR         0x80000014  /* PCSR Base Address Register */
 261 #define ILR             0x8000003c  /* PCI Interrupt Line Register */
 262 #define IPR             0x8000003d  /* Interrupt Pin Register */
 263 #define MINGNT          0x8000003e  /* MIN GNI */
 264 #define MAXLAT          0x8000003f  /* MAX LAT */
 265 #define PCIACR          0x80000046  /* PCI Arbiter Control Register */
 266 #define PMCR1           0x80000070  /* Power management config. 1 */
 267 #define PMCR2           0x80000072  /* Power management config. 2 */
 268 #define ODCR            0x80000073  /* Output Driver Control Register */
 269 #define CLKDCR          0x80000074  /* CLK Driver Control Register */
 270 #if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
 271 #define MIOCR1          0x80000076  /* Miscellaneous I/O Control Register 1 */
 272 #define MIOCR2          0x80000077  /* Miscellaneous I/O Control Register 2 */
 273 #endif
 274 #define EUMBBAR         0x80000078  /* Embedded Utilities Memory Block Base Address Register */
 275 #define EUMBBAR_VAL     0x80500000  /* PCI Relocation offset for EUMB region */
 276 #define EUMBSIZE        0x00100000  /* Size of EUMB region */
 277
 278 #define MSAR1           0x80000080  /* Memory Starting Address Register 1 */
 279 #define MSAR2           0x80000084  /* Memory Starting Address Register 2 */
 280 #define EMSAR1          0x80000088  /* Extended Memory Starting Address Register 1*/
 281 #define EMSAR2          0x8000008c  /* Extended Memory Starting Address Register 2*/
 282 #define MEAR1           0x80000090  /* Memory Ending Address Register 1 */
 283 #define MEAR2           0x80000094  /* Memory Ending Address Register 2 */
 284 #define EMEAR1          0x80000098  /* Extended Memory Ending Address Register 1 */
 285 #define EMEAR2          0x8000009c  /* Extended Memory Ending Address Register 2 */
 286 #define MBER            0x800000a0  /* Memory bank Enable Register*/
 287 #define MPMR            0x800000a3  /* Memory Page Mode Register (stores PGMAX) */
 288 #define PICR1           0x800000a8  /* Processor Interface Configuration Register 1 */
 289 #define PICR2           0x800000ac  /* Processor Interface Configuration Register 2 */
 290 #define ECCSBECR        0x800000b8  /* ECC Single-Bit Error Counter Register */
 291 #define ECCSBETR        0x800000b8  /* ECC Single-Bit Error Trigger Register */
 292 #define ERRENR1         0x800000c0  /* Error Enableing Register 1 */
 293 #define ERRENR2         0x800000c4  /* Error Enableing Register 2 */
 294 #define ERRDR1          0x800000c1  /* Error Detection Register 1 */
 295 #define IPBESR          0x800000c3  /* Internal Processor Error Status Register */
 296 #define ERRDR2          0x800000c5  /* Error Detection Register 2 */
 297 #define PBESR           0x800000c7  /* PCI Bus Error Status Register */
 298 #define PBEAR           0x800000c8  /* Processor/PCI Bus Error Status Register */
 299 #define AMBOR           0x800000e0  /* Address Map B Options Register */
 300 #define PCMBCR          0x800000e1  /* PCI/Memory Buffer Configuration */
 301 #define MCCR1           0x800000f0  /* Memory Control Configuration Register 1 */
 302 #define MCCR2           0x800000f4  /* Memory Control Configuration Register 2 */
 303 #define MCCR3           0x800000f8  /* Memory Control Configuration Register 3 */
 304 #define MCCR4           0x800000fc  /* Memory Control Configuration Register 4 */
 305
 306 /* some values for some of the above */
 307
 308 #define PICR1_CF_APARK          0x00000008
 309 #define PICR1_LE_MODE           0x00000020
 310 #define PICR1_ST_GATH_EN        0x00000040
 311 #if defined(CONFIG_MPC8240)
 312 #define PICR1_EN_PCS            0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
 313 #elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
 314 #define PICR1_NO_BUSW_CK        0x00000080 /* no bus width check for flash writes */
 315 #define PICR1_DEC               0x00000100 /* Time Base enable on 8245/8241 */
 316 #define ERCR1                   0x800000d0  /* Extended ROM Configuration Register 1 */
 317 #define ERCR2                   0x800000d4  /* Extended ROM Configuration Register 2 */
 318 #define ERCR3                   0x800000d8  /* Extended ROM Configuration Register 3 */
 319 #define ERCR4                   0x800000dc  /* Extended ROM Configuration Register 4 */
 320 #define MIOCR1                  0x80000076  /* Miscellaneous I/O Control Register 1 */
 321 #define MIOCR1_ADR_X            0x80000074  /* Miscellaneous I/O Control Register 1 */
 322 #define MIOCR1_SHIFT            2
 323 #define MIOCR2                  0x80000077  /* Miscellaneous I/O Control Register 2 */
 324 #define MIOCR2_ADR_X            0x80000074  /* Miscellaneous I/O Control Register 1 */
 325 #define MIOCR2_SHIFT            3
 326 #define ODCR_ADR_X              0x80000070      /* Output Driver Control register */
 327 #define ODCR_SHIFT              3
 328 #define PMCR2_ADR               0x80000072      /* Power Mgmnt Cfg 2 register */
 329 #define PMCR2_ADR_X             0x80000070
 330 #define PMCR2_SHIFT             3
 331 #define PMCR1_ADR               0x80000070      /* Power Mgmnt Cfg 1 reister */
 332 #else
 333 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 334 #endif
 335 #define PICR1_CF_DPARK          0x00000200
 336 #define PICR1_MCP_EN            0x00000800
 337 #define PICR1_FLASH_WR_EN       0x00001000
 338 #ifdef CONFIG_MPC8240
 339 #define PICR1_ADDRESS_MAP       0x00010000
 340 #define PIRC1_MSK               0xff000000
 341 #endif
 342 #define PICR1_PROC_TYPE_MSK     0x00060000
 343 #define PICR1_PROC_TYPE_603E    0x00040000
 344 #define PICR1_RCS0              0x00100000
 345
 346 #define PICR2_CF_SNOOP_WS_MASK  0x000c0000
 347 #define PICR2_CF_SNOOP_WS_0WS   0x00000000
 348 #define PICR2_CF_SNOOP_WS_1WS   0x00040000
 349 #define PICR2_CF_SNOOP_WS_2WS   0x00080000
 350 #define PICR2_CF_SNOOP_WS_3WS   0x000c0000
 351 #define PICR2_CF_APHASE_WS_MASK 0x0000000c
 352 #define PICR2_CF_APHASE_WS_0WS  0x00000000
 353 #define PICR2_CF_APHASE_WS_1WS  0x00000004
 354 #define PICR2_CF_APHASE_WS_2WS  0x00000008
 355 #define PICR2_CF_APHASE_WS_3WS  0x0000000c
 356
 357 #define MCCR1_ROMNAL_SHIFT      28
 358 #define MCCR1_ROMNAL_MSK        0xf0000000
 359 #define MCCR1_ROMFAL_SHIFT      23
 360 #define MCCR1_ROMFAL_MSK        0x0f800000
 361 #define MCCR1_DBUS_SIZE0        0x00400000
 362 #define MCCR1_BURST             0x00100000
 363 #define MCCR1_MEMGO             0x00080000
 364 #define MCCR1_SREN              0x00040000
 365 #if defined(CONFIG_MPC8240)
 366 #define MCCR1_RAM_TYPE          0x00020000
 367 #elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
 368 #define MCCR1_SDRAM_EN          0x00020000
 369 #else
 370 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 371 #endif
 372 #define MCCR1_PCKEN             0x00010000
 373 #define MCCR1_BANK1ROW_SHIFT    2
 374 #define MCCR1_BANK2ROW_SHIFT    4
 375 #define MCCR1_BANK3ROW_SHIFT    6
 376 #define MCCR1_BANK4ROW_SHIFT    8
 377 #define MCCR1_BANK5ROW_SHIFT    10
 378 #define MCCR1_BANK6ROW_SHIFT    12
 379 #define MCCR1_BANK7ROW_SHIFT    14
 380
 381 #define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
 382 #define MCCR2_TS_WAIT_TIMER_SHIFT 29
 383 #define MCCR2_ASRISE_MSK        0x1e000000
 384 #define MCCR2_ASRISE_SHIFT      25
 385 #define MCCR2_ASFALL_MSK        0x01e00000
 386 #define MCCR2_ASFALL_SHIFT      21
 387
 388 #define MCCR2_INLINE_PAR_NOT_ECC    0x00100000
 389 #define MCCR2_WRITE_PARITY_CHK  0x00080000
 390 #define MCCR2_INLFRD_PARECC_CHK_EN  0x00040000
 391 #ifdef CONFIG_MPC8240
 392 #define MCCR2_ECC_EN            0x00020000
 393 #define MCCR2_EDO               0x00010000
 394 #endif
 395 #define MCCR2_REFINT_MSK        0x0000fffc
 396 #define MCCR2_REFINT_SHIFT      2
 397 #define MCCR2_RSV_PG            0x00000002
 398 #define MCCR2_PMW_PAR           0x00000001
 399
 400 #define MCCR3_BSTOPRE2TO5_MSK   0xf0000000 /*BSTOPRE[2-5]*/
 401 #define MCCR3_BSTOPRE2TO5_SHIFT 28
 402 #define MCCR3_REFREC_MSK        0x0f000000
 403 #define MCCR3_REFREC_SHIFT      24
 404 #ifdef CONFIG_MPC8240
 405 #define MCCR3_RDLAT_MSK         0x00f00000
 406 #define MCCR3_RDLAT_SHIFT       20
 407 #define MCCR3_CPX               0x00010000
 408 #define MCCR3_RAS6P_MSK         0x00078000
 409 #define MCCR3_RAS6P_SHIFT       15
 410 #define MCCR3_CAS5_MSK          0x00007000
 411 #define MCCR3_CAS5_SHIFT        12
 412 #define MCCR3_CP4_MSK           0x00000e00
 413 #define MCCR3_CP4_SHIFT         9
 414 #define MCCR3_CAS3_MSK          0x000001c0
 415 #define MCCR3_CAS3_SHIFT        6
 416 #define MCCR3_RCD2_MSK          0x00000038
 417 #define MCCR3_RCD2_SHIFT        3
 418 #define MCCR3_RP1_MSK           0x00000007
 419 #define MCCR3_RP1_SHIFT         0
 420 #endif
 421
 422 #define MCCR4_PRETOACT_MSK      0xf0000000
 423 #define MCCR4_PRETOACT_SHIFT    28
 424 #define MCCR4_ACTTOPRE_MSK      0x0f000000
 425 #define MCCR4_ACTTOPRE_SHIFT    24
 426 #define MCCR4_WMODE             0x00800000
 427 #define MCCR4_INLINE            0x00400000
 428 #if defined(CONFIG_MPC8240)
 429 #define MCCR4_BIT21             0x00200000 /* this include cos DINK code sets it- unknown function*/
 430 #elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
 431 #define MCCR4_EXTROM            0x00200000 /* enables Extended ROM space */
 432 #else
 433 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 434 #endif
 435 #define MCCR4_REGISTERED        0x00100000
 436 #define MCCR4_BSTOPRE0TO1_MSK   0x000c0000 /*BSTOPRE[0-1]*/
 437 #define MCCR4_BSTOPRE0TO1_SHIFT 18
 438 #define MCCR4_REGDIMM           0x00008000
 439 #define MCCR4_SDMODE_MSK        0x00007f00
 440 #define MCCR4_SDMODE_SHIFT      8
 441 #define MCCR4_ACTTORW_MSK       0x000000f0
 442 #define MCCR4_ACTTORW_SHIFT     4
 443 #define MCCR4_BSTOPRE6TO9_MSK   0x0000000f /*BSTOPRE[6-9]*/
 444 #define MCCR4_BSTOPRE6TO9_SHIFT 0
 445 #define MCCR4_DBUS_SIZE2_SHIFT  17
 446
 447 #define MICR_ADDR_MASK          0x0ff00000
 448 #define MICR_ADDR_SHIFT         20
 449 #define MICR_EADDR_MASK         0x30000000
 450 #define MICR_EADDR_SHIFT        28
 451
 452 #define BATU_BEPI_MSK           0xfffe0000
 453 #define BATU_BL_MSK             0x00001ffc
 454
 455 #define BATU_BL_128K            0x00000000
 456 #define BATU_BL_256K            0x00000004
 457 #define BATU_BL_512K            0x0000000c
 458 #define BATU_BL_1M              0x0000001c
 459 #define BATU_BL_2M              0x0000003c
 460 #define BATU_BL_4M              0x0000007c
 461 #define BATU_BL_8M              0x000000fc
 462 #define BATU_BL_16M             0x000001fc
 463 #define BATU_BL_32M             0x000003fc
 464 #define BATU_BL_64M             0x000007fc
 465 #define BATU_BL_128M            0x00000ffc
 466 #define BATU_BL_256M            0x00001ffc
 467
 468 #define BATU_VS                 0x00000002
 469 #define BATU_VP                 0x00000001
 470
 471 #define BATL_BRPN_MSK           0xfffe0000
 472 #define BATL_WIMG_MSK           0x00000078
 473
 474 #define BATL_WRITETHROUGH       0x00000040
 475 #define BATL_CACHEINHIBIT       0x00000020
 476 #define BATL_MEMCOHERENCE       0x00000010
 477 #define BATL_GUARDEDSTORAGE     0x00000008
 478
 479 #define BATL_PP_MSK             0x00000003
 480 #define BATL_PP_00              0x00000000 /* No access */
 481 #define BATL_PP_01              0x00000001 /* Read-only */
 482 #define BATL_PP_10              0x00000002 /* Read-write */
 483 #define BATL_PP_11              0x00000003
 484
 485 /*
 486  * I'd attempt to do defines for the PP bits, but it's use is a bit
 487  * too complex, see the PowerPC Operating Environment Architecture
 488  * section in the PowerPc arch book, chapter 4.
 489  */
 490
 491 /*eumb and epic config*/
 492
 493 #define EPIC_FPR                0x00041000
 494 #define EPIC_GCR                0x00041020
 495 #define EPIC_EICR               0x00041030
 496 #define EPIC_EVI                0x00041080
 497 #define EPIC_PI                 0x00041090
 498 #define EPIC_SVR                0x000410E0
 499 #define EPIC_TFRR               0x000410F0
 500
 501 /*
 502  * Note the information for these is rather mangled in the 8240 manual.
 503  * These are guesses.
 504  */
 505
 506 #define EPIC_GTCCR0             0x00041100
 507 #define EPIC_GTCCR1             0x00041140
 508 #define EPIC_GTCCR2             0x00041180
 509 #define EPIC_GTCCR3             0x000411C0
 510 #define EPIC_GTBCR0             0x00041110
 511 #define EPIC_GTBCR1             0x00041150
 512 #define EPIC_GTBCR2             0x00041190
 513 #define EPIC_GTBCR3             0x000411D0
 514 #define EPIC_GTVPR0             0x00041120
 515 #define EPIC_GTVPR1             0x00041160
 516 #define EPIC_GTVPR2             0x000411a0
 517 #define EPIC_GTVPR3             0x000411e0
 518 #define EPIC_GTDR0              0x00041130
 519 #define EPIC_GTDR1              0x00041170
 520 #define EPIC_GTDR2              0x000411b0
 521 #define EPIC_GTDR3              0x000411f0
 522
 523 #define EPIC_IVPR0              0x00050200
 524 #define EPIC_IVPR1              0x00050220
 525 #define EPIC_IVPR2              0x00050240
 526 #define EPIC_IVPR3              0x00050260
 527 #define EPIC_IVPR4              0x00050280
 528
 529 #define EPIC_SVPR0              0x00050200
 530 #define EPIC_SVPR1              0x00050220
 531 #define EPIC_SVPR2              0x00050240
 532 #define EPIC_SVPR3              0x00050260
 533 #define EPIC_SVPR4              0x00050280
 534 #define EPIC_SVPR5              0x000502A0
 535 #define EPIC_SVPR6              0x000502C0
 536 #define EPIC_SVPR7              0x000502E0
 537 #define EPIC_SVPR8              0x00050300
 538 #define EPIC_SVPR9              0x00050320
 539 #define EPIC_SVPRa              0x00050340
 540 #define EPIC_SVPRb              0x00050360
 541 #define EPIC_SVPRc              0x00050380
 542 #define EPIC_SVPRd              0x000503A0
 543 #define EPIC_SVPRe              0x000503C0
 544 #define EPIC_SVPRf              0x000503E0
 545
 546 /* MPC8240 Byte Swap/PCI Support Macros */
 547 #define BYTE_SWAP_16_BIT(x)    ( (((x) & 0x00ff) << 8) | ( (x) >> 8) )
 548 #define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
 549                      (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
 550 #define PCISWAP(x)   LONGSWAP(x)
 551
 552 #ifndef __ASSEMBLY__
 553
 554 /*
 555  * MPC107 Support
 556  *
 557  */
 558 unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
 559 void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
 560 void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
 561 void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
 562 void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
 563 unsigned char mpc824x_mpc107_read8(unsigned int address);
 564 unsigned short mpc824x_mpc107_read16(unsigned int address);
 565 unsigned int mpc824x_mpc107_read32(unsigned int address);
 566 unsigned int mpc824x_eummbar_read(unsigned int regNum);
 567 void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);
 568
 569 #ifdef CONFIG_PCI
 570 struct pci_controller;
 571 void pci_cpm824x_init(struct pci_controller* hose);
 572 #endif
 573
 574 #endif /* __ASSEMBLY__ */
 575
 576 #endif /* __MPC824X_H__ */