include/mpc85xx.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * Copyright(c) 2003 Motorola Inc.
   4  * Xianghua Xiao (x.xiao@motorola.com)
   5  */
   6
   7 #ifndef __MPC85xx_H__
   8 #define __MPC85xx_H__
   9
  10 #define EXC_OFF_SYS_RESET       0x0100  /* System reset */
  11
  12 #if defined(CONFIG_E500)
  13 #include <e500.h>
  14 #endif
  15
  16 /*
  17  * SCCR - System Clock Control Register, 9-8
  18  */
  19 #define SCCR_CLPD       0x00000004      /* CPM Low Power Disable */
  20 #define SCCR_DFBRG_MSK  0x00000003      /* Division by BRGCLK Mask */
  21 #define SCCR_DFBRG_SHIFT 0
  22
  23 #define SCCR_DFBRG00    0x00000000      /* BRGCLK division by 4 */
  24 #define SCCR_DFBRG01    0x00000001      /* BRGCLK div by 16 (normal) */
  25 #define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
  26 #define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
  27
  28 /*
  29  * Local Bus Controller - memory controller registers
  30  */
  31 #define BRx_V           0x00000001      /* Bank Valid                   */
  32 #define BRx_MS_GPCM     0x00000000      /* G.P.C.M. Machine Select      */
  33 #define BRx_MS_SDRAM    0x00000000      /* SDRAM Machine Select         */
  34 #define BRx_MS_UPMA     0x00000080      /* U.P.M.A Machine Select       */
  35 #define BRx_MS_UPMB     0x000000a0      /* U.P.M.B Machine Select       */
  36 #define BRx_MS_UPMC     0x000000c0      /* U.P.M.C Machine Select       */
  37 #define BRx_PS_8        0x00000800      /*  8 bit port size             */
  38 #define BRx_PS_32       0x00001800      /* 32 bit port size             */
  39 #define BRx_BA_MSK      0xffff8000      /* Base Address Mask            */
  40
  41 #define ORxG_EAD        0x00000001      /* External addr latch delay    */
  42 #define ORxG_EHTR       0x00000002      /* Extended hold time on read   */
  43 #define ORxG_TRLX       0x00000004      /* Timing relaxed               */
  44 #define ORxG_SETA       0x00000008      /* External address termination */
  45 #define ORxG_SCY_10_CLK 0x000000a0      /* 10 clock cycles wait states  */
  46 #define ORxG_SCY_15_CLK 0x000000f0      /* 15 clock cycles wait states  */
  47 #define ORxG_XACS       0x00000100      /* Extra addr to CS setup       */
  48 #define ORxG_ACS_DIV2   0x00000600      /* CS is output 1/2 a clock later*/
  49 #define ORxG_CSNT       0x00000800      /* Chip Select Negation Time    */
  50
  51 #define ORxU_BI         0x00000100      /* Burst Inhibit                */
  52 #define ORxU_AM_MSK     0xffff8000      /* Address Mask Mask            */
  53
  54 #define MxMR_OP_NORM    0x00000000      /* Normal Operation             */
  55 #define MxMR_DSx_2_CYCL 0x00400000      /* 2 cycle Disable Period       */
  56 #define MxMR_OP_WARR    0x10000000      /* Write to Array               */
  57 #define MxMR_BSEL       0x80000000      /* Bus Select                   */
  58
  59 /* helpers to convert values into an OR address mask (GPCM mode) */
  60 #define P2SZ_TO_AM(s)   ((~((s) - 1)) & 0xffff8000)     /* must be pow of 2 */
  61 #define MEG_TO_AM(m)    P2SZ_TO_AM((m) << 20)
  62
  63 #endif  /* __MPC85xx_H__ */