include/nios2-yanu.h

   1 /*
   2  * (C) Copyright 2006, Imagos S.a.s <www.imagos.it>
   3  * Renato Andreola <renato.andreola@imagos.it>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*************************************************************************
   9  * Altera NiosII YANU serial interface by Imagos
  10  * please see  http://www.opencores.org/project,yanu for
  11  * information/downloads
  12  ************************************************************************/
  13
  14 #ifndef __NIOS2_YANU_H__
  15 #define __NIOS2_YANU_H__
  16
  17 #define YANU_MAX_PRESCALER_N   ((1 << 4) - 1)   /* 15 */
  18 #define YANU_MAX_PRESCALER_M   ((1 << 11) -1)   /* 2047 */
  19 #define YANU_FIFO_SIZE         (16)
  20 #define YANU_RXFIFO_SIZE       (YANU_FIFO_SIZE)
  21 #define YANU_TXFIFO_SIZE       (YANU_FIFO_SIZE)
  22
  23 #define YANU_RXFIFO_DLY        (10*11)
  24 #define YANU_TXFIFO_THR        (10)
  25 #define YANU_DATA_CHAR_MASK    (0xFF)
  26
  27 /* data register */
  28 #define YANU_DATA_OFFSET       (0)      /* data register offset */
  29
  30 #define YANU_CONTROL_OFFSET    (4)      /* control register offset */
  31 /* interrupt enable */
  32 #define YANU_CONTROL_IE_RRDY   (1<<0)   /* ie on received character ready */
  33 #define YANU_CONTROL_IE_OE     (1<<1)   /* ie on rx overrun    */
  34 #define YANU_CONTROL_IE_BRK    (1<<2)   /* ie on break detect  */
  35 #define YANU_CONTROL_IE_FE     (1<<3)   /* ie on framing error */
  36 #define YANU_CONTROL_IE_PE     (1<<4)   /* ie on parity error  */
  37 #define YANU_CONTROL_IE_TRDY   (1<<5)   /* ie interrupt on tranmitter ready */
  38 /* control bits */
  39 #define YANU_CONTROL_BITS_POS  (6)      /* bits number pos */
  40 #define YANU_CONTROL_BITS      (1<<YANU_CONTROL_BITS_POS)       /* number of rx/tx bits per word. 3 bit unsigned integer */
  41 #define YANU_CONTROL_BITS_N    (3)      /* ... its bit filed length */
  42 #define YANU_CONTROL_PARENA    (1<<9)   /*  enable parity bit transmission/reception */
  43 #define YANU_CONTROL_PAREVEN   (1<<10)  /* parity even */
  44 #define YANU_CONTROL_STOPS     (1<<11)  /* number of stop bits */
  45 #define YANU_CONTROL_HHENA     (1<<12)  /* Harware Handshake enable... */
  46 #define YANU_CONTROL_FORCEBRK  (1<<13)  /* if set than txd = active (0) */
  47 /* tuning part */
  48 #define YANU_CONTROL_RDYDLY    (1<<14)  /* delay from "first" before setting rrdy (in bit) */
  49 #define YANU_CONTROL_RDYDLY_N  (8)      /* ... its bit filed length */
  50 #define YANU_CONTROL_TXTHR     (1<<22)  /* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */
  51 #define YANU_CONTROL_TXTHR_N   (4)      /* ... its bit field length */
  52
  53 #define YANU_BAUD_OFFSET  (8)   /* baud register offset */
  54 #define YANU_BAUDM        (1<<0)        /* baud mantissa lsb */
  55 #define YANU_BAUDM_N      (12)  /* ...its bit filed length */
  56 #define YANU_BAUDE        (1<<12)       /* baud exponent lsb */
  57 #define YANU_BAUDE_N      (4)   /* ...its bit field length */
  58
  59 #define YANU_ACTION_OFFSET   (12)       /* action register... write only */
  60 #define YANU_ACTION_RRRDY    (1<<0)     /* reset rrdy */
  61 #define YANU_ACTION_ROE      (1<<1)     /* reset oe */
  62 #define YANU_ACTION_RBRK     (1<<2)     /* reset brk */
  63 #define YANU_ACTION_RFE      (1<<3)     /* reset fe  */
  64 #define YANU_ACTION_RPE      (1<<4)     /* reset pe  */
  65 #define YANU_ACTION_SRRDY    (1<<5)     /* set rrdy  */
  66 #define YANU_ACTION_SOE      (1<<6)     /* set oe    */
  67 #define YANU_ACTION_SBRK     (1<<7)     /* set brk   */
  68 #define YANU_ACTION_SFE      (1<<8)     /* set fe    */
  69 #define YANU_ACTION_SPE      (1<<9)     /* set pe    */
  70 #define YANU_ACTION_RFIFO_PULL  (1<<10) /* pull a char from rx fifo we MUST do it before taking a char */
  71 #define YANU_ACTION_RFIFO_CLEAR (1<<11) /* clear rx fifo */
  72 #define YANU_ACTION_TFIFO_CLEAR (1<<12) /* clear tx fifo */
  73 #define YANU_ACTION_RTRDY       (1<<13) /* clear trdy    */
  74 #define YANU_ACTION_STRDY       (1<<14) /* set trdy      */
  75
  76 #define YANU_STATUS_OFFSET   (16)
  77 #define YANU_STATUS_RRDY     (1<<0)     /* rxrdy flag */
  78 #define YANU_STATUS_TRDY     (1<<1)     /* txrdy flag */
  79 #define YANU_STATUS_OE       (1<<2)     /* rx overrun error */
  80 #define YANU_STATUS_BRK      (1<<3)     /* rx break detect flag */
  81 #define YANU_STATUS_FE       (1<<4)     /* rx framing error flag */
  82 #define YANU_STATUS_PE       (1<<5)     /* rx parity erro flag */
  83 #define YANU_RFIFO_CHARS_POS (6)
  84 #define YANU_RFIFO_CHARS     (1<<RFIFO_CHAR_POS)        /* number of chars into rx fifo */
  85 #define YANU_RFIFO_CHARS_N   (5)        /* ...its bit field length: 32 chars */
  86 #define YANU_TFIFO_CHARS_POS (11)
  87 #define YANU_TFIFO_CHARS     (1<<TFIFO_CHAR_POS)        /* number of chars into tx fifo */
  88 #define YANU_TFIFO_CHARS_N   (5)        /* ...its bit field length: 32 chars */
  89
  90 typedef volatile struct yanu_uart_t {
  91         volatile unsigned data;
  92         volatile unsigned control;      /* control register (RW) 32-bit   */
  93         volatile unsigned baud; /* baud/prescaler register (RW) 32-bit */
  94         volatile unsigned action;       /* action register (W) 32-bit */
  95         volatile unsigned status;       /* status register (R) 32-bit */
  96         volatile unsigned magic;        /* magic register (R) 32-bit */
  97 } yanu_uart_t;
  98
  99 #endif