include/ns87308.h

   1 /*
   2  * (C) Copyright 2000
   3  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _NS87308_H_
   9 #define _NS87308_H_
  10
  11 #include <asm/pci_io.h>
  12
  13 /* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
  14    functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
  15
  16 void initialise_ns87308(void);
  17
  18 /*
  19  * The following struct represents the GPIO registers on the NS87308/NS97307
  20  */
  21 struct GPIO
  22 {
  23   unsigned char dta1;  /* 0 data port 1 */
  24   unsigned char dir1;  /* 1 direction port 1 */
  25   unsigned char out1;  /* 2 output type port 1 */
  26   unsigned char puc1;  /* 3 pull-up control port 1 */
  27   unsigned char dta2;  /* 4 data port 2 */
  28   unsigned char dir2;  /* 5 direction port 2 */
  29   unsigned char out2;  /* 6 output type port 2 */
  30   unsigned char puc2;  /* 7 pull-up control port 2  */
  31 };
  32
  33 /*
  34  * The following represents the power management registers on the NS87308/NS97307
  35  */
  36 #define PWM_FER1 0  /* 0 function enable reg. 1 */
  37 #define PWM_FER2 1  /* 1 function enable reg. 2 */
  38 #define PWM_PMC1 2  /* 2 power mgmt. control 1 */
  39 #define PWM_PMC2 3  /* 3 power mgmt. control 2 */
  40 #define PWM_PMC3 4  /* 4 power mgmt. control 3 */
  41 #define PWM_WDTO 5  /* 5 watchdog time-out */
  42 #define PWM_WDCF 6  /* 6 watchdog config. */
  43 #define PWM_WDST 7  /* 7 watchdog status  */
  44
  45 /*PNP config registers:
  46  * these depend on the stated of BADDR1 and BADDR0 on startup
  47  * so there's three versions here with the last two digits indicating
  48  * for which configuration their valid
  49  * the 1st of the two digits indicates the state of BADDR1
  50  * the 2st of the two digits indicates the state of BADDR0
  51  */
  52
  53
  54 #define IO_INDEX_OFFSET_0x 0x0279  /* full PnP isa Mode */
  55 #define IO_INDEX_OFFSET_10 0x015C  /* PnP motherboard mode */
  56 #define IO_INDEX_OFFSET_11 0x002E  /* PnP motherboard mode */
  57 #define IO_DATA_OFFSET_0x  0x0A79  /* full PnP isa Mode */
  58 #define IO_DATA_OFFSET_10  0x015D  /* PnP motherboard mode */
  59 #define IO_DATA_OFFSET_11  0x002F  /* PnP motherboard mode */
  60
  61 #if defined(CONFIG_SYS_NS87308_BADDR_0x)
  62 #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
  63 #define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
  64 #elif defined(CONFIG_SYS_NS87308_BADDR_10)
  65 #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
  66 #define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
  67 #elif defined(CONFIG_SYS_NS87308_BADDR_11)
  68 #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
  69 #define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
  70 #endif
  71
  72 /* PnP register definitions */
  73
  74 #define SET_RD_DATA_PORT    0x00
  75 #define SERIAL_ISOLATION    0x01
  76 #define CONFIG_CONTROL      0x02
  77 #define WAKE_CSN            0x03
  78 #define RES_DATA            0x04
  79 #define STATUS              0x05
  80 #define SET_CSN             0x06
  81 #define LOGICAL_DEVICE      0x07
  82
  83 /*vendor defined values */
  84 #define SID_REG             0x20
  85 #define SUPOERIO_CONF1      0x21
  86 #define SUPOERIO_CONF2      0x22
  87 #define PGCS_INDEX          0x23
  88 #define PGCS_DATA           0x24
  89
  90 /* values above 30 are different for each logical device
  91    but I can't be arsed to enter them all. the ones here
  92    are pretty consistent between all logical devices
  93    feel free to correct the situation if you want.. ;)
  94    */
  95 #define ACTIVATE            0x30
  96 #define ACTIVATE_OFF        0x00
  97 #define ACTIVATE_ON         0x01
  98
  99 #define BASE_ADDR_HIGH      0x60
 100 #define BASE_ADDR_LOW       0x61
 101 #define LUN_CONFIG_REG          0xF0
 102 #define DBASE_HIGH                      0x60    /* SIO KBC data base address, 15:8 */
 103 #define DBASE_LOW                       0x61    /* SIO KBC data base address,  7:0 */
 104 #define CBASE_HIGH                      0x62    /* SIO KBC command base addr, 15:8 */
 105 #define CBASE_LOW                       0x63    /* SIO KBC command base addr,  7:0 */
 106
 107 /* the logical devices*/
 108 #define LDEV_KBC1           0x00        /* 2 devices for keyboard and mouse controller*/
 109 #define LDEV_KBC2           0x01
 110 #define LDEV_MOUSE          0x01
 111 #define LDEV_RTC_APC        0x02        /*Real Time Clock and Advanced Power Control*/
 112 #define LDEV_FDC            0x03        /*floppy disk controller*/
 113 #define LDEV_PARP           0x04        /*Parallel port*/
 114 #define LDEV_UART2          0x05
 115 #define LDEV_UART1          0x06
 116 #define LDEV_GPIO           0x07    /*General Purpose IO and chip select output signals*/
 117 #define LDEV_POWRMAN        0x08    /*Power Managment*/
 118
 119 #define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1)
 120 #define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2)
 121 #define CONFIG_SYS_NS87308_MOUSE        (1 << LDEV_MOUSE)
 122 #define CONFIG_SYS_NS87308_RTC_APC      (1 << LDEV_RTC_APC)
 123 #define CONFIG_SYS_NS87308_FDC          (1 << LDEV_FDC)
 124 #define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP)
 125 #define CONFIG_SYS_NS87308_UART2        (1 << LDEV_UART2)
 126 #define CONFIG_SYS_NS87308_UART1        (1 << LDEV_UART1)
 127 #define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO)
 128 #define CONFIG_SYS_NS87308_POWRMAN      (1 << LDEV_POWRMAN)
 129
 130 /*some functions and macro's for doing configuration */
 131
 132 static inline void read_pnp_config(unsigned char index, unsigned char *data)
 133 {
 134     pci_writeb(index,IO_INDEX);
 135     pci_readb(IO_DATA, *data);
 136 }
 137
 138 static inline void write_pnp_config(unsigned char index, unsigned char data)
 139 {
 140     pci_writeb(index,IO_INDEX);
 141     pci_writeb(data, IO_DATA);
 142 }
 143
 144 static inline void pnp_set_device(unsigned char dev)
 145 {
 146     write_pnp_config(LOGICAL_DEVICE, dev);
 147 }
 148
 149 static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
 150 {
 151     pci_writeb(index, CONFIG_SYS_ISA_IO + base);
 152     eieio();
 153     pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
 154 }
 155
 156 /*void write_pnp_config(unsigned char index, unsigned char data);
 157 void pnp_set_device(unsigned char dev);
 158 */
 159
 160 #define PNP_SET_DEVICE_BASE(dev,base) \
 161    pnp_set_device(dev); \
 162    write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
 163    write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
 164    write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
 165    write_pnp_config(ACTIVATE, ACTIVATE_ON);
 166
 167 #define PNP_ACTIVATE_DEVICE(dev) \
 168    pnp_set_device(dev); \
 169    write_pnp_config(ACTIVATE, ACTIVATE_ON);
 170
 171 #define PNP_DEACTIVATE_DEVICE(dev) \
 172    pnp_set_device(dev); \
 173    write_pnp_config(ACTIVATE, ACTIVATE_OFF);
 174
 175
 176 static inline void write_pgcs_config(unsigned char index, unsigned char data)
 177 {
 178     write_pnp_config(PGCS_INDEX, index);
 179     write_pnp_config(PGCS_DATA, data);
 180 }
 181
 182 /* these macrose configure the 3 CS lines
 183    on the sandpoint board these controll NVRAM
 184    CS0 is connected to NVRAMCS
 185    CS1 is connected to NVRAMAS0
 186    CS2 is connected to NVRAMAS1
 187    */
 188 #define PGCS_CS_ASSERT_ON_WRITE 0x10
 189 #define PGCS_CS_ASSERT_ON_READ  0x20
 190
 191 #define PNP_PGCS_CSLINE_BASE(cs, base) \
 192   write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
 193   write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
 194
 195 #define PNP_PGCS_CSLINE_CONF(cs, conf) \
 196   write_pgcs_config(((cs) << 2) + 2, (conf) );
 197
 198
 199 /* The following sections are for 87308 extensions to the standard compoents it emulates */
 200
 201 /* extensions to 16550*/
 202
 203 #define MCR_MDSL_MSK    0xe0 /*mode select mask*/
 204 #define MCR_MDSL_UART   0x00 /*uart, default*/
 205 #define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
 206 #define MCR_MDSL_SIR    0x03 /*SIR*/
 207 #define MCR_MDSL_CIR    0x06 /*Consumer IR*/
 208
 209 #define FCR_TXFTH0      0x10    /* these bits control threshod of data level in fifo */
 210 #define FCR_TXFTH1      0x20    /* for interrupt trigger */
 211
 212 /*
 213  * Default NS87308 configuration
 214  */
 215 #ifndef CONFIG_SYS_NS87308_KBC1_BASE
 216 #define CONFIG_SYS_NS87308_KBC1_BASE    0x0060
 217 #endif
 218 #ifndef CONFIG_SYS_NS87308_RTC_BASE
 219 #define CONFIG_SYS_NS87308_RTC_BASE     0x0070
 220 #endif
 221 #ifndef CONFIG_SYS_NS87308_FDC_BASE
 222 #define CONFIG_SYS_NS87308_FDC_BASE     0x03F0
 223 #endif
 224 #ifndef CONFIG_SYS_NS87308_LPT_BASE
 225 #define CONFIG_SYS_NS87308_LPT_BASE     0x0278
 226 #endif
 227 #ifndef CONFIG_SYS_NS87308_UART1_BASE
 228 #define CONFIG_SYS_NS87308_UART1_BASE   0x03F8
 229 #endif
 230 #ifndef CONFIG_SYS_NS87308_UART2_BASE
 231 #define CONFIG_SYS_NS87308_UART2_BASE   0x02F8
 232 #endif
 233
 234 #endif /*_NS87308_H_*/