include/pcmcia.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _PCMCIA_H
   9 #define _PCMCIA_H
  10
  11 #include <common.h>
  12 #include <config.h>
  13
  14 /*
  15  * Allow configuration to select PCMCIA slot,
  16  * or try to generate a useful default
  17  */
  18 #if defined(CONFIG_CMD_PCMCIA) || \
  19     (defined(CONFIG_CMD_IDE) && \
  20         (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
  21
  22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  23
  24                                         /* The RPX series use SLOT_B    */
  25 #if defined(CONFIG_RPXLITE)
  26 # define CONFIG_PCMCIA_SLOT_B
  27 #elif defined(CONFIG_FADS)              /* The FADS series are a mess   */
  28 # if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821)
  29 #  define CONFIG_PCMCIA_SLOT_A
  30 # else
  31 #  define CONFIG_PCMCIA_SLOT_B
  32 # endif
  33 #elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
  34 # define        CONFIG_PCMCIA_SLOT_B    /* The TQM8xxL use SLOT_B       */
  35 #elif defined(CONFIG_SPD823TS)          /* The SPD8xx  use SLOT_B       */
  36 # define CONFIG_PCMCIA_SLOT_B
  37 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)   /* The IVM* use SLOT_A  */
  38 # define CONFIG_PCMCIA_SLOT_A
  39 #elif defined(CONFIG_LWMON)             /* The LWMON  use SLOT_B        */
  40 # define CONFIG_PCMCIA_SLOT_B
  41 #elif defined(CONFIG_ICU862)            /* The ICU862 use SLOT_B        */
  42 # define CONFIG_PCMCIA_SLOT_B
  43 #elif defined(CONFIG_R360MPI)           /* The R360MPI use SLOT_B       */
  44 # define CONFIG_PCMCIA_SLOT_B
  45 #elif defined(CONFIG_ATC)               /* The ATC use SLOT_A   */
  46 # define CONFIG_PCMCIA_SLOT_A
  47 #elif defined(CONFIG_NETTA)
  48 # define CONFIG_PCMCIA_SLOT_A
  49 #elif defined(CONFIG_UC100)             /* The UC100 use SLOT_B         */
  50 # define CONFIG_PCMCIA_SLOT_B
  51 #else
  52 # error "PCMCIA Slot not configured"
  53 #endif
  54
  55 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
  56
  57 /* Make sure exactly one slot is defined - we support only one for now */
  58 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  59 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
  60 #endif
  61 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
  62 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
  63 #endif
  64
  65 #ifndef PCMCIA_SOCKETS_NO
  66 #define PCMCIA_SOCKETS_NO       1
  67 #endif
  68 #ifndef PCMCIA_MEM_WIN_NO
  69 #define PCMCIA_MEM_WIN_NO       4
  70 #endif
  71 #define PCMCIA_IO_WIN_NO        2
  72
  73 /* define _slot_ to be able to optimize macros */
  74 #ifdef CONFIG_PCMCIA_SLOT_A
  75 # define _slot_                 0
  76 # define PCMCIA_SLOT_MSG        "slot A"
  77 # define PCMCIA_SLOT_x          PCMCIA_PSLOT_A
  78 #else
  79 # define _slot_                 1
  80 # define PCMCIA_SLOT_MSG        "slot B"
  81 # define PCMCIA_SLOT_x          PCMCIA_PSLOT_B
  82 #endif
  83
  84 /*
  85  * The TQM850L hardware has two pins swapped! Grrrrgh!
  86  */
  87 #ifdef  CONFIG_TQM850L
  88 #define __MY_PCMCIA_GCRX_CXRESET        PCMCIA_GCRX_CXOE
  89 #define __MY_PCMCIA_GCRX_CXOE           PCMCIA_GCRX_CXRESET
  90 #else
  91 #define __MY_PCMCIA_GCRX_CXRESET        PCMCIA_GCRX_CXRESET
  92 #define __MY_PCMCIA_GCRX_CXOE           PCMCIA_GCRX_CXOE
  93 #endif
  94
  95 /*
  96  * This structure is used to address each window in the PCMCIA controller.
  97  *
  98  * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
  99  * after pcmcia_win_t[n]...
 100  */
 101
 102 typedef struct {
 103         ulong   br;
 104         ulong   or;
 105 } pcmcia_win_t;
 106
 107 /*
 108  * Definitions for PCMCIA control registers to operate in IDE mode
 109  *
 110  * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
 111  * to be done later (depending on CPU clock)
 112  */
 113
 114 /* Window 0:
 115  *      Base: 0xFE100000        CS1
 116  *      Port Size:     2 Bytes
 117  *      Port Size:    16 Bit
 118  *      Common Memory Space
 119  */
 120
 121 #define CONFIG_SYS_PCMCIA_PBR0          0xFE100000
 122 #define CONFIG_SYS_PCMCIA_POR0      (   PCMCIA_BSIZE_2  \
 123                             |   PCMCIA_PPS_16   \
 124                             |   PCMCIA_PRS_MEM  \
 125                             |   PCMCIA_SLOT_x   \
 126                             |   PCMCIA_PV       \
 127                             )
 128
 129 /* Window 1:
 130  *      Base: 0xFE100080        CS1
 131  *      Port Size:     8 Bytes
 132  *      Port Size:     8 Bit
 133  *      Common Memory Space
 134  */
 135
 136 #define CONFIG_SYS_PCMCIA_PBR1          0xFE100080
 137 #define CONFIG_SYS_PCMCIA_POR1      (   PCMCIA_BSIZE_8  \
 138                             |   PCMCIA_PPS_8    \
 139                             |   PCMCIA_PRS_MEM  \
 140                             |   PCMCIA_SLOT_x   \
 141                             |   PCMCIA_PV       \
 142                             )
 143
 144 /* Window 2:
 145  *      Base: 0xFE100100        CS2
 146  *      Port Size:     8 Bytes
 147  *      Port Size:     8 Bit
 148  *      Common Memory Space
 149  */
 150
 151 #define CONFIG_SYS_PCMCIA_PBR2          0xFE100100
 152 #define CONFIG_SYS_PCMCIA_POR2      (   PCMCIA_BSIZE_8  \
 153                             |   PCMCIA_PPS_8    \
 154                             |   PCMCIA_PRS_MEM  \
 155                             |   PCMCIA_SLOT_x   \
 156                             |   PCMCIA_PV       \
 157                             )
 158
 159 /* Window 3:
 160  *      not used
 161  */
 162 #define CONFIG_SYS_PCMCIA_PBR3          0
 163 #define CONFIG_SYS_PCMCIA_POR3          0
 164
 165 /* Window 4:
 166  *      Base: 0xFE100C00        CS1
 167  *      Port Size:     2 Bytes
 168  *      Port Size:    16 Bit
 169  *      Common Memory Space
 170  */
 171
 172 #define CONFIG_SYS_PCMCIA_PBR4          0xFE100C00
 173 #define CONFIG_SYS_PCMCIA_POR4      (   PCMCIA_BSIZE_2  \
 174                             |   PCMCIA_PPS_16   \
 175                             |   PCMCIA_PRS_MEM  \
 176                             |   PCMCIA_SLOT_x   \
 177                             |   PCMCIA_PV       \
 178                             )
 179
 180 /* Window 5:
 181  *      Base: 0xFE100C80        CS1
 182  *      Port Size:     8 Bytes
 183  *      Port Size:     8 Bit
 184  *      Common Memory Space
 185  */
 186
 187 #define CONFIG_SYS_PCMCIA_PBR5          0xFE100C80
 188 #define CONFIG_SYS_PCMCIA_POR5      (   PCMCIA_BSIZE_8  \
 189                             |   PCMCIA_PPS_8    \
 190                             |   PCMCIA_PRS_MEM  \
 191                             |   PCMCIA_SLOT_x   \
 192                             |   PCMCIA_PV       \
 193                             )
 194
 195 /* Window 6:
 196  *      Base: 0xFE100D00        CS2
 197  *      Port Size:     8 Bytes
 198  *      Port Size:     8 Bit
 199  *      Common Memory Space
 200  */
 201
 202 #define CONFIG_SYS_PCMCIA_PBR6          0xFE100D00
 203 #define CONFIG_SYS_PCMCIA_POR6      (   PCMCIA_BSIZE_8  \
 204                             |   PCMCIA_PPS_8    \
 205                             |   PCMCIA_PRS_MEM  \
 206                             |   PCMCIA_SLOT_x   \
 207                             |   PCMCIA_PV       \
 208                             )
 209
 210 /* Window 7:
 211  *      not used
 212  */
 213 #define CONFIG_SYS_PCMCIA_PBR7          0
 214 #define CONFIG_SYS_PCMCIA_POR7          0
 215
 216 /**********************************************************************/
 217
 218 /*
 219  * CIS Tupel codes
 220  */
 221 #define CISTPL_NULL             0x00
 222 #define CISTPL_DEVICE           0x01
 223 #define CISTPL_LONGLINK_CB      0x02
 224 #define CISTPL_INDIRECT         0x03
 225 #define CISTPL_CONFIG_CB        0x04
 226 #define CISTPL_CFTABLE_ENTRY_CB 0x05
 227 #define CISTPL_LONGLINK_MFC     0x06
 228 #define CISTPL_BAR              0x07
 229 #define CISTPL_PWR_MGMNT        0x08
 230 #define CISTPL_EXTDEVICE        0x09
 231 #define CISTPL_CHECKSUM         0x10
 232 #define CISTPL_LONGLINK_A       0x11
 233 #define CISTPL_LONGLINK_C       0x12
 234 #define CISTPL_LINKTARGET       0x13
 235 #define CISTPL_NO_LINK          0x14
 236 #define CISTPL_VERS_1           0x15
 237 #define CISTPL_ALTSTR           0x16
 238 #define CISTPL_DEVICE_A         0x17
 239 #define CISTPL_JEDEC_C          0x18
 240 #define CISTPL_JEDEC_A          0x19
 241 #define CISTPL_CONFIG           0x1a
 242 #define CISTPL_CFTABLE_ENTRY    0x1b
 243 #define CISTPL_DEVICE_OC        0x1c
 244 #define CISTPL_DEVICE_OA        0x1d
 245 #define CISTPL_DEVICE_GEO       0x1e
 246 #define CISTPL_DEVICE_GEO_A     0x1f
 247 #define CISTPL_MANFID           0x20
 248 #define CISTPL_FUNCID           0x21
 249 #define CISTPL_FUNCE            0x22
 250 #define CISTPL_SWIL             0x23
 251 #define CISTPL_END              0xff
 252
 253 /*
 254  * CIS Function ID codes
 255  */
 256 #define CISTPL_FUNCID_MULTI     0x00
 257 #define CISTPL_FUNCID_MEMORY    0x01
 258 #define CISTPL_FUNCID_SERIAL    0x02
 259 #define CISTPL_FUNCID_PARALLEL  0x03
 260 #define CISTPL_FUNCID_FIXED     0x04
 261 #define CISTPL_FUNCID_VIDEO     0x05
 262 #define CISTPL_FUNCID_NETWORK   0x06
 263 #define CISTPL_FUNCID_AIMS      0x07
 264 #define CISTPL_FUNCID_SCSI      0x08
 265
 266 /*
 267  * Fixed Disk FUNCE codes
 268  */
 269 #define CISTPL_IDE_INTERFACE    0x01
 270
 271 #define CISTPL_FUNCE_IDE_IFACE  0x01
 272 #define CISTPL_FUNCE_IDE_MASTER 0x02
 273 #define CISTPL_FUNCE_IDE_SLAVE  0x03
 274
 275 /* First feature byte */
 276 #define CISTPL_IDE_SILICON      0x04
 277 #define CISTPL_IDE_UNIQUE       0x08
 278 #define CISTPL_IDE_DUAL         0x10
 279
 280 /* Second feature byte */
 281 #define CISTPL_IDE_HAS_SLEEP    0x01
 282 #define CISTPL_IDE_HAS_STANDBY  0x02
 283 #define CISTPL_IDE_HAS_IDLE     0x04
 284 #define CISTPL_IDE_LOW_POWER    0x08
 285 #define CISTPL_IDE_REG_INHIBIT  0x10
 286 #define CISTPL_IDE_HAS_INDEX    0x20
 287 #define CISTPL_IDE_IOIS16       0x40
 288
 289 #endif
 290
 291 #ifdef  CONFIG_8xx
 292 extern u_int *pcmcia_pgcrx[];
 293 #define PCMCIA_PGCRX(slot)      (*pcmcia_pgcrx[slot])
 294 #endif
 295
 296 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
 297 extern int check_ide_device(int slot);
 298 #endif
 299
 300 #endif /* _PCMCIA_H */