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1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
25 /*--------------------------------------------------------------------- */
26 /* Special Purpose Registers */
27 /*--------------------------------------------------------------------- */
28 #define dec 0x016 /* decrementer */
29 #define srr0 0x01a /* save/restore register 0 */
30 #define srr1 0x01b /* save/restore register 1 */
31 #define pid 0x030 /* process id */
32 #define decar 0x036 /* decrementer auto-reload */
33 #define csrr0 0x03a /* critical save/restore register 0 */
34 #define csrr1 0x03b /* critical save/restore register 1 */
35 #define dear 0x03d /* data exception address register */
36 #define esr 0x03e /* exception syndrome register */
37 #define ivpr 0x03f /* interrupt prefix register */
38 #define usprg0 0x100 /* user special purpose register general 0 */
39 #define usprg1 0x110 /* user special purpose register general 1 */
40 #define sprg1 0x111 /* special purpose register general 1 */
41 #define sprg2 0x112 /* special purpose register general 2 */
42 #define sprg3 0x113 /* special purpose register general 3 */
43 #define sprg4 0x114 /* special purpose register general 4 */
44 #define sprg5 0x115 /* special purpose register general 5 */
45 #define sprg6 0x116 /* special purpose register general 6 */
46 #define sprg7 0x117 /* special purpose register general 7 */
47 #define tbl 0x11c /* time base lower (supervisor)*/
48 #define tbu 0x11d /* time base upper (supervisor)*/
49 #define pir 0x11e /* processor id register */
50 /*#define pvr 0x11f processor version register */
51 #define dbsr 0x130 /* debug status register */
52 #define dbcr0 0x134 /* debug control register 0 */
53 #define dbcr1 0x135 /* debug control register 1 */
54 #define dbcr2 0x136 /* debug control register 2 */
55 #define iac1 0x138 /* instruction address compare 1 */
56 #define iac2 0x139 /* instruction address compare 2 */
57 #define iac3 0x13a /* instruction address compare 3 */
58 #define iac4 0x13b /* instruction address compare 4 */
59 #define dac1 0x13c /* data address compare 1 */
60 #define dac2 0x13d /* data address compare 2 */
61 #define dvc1 0x13e /* data value compare 1 */
62 #define dvc2 0x13f /* data value compare 2 */
63 #define tsr 0x150 /* timer status register */
64 #define tcr 0x154 /* timer control register */
65 #define ivor0 0x190 /* interrupt vector offset register 0 */
66 #define ivor1 0x191 /* interrupt vector offset register 1 */
67 #define ivor2 0x192 /* interrupt vector offset register 2 */
68 #define ivor3 0x193 /* interrupt vector offset register 3 */
69 #define ivor4 0x194 /* interrupt vector offset register 4 */
70 #define ivor5 0x195 /* interrupt vector offset register 5 */
71 #define ivor6 0x196 /* interrupt vector offset register 6 */
72 #define ivor7 0x197 /* interrupt vector offset register 7 */
73 #define ivor8 0x198 /* interrupt vector offset register 8 */
74 #define ivor9 0x199 /* interrupt vector offset register 9 */
75 #define ivor10 0x19a /* interrupt vector offset register 10 */
76 #define ivor11 0x19b /* interrupt vector offset register 11 */
77 #define ivor12 0x19c /* interrupt vector offset register 12 */
78 #define ivor13 0x19d /* interrupt vector offset register 13 */
79 #define ivor14 0x19e /* interrupt vector offset register 14 */
80 #define ivor15 0x19f /* interrupt vector offset register 15 */
81 #if defined(CONFIG_440_GX)
82 #define mcsrr0 0x23a /* machine check save/restore register 0 */
83 #define mcsrr1 0x23b /* mahcine check save/restore register 1 */
84 #define mcsr 0x23c /* machine check status register */
86 #define inv0 0x370 /* instruction cache normal victim 0 */
87 #define inv1 0x371 /* instruction cache normal victim 1 */
88 #define inv2 0x372 /* instruction cache normal victim 2 */
89 #define inv3 0x373 /* instruction cache normal victim 3 */
90 #define itv0 0x374 /* instruction cache transient victim 0 */
91 #define itv1 0x375 /* instruction cache transient victim 1 */
92 #define itv2 0x376 /* instruction cache transient victim 2 */
93 #define itv3 0x377 /* instruction cache transient victim 3 */
94 #define dnv0 0x390 /* data cache normal victim 0 */
95 #define dnv1 0x391 /* data cache normal victim 1 */
96 #define dnv2 0x392 /* data cache normal victim 2 */
97 #define dnv3 0x393 /* data cache normal victim 3 */
98 #define dtv0 0x394 /* data cache transient victim 0 */
99 #define dtv1 0x395 /* data cache transient victim 1 */
100 #define dtv2 0x396 /* data cache transient victim 2 */
101 #define dtv3 0x397 /* data cache transient victim 3 */
102 #define dvlim 0x398 /* data cache victim limit */
103 #define ivlim 0x399 /* instruction cache victim limit */
104 #define rstcfg 0x39b /* reset configuration */
105 #define dcdbtrl 0x39c /* data cache debug tag register low */
106 #define dcdbtrh 0x39d /* data cache debug tag register high */
107 #define icdbtrl 0x39e /* instruction cache debug tag register low */
108 #define icdbtrh 0x39f /* instruction cache debug tag register high */
109 #define mmucr 0x3b2 /* mmu control register */
110 #define ccr0 0x3b3 /* core configuration register 0 */
111 #define icdbdr 0x3d3 /* instruction cache debug data register */
112 #define dbdr 0x3f3 /* debug data register */
114 /******************************************************************************
116 ******************************************************************************/
118 /*-----------------------------------------------------------------------------
119 | Clocking Controller
120 +----------------------------------------------------------------------------*/
121 #define CLOCKING_DCR_BASE 0x0c
122 #define clkcfga (CLOCKING_DCR_BASE+0x0)
123 #define clkcfgd (CLOCKING_DCR_BASE+0x1)
125 /* values for clkcfga register - indirect addressing of these regs */
126 #define clk_clkukpd 0x0020
127 #define clk_pllc 0x0040
128 #define clk_plld 0x0060
129 #define clk_primad 0x0080
130 #define clk_primbd 0x00a0
131 #define clk_opbd 0x00c0
132 #define clk_perd 0x00e0
133 #define clk_mald 0x0100
134 #define clk_icfg 0x0140
136 /* 440gx sdr register definations */
137 #define SDR_DCR_BASE 0x0e
138 #define sdrcfga (SDR_DCR_BASE+0x0)
139 #define sdrcfgd (SDR_DCR_BASE+0x1)
140 #define sdr_sdstp0 0x0020 /* */
141 #define sdr_sdstp1 0x0021 /* */
142 #define sdr_pinstp 0x0040
143 #define sdr_sdcs 0x0060
144 #define sdr_ecid0 0x0080
145 #define sdr_ecid1 0x0081
146 #define sdr_ecid2 0x0082
147 #define sdr_jtag 0x00c0
148 #define sdr_ddrdl 0x00e0
149 #define sdr_ebc 0x0100
150 #define sdr_uart0 0x0120 /* UART0 Config */
151 #define sdr_uart1 0x0121 /* UART1 Config */
152 #define sdr_cp440 0x0180
153 #define sdr_xcr 0x01c0
154 #define sdr_xpllc 0x01c1
155 #define sdr_xplld 0x01c2
156 #define sdr_srst 0x0200
157 #define sdr_slpipe 0x0220
158 #define sdr_amp 0x0240
159 #define sdr_mirq0 0x0260
160 #define sdr_mirq1 0x0261
161 #define sdr_maltbl 0x0280
162 #define sdr_malrbl 0x02a0
163 #define sdr_maltbs 0x02c0
164 #define sdr_malrbs 0x02e0
165 #define sdr_cust0 0x4000
166 #define sdr_sdstp2 0x4001
167 #define sdr_cust1 0x4002
168 #define sdr_sdstp3 0x4003
169 #define sdr_pfc0 0x4100 /* Pin Function 0 */
170 #define sdr_pfc1 0x4101 /* Pin Function 1 */
171 #define sdr_plbtr 0x4200
172 #define sdr_mfr 0x4300 /* SDR0_MFR reg */
175 /*-----------------------------------------------------------------------------
177 +----------------------------------------------------------------------------*/
178 #define SDRAM_DCR_BASE 0x10
179 #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
180 #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
182 /* values for memcfga register - indirect addressing of these regs */
183 #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
184 #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
185 #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
186 #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
187 #define mem_bear 0x0010 /* bus error address reg */
188 #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
189 #define mem_mirq_set 0x0012 /* bus master interrupt (set) */
190 #define mem_slio 0x0018 /* ddr sdram slave interface options */
191 #define mem_cfg0 0x0020 /* ddr sdram options 0 */
192 #define mem_cfg1 0x0021 /* ddr sdram options 1 */
193 #define mem_devopt 0x0022 /* ddr sdram device options */
194 #define mem_mcsts 0x0024 /* memory controller status */
195 #define mem_rtr 0x0030 /* refresh timer register */
196 #define mem_pmit 0x0034 /* power management idle timer */
197 #define mem_uabba 0x0038 /* plb UABus base address */
198 #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
199 #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
200 #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
201 #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
202 #define mem_tr0 0x0080 /* sdram timing register 0 */
203 #define mem_tr1 0x0081 /* sdram timing register 1 */
204 #define mem_clktr 0x0082 /* ddr clock timing register */
205 #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
206 #define mem_dlycal 0x0084 /* delay line calibration register */
207 #define mem_eccesr 0x0098 /* ECC error status */
209 /*-----------------------------------------------------------------------------
210 | Extrnal Bus Controller
211 +----------------------------------------------------------------------------*/
212 #define EBC_DCR_BASE 0x12
213 #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
214 #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
215 /* values for ebccfga register - indirect addressing of these regs */
216 #define pb0cr 0x00 /* periph bank 0 config reg */
217 #define pb1cr 0x01 /* periph bank 1 config reg */
218 #define pb2cr 0x02 /* periph bank 2 config reg */
219 #define pb3cr 0x03 /* periph bank 3 config reg */
220 #define pb4cr 0x04 /* periph bank 4 config reg */
221 #define pb5cr 0x05 /* periph bank 5 config reg */
222 #define pb6cr 0x06 /* periph bank 6 config reg */
223 #define pb7cr 0x07 /* periph bank 7 config reg */
224 #define pb0ap 0x10 /* periph bank 0 access parameters */
225 #define pb1ap 0x11 /* periph bank 1 access parameters */
226 #define pb2ap 0x12 /* periph bank 2 access parameters */
227 #define pb3ap 0x13 /* periph bank 3 access parameters */
228 #define pb4ap 0x14 /* periph bank 4 access parameters */
229 #define pb5ap 0x15 /* periph bank 5 access parameters */
230 #define pb6ap 0x16 /* periph bank 6 access parameters */
231 #define pb7ap 0x17 /* periph bank 7 access parameters */
232 #define pbear 0x20 /* periph bus error addr reg */
233 #define pbesr 0x21 /* periph bus error status reg */
234 #define xbcfg 0x23 /* external bus configuration reg */
235 #define xbcid 0x23 /* external bus core id reg */
237 /*-----------------------------------------------------------------------------
239 +----------------------------------------------------------------------------*/
240 #define ISRAM0_DCR_BASE 0x020
241 #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
242 #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
243 #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
244 #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
245 #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
246 #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
247 #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
248 #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
249 #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
250 #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
251 #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
253 /*-----------------------------------------------------------------------------
255 +----------------------------------------------------------------------------*/
256 #if defined (CONFIG_440_GX)
257 #define L2_CACHE_BASE 0x030
258 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
259 #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
260 #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
261 #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
262 #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
263 #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
264 #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
265 #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
267 #endif /* CONFIG_440_GX */
269 /*-----------------------------------------------------------------------------
271 +----------------------------------------------------------------------------*/
272 /* TODO: as needed */
274 /*-----------------------------------------------------------------------------
275 | Clocking, Power Management and Chip Control
276 +----------------------------------------------------------------------------*/
277 #define CNTRL_DCR_BASE 0x0b0
278 #if defined (CONFIG_440_GX)
279 #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
280 #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
281 #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
283 #define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */
284 #define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */
285 #define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */
288 #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
289 #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
290 #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
291 #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
293 #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
294 #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
295 #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
296 #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
298 #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
299 #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
301 /*-----------------------------------------------------------------------------
302 | Universal interrupt controller
303 +----------------------------------------------------------------------------*/
304 #define UIC0_DCR_BASE 0xc0
305 #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
306 #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
307 #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
308 #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
309 #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
310 #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
311 #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
312 #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
314 #define UIC1_DCR_BASE 0xd0
315 #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
316 #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
317 #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
318 #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
319 #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
320 #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
321 #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
322 #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
324 #if defined(CONFIG_440_GX)
325 #define UIC2_DCR_BASE 0x210
326 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
327 #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
328 #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
329 #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
330 #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
331 #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
332 #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
333 #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
336 #define UIC_DCR_BASE 0x200
337 #define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
338 #define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
339 #define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
340 #define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
341 #define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
342 #define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
343 #define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
344 #define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
345 #endif /* CONFIG_440_GX */
347 /* The following is for compatibility with 405 code */
353 #define uicmsr uic0msr
355 #define uicvcr uic0vcr
357 /*-----------------------------------------------------------------------------
359 +----------------------------------------------------------------------------*/
360 #define DMA_DCR_BASE 0x100
361 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
362 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
363 #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
364 #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
365 #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
366 #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
367 #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
368 #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
369 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
370 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
371 #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
372 #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
373 #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
374 #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
375 #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
376 #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
377 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
378 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
379 #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
380 #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
381 #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
382 #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
383 #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
384 #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
385 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
386 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
387 #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
388 #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
389 #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
390 #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
391 #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
392 #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
393 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
394 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
395 #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
396 #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
398 /*-----------------------------------------------------------------------------
399 | Memory Access Layer
400 +----------------------------------------------------------------------------*/
401 #define MAL_DCR_BASE 0x180
402 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
403 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
404 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
405 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
406 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
407 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
408 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
409 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
410 #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
411 #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
412 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
413 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
414 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
415 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
416 #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
417 #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
418 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
419 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
420 #if defined(CONFIG_440_GX)
421 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
422 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
423 #endif /* CONFIG_440_GX */
424 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
425 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
426 #if defined(CONFIG_440_GX)
427 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
428 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
429 #endif /* CONFIG_440_GX */
430 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
431 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
432 #if defined(CONFIG_440_GX)
433 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
434 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
435 #endif /* CONFIG_440_GX */
438 /*---------------------------------------------------------------------------+
439 | Universal interrupt controller 0 interrupts (UIC0)
440 +---------------------------------------------------------------------------*/
441 #define UIC_U0 0x80000000 /* UART 0 */
442 #define UIC_U1 0x40000000 /* UART 1 */
443 #define UIC_IIC0 0x20000000 /* IIC */
444 #define UIC_IIC1 0x10000000 /* IIC */
445 #define UIC_PIM 0x08000000 /* PCI inbound message */
446 #define UIC_PCRW 0x04000000 /* PCI command register write */
447 #define UIC_PPM 0x02000000 /* PCI power management */
448 #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
449 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
450 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
451 #define UIC_MTE 0x00200000 /* MAL TXEOB */
452 #define UIC_MRE 0x00100000 /* MAL RXEOB */
453 #define UIC_D0 0x00080000 /* DMA channel 0 */
454 #define UIC_D1 0x00040000 /* DMA channel 1 */
455 #define UIC_D2 0x00020000 /* DMA channel 2 */
456 #define UIC_D3 0x00010000 /* DMA channel 3 */
457 #define UIC_RSVD0 0x00008000 /* Reserved */
458 #define UIC_RSVD1 0x00004000 /* Reserved */
459 #define UIC_CT0 0x00002000 /* GPT compare timer 0 */
460 #define UIC_CT1 0x00001000 /* GPT compare timer 1 */
461 #define UIC_CT2 0x00000800 /* GPT compare timer 2 */
462 #define UIC_CT3 0x00000400 /* GPT compare timer 3 */
463 #define UIC_CT4 0x00000200 /* GPT compare timer 4 */
464 #define UIC_EIR0 0x00000100 /* External interrupt 0 */
465 #define UIC_EIR1 0x00000080 /* External interrupt 1 */
466 #define UIC_EIR2 0x00000040 /* External interrupt 2 */
467 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
468 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
469 #define UIC_EIR5 0x00000008 /* External interrupt 5 */
470 #define UIC_EIR6 0x00000004 /* External interrupt 6 */
471 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
472 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
474 /* For compatibility with 405 code */
475 #define UIC_MAL_TXEOB UIC_MTE
476 #define UIC_MAL_RXEOB UIC_MRE
478 /*---------------------------------------------------------------------------+
479 | Universal interrupt controller 1 interrupts (UIC1)
480 +---------------------------------------------------------------------------*/
481 #define UIC_MS 0x80000000 /* MAL SERR */
482 #define UIC_MTDE 0x40000000 /* MAL TXDE */
483 #define UIC_MRDE 0x20000000 /* MAL RXDE */
484 #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
485 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
486 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
487 #define UIC_EBMI 0x02000000 /* EBMI interrupt status */
488 #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
489 #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
490 #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
491 #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
492 #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
493 #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
494 #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
495 #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
496 #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
497 #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
498 #define UIC_PPMI 0x00004000 /* PPM interrupt status */
499 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
500 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
501 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
502 #define UIC_EIR10 0x00000400 /* External interrupt 10 */
503 #define UIC_EIR11 0x00000200 /* External interrupt 11 */
504 #define UIC_EIR12 0x00000100 /* External interrupt 12 */
505 #define UIC_SRE 0x00000080 /* Serial ROM error */
506 #define UIC_RSVD2 0x00000040 /* Reserved */
507 #define UIC_RSVD3 0x00000020 /* Reserved */
508 #define UIC_PAE 0x00000010 /* PCI asynchronous error */
509 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
510 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
511 #define UIC_ETH1 0x00000002 /* Ethernet 1 */
512 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
514 /* For compatibility with 405 code */
515 #define UIC_MAL_SERR UIC_MS
516 #define UIC_MAL_TXDE UIC_MTDE
517 #define UIC_MAL_RXDE UIC_MRDE
518 #define UIC_ENET UIC_ETH0
520 /*---------------------------------------------------------------------------+
521 | Universal interrupt controller 2 interrupts (UIC2)
522 +---------------------------------------------------------------------------*/
523 #if defined(CONFIG_440_GX)
524 #define UIC_ETH2 0x80000000 /* Ethernet 2 */
525 #define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
526 #define UIC_ETH3 0x20000000 /* Ethernet 3 */
527 #define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */
528 #define UIC_TAH0 0x08000000 /* TAH 0 */
529 #define UIC_TAH1 0x04000000 /* TAH 1 */
530 #define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */
531 #define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */
532 #define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */
533 #define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */
534 #define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */
535 #define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */
536 #define UIC_IMUTO 0x00080000 /* IMU timeout */
537 #define UIC_MSI12 0x00040000 /* PCI MSI level 12 */
538 #define UIC_MSI13 0x00020000 /* PCI MSI level 13 */
539 #define UIC_MSI14 0x00010000 /* PCI MSI level 14 */
540 #define UIC_MSI15 0x00008000 /* PCI MSI level 15 */
541 #define UIC_EIR13 0x00004000 /* External interrupt 13 */
542 #define UIC_EIR14 0x00002000 /* External interrupt 14 */
543 #define UIC_EIR15 0x00001000 /* External interrupt 15 */
544 #define UIC_EIR16 0x00000800 /* External interrupt 16 */
545 #define UIC_EIR17 0x00000400 /* External interrupt 17 */
546 #define UIC_PCIVPD 0x00000200 /* PCI VPD */
547 #define UIC_L2C 0x00000100 /* L2 Cache */
548 #define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */
549 #define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */
550 #define UIC_RSVD26 0x00000020 /* Reserved */
551 #define UIC_RSVD27 0x00000010 /* Reserved */
552 #define UIC_RSVD28 0x00000008 /* Reserved */
553 #define UIC_RSVD29 0x00000004 /* Reserved */
554 #define UIC_RSVD30 0x00000002 /* Reserved */
555 #define UIC_RSVD31 0x00000001 /* Reserved */
556 #endif /* CONFIG_440_GX */
558 /*---------------------------------------------------------------------------+
559 | Universal interrupt controller Base 0 interrupts (UICB0)
560 +---------------------------------------------------------------------------*/
561 #if defined(CONFIG_440_GX)
562 #define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
563 #define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
564 #define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
565 #define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */
566 #define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */
567 #define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */
569 #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
570 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
571 #endif /* CONFIG_440_GX */
573 /*-----------------------------------------------------------------------------+
575 +-----------------------------------------------------------------------------*/
576 #if !defined (CONFIG_440_GX)
577 #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
578 #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
579 #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
580 #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
581 #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
582 #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
583 #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
584 #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
585 #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
586 #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
587 #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
588 #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
590 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
591 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
592 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
593 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
594 #else /* !CONFIG_440_GX */
595 #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
596 #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
597 #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
598 #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
599 #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
600 #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
601 #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
602 #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
603 #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
605 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
606 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
607 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
608 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
610 /* Strap 1 Register */
611 #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
612 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
613 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
614 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
615 #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
616 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
617 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
618 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
619 #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
620 #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
621 #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
622 #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
623 #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
624 #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
625 #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
626 #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
627 #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
628 #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
629 #endif /* CONFIG_440_GX */
631 /*-----------------------------------------------------------------------------
632 | IIC Register Offsets
633 '----------------------------------------------------------------------------*/
634 #define IICMDBUF 0x00
635 #define IICSDBUF 0x02
636 #define IICLMADR 0x04
637 #define IICHMADR 0x05
639 #define IICMDCNTL 0x07
641 #define IICEXTSTS 0x09
642 #define IICLSADR 0x0A
643 #define IICHSADR 0x0B
644 #define IICCLKDIV 0x0C
645 #define IICINTRMSK 0x0D
646 #define IICXFRCNT 0x0E
647 #define IICXTCNTLSS 0x0F
648 #define IICDIRECTCNTL 0x10
650 /*-----------------------------------------------------------------------------
651 | UART Register Offsets
652 '----------------------------------------------------------------------------*/
653 #define DATA_REG 0x00
656 #define INT_ENABLE 0x01
657 #define FIFO_CONTROL 0x02
658 #define LINE_CONTROL 0x03
659 #define MODEM_CONTROL 0x04
660 #define LINE_STATUS 0x05
661 #define MODEM_STATUS 0x06
664 /*-----------------------------------------------------------------------------
665 | PCI Internal Registers et. al. (accessed via plb)
666 +----------------------------------------------------------------------------*/
667 #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000)
668 #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004)
669 #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
670 #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
672 #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
673 #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
674 #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
675 #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
676 #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
677 #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
678 #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
679 #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
680 #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
681 #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
682 #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
683 #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
684 #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
685 #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
686 #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
687 #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
688 #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
689 #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
690 #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
691 #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
692 #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
693 #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
694 #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
695 #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
696 #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
697 #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
698 #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
699 #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
701 #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
702 #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
704 #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
705 #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
706 #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
707 #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
708 #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
709 #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
710 #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
711 #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
712 #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
713 #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
714 #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
716 #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
717 #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
718 #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
719 #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
720 #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
721 #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
722 #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
723 #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
724 #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
726 #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
729 * Macros for accessing the indirect EBC registers
731 #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
732 #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
735 * Macros for accessing the indirect SDRAM controller registers
737 #define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
738 #define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
741 * Macros for accessing the indirect clocking controller registers
743 #define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
744 #define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
747 * Macros for accessing the sdr controller registers
749 #define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
750 #define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
757 unsigned long pllFwdDivA
;
758 unsigned long pllFwdDivB
;
759 unsigned long pllFbkDiv
;
760 unsigned long pllOpbDiv
;
761 unsigned long pllExtBusDiv
;
762 unsigned long freqVCOMhz
; /* in MHz */
763 unsigned long freqProcessor
;
764 unsigned long freqPLB
;
765 unsigned long freqOPB
;
766 unsigned long freqEPB
;
769 #endif /* _ASMLANGUAGE */
771 #define RESET_VECTOR 0xfffffffc
772 #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
773 line aligned data. */
775 #endif /* __PPC440_H__ */
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