include/ppc_asm.tmpl

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * This file contains all the macros and symbols which define
  26  * a PowerPC assembly language environment.
  27  */
  28 #ifndef __PPC_ASM_TMPL__
  29 #define __PPC_ASM_TMPL__
  30
  31 /***************************************************************************
  32  *
  33  * These definitions simplify the ugly declarations necessary for GOT
  34  * definitions.
  35  *
  36  * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
  37  *
  38  * Uses r14 to access the GOT
  39  */
  40
  41 #define START_GOT                       \
  42         .section        ".got2","aw";   \
  43 .LCTOC1 = .+32768
  44
  45 #define END_GOT                         \
  46         .text
  47
  48 #define GET_GOT                         \
  49         bl      1f              ;       \
  50         .text   2               ;       \
  51 0:      .long   .LCTOC1-1f      ;       \
  52         .text                   ;       \
  53 1:      mflr    r14             ;       \
  54         lwz     r0,0b-1b(r14)   ;       \
  55         add     r14,r0,r14      ;
  56
  57 #define GOT_ENTRY(NAME)         .L_ ## NAME = . - .LCTOC1 ; .long NAME
  58
  59 #define GOT(NAME)               .L_ ## NAME (r14)
  60
  61
  62 /***************************************************************************
  63  * Register names
  64  */
  65 #define r0      0
  66 #define r1      1
  67 #define r2      2
  68 #define r3      3
  69 #define r4      4
  70 #define r5      5
  71 #define r6      6
  72 #define r7      7
  73 #define r8      8
  74 #define r9      9
  75 #define r10     10
  76 #define r11     11
  77 #define r12     12
  78 #define r13     13
  79 #define r14     14
  80 #define r15     15
  81 #define r16     16
  82 #define r17     17
  83 #define r18     18
  84 #define r19     19
  85 #define r20     20
  86 #define r21     21
  87 #define r22     22
  88 #define r23     23
  89 #define r24     24
  90 #define r25     25
  91 #define r26     26
  92 #define r27     27
  93 #define r28     28
  94 #define r29     29
  95 #define r30     30
  96 #define r31     31
  97
  98
  99 #if defined(CONFIG_8xx) || defined(CONFIG_MPC824X)
 100
 101 /* Some special registers */
 102
 103 #define ICR     148     /* Interrupt Cause Register (37-44) */
 104 #define DER     149
 105 #define COUNTA  150     /* Breakpoint Counter       (37-44) */
 106 #define COUNTB  151     /* Breakpoint Counter       (37-44) */
 107 #define LCTRL1  156     /* Load/Store Support       (37-40) */
 108 #define LCTRL2  157     /* Load/Store Support       (37-41) */
 109 #define ICTRL   158
 110
 111 #endif  /* CONFIG_8xx, CONFIG_MPC824X */
 112
 113
 114 #if  defined(CONFIG_5xx)
 115 /* Some special purpose registers */
 116 #define DER     149             /* Debug Enable Register                */
 117 #define COUNTA  150             /* Breakpoint Counter                   */
 118 #define COUNTB  151             /* Breakpoint Counter                   */
 119 #define LCTRL1  156             /* Load/Store Support                   */
 120 #define LCTRL2  157             /* Load/Store Support                   */
 121 #define ICTRL   158             /* I-Bus Support Control Register       */
 122 #define EID     81
 123 #endif  /* CONFIG_5xx */
 124
 125 #if defined(CONFIG_8xx)
 126
 127 /* Registers in the processor's internal memory map that we use.
 128 */
 129 #define SYPCR   0x00000004
 130 #define BR0     0x00000100
 131 #define OR0     0x00000104
 132 #define BR1     0x00000108
 133 #define OR1     0x0000010c
 134 #define BR2     0x00000110
 135 #define OR2     0x00000114
 136 #define BR3     0x00000118
 137 #define OR3     0x0000011c
 138 #define BR4     0x00000120
 139 #define OR4     0x00000124
 140
 141 #define MAR     0x00000164
 142 #define MCR     0x00000168
 143 #define MAMR    0x00000170
 144 #define MBMR    0x00000174
 145 #define MSTAT   0x00000178
 146 #define MPTPR   0x0000017a
 147 #define MDR     0x0000017c
 148
 149 #define TBSCR   0x00000200
 150 #define TBREFF0 0x00000204
 151
 152 #define PLPRCR  0x00000284
 153
 154 #elif defined(CONFIG_8260)
 155
 156 #define HID2            1011
 157
 158 #define HID0_IFEM       (1<<7)
 159
 160 #define HID0_ICE_BITPOS 16
 161 #define HID0_DCE_BITPOS 17
 162
 163 #define IM_REGBASE      0x10000
 164 #define IM_SYPCR        (IM_REGBASE+0x0004)
 165 #define IM_SWSR         (IM_REGBASE+0x000e)
 166 #define IM_BR0          (IM_REGBASE+0x0100)
 167 #define IM_OR0          (IM_REGBASE+0x0104)
 168 #define IM_BR1          (IM_REGBASE+0x0108)
 169 #define IM_OR1          (IM_REGBASE+0x010c)
 170 #define IM_BR2          (IM_REGBASE+0x0110)
 171 #define IM_OR2          (IM_REGBASE+0x0114)
 172 #define IM_MPTPR        (IM_REGBASE+0x0184)
 173 #define IM_PSDMR        (IM_REGBASE+0x0190)
 174 #define IM_PSRT         (IM_REGBASE+0x019c)
 175 #define IM_IMMR         (IM_REGBASE+0x01a8)
 176 #define IM_SCCR         (IM_REGBASE+0x0c80)
 177
 178 #endif
 179
 180 #define curptr r2
 181
 182 #define SYNC \
 183         sync; \
 184         isync
 185
 186 /*
 187  * Macros for storing registers into and loading registers from
 188  * exception frames.
 189  */
 190 #define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
 191 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
 192 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
 193 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
 194 #define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
 195 #define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
 196 #define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
 197 #define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
 198 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
 199 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
 200
 201 /*
 202  * GCC sometimes accesses words at negative offsets from the stack
 203  * pointer, although the SysV ABI says it shouldn't.  To cope with
 204  * this, we leave this much untouched space on the stack on exception
 205  * entry.
 206  */
 207 #define STACK_UNDERHEAD 64
 208
 209 /*
 210  * Exception entry code.  This code runs with address translation
 211  * turned off, i.e. using physical addresses.
 212  * We assume sprg3 has the physical address of the current
 213  * task's thread_struct.
 214  */
 215 #define EXCEPTION_PROLOG        \
 216         mtspr   SPRG0,r20;      \
 217         mtspr   SPRG1,r21;      \
 218         mfcr    r20;            \
 219         subi    r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD;  /* alloc exc. frame */\
 220         stw     r20,_CCR(r21);          /* save registers */ \
 221         stw     r22,GPR22(r21); \
 222         stw     r23,GPR23(r21); \
 223         mfspr   r20,SPRG0;      \
 224         stw     r20,GPR20(r21); \
 225         mfspr   r22,SPRG1;      \
 226         stw     r22,GPR21(r21); \
 227         mflr    r20;            \
 228         stw     r20,_LINK(r21); \
 229         mfctr   r22;            \
 230         stw     r22,_CTR(r21);  \
 231         mfspr   r20,XER;        \
 232         stw     r20,_XER(r21);  \
 233         mfspr   r22,SRR0;       \
 234         mfspr   r23,SRR1;       \
 235         stw     r0,GPR0(r21);   \
 236         stw     r1,GPR1(r21);   \
 237         stw     r2,GPR2(r21);   \
 238         stw     r1,0(r21);      \
 239         mr      r1,r21;                 /* set new kernel sp */ \
 240         SAVE_4GPRS(3, r21);
 241 /*
 242  * Note: code which follows this uses cr0.eq (set if from kernel),
 243  * r21, r22 (SRR0), and r23 (SRR1).
 244  */
 245
 246 /*
 247  * Critical exception entry code.  This is just like the other exception
 248  * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1.
 249  */
 250 #define CRITICAL_EXCEPTION_PROLOG       \
 251         mtspr   SPRG0,r20;      \
 252         mtspr   SPRG1,r21;      \
 253         mfcr    r20;            \
 254         subi    r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD;  /* alloc exc. frame */\
 255         stw     r20,_CCR(r21);          /* save registers */ \
 256         stw     r22,GPR22(r21); \
 257         stw     r23,GPR23(r21); \
 258         mfspr   r20,SPRG0;      \
 259         stw     r20,GPR20(r21); \
 260         mfspr   r22,SPRG1;      \
 261         stw     r22,GPR21(r21); \
 262         mflr    r20;            \
 263         stw     r20,_LINK(r21); \
 264         mfctr   r22;            \
 265         stw     r22,_CTR(r21);  \
 266         mfspr   r20,XER;        \
 267         stw     r20,_XER(r21);  \
 268         mfspr   r22,990;        /* SRR2 */      \
 269         mfspr   r23,991;        /* SRR3 */      \
 270         stw     r0,GPR0(r21);   \
 271         stw     r1,GPR1(r21);   \
 272         stw     r2,GPR2(r21);   \
 273         stw     r1,0(r21);      \
 274         mr      r1,r21;                 /* set new kernel sp */ \
 275         SAVE_4GPRS(3, r21);
 276 /*
 277  * Note: code which follows this uses cr0.eq (set if from kernel),
 278  * r21, r22 (SRR2), and r23 (SRR3).
 279  */
 280
 281 /*
 282  * Exception vectors.
 283  *
 284  * The data words for `hdlr' and `int_return' are initialized with
 285  * OFFSET values only; they must be relocated first before they can
 286  * be used!
 287  */
 288 #define STD_EXCEPTION(n, label, hdlr)                   \
 289         . = n;                                          \
 290 label:                                                  \
 291         EXCEPTION_PROLOG;                               \
 292         lwz     r3,GOT(transfer_to_handler);            \
 293         mtlr    r3;                                     \
 294         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 295         li      r20,MSR_KERNEL;                         \
 296         rlwimi  r20,r23,0,25,25;                        \
 297         blrl    ;                                       \
 298 .L_ ## label :                                          \
 299         .long   hdlr - _start + EXC_OFF_SYS_RESET;      \
 300         .long   int_return - _start + EXC_OFF_SYS_RESET
 301
 302
 303 #define CRIT_EXCEPTION(n, label, hdlr)                  \
 304         . = n;                                          \
 305 label:                                                  \
 306         CRITICAL_EXCEPTION_PROLOG;                      \
 307         lwz     r3,GOT(transfer_to_handler);            \
 308         mtlr    r3;                                     \
 309         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 310         li      r20,MSR_KERNEL;                         \
 311         rlwimi  r20,r23,0,25,25;                        \
 312         blrl    ;                                       \
 313 .L_ ## label :                                          \
 314         .long   hdlr - _start + EXC_OFF_SYS_RESET;      \
 315         .long   crit_return - _start + EXC_OFF_SYS_RESET
 316
 317 #endif  /* __PPC_ASM_TMPL__ */