include/tsec.h

   1 /*
   2  *  tsec.h
   3  *
   4  *  Driver for the Motorola Triple Speed Ethernet Controller
   5  *
   6  *  This software may be used and distributed according to the
   7  *  terms of the GNU Public License, Version 2, incorporated
   8  *  herein by reference.
   9  *
  10  * Copyright 2004, 2007, 2009  Freescale Semiconductor, Inc.
  11  * (C) Copyright 2003, Motorola, Inc.
  12  * maintained by Xianghua Xiao (x.xiao@motorola.com)
  13  * author Andy Fleming
  14  *
  15  */
  16
  17 #ifndef __TSEC_H
  18 #define __TSEC_H
  19
  20 #include <net.h>
  21 #include <config.h>
  22
  23 #define TSEC_SIZE               0x01000
  24 #define TSEC_MDIO_OFFSET        0x01000
  25
  26 #define STD_TSEC_INFO(num) \
  27 {                       \
  28         .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
  29         .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
  30         .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
  31                                          + (num - 1) * TSEC_MDIO_OFFSET), \
  32         .devname = CONFIG_TSEC##num##_NAME, \
  33         .phyaddr = TSEC##num##_PHY_ADDR, \
  34         .flags = TSEC##num##_FLAGS \
  35 }
  36
  37 #define SET_STD_TSEC_INFO(x, num) \
  38 {                       \
  39         x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
  40         x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
  41         x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
  42                                           + (num - 1) * TSEC_MDIO_OFFSET); \
  43         x.devname = CONFIG_TSEC##num##_NAME; \
  44         x.phyaddr = TSEC##num##_PHY_ADDR; \
  45         x.flags = TSEC##num##_FLAGS;\
  46 }
  47
  48 #define MAC_ADDR_LEN 6
  49
  50 /* #define TSEC_TIMEOUT 1000000 */
  51 #define TSEC_TIMEOUT 1000
  52 #define TOUT_LOOP       1000000
  53
  54 #define PHY_AUTONEGOTIATE_TIMEOUT       5000 /* in ms */
  55
  56 /* TBI register addresses */
  57 #define TBI_CR                  0x00
  58 #define TBI_SR                  0x01
  59 #define TBI_ANA                 0x04
  60 #define TBI_ANLPBPA             0x05
  61 #define TBI_ANEX                0x06
  62 #define TBI_TBICON              0x11
  63
  64 /* TBI MDIO register bit fields*/
  65 #define TBICON_CLK_SELECT       0x0020
  66 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
  67 #define TBIANA_SYMMETRIC_PAUSE  0x0080
  68 #define TBIANA_HALF_DUPLEX      0x0040
  69 #define TBIANA_FULL_DUPLEX      0x0020
  70 #define TBICR_PHY_RESET         0x8000
  71 #define TBICR_ANEG_ENABLE       0x1000
  72 #define TBICR_RESTART_ANEG      0x0200
  73 #define TBICR_FULL_DUPLEX       0x0100
  74 #define TBICR_SPEED1_SET        0x0040
  75
  76
  77 /* MAC register bits */
  78 #define MACCFG1_SOFT_RESET      0x80000000
  79 #define MACCFG1_RESET_RX_MC     0x00080000
  80 #define MACCFG1_RESET_TX_MC     0x00040000
  81 #define MACCFG1_RESET_RX_FUN    0x00020000
  82 #define MACCFG1_RESET_TX_FUN    0x00010000
  83 #define MACCFG1_LOOPBACK        0x00000100
  84 #define MACCFG1_RX_FLOW         0x00000020
  85 #define MACCFG1_TX_FLOW         0x00000010
  86 #define MACCFG1_SYNCD_RX_EN     0x00000008
  87 #define MACCFG1_RX_EN           0x00000004
  88 #define MACCFG1_SYNCD_TX_EN     0x00000002
  89 #define MACCFG1_TX_EN           0x00000001
  90
  91 #define MACCFG2_INIT_SETTINGS   0x00007205
  92 #define MACCFG2_FULL_DUPLEX     0x00000001
  93 #define MACCFG2_IF              0x00000300
  94 #define MACCFG2_GMII            0x00000200
  95 #define MACCFG2_MII             0x00000100
  96
  97 #define ECNTRL_INIT_SETTINGS    0x00001000
  98 #define ECNTRL_TBI_MODE         0x00000020
  99 #define ECNTRL_R100             0x00000008
 100 #define ECNTRL_SGMII_MODE       0x00000002
 101
 102 #define miim_end -2
 103 #define miim_read -1
 104
 105 #ifndef CONFIG_SYS_TBIPA_VALUE
 106     #define CONFIG_SYS_TBIPA_VALUE      0x1f
 107 #endif
 108 #define MIIMCFG_INIT_VALUE      0x00000003
 109 #define MIIMCFG_RESET           0x80000000
 110
 111 #define MIIMIND_BUSY            0x00000001
 112 #define MIIMIND_NOTVALID        0x00000004
 113
 114 #define MIIM_CONTROL            0x00
 115 #define MIIM_CONTROL_RESET      0x00009140
 116 #define MIIM_CONTROL_INIT       0x00001140
 117 #define MIIM_CONTROL_RESTART    0x00001340
 118 #define MIIM_ANEN               0x00001000
 119
 120 #define MIIM_CR                 0x00
 121 #define MIIM_CR_RST             0x00008000
 122 #define MIIM_CR_INIT            0x00001000
 123
 124 #define MIIM_STATUS             0x1
 125 #define MIIM_STATUS_AN_DONE     0x00000020
 126 #define MIIM_STATUS_LINK        0x0004
 127
 128 #define MIIM_PHYIR1             0x2
 129 #define MIIM_PHYIR2             0x3
 130
 131 #define MIIM_ANAR               0x4
 132 #define MIIM_ANAR_INIT          0x1e1
 133
 134 #define MIIM_TBI_ANLPBPA        0x5
 135 #define MIIM_TBI_ANLPBPA_HALF   0x00000040
 136 #define MIIM_TBI_ANLPBPA_FULL   0x00000020
 137
 138 #define MIIM_TBI_ANEX           0x6
 139 #define MIIM_TBI_ANEX_NP        0x00000004
 140 #define MIIM_TBI_ANEX_PRX       0x00000002
 141
 142 #define MIIM_GBIT_CONTROL       0x9
 143 #define MIIM_GBIT_CONTROL_INIT  0xe00
 144
 145 #define MIIM_EXT_PAGE_ACCESS    0x1f
 146
 147 /* Broadcom BCM54xx -- taken from linux sungem_phy */
 148 #define MIIM_BCM54xx_AUXCNTL                    0x18
 149 #define MIIM_BCM54xx_AUXCNTL_ENCODE(val)        ((val & 0x7) << 12)|(val & 0x7)
 150 #define MIIM_BCM54xx_AUXSTATUS                  0x19
 151 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK    0x0700
 152 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT   8
 153
 154 #define MIIM_BCM54XX_SHD        0x1c    /* 0x1c shadow registers */
 155 #define MIIM_BCM54XX_SHD_WRITE  0x8000
 156 #define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
 157 #define MIIM_BCM54XX_SHD_DATA(x)        ((x & 0x3ff) << 0)
 158 #define MIIM_BCM54XX_SHD_WR_ENCODE(val, data)   \
 159         (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
 160          MIIM_BCM54XX_SHD_DATA(data))
 161
 162 #define MIIM_BCM54XX_EXP_DATA   0x15    /* Expansion register data */
 163 #define MIIM_BCM54XX_EXP_SEL    0x17    /* Expansion register select */
 164 #define MIIM_BCM54XX_EXP_SEL_SSD        0x0e00  /* Secondary SerDes select */
 165 #define MIIM_BCM54XX_EXP_SEL_ER 0x0f00  /* Expansion register select */
 166
 167 /* Cicada Auxiliary Control/Status Register */
 168 #define MIIM_CIS8201_AUX_CONSTAT        0x1c
 169 #define MIIM_CIS8201_AUXCONSTAT_INIT    0x0004
 170 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX  0x0020
 171 #define MIIM_CIS8201_AUXCONSTAT_SPEED   0x0018
 172 #define MIIM_CIS8201_AUXCONSTAT_GBIT    0x0010
 173 #define MIIM_CIS8201_AUXCONSTAT_100     0x0008
 174
 175 /* Cicada Extended Control Register 1 */
 176 #define MIIM_CIS8201_EXT_CON1           0x17
 177 #define MIIM_CIS8201_EXTCON1_INIT       0x0000
 178
 179 /* Cicada 8204 Extended PHY Control Register 1 */
 180 #define MIIM_CIS8204_EPHY_CON           0x17
 181 #define MIIM_CIS8204_EPHYCON_INIT       0x0006
 182 #define MIIM_CIS8204_EPHYCON_RGMII      0x1100
 183
 184 /* Cicada 8204 Serial LED Control Register */
 185 #define MIIM_CIS8204_SLED_CON           0x1b
 186 #define MIIM_CIS8204_SLEDCON_INIT       0x1115
 187
 188 #define MIIM_GBIT_CON           0x09
 189 #define MIIM_GBIT_CON_ADVERT    0x0e00
 190
 191 /* Entry for Vitesse VSC8244 regs starts here */
 192 /* Vitesse VSC8244 Auxiliary Control/Status Register */
 193 #define MIIM_VSC8244_AUX_CONSTAT        0x1c
 194 #define MIIM_VSC8244_AUXCONSTAT_INIT    0x0000
 195 #define MIIM_VSC8244_AUXCONSTAT_DUPLEX  0x0020
 196 #define MIIM_VSC8244_AUXCONSTAT_SPEED   0x0018
 197 #define MIIM_VSC8244_AUXCONSTAT_GBIT    0x0010
 198 #define MIIM_VSC8244_AUXCONSTAT_100     0x0008
 199 #define MIIM_CONTROL_INIT_LOOPBACK      0x4000
 200
 201 /* Vitesse VSC8244 Extended PHY Control Register 1 */
 202 #define MIIM_VSC8244_EPHY_CON           0x17
 203 #define MIIM_VSC8244_EPHYCON_INIT       0x0006
 204
 205 /* Vitesse VSC8244 Serial LED Control Register */
 206 #define MIIM_VSC8244_LED_CON            0x1b
 207 #define MIIM_VSC8244_LEDCON_INIT        0xF011
 208
 209 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */
 210 /* Vitesse VSC8601 Extended PHY Control Register 1 */
 211 #define MIIM_VSC8601_EPHY_CON           0x17
 212 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
 213 #define MIIM_VSC8601_SKEW_CTRL          0x1c
 214
 215 /* 88E1011 PHY Status Register */
 216 #define MIIM_88E1011_PHY_STATUS         0x11
 217 #define MIIM_88E1011_PHYSTAT_SPEED      0xc000
 218 #define MIIM_88E1011_PHYSTAT_GBIT       0x8000
 219 #define MIIM_88E1011_PHYSTAT_100        0x4000
 220 #define MIIM_88E1011_PHYSTAT_DUPLEX     0x2000
 221 #define MIIM_88E1011_PHYSTAT_SPDDONE    0x0800
 222 #define MIIM_88E1011_PHYSTAT_LINK       0x0400
 223
 224 #define MIIM_88E1011_PHY_SCR            0x10
 225 #define MIIM_88E1011_PHY_MDI_X_AUTO     0x0060
 226
 227 /* 88E1111 PHY LED Control Register */
 228 #define MIIM_88E1111_PHY_LED_CONTROL    24
 229 #define MIIM_88E1111_PHY_LED_DIRECT     0x4100
 230 #define MIIM_88E1111_PHY_LED_COMBINE    0x411C
 231
 232 /* 88E1121 PHY LED Control Register */
 233 #define MIIM_88E1121_PHY_LED_CTRL       16
 234 #define MIIM_88E1121_PHY_LED_PAGE       3
 235 #define MIIM_88E1121_PHY_LED_DEF        0x0030
 236
 237 /* 88E1121 PHY IRQ Enable/Status Register */
 238 #define MIIM_88E1121_PHY_IRQ_EN         18
 239 #define MIIM_88E1121_PHY_IRQ_STATUS     19
 240
 241 #define MIIM_88E1121_PHY_PAGE           22
 242
 243 /* 88E1145 Extended PHY Specific Control Register */
 244 #define MIIM_88E1145_PHY_EXT_CR 20
 245 #define MIIM_M88E1145_RGMII_RX_DELAY    0x0080
 246 #define MIIM_M88E1145_RGMII_TX_DELAY    0x0002
 247
 248 #define MIIM_88E1145_PHY_PAGE   29
 249 #define MIIM_88E1145_PHY_CAL_OV 30
 250
 251 /* RTL8211B PHY Status Register */
 252 #define MIIM_RTL8211B_PHY_STATUS        0x11
 253 #define MIIM_RTL8211B_PHYSTAT_SPEED     0xc000
 254 #define MIIM_RTL8211B_PHYSTAT_GBIT      0x8000
 255 #define MIIM_RTL8211B_PHYSTAT_100       0x4000
 256 #define MIIM_RTL8211B_PHYSTAT_DUPLEX    0x2000
 257 #define MIIM_RTL8211B_PHYSTAT_SPDDONE   0x0800
 258 #define MIIM_RTL8211B_PHYSTAT_LINK      0x0400
 259
 260 /* DM9161 Control register values */
 261 #define MIIM_DM9161_CR_STOP     0x0400
 262 #define MIIM_DM9161_CR_RSTAN    0x1200
 263
 264 #define MIIM_DM9161_SCR         0x10
 265 #define MIIM_DM9161_SCR_INIT    0x0610
 266
 267 /* DM9161 Specified Configuration and Status Register */
 268 #define MIIM_DM9161_SCSR        0x11
 269 #define MIIM_DM9161_SCSR_100F   0x8000
 270 #define MIIM_DM9161_SCSR_100H   0x4000
 271 #define MIIM_DM9161_SCSR_10F    0x2000
 272 #define MIIM_DM9161_SCSR_10H    0x1000
 273
 274 /* DM9161 10BT Configuration/Status */
 275 #define MIIM_DM9161_10BTCSR     0x12
 276 #define MIIM_DM9161_10BTCSR_INIT        0x7800
 277
 278 /* LXT971 Status 2 registers */
 279 #define MIIM_LXT971_SR2              0x11  /* Status Register 2  */
 280 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
 281 #define MIIM_LXT971_SR2_10HDX      0x0000  /*  10 Mbit half duplex selected */
 282 #define MIIM_LXT971_SR2_10FDX      0x0200  /*  10 Mbit full duplex selected */
 283 #define MIIM_LXT971_SR2_100HDX     0x4000  /* 100 Mbit half duplex selected */
 284 #define MIIM_LXT971_SR2_100FDX     0x4200  /* 100 Mbit full duplex selected */
 285
 286 /* DP83865 Control register values */
 287 #define MIIM_DP83865_CR_INIT    0x9200
 288
 289 /* DP83865 Link and Auto-Neg Status Register */
 290 #define MIIM_DP83865_LANR       0x11
 291 #define MIIM_DP83865_SPD_MASK   0x0018
 292 #define MIIM_DP83865_SPD_1000   0x0010
 293 #define MIIM_DP83865_SPD_100    0x0008
 294 #define MIIM_DP83865_DPX_FULL   0x0002
 295
 296 #define MIIM_READ_COMMAND       0x00000001
 297
 298 #define MRBLR_INIT_SETTINGS     PKTSIZE_ALIGN
 299
 300 #define MINFLR_INIT_SETTINGS    0x00000040
 301
 302 #define DMACTRL_INIT_SETTINGS   0x000000c3
 303 #define DMACTRL_GRS             0x00000010
 304 #define DMACTRL_GTS             0x00000008
 305
 306 #define TSTAT_CLEAR_THALT       0x80000000
 307 #define RSTAT_CLEAR_RHALT       0x00800000
 308
 309
 310 #define IEVENT_INIT_CLEAR       0xffffffff
 311 #define IEVENT_BABR             0x80000000
 312 #define IEVENT_RXC              0x40000000
 313 #define IEVENT_BSY              0x20000000
 314 #define IEVENT_EBERR            0x10000000
 315 #define IEVENT_MSRO             0x04000000
 316 #define IEVENT_GTSC             0x02000000
 317 #define IEVENT_BABT             0x01000000
 318 #define IEVENT_TXC              0x00800000
 319 #define IEVENT_TXE              0x00400000
 320 #define IEVENT_TXB              0x00200000
 321 #define IEVENT_TXF              0x00100000
 322 #define IEVENT_IE               0x00080000
 323 #define IEVENT_LC               0x00040000
 324 #define IEVENT_CRL              0x00020000
 325 #define IEVENT_XFUN             0x00010000
 326 #define IEVENT_RXB0             0x00008000
 327 #define IEVENT_GRSC             0x00000100
 328 #define IEVENT_RXF0             0x00000080
 329
 330 #define IMASK_INIT_CLEAR        0x00000000
 331 #define IMASK_TXEEN             0x00400000
 332 #define IMASK_TXBEN             0x00200000
 333 #define IMASK_TXFEN             0x00100000
 334 #define IMASK_RXFEN0            0x00000080
 335
 336
 337 /* Default Attribute fields */
 338 #define ATTR_INIT_SETTINGS     0x000000c0
 339 #define ATTRELI_INIT_SETTINGS  0x00000000
 340
 341
 342 /* TxBD status field bits */
 343 #define TXBD_READY              0x8000
 344 #define TXBD_PADCRC             0x4000
 345 #define TXBD_WRAP               0x2000
 346 #define TXBD_INTERRUPT          0x1000
 347 #define TXBD_LAST               0x0800
 348 #define TXBD_CRC                0x0400
 349 #define TXBD_DEF                0x0200
 350 #define TXBD_HUGEFRAME          0x0080
 351 #define TXBD_LATECOLLISION      0x0080
 352 #define TXBD_RETRYLIMIT         0x0040
 353 #define TXBD_RETRYCOUNTMASK     0x003c
 354 #define TXBD_UNDERRUN           0x0002
 355 #define TXBD_STATS              0x03ff
 356
 357 /* RxBD status field bits */
 358 #define RXBD_EMPTY              0x8000
 359 #define RXBD_RO1                0x4000
 360 #define RXBD_WRAP               0x2000
 361 #define RXBD_INTERRUPT          0x1000
 362 #define RXBD_LAST               0x0800
 363 #define RXBD_FIRST              0x0400
 364 #define RXBD_MISS               0x0100
 365 #define RXBD_BROADCAST          0x0080
 366 #define RXBD_MULTICAST          0x0040
 367 #define RXBD_LARGE              0x0020
 368 #define RXBD_NONOCTET           0x0010
 369 #define RXBD_SHORT              0x0008
 370 #define RXBD_CRCERR             0x0004
 371 #define RXBD_OVERRUN            0x0002
 372 #define RXBD_TRUNCATED          0x0001
 373 #define RXBD_STATS              0x003f
 374
 375 typedef struct txbd8
 376 {
 377         ushort       status;         /* Status Fields */
 378         ushort       length;         /* Buffer length */
 379         uint         bufPtr;         /* Buffer Pointer */
 380 } txbd8_t;
 381
 382 typedef struct rxbd8
 383 {
 384         ushort       status;         /* Status Fields */
 385         ushort       length;         /* Buffer Length */
 386         uint         bufPtr;         /* Buffer Pointer */
 387 } rxbd8_t;
 388
 389 typedef struct rmon_mib
 390 {
 391         /* Transmit and Receive Counters */
 392         uint    tr64;           /* Transmit and Receive 64-byte Frame Counter */
 393         uint    tr127;          /* Transmit and Receive 65-127 byte Frame Counter */
 394         uint    tr255;          /* Transmit and Receive 128-255 byte Frame Counter */
 395         uint    tr511;          /* Transmit and Receive 256-511 byte Frame Counter */
 396         uint    tr1k;           /* Transmit and Receive 512-1023 byte Frame Counter */
 397         uint    trmax;          /* Transmit and Receive 1024-1518 byte Frame Counter */
 398         uint    trmgv;          /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
 399         /* Receive Counters */
 400         uint    rbyt;           /* Receive Byte Counter */
 401         uint    rpkt;           /* Receive Packet Counter */
 402         uint    rfcs;           /* Receive FCS Error Counter */
 403         uint    rmca;           /* Receive Multicast Packet (Counter) */
 404         uint    rbca;           /* Receive Broadcast Packet */
 405         uint    rxcf;           /* Receive Control Frame Packet */
 406         uint    rxpf;           /* Receive Pause Frame Packet */
 407         uint    rxuo;           /* Receive Unknown OP Code */
 408         uint    raln;           /* Receive Alignment Error */
 409         uint    rflr;           /* Receive Frame Length Error */
 410         uint    rcde;           /* Receive Code Error */
 411         uint    rcse;           /* Receive Carrier Sense Error */
 412         uint    rund;           /* Receive Undersize Packet */
 413         uint    rovr;           /* Receive Oversize Packet */
 414         uint    rfrg;           /* Receive Fragments */
 415         uint    rjbr;           /* Receive Jabber */
 416         uint    rdrp;           /* Receive Drop */
 417         /* Transmit Counters */
 418         uint    tbyt;           /* Transmit Byte Counter */
 419         uint    tpkt;           /* Transmit Packet */
 420         uint    tmca;           /* Transmit Multicast Packet */
 421         uint    tbca;           /* Transmit Broadcast Packet */
 422         uint    txpf;           /* Transmit Pause Control Frame */
 423         uint    tdfr;           /* Transmit Deferral Packet */
 424         uint    tedf;           /* Transmit Excessive Deferral Packet */
 425         uint    tscl;           /* Transmit Single Collision Packet */
 426         /* (0x2_n700) */
 427         uint    tmcl;           /* Transmit Multiple Collision Packet */
 428         uint    tlcl;           /* Transmit Late Collision Packet */
 429         uint    txcl;           /* Transmit Excessive Collision Packet */
 430         uint    tncl;           /* Transmit Total Collision */
 431
 432         uint    res2;
 433
 434         uint    tdrp;           /* Transmit Drop Frame */
 435         uint    tjbr;           /* Transmit Jabber Frame */
 436         uint    tfcs;           /* Transmit FCS Error */
 437         uint    txcf;           /* Transmit Control Frame */
 438         uint    tovr;           /* Transmit Oversize Frame */
 439         uint    tund;           /* Transmit Undersize Frame */
 440         uint    tfrg;           /* Transmit Fragments Frame */
 441         /* General Registers */
 442         uint    car1;           /* Carry Register One */
 443         uint    car2;           /* Carry Register Two */
 444         uint    cam1;           /* Carry Register One Mask */
 445         uint    cam2;           /* Carry Register Two Mask */
 446 } rmon_mib_t;
 447
 448 typedef struct tsec_hash_regs
 449 {
 450         uint    iaddr0;         /* Individual Address Register 0 */
 451         uint    iaddr1;         /* Individual Address Register 1 */
 452         uint    iaddr2;         /* Individual Address Register 2 */
 453         uint    iaddr3;         /* Individual Address Register 3 */
 454         uint    iaddr4;         /* Individual Address Register 4 */
 455         uint    iaddr5;         /* Individual Address Register 5 */
 456         uint    iaddr6;         /* Individual Address Register 6 */
 457         uint    iaddr7;         /* Individual Address Register 7 */
 458         uint    res1[24];
 459         uint    gaddr0;         /* Group Address Register 0 */
 460         uint    gaddr1;         /* Group Address Register 1 */
 461         uint    gaddr2;         /* Group Address Register 2 */
 462         uint    gaddr3;         /* Group Address Register 3 */
 463         uint    gaddr4;         /* Group Address Register 4 */
 464         uint    gaddr5;         /* Group Address Register 5 */
 465         uint    gaddr6;         /* Group Address Register 6 */
 466         uint    gaddr7;         /* Group Address Register 7 */
 467         uint    res2[24];
 468 } tsec_hash_t;
 469
 470 typedef struct tsec_mdio {
 471         uint    res1[4];
 472         uint    ieventm;
 473         uint    imaskm;
 474         uint    res2;
 475         uint    emapm;
 476         uint    res3[320];
 477         uint    miimcfg;        /* MII Management: Configuration */
 478         uint    miimcom;        /* MII Management: Command */
 479         uint    miimadd;        /* MII Management: Address */
 480         uint    miimcon;        /* MII Management: Control */
 481         uint    miimstat;       /* MII Management: Status */
 482         uint    miimind;        /* MII Management: Indicators */
 483         uint    res4[690];
 484 } tsec_mdio_t;
 485
 486 typedef struct tsec
 487 {
 488         /* General Control and Status Registers (0x2_n000) */
 489         uint    res000[4];
 490
 491         uint    ievent;         /* Interrupt Event */
 492         uint    imask;          /* Interrupt Mask */
 493         uint    edis;           /* Error Disabled */
 494         uint    res01c;
 495         uint    ecntrl;         /* Ethernet Control */
 496         uint    minflr;         /* Minimum Frame Length */
 497         uint    ptv;            /* Pause Time Value */
 498         uint    dmactrl;        /* DMA Control */
 499         uint    tbipa;          /* TBI PHY Address */
 500
 501         uint    res034[3];
 502         uint    res040[48];
 503
 504         /* Transmit Control and Status Registers (0x2_n100) */
 505         uint    tctrl;          /* Transmit Control */
 506         uint    tstat;          /* Transmit Status */
 507         uint    res108;
 508         uint    tbdlen;         /* Tx BD Data Length */
 509         uint    res110[5];
 510         uint    ctbptr;         /* Current TxBD Pointer */
 511         uint    res128[23];
 512         uint    tbptr;          /* TxBD Pointer */
 513         uint    res188[30];
 514         /* (0x2_n200) */
 515         uint    res200;
 516         uint    tbase;          /* TxBD Base Address */
 517         uint    res208[42];
 518         uint    ostbd;          /* Out of Sequence TxBD */
 519         uint    ostbdp;         /* Out of Sequence Tx Data Buffer Pointer */
 520         uint    res2b8[18];
 521
 522         /* Receive Control and Status Registers (0x2_n300) */
 523         uint    rctrl;          /* Receive Control */
 524         uint    rstat;          /* Receive Status */
 525         uint    res308;
 526         uint    rbdlen;         /* RxBD Data Length */
 527         uint    res310[4];
 528         uint    res320;
 529         uint    crbptr; /* Current Receive Buffer Pointer */
 530         uint    res328[6];
 531         uint    mrblr;  /* Maximum Receive Buffer Length */
 532         uint    res344[16];
 533         uint    rbptr;  /* RxBD Pointer */
 534         uint    res388[30];
 535         /* (0x2_n400) */
 536         uint    res400;
 537         uint    rbase;  /* RxBD Base Address */
 538         uint    res408[62];
 539
 540         /* MAC Registers (0x2_n500) */
 541         uint    maccfg1;        /* MAC Configuration #1 */
 542         uint    maccfg2;        /* MAC Configuration #2 */
 543         uint    ipgifg;         /* Inter Packet Gap/Inter Frame Gap */
 544         uint    hafdup;         /* Half-duplex */
 545         uint    maxfrm;         /* Maximum Frame */
 546         uint    res514;
 547         uint    res518;
 548
 549         uint    res51c;
 550
 551         uint    resmdio[6];
 552
 553         uint    res538;
 554
 555         uint    ifstat;         /* Interface Status */
 556         uint    macstnaddr1;    /* Station Address, part 1 */
 557         uint    macstnaddr2;    /* Station Address, part 2 */
 558         uint    res548[46];
 559
 560         /* (0x2_n600) */
 561         uint    res600[32];
 562
 563         /* RMON MIB Registers (0x2_n680-0x2_n73c) */
 564         rmon_mib_t      rmon;
 565         uint    res740[48];
 566
 567         /* Hash Function Registers (0x2_n800) */
 568         tsec_hash_t     hash;
 569
 570         uint    res900[128];
 571
 572         /* Pattern Registers (0x2_nb00) */
 573         uint    resb00[62];
 574         uint    attr;      /* Default Attribute Register */
 575         uint    attreli;           /* Default Attribute Extract Length and Index */
 576
 577         /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
 578         uint    resc00[256];
 579 } tsec_t;
 580
 581 #define TSEC_GIGABIT (1)
 582
 583 /* This flag currently only has
 584  * meaning if we're using the eTSEC */
 585 #define TSEC_REDUCED    (1 << 1)        /* MAC-PHY interface uses RGMII */
 586 #define TSEC_SGMII      (1 << 2)        /* MAC-PHY interface uses SGMII */
 587 #define TSEC_FIBER      (1 << 3)        /* PHY uses fiber, eg 1000 Base-X */
 588
 589 struct tsec_private {
 590         volatile tsec_t *regs;
 591         volatile tsec_mdio_t *phyregs;
 592         volatile tsec_mdio_t *phyregs_sgmii;
 593         struct phy_info *phyinfo;
 594         uint phyaddr;
 595         u32 flags;
 596         uint link;
 597         uint duplexity;
 598         uint speed;
 599 };
 600
 601
 602 /*
 603  * struct phy_cmd:  A command for reading or writing a PHY register
 604  *
 605  * mii_reg:  The register to read or write
 606  *
 607  * mii_data:  For writes, the value to put in the register.
 608  *      A value of -1 indicates this is a read.
 609  *
 610  * funct: A function pointer which is invoked for each command.
 611  *      For reads, this function will be passed the value read
 612  *      from the PHY, and process it.
 613  *      For writes, the result of this function will be written
 614  *      to the PHY register
 615  */
 616 struct phy_cmd {
 617         uint mii_reg;
 618         uint mii_data;
 619         uint (*funct) (uint mii_reg, struct tsec_private * priv);
 620 };
 621
 622 /* struct phy_info: a structure which defines attributes for a PHY
 623  *
 624  * id will contain a number which represents the PHY.  During
 625  * startup, the driver will poll the PHY to find out what its
 626  * UID--as defined by registers 2 and 3--is.  The 32-bit result
 627  * gotten from the PHY will be shifted right by "shift" bits to
 628  * discard any bits which may change based on revision numbers
 629  * unimportant to functionality
 630  *
 631  * The struct phy_cmd entries represent pointers to an arrays of
 632  * commands which tell the driver what to do to the PHY.
 633  */
 634 struct phy_info {
 635         uint id;
 636         char *name;
 637         uint shift;
 638         /* Called to configure the PHY, and modify the controller
 639          * based on the results */
 640         struct phy_cmd *config;
 641
 642         /* Called when starting up the controller */
 643         struct phy_cmd *startup;
 644
 645         /* Called when bringing down the controller */
 646         struct phy_cmd *shutdown;
 647 };
 648
 649 struct tsec_info_struct {
 650         tsec_t *regs;
 651         tsec_mdio_t *miiregs;
 652         tsec_mdio_t *miiregs_sgmii;
 653         char *devname;
 654         unsigned int phyaddr;
 655         u32 flags;
 656 };
 657
 658 int tsec_standard_init(bd_t *bis);
 659 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
 660
 661 #endif /* __TSEC_H */