include/usb/ehci-fsl.h

   1 /*
   2  * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
   3  * Copyright (c) 2005 MontaVista Software
   4  * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef _EHCI_FSL_H
  23 #define _EHCI_FSL_H
  24
  25 #include <asm/processor.h>
  26
  27 /* Global offsets */
  28 #define FSL_SKIP_PCI            0x100
  29
  30 /* offsets for the non-ehci registers in the FSL SOC USB controller */
  31 #define FSL_SOC_USB_ULPIVP      0x170
  32 #define FSL_SOC_USB_PORTSC1     0x184
  33 #define PORT_PTS_MSK            (3 << 30)
  34 #define PORT_PTS_UTMI           (0 << 30)
  35 #define PORT_PTS_ULPI           (2 << 30)
  36 #define PORT_PTS_SERIAL         (3 << 30)
  37 #define PORT_PTS_PTW            (1 << 28)
  38
  39 /* USBMODE Register bits */
  40 #define CM_IDLE                 (0 << 0)
  41 #define CM_RESERVED             (1 << 0)
  42 #define CM_DEVICE               (2 << 0)
  43 #define CM_HOST                 (3 << 0)
  44 #define USBMODE_RESERVED_2      (0 << 2)
  45 #define SLOM                    (1 << 3)
  46 #define SDIS                    (1 << 4)
  47
  48 /* CONTROL Register bits */
  49 #define ULPI_INT_EN             (1 << 0)
  50 #define WU_INT_EN               (1 << 1)
  51 #define USB_EN                  (1 << 2)
  52 #define LSF_EN                  (1 << 3)
  53 #define KEEP_OTG_ON             (1 << 4)
  54 #define OTG_PORT                (1 << 5)
  55 #define REFSEL_12MHZ            (0 << 6)
  56 #define REFSEL_16MHZ            (1 << 6)
  57 #define REFSEL_48MHZ            (2 << 6)
  58 #define PLL_RESET               (1 << 8)
  59 #define UTMI_PHY_EN             (1 << 9)
  60 #define PHY_CLK_SEL_UTMI        (0 << 10)
  61 #define PHY_CLK_SEL_ULPI        (1 << 10)
  62 #define CLKIN_SEL_USB_CLK       (0 << 11)
  63 #define CLKIN_SEL_USB_CLK2      (1 << 11)
  64 #define CLKIN_SEL_SYS_CLK       (2 << 11)
  65 #define CLKIN_SEL_SYS_CLK2      (3 << 11)
  66 #define RESERVED_18             (0 << 13)
  67 #define RESERVED_17             (0 << 14)
  68 #define RESERVED_16             (0 << 15)
  69 #define WU_INT                  (1 << 16)
  70 #define PHY_CLK_VALID           (1 << 17)
  71
  72 #define FSL_SOC_USB_PORTSC2     0x188
  73 #define FSL_SOC_USB_USBMODE     0x1a8
  74 #define FSL_SOC_USB_SNOOP1      0x400   /* NOTE: big-endian */
  75 #define FSL_SOC_USB_SNOOP2      0x404   /* NOTE: big-endian */
  76 #define FSL_SOC_USB_AGECNTTHRSH 0x408   /* NOTE: big-endian */
  77 #define FSL_SOC_USB_PRICTRL     0x40c   /* NOTE: big-endian */
  78 #define FSL_SOC_USB_SICTRL      0x410   /* NOTE: big-endian */
  79 #define FSL_SOC_USB_CTRL        0x500   /* NOTE: big-endian */
  80 #define SNOOP_SIZE_2GB          0x1e
  81
  82 /* System Clock Control Register */
  83 #define MPC83XX_SCCR_USB_MASK           0x00f00000
  84 #define MPC83XX_SCCR_USB_DRCM_11        0x00300000
  85 #define MPC83XX_SCCR_USB_DRCM_01        0x00100000
  86 #define MPC83XX_SCCR_USB_DRCM_10        0x00200000
  87
  88 #if defined(CONFIG_MPC83xx)
  89 #define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
  90 #elif defined(CONFIG_MPC85xx)
  91 #define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
  92 #endif
  93
  94 /*
  95  * USB Registers
  96  */
  97 struct usb_ehci {
  98         u8      res1[0x100];
  99         u16     caplength;      /* 0x100 - Capability Register Length */
 100         u16     hciversion;     /* 0x102 - Host Interface Version */
 101         u32     hcsparams;      /* 0x104 - Host Structural Parameters */
 102         u32     hccparams;      /* 0x108 - Host Capability Parameters */
 103         u8      res2[0x14];
 104         u32     dciversion;     /* 0x120 - Device Interface Version */
 105         u32     dciparams;      /* 0x124 - Device Controller Params */
 106         u8      res3[0x18];
 107         u32     usbcmd;         /* 0x140 - USB Command */
 108         u32     usbsts;         /* 0x144 - USB Status */
 109         u32     usbintr;        /* 0x148 - USB Interrupt Enable */
 110         u32     frindex;        /* 0x14C - USB Frame Index */
 111         u8      res4[0x4];
 112         u32     perlistbase;    /* 0x154 - Periodic List Base
 113                                          - USB Device Address */
 114         u32     ep_list_addr;   /* 0x158 - Next Asynchronous List
 115                                          - End Point Address */
 116         u8      res5[0x4];
 117         u32     burstsize;      /* 0x160 - Programmable Burst Size */
 118         u32     txfilltuning;   /* 0x164 - Host TT Transmit
 119                                            pre-buffer packet tuning */
 120         u8      res6[0x8];
 121         u32     ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
 122         u8      res7[0xc];
 123         u32     config_flag;    /* 0x180 - Configured Flag Register */
 124         u32     portsc;         /* 0x184 - Port status/control */
 125         u8      res8[0x20];
 126         u32     usbmode;        /* 0x1a8 - USB Device Mode */
 127         u32     epsetupstat;    /* 0x1ac - End Point Setup Status */
 128         u32     epprime;        /* 0x1b0 - End Point Init Status */
 129         u32     epflush;        /* 0x1b4 - End Point De-initlialize */
 130         u32     epstatus;       /* 0x1b8 - End Point Status */
 131         u32     epcomplete;     /* 0x1bc - End Point Complete */
 132         u32     epctrl0;        /* 0x1c0 - End Point Control 0 */
 133         u32     epctrl1;        /* 0x1c4 - End Point Control 1 */
 134         u32     epctrl2;        /* 0x1c8 - End Point Control 2 */
 135         u32     epctrl3;        /* 0x1cc - End Point Control 3 */
 136         u32     epctrl4;        /* 0x1d0 - End Point Control 4 */
 137         u32     epctrl5;        /* 0x1d4 - End Point Control 5 */
 138         u8      res9[0x228];
 139         u32     snoop1;         /* 0x400 - Snoop 1 */
 140         u32     snoop2;         /* 0x404 - Snoop 2 */
 141         u32     age_cnt_limit;  /* 0x408 - Age Count Threshold */
 142         u32     prictrl;        /* 0x40c - Priority Control */
 143         u32     sictrl;         /* 0x410 - System Interface Control */
 144         u8      res10[0xEC];
 145         u32     control;        /* 0x500 - Control */
 146         u8      res11[0xafc];
 147 };
 148
 149 #endif /* _EHCI_FSL_H */