]>
git.ipfire.org Git - people/ms/u-boot.git/blob - post/board/lwmon5/fpga.c
2 * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
4 * Developed for DENX Software Engineering GmbH
6 * SPDX-License-Identifier: GPL-2.0+
10 /* This test performs testing of FPGA SCRATCH register,
11 * gets FPGA version and run get_ram_size() on FPGA memory
18 DECLARE_GLOBAL_DATA_PTR
;
20 #define FPGA_SCRATCH_REG 0xC4000050
21 #define FPGA_VERSION_REG 0xC4000040
22 #define FPGA_RAM_START 0xC4200000
23 #define FPGA_RAM_END 0xC4203FFF
24 #define FPGA_STAT 0xC400000C
25 #define FPGA_BUFFER 0x00800000
26 #define FPGA_RAM_SIZE (FPGA_RAM_END - FPGA_RAM_START + 1)
28 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
30 const static unsigned long pattern
[] = {
45 const static unsigned long otherpattern
= 0x01234567;
47 static int one_scratch_test(uint value
)
52 out_be32((void *)FPGA_SCRATCH_REG
, value
);
53 /* read other location (protect against data lines capacity) */
54 ret
= in_be16((void *)FPGA_VERSION_REG
);
55 /* verify test pattern */
56 read_value
= in_be32((void *)FPGA_SCRATCH_REG
);
57 if (read_value
!= value
) {
58 post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
66 static int fpga_post_test1(ulong
*start
, ulong size
, ulong val
)
73 for (i
= 0; i
< size
/ sizeof(ulong
); i
++) {
79 for (i
= 0; i
< size
/ sizeof(ulong
); i
++) {
81 if (readback
!= val
) {
82 post_log("FPGA Memory error at %08x, "
83 "wrote %08x, read %08x !\n",
84 mem
+ i
, val
, readback
);
94 static int fpga_post_test2(ulong
*start
, ulong size
)
101 for (i
= 0; i
< size
/ sizeof(ulong
); i
++) {
102 mem
[i
] = 1 << (i
% 32);
107 for (i
= 0; i
< size
/ sizeof(ulong
); i
++) {
109 if (readback
!= 1 << (i
% 32)) {
110 post_log("FPGA Memory error at %08x, "
111 "wrote %08x, read %08x !\n",
112 mem
+ i
, 1 << (i
% 32), readback
);
123 static int fpga_post_test3(ulong
*start
, ulong size
)
130 for (i
= 0; i
< size
/ sizeof(ulong
); i
++) {
136 for (i
= 0; i
< size
/ sizeof(ulong
); i
++) {
139 post_log("FPGA Memory error at %08x, "
140 "wrote %08x, read %08x !\n",
141 mem
+ i
, i
, readback
);
152 static int fpga_post_test4(ulong
*start
, ulong size
)
159 for (i
= 0; i
< size
/ sizeof(ulong
); i
++) {
165 for (i
= 0; i
< size
/ sizeof(ulong
); i
++) {
167 if (readback
!= ~i
) {
168 post_log("FPGA Memory error at %08x, "
169 "wrote %08x, read %08x !\n",
170 mem
+ i
, ~i
, readback
);
181 /* FPGA Memory-pattern-test */
182 static int fpga_mem_test(void)
185 ulong
* start
= (ulong
*)FPGA_RAM_START
;
186 ulong size
= FPGA_RAM_SIZE
;
189 ret
= fpga_post_test1(start
, size
, 0x00000000);
192 ret
= fpga_post_test1(start
, size
, 0xffffffff);
195 ret
= fpga_post_test1(start
, size
, 0x55555555);
198 ret
= fpga_post_test1(start
, size
, 0xaaaaaaaa);
203 ret
= fpga_post_test2(start
, size
);
206 ret
= fpga_post_test3(start
, size
);
209 ret
= fpga_post_test4(start
, size
);
214 /* Verify FPGA addresslines */
215 static int fpga_post_addrline(ulong
*address
, ulong
*base
, ulong size
)
217 unsigned long *target
;
219 unsigned long readback
;
223 end
= (ulong
*)((ulong
)base
+ size
);
226 for (xor = sizeof(ulong
); xor > 0; xor <<= 1) {
227 target
= (ulong
*)((ulong
)address
^ xor);
228 if ((target
>= base
) && (target
< end
)) {
232 if (readback
== *address
) {
233 post_log("Memory (address line) error at %08x"
234 "XOR value %08x !\n",
235 address
, target
, xor);
245 /* Verify FPGA addresslines */
246 static int fpga_post_dataline(ulong
*address
)
248 unsigned long temp32
= 0;
252 for (i
= 0; i
< ARRAY_SIZE(pattern
); i
++) {
253 *address
= pattern
[i
];
255 * Put a different pattern on the data lines: otherwise they
256 * may float long enough to read back what we wrote.
258 *(address
+ 1) = otherpattern
;
261 if (temp32
!= pattern
[i
]){
262 post_log("Memory (date line) error at %08x, "
263 "wrote %08x, read %08x !\n",
264 address
, pattern
[i
], temp32
);
272 /* Verify FPGA, get version & memory size */
273 int fpga_post_test(int flags
)
281 old_value
= in_be32((void *)FPGA_SCRATCH_REG
);
283 if (one_scratch_test(0x55555555))
285 if (one_scratch_test(0xAAAAAAAA))
288 out_be32((void *)FPGA_SCRATCH_REG
, old_value
);
290 version
= in_be32((void *)FPGA_VERSION_REG
);
291 post_log("FPGA version %u.%u\n",
292 (version
>> 8) & 0xFF, version
& 0xFF);
294 /* Enable write to FPGA RAM */
295 out_be32((void *)FPGA_STAT
, in_be32((void *)FPGA_STAT
) | 0x1000);
298 read_value
= get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1
, FPGA_RAM_SIZE
);
299 post_log("FPGA RAM size %d bytes\n", read_value
);
302 /* copy fpga memory to DDR2 RAM*/
303 memcpy((void *)FPGA_BUFFER
,(void *)FPGA_RAM_START
, FPGA_RAM_SIZE
);
307 if (fpga_post_dataline((ulong
*)FPGA_RAM_START
)) {
313 /* Test addresslines */
314 if (fpga_post_addrline((ulong
*)FPGA_RAM_START
,
315 (ulong
*)FPGA_RAM_START
, FPGA_RAM_SIZE
)) {
320 if (fpga_post_addrline((ulong
*)FPGA_RAM_END
- sizeof(long),
321 (ulong
*)FPGA_RAM_START
, FPGA_RAM_SIZE
)) {
327 /* Memory Pattern Test */
328 if (fpga_mem_test()) {
335 memcpy((void *)FPGA_RAM_START
,(void *)FPGA_BUFFER
, FPGA_RAM_SIZE
);
339 /* Disable write to RAM */
340 out_be32((void *)FPGA_STAT
, in_be32((void *)FPGA_STAT
) & 0xEFFF);
344 #endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC3 */