post/cpu/mpc8xx/ether.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9
  10 /*
  11  * Ethernet test
  12  *
  13  * The Serial Communication Controllers (SCC) listed in ctlr_list array below
  14  * are tested in the loopback ethernet mode.
  15  * The controllers are configured accordingly and several packets
  16  * are transmitted. The configurable test parameters are:
  17  *   MIN_PACKET_LENGTH - minimum size of packet to transmit
  18  *   MAX_PACKET_LENGTH - maximum size of packet to transmit
  19  *   TEST_NUM - number of tests
  20  */
  21
  22 #include <post.h>
  23 #if CONFIG_POST & CONFIG_SYS_POST_ETHER
  24 #if defined(CONFIG_8xx)
  25 #include <commproc.h>
  26 #elif defined(CONFIG_MPC8260)
  27 #include <asm/cpm_8260.h>
  28 #else
  29 #error "Apparently a bad configuration, please fix."
  30 #endif
  31
  32 #include <command.h>
  33 #include <net.h>
  34 #include <serial.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define MIN_PACKET_LENGTH       64
  39 #define MAX_PACKET_LENGTH       256
  40 #define TEST_NUM                1
  41
  42 #define CTLR_SCC 0
  43
  44 extern void spi_init_f (void);
  45 extern void spi_init_r (void);
  46
  47 /* The list of controllers to test */
  48 #if defined(CONFIG_MPC823)
  49 static int ctlr_list[][2] = { {CTLR_SCC, 1} };
  50 #else
  51 static int ctlr_list[][2] = { };
  52 #endif
  53
  54 static struct {
  55         void (*init) (int index);
  56         void (*halt) (int index);
  57         int (*send) (int index, volatile void *packet, int length);
  58         int (*recv) (int index, void *packet, int length);
  59 } ctlr_proc[1];
  60
  61 static char *ctlr_name[1] = { "SCC" };
  62
  63 /* Ethernet Transmit and Receive Buffers */
  64 #define DBUF_LENGTH  1520
  65
  66 #define TX_BUF_CNT 2
  67
  68 #define TOUT_LOOP 100
  69
  70 static char txbuf[DBUF_LENGTH];
  71
  72 static uint rxIdx;              /* index of the current RX buffer */
  73 static uint txIdx;              /* index of the current TX buffer */
  74
  75 /*
  76   * SCC Ethernet Tx and Rx buffer descriptors allocated at the
  77   *  immr->udata_bd address on Dual-Port RAM
  78   * Provide for Double Buffering
  79   */
  80
  81 typedef volatile struct CommonBufferDescriptor {
  82         cbd_t rxbd[PKTBUFSRX];          /* Rx BD */
  83         cbd_t txbd[TX_BUF_CNT];         /* Tx BD */
  84 } RTXBD;
  85
  86 static RTXBD *rtx;
  87
  88   /*
  89    * SCC callbacks
  90    */
  91
  92 static void scc_init (int scc_index)
  93 {
  94         uchar ea[6];
  95
  96         static int proff[] = {
  97                                 PROFF_SCC1,
  98                                 PROFF_SCC2,
  99                                 PROFF_SCC3,
 100                                 PROFF_SCC4,
 101         };
 102         static unsigned int cpm_cr[] = {
 103                                 CPM_CR_CH_SCC1,
 104                                 CPM_CR_CH_SCC2,
 105                                 CPM_CR_CH_SCC3,
 106                                 CPM_CR_CH_SCC4,
 107         };
 108
 109         int i;
 110         scc_enet_t *pram_ptr;
 111
 112         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 113
 114         immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
 115                         ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 116
 117         pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
 118
 119         rxIdx = 0;
 120         txIdx = 0;
 121
 122         rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
 123
 124 #if 0
 125
 126 #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
 127         /* Configure port A pins for Txd and Rxd.
 128          */
 129         immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
 130         immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
 131         immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
 132 #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
 133         /* Configure port B pins for Txd and Rxd.
 134          */
 135         immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
 136         immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
 137         immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
 138 #else
 139 #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
 140 #endif
 141
 142 #if defined(PC_ENET_LBK)
 143         /* Configure port C pins to disable External Loopback
 144          */
 145         immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
 146         immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
 147         immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
 148         immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK;      /* Disable Loopback */
 149 #endif /* PC_ENET_LBK */
 150
 151         /* Configure port C pins to enable CLSN and RENA.
 152          */
 153         immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
 154         immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
 155         immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
 156
 157         /* Configure port A for TCLK and RCLK.
 158          */
 159         immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
 160         immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
 161
 162         /*
 163          * Configure Serial Interface clock routing -- see section 16.7.5.3
 164          * First, clear all SCC bits to zero, then set the ones we want.
 165          */
 166
 167         immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
 168         immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
 169 #else
 170         /*
 171          * SCC2 receive clock is BRG2
 172          * SCC2 transmit clock is BRG3
 173          */
 174         immr->im_cpm.cp_brgc2 = 0x0001000C;
 175         immr->im_cpm.cp_brgc3 = 0x0001000C;
 176
 177         immr->im_cpm.cp_sicr &= ~0x00003F00;
 178         immr->im_cpm.cp_sicr |=  0x00000a00;
 179 #endif /* 0 */
 180
 181
 182         /*
 183          * Initialize SDCR -- see section 16.9.23.7
 184          * SDMA configuration register
 185          */
 186         immr->im_siu_conf.sc_sdcr = 0x01;
 187
 188
 189         /*
 190          * Setup SCC Ethernet Parameter RAM
 191          */
 192
 193         pram_ptr->sen_genscc.scc_rfcr = 0x18;   /* Normal Operation and Mot byte ordering */
 194         pram_ptr->sen_genscc.scc_tfcr = 0x18;   /* Mot byte ordering, Normal access */
 195
 196         pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH;   /* max. ET package len 1520 */
 197
 198         pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]);        /* Set RXBD tbl start at Dual Port */
 199         pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]);        /* Set TXBD tbl start at Dual Port */
 200
 201         /*
 202          * Setup Receiver Buffer Descriptors (13.14.24.18)
 203          * Settings:
 204          *     Empty, Wrap
 205          */
 206
 207         for (i = 0; i < PKTBUFSRX; i++) {
 208                 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 209                 rtx->rxbd[i].cbd_datlen = 0;    /* Reset */
 210                 rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
 211         }
 212
 213         rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 214
 215         /*
 216          * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
 217          * Settings:
 218          *    Add PADs to Short FRAMES, Wrap, Last, Tx CRC
 219          */
 220
 221         for (i = 0; i < TX_BUF_CNT; i++) {
 222                 rtx->txbd[i].cbd_sc =
 223                                 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
 224                 rtx->txbd[i].cbd_datlen = 0;    /* Reset */
 225                 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
 226         }
 227
 228         rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
 229
 230         /*
 231          * Enter Command:  Initialize Rx Params for SCC
 232          */
 233
 234         do {                            /* Spin until ready to issue command    */
 235                 __asm__ ("eieio");
 236         } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
 237         /* Issue command */
 238         immr->im_cpm.cp_cpcr =
 239                         ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) |
 240                          CPM_CR_FLG);
 241         do {                            /* Spin until command processed     */
 242                 __asm__ ("eieio");
 243         } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
 244
 245         /*
 246          * Ethernet Specific Parameter RAM
 247          *     see table 13-16, pg. 660,
 248          *     pg. 681 (example with suggested settings)
 249          */
 250
 251         pram_ptr->sen_cpres = ~(0x0);   /* Preset CRC */
 252         pram_ptr->sen_cmask = 0xdebb20e3;       /* Constant Mask for CRC */
 253         pram_ptr->sen_crcec = 0x0;      /* Error Counter CRC (unused) */
 254         pram_ptr->sen_alec = 0x0;       /* Alignment Error Counter (unused) */
 255         pram_ptr->sen_disfc = 0x0;      /* Discard Frame Counter (unused) */
 256         pram_ptr->sen_pads = 0x8888;    /* Short Frame PAD Characters */
 257
 258         pram_ptr->sen_retlim = 15;      /* Retry Limit Threshold */
 259         pram_ptr->sen_maxflr = 1518;    /* MAX Frame Length Register */
 260         pram_ptr->sen_minflr = 64;      /* MIN Frame Length Register */
 261
 262         pram_ptr->sen_maxd1 = DBUF_LENGTH;      /* MAX DMA1 Length Register */
 263         pram_ptr->sen_maxd2 = DBUF_LENGTH;      /* MAX DMA2 Length Register */
 264
 265         pram_ptr->sen_gaddr1 = 0x0;     /* Group Address Filter 1 (unused) */
 266         pram_ptr->sen_gaddr2 = 0x0;     /* Group Address Filter 2 (unused) */
 267         pram_ptr->sen_gaddr3 = 0x0;     /* Group Address Filter 3 (unused) */
 268         pram_ptr->sen_gaddr4 = 0x0;     /* Group Address Filter 4 (unused) */
 269
 270         eth_getenv_enetaddr("ethaddr", ea);
 271         pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
 272         pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
 273         pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
 274
 275         pram_ptr->sen_pper = 0x0;       /* Persistence (unused) */
 276         pram_ptr->sen_iaddr1 = 0x0;     /* Individual Address Filter 1 (unused) */
 277         pram_ptr->sen_iaddr2 = 0x0;     /* Individual Address Filter 2 (unused) */
 278         pram_ptr->sen_iaddr3 = 0x0;     /* Individual Address Filter 3 (unused) */
 279         pram_ptr->sen_iaddr4 = 0x0;     /* Individual Address Filter 4 (unused) */
 280         pram_ptr->sen_taddrh = 0x0;     /* Tmp Address (MSB) (unused) */
 281         pram_ptr->sen_taddrm = 0x0;     /* Tmp Address (unused) */
 282         pram_ptr->sen_taddrl = 0x0;     /* Tmp Address (LSB) (unused) */
 283
 284         /*
 285          * Enter Command:  Initialize Tx Params for SCC
 286          */
 287
 288         do {                            /* Spin until ready to issue command    */
 289                 __asm__ ("eieio");
 290         } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
 291         /* Issue command */
 292         immr->im_cpm.cp_cpcr =
 293                         ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
 294                          CPM_CR_FLG);
 295         do {                            /* Spin until command processed     */
 296                 __asm__ ("eieio");
 297         } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
 298
 299         /*
 300          * Mask all Events in SCCM - we use polling mode
 301          */
 302         immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;
 303
 304         /*
 305          * Clear Events in SCCE -- Clear bits by writing 1's
 306          */
 307
 308         immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);
 309
 310
 311         /*
 312          * Initialize GSMR High 32-Bits
 313          * Settings:  Normal Mode
 314          */
 315
 316         immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;
 317
 318         /*
 319          * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
 320          * Settings:
 321          *     TCI = Invert
 322          *     TPL =  48 bits
 323          *     TPP = Repeating 10's
 324          *     LOOP = Loopback
 325          *     MODE = Ethernet
 326          */
 327
 328         immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
 329                                                     SCC_GSMRL_TPL_48 |
 330                                                     SCC_GSMRL_TPP_10 |
 331                                                     SCC_GSMRL_DIAG_LOOP |
 332                                                     SCC_GSMRL_MODE_ENET);
 333
 334         /*
 335          * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
 336          */
 337
 338         immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;
 339
 340         /*
 341          * Initialize the PSMR
 342          * Settings:
 343          *  CRC = 32-Bit CCITT
 344          *  NIB = Begin searching for SFD 22 bits after RENA
 345          *  LPB = Loopback Enable (Needed when FDE is set)
 346          */
 347         immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
 348                         SCC_PSMR_NIB22 | SCC_PSMR_LPB;
 349
 350         /*
 351          * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
 352          */
 353
 354         immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
 355                         (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 356 }
 357
 358 static void scc_halt (int scc_index)
 359 {
 360         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 361
 362         immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
 363                         ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 364         immr->im_ioport.iop_pcso  &=  ~(PC_ENET_CLSN | PC_ENET_RENA);
 365 }
 366
 367 static int scc_send (int index, volatile void *packet, int length)
 368 {
 369         int i, j = 0;
 370
 371         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
 372                 udelay (1);             /* will also trigger Wd if needed */
 373                 j++;
 374         }
 375         if (j >= TOUT_LOOP)
 376                 printf ("TX not ready\n");
 377         rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
 378         rtx->txbd[txIdx].cbd_datlen = length;
 379         rtx->txbd[txIdx].cbd_sc |=
 380                         (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
 381         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
 382                 udelay (1);             /* will also trigger Wd if needed */
 383                 j++;
 384         }
 385         if (j >= TOUT_LOOP)
 386                 printf ("TX timeout\n");
 387         i = (rtx->txbd[txIdx].
 388                  cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
 389         return i;
 390 }
 391
 392 static int scc_recv (int index, void *packet, int max_length)
 393 {
 394         int length = -1;
 395
 396         if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
 397                 goto Done;              /* nothing received */
 398         }
 399
 400         if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
 401                 length = rtx->rxbd[rxIdx].cbd_datlen - 4;
 402                 memcpy (packet,
 403                         (void *)(net_rx_packets[rxIdx]),
 404                         length < max_length ? length : max_length);
 405         }
 406
 407         /* Give the buffer back to the SCC. */
 408         rtx->rxbd[rxIdx].cbd_datlen = 0;
 409
 410         /* wrap around buffer index when necessary */
 411         if ((rxIdx + 1) >= PKTBUFSRX) {
 412                 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
 413                                 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
 414                 rxIdx = 0;
 415         } else {
 416                 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
 417                 rxIdx++;
 418         }
 419
 420 Done:
 421         return length;
 422 }
 423
 424   /*
 425    * Test routines
 426    */
 427
 428 static void packet_fill (char *packet, int length)
 429 {
 430         char c = (char) length;
 431         int i;
 432
 433         packet[0] = 0xFF;
 434         packet[1] = 0xFF;
 435         packet[2] = 0xFF;
 436         packet[3] = 0xFF;
 437         packet[4] = 0xFF;
 438         packet[5] = 0xFF;
 439
 440         for (i = 6; i < length; i++) {
 441                 packet[i] = c++;
 442         }
 443 }
 444
 445 static int packet_check (char *packet, int length)
 446 {
 447         char c = (char) length;
 448         int i;
 449
 450         for (i = 6; i < length; i++) {
 451                 if (packet[i] != c++)
 452                         return -1;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static int test_ctlr (int ctlr, int index)
 459 {
 460         int res = -1;
 461         char packet_send[MAX_PACKET_LENGTH];
 462         char packet_recv[MAX_PACKET_LENGTH];
 463         int length;
 464         int i;
 465         int l;
 466
 467         ctlr_proc[ctlr].init (index);
 468
 469         for (i = 0; i < TEST_NUM; i++) {
 470                 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
 471                         packet_fill (packet_send, l);
 472
 473                         ctlr_proc[ctlr].send (index, packet_send, l);
 474
 475                         length = ctlr_proc[ctlr].recv (index, packet_recv,
 476                                                         MAX_PACKET_LENGTH);
 477
 478                         if (length != l || packet_check (packet_recv, length) < 0) {
 479                                 goto Done;
 480                         }
 481                 }
 482         }
 483
 484         res = 0;
 485
 486 Done:
 487
 488         ctlr_proc[ctlr].halt (index);
 489
 490         /*
 491          * SCC2 Ethernet parameter RAM space overlaps
 492          * the SPI parameter RAM space. So we need to restore
 493          * the SPI configuration after SCC2 ethernet test.
 494          */
 495 #if defined(CONFIG_SPI)
 496         if (ctlr == CTLR_SCC && index == 1) {
 497                 spi_init_f ();
 498                 spi_init_r ();
 499         }
 500 #endif
 501
 502         if (res != 0) {
 503                 post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
 504                                   index + 1);
 505         }
 506
 507         return res;
 508 }
 509
 510 int ether_post_test (int flags)
 511 {
 512         int res = 0;
 513         int i;
 514
 515         ctlr_proc[CTLR_SCC].init = scc_init;
 516         ctlr_proc[CTLR_SCC].halt = scc_halt;
 517         ctlr_proc[CTLR_SCC].send = scc_send;
 518         ctlr_proc[CTLR_SCC].recv = scc_recv;
 519
 520         for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
 521                 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
 522                         res = -1;
 523                 }
 524         }
 525
 526 #if !defined(CONFIG_8xx_CONS_NONE)
 527         serial_reinit_all ();
 528 #endif
 529         return res;
 530 }
 531
 532 #endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */