post/cpu/mpc8xx/spr.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * SPR test
  28  *
  29  * The test checks the contents of Special Purpose Registers (SPR) listed
  30  * in the spr_test_list array below.
  31  * Each SPR value is read using mfspr instruction, some bits are masked
  32  * according to the table and the resulting value is compared to the
  33  * corresponding table value.
  34  */
  35
  36 #include <post.h>
  37
  38 #if CONFIG_POST & CFG_POST_SPR
  39
  40 static struct
  41 {
  42     int number;
  43     char * name;
  44     unsigned long mask;
  45     unsigned long value;
  46 } spr_test_list [] = {
  47         /* Standard Special-Purpose Registers */
  48
  49         {1,     "XER",          0x00000000,     0x00000000},
  50         {8,     "LR",           0x00000000,     0x00000000},
  51         {9,     "CTR",          0x00000000,     0x00000000},
  52         {18,    "DSISR",        0x00000000,     0x00000000},
  53         {19,    "DAR",          0x00000000,     0x00000000},
  54         {22,    "DEC",          0x00000000,     0x00000000},
  55         {26,    "SRR0",         0x00000000,     0x00000000},
  56         {27,    "SRR1",         0x00000000,     0x00000000},
  57         {272,   "SPRG0",        0x00000000,     0x00000000},
  58         {273,   "SPRG1",        0x00000000,     0x00000000},
  59         {274,   "SPRG2",        0x00000000,     0x00000000},
  60         {275,   "SPRG3",        0x00000000,     0x00000000},
  61         {287,   "PVR",          0xFFFF0000,     0x00500000},
  62
  63         /* Additional Special-Purpose Registers */
  64
  65         {144,   "CMPA",         0x00000000,     0x00000000},
  66         {145,   "CMPB",         0x00000000,     0x00000000},
  67         {146,   "CMPC",         0x00000000,     0x00000000},
  68         {147,   "CMPD",         0x00000000,     0x00000000},
  69         {148,   "ICR",          0xFFFFFFFF,     0x00000000},
  70         {149,   "DER",          0x00000000,     0x00000000},
  71         {150,   "COUNTA",       0xFFFFFFFF,     0x00000000},
  72         {151,   "COUNTB",       0xFFFFFFFF,     0x00000000},
  73         {152,   "CMPE",         0x00000000,     0x00000000},
  74         {153,   "CMPF",         0x00000000,     0x00000000},
  75         {154,   "CMPG",         0x00000000,     0x00000000},
  76         {155,   "CMPH",         0x00000000,     0x00000000},
  77         {156,   "LCTRL1",       0xFFFFFFFF,     0x00000000},
  78         {157,   "LCTRL2",       0xFFFFFFFF,     0x00000000},
  79         {158,   "ICTRL",        0xFFFFFFFF,     0x00000007},
  80         {159,   "BAR",          0x00000000,     0x00000000},
  81         {630,   "DPDR",         0x00000000,     0x00000000},
  82         {631,   "DPIR",         0x00000000,     0x00000000},
  83         {638,   "IMMR",         0xFFFF0000,     CFG_IMMR  },
  84         {560,   "IC_CST",       0x8E380000,     0x00000000},
  85         {561,   "IC_ADR",       0x00000000,     0x00000000},
  86         {562,   "IC_DAT",       0x00000000,     0x00000000},
  87         {568,   "DC_CST",       0xEF380000,     0x00000000},
  88         {569,   "DC_ADR",       0x00000000,     0x00000000},
  89         {570,   "DC_DAT",       0x00000000,     0x00000000},
  90         {784,   "MI_CTR",       0xFFFFFFFF,     0x00000000},
  91         {786,   "MI_AP",        0x00000000,     0x00000000},
  92         {787,   "MI_EPN",       0x00000000,     0x00000000},
  93         {789,   "MI_TWC",       0xFFFFFE02,     0x00000000},
  94         {790,   "MI_RPN",       0x00000000,     0x00000000},
  95         {816,   "MI_DBCAM",     0x00000000,     0x00000000},
  96         {817,   "MI_DBRAM0",    0x00000000,     0x00000000},
  97         {818,   "MI_DBRAM1",    0x00000000,     0x00000000},
  98         {792,   "MD_CTR",       0xFFFFFFFF,     0x04000000},
  99         {793,   "M_CASID",      0xFFFFFFF0,     0x00000000},
 100         {794,   "MD_AP",        0x00000000,     0x00000000},
 101         {795,   "MD_EPN",       0x00000000,     0x00000000},
 102         {796,   "M_TWB",        0x00000003,     0x00000000},
 103         {797,   "MD_TWC",       0x00000003,     0x00000000},
 104         {798,   "MD_RPN",       0x00000000,     0x00000000},
 105         {799,   "M_TW",         0x00000000,     0x00000000},
 106         {824,   "MD_DBCAM",     0x00000000,     0x00000000},
 107         {825,   "MD_DBRAM0",    0x00000000,     0x00000000},
 108         {826,   "MD_DBRAM1",    0x00000000,     0x00000000},
 109 };
 110
 111 static int spr_test_list_size =
 112                 sizeof (spr_test_list) / sizeof (spr_test_list[0]);
 113
 114 int spr_post_test (int flags)
 115 {
 116         int ret = 0;
 117         int ic = icache_status ();
 118         int i;
 119
 120         unsigned long code[] = {
 121                 0x7c6002a6,                             /* mfspr r3,SPR */
 122                 0x4e800020                              /* blr          */
 123         };
 124         unsigned long (*get_spr) (void) = (void *) code;
 125
 126         if (ic)
 127                 icache_disable ();
 128
 129         for (i = 0; i < spr_test_list_size; i++) {
 130                 int num = spr_test_list[i].number;
 131
 132                 /* mfspr r3,num */
 133                 code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
 134
 135                 if ((get_spr () & spr_test_list[i].mask) !=
 136                         (spr_test_list[i].value & spr_test_list[i].mask)) {
 137                         post_log ("The value of %s special register "
 138                                   "is incorrect: 0x%08X\n",
 139                                         spr_test_list[i].name, get_spr ());
 140                         ret = -1;
 141                 }
 142         }
 143
 144         if (ic)
 145                 icache_enable ();
 146
 147         return ret;
 148 }
 149 #endif /* CONFIG_POST & CFG_POST_SPR */