post/cpu/mpc8xx/uart.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9
  10 /*
  11  * UART test
  12  *
  13  * The Serial Management Controllers (SMC) and the Serial Communication
  14  * Controllers (SCC) listed in ctlr_list array below are tested in
  15  * the loopback UART mode.
  16  * The controllers are configured accordingly and several characters
  17  * are transmitted. The configurable test parameters are:
  18  *   MIN_PACKET_LENGTH - minimum size of packet to transmit
  19  *   MAX_PACKET_LENGTH - maximum size of packet to transmit
  20  *   TEST_NUM - number of tests
  21  */
  22
  23 #include <post.h>
  24 #if CONFIG_POST & CONFIG_SYS_POST_UART
  25 #if defined(CONFIG_8xx)
  26 #include <commproc.h>
  27 #elif defined(CONFIG_MPC8260)
  28 #include <asm/cpm_8260.h>
  29 #else
  30 #error "Apparently a bad configuration, please fix."
  31 #endif
  32 #include <command.h>
  33 #include <serial.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define CTLR_SMC 0
  38 #define CTLR_SCC 1
  39
  40 /* The list of controllers to test */
  41 #if defined(CONFIG_MPC823)
  42 static int ctlr_list[][2] =
  43                 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
  44 #else
  45 static int ctlr_list[][2] = { };
  46 #endif
  47
  48 static struct {
  49         void (*init) (int index);
  50         void (*halt) (int index);
  51         void (*putc) (int index, const char c);
  52         int (*getc) (int index);
  53 } ctlr_proc[2];
  54
  55 static char *ctlr_name[2] = { "SMC", "SCC" };
  56
  57 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
  58 static int proff_scc[] =
  59                 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
  60
  61 /*
  62  * SMC callbacks
  63  */
  64
  65 static void smc_init (int smc_index)
  66 {
  67         static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
  68
  69         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  70         volatile smc_t *sp;
  71         volatile smc_uart_t *up;
  72         volatile cbd_t *tbdf, *rbdf;
  73         volatile cpm8xx_t *cp = &(im->im_cpm);
  74         uint dpaddr;
  75
  76         /* initialize pointers to SMC */
  77
  78         sp = (smc_t *) & (cp->cp_smc[smc_index]);
  79         up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
  80
  81         /* Disable transmitter/receiver.
  82          */
  83         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
  84
  85         /* Enable SDMA.
  86          */
  87         im->im_siu_conf.sc_sdcr = 1;
  88
  89         /* clear error conditions */
  90 #ifdef  CONFIG_SYS_SDSR
  91         im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
  92 #else
  93         im->im_sdma.sdma_sdsr = 0x83;
  94 #endif
  95
  96         /* clear SDMA interrupt mask */
  97 #ifdef  CONFIG_SYS_SDMR
  98         im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
  99 #else
 100         im->im_sdma.sdma_sdmr = 0x00;
 101 #endif
 102
 103         /* Set the physical address of the host memory buffers in
 104          * the buffer descriptors.
 105          */
 106
 107 #ifdef CONFIG_SYS_ALLOC_DPRAM
 108         dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
 109 #else
 110         dpaddr = CPM_POST_BASE;
 111 #endif
 112
 113         /* Allocate space for two buffer descriptors in the DP ram.
 114          * For now, this address seems OK, but it may have to
 115          * change with newer versions of the firmware.
 116          * damm: allocating space after the two buffers for rx/tx data
 117          */
 118
 119         rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
 120         rbdf->cbd_bufaddr = (uint) (rbdf + 2);
 121         rbdf->cbd_sc = 0;
 122         tbdf = rbdf + 1;
 123         tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
 124         tbdf->cbd_sc = 0;
 125
 126         /* Set up the uart parameters in the parameter ram.
 127          */
 128         up->smc_rbase = dpaddr;
 129         up->smc_tbase = dpaddr + sizeof (cbd_t);
 130         up->smc_rfcr = SMC_EB;
 131         up->smc_tfcr = SMC_EB;
 132
 133         /* Set UART mode, 8 bit, no parity, one stop.
 134          * Enable receive and transmit.
 135          * Set local loopback mode.
 136          */
 137         sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
 138
 139         /* Mask all interrupts and remove anything pending.
 140          */
 141         sp->smc_smcm = 0;
 142         sp->smc_smce = 0xff;
 143
 144         /* Set up the baud rate generator.
 145          */
 146         cp->cp_simode = 0x00000000;
 147
 148         cp->cp_brgc1 =
 149                         (((gd->cpu_clk / 16 / gd->baudrate) -
 150                           1) << 1) | CPM_BRG_EN;
 151
 152         /* Make the first buffer the only buffer.
 153          */
 154         tbdf->cbd_sc |= BD_SC_WRAP;
 155         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 156
 157         /* Single character receive.
 158          */
 159         up->smc_mrblr = 1;
 160         up->smc_maxidl = 0;
 161
 162         /* Initialize Tx/Rx parameters.
 163          */
 164
 165         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 166                 ;
 167
 168         cp->cp_cpcr =
 169                         mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
 170
 171         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 172                 ;
 173
 174         /* Enable transmitter/receiver.
 175          */
 176         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 177 }
 178
 179 static void smc_halt(int smc_index)
 180 {
 181 }
 182
 183 static void smc_putc (int smc_index, const char c)
 184 {
 185         volatile cbd_t *tbdf;
 186         volatile char *buf;
 187         volatile smc_uart_t *up;
 188         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 189         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 190
 191         up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
 192
 193         tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
 194
 195         /* Wait for last character to go.
 196          */
 197
 198         buf = (char *) tbdf->cbd_bufaddr;
 199 #if 0
 200         __asm__ ("eieio");
 201         while (tbdf->cbd_sc & BD_SC_READY)
 202                 __asm__ ("eieio");
 203 #endif
 204
 205         *buf = c;
 206         tbdf->cbd_datlen = 1;
 207         tbdf->cbd_sc |= BD_SC_READY;
 208         __asm__ ("eieio");
 209 #if 1
 210         while (tbdf->cbd_sc & BD_SC_READY)
 211                 __asm__ ("eieio");
 212 #endif
 213 }
 214
 215 static int smc_getc (int smc_index)
 216 {
 217         volatile cbd_t *rbdf;
 218         volatile unsigned char *buf;
 219         volatile smc_uart_t *up;
 220         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 221         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 222         unsigned char c;
 223         int i;
 224
 225         up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
 226
 227         rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
 228
 229         /* Wait for character to show up.
 230          */
 231         buf = (unsigned char *) rbdf->cbd_bufaddr;
 232 #if 0
 233         while (rbdf->cbd_sc & BD_SC_EMPTY);
 234 #else
 235         for (i = 100; i > 0; i--) {
 236                 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
 237                         break;
 238                 udelay (1000);
 239         }
 240
 241         if (i == 0)
 242                 return -1;
 243 #endif
 244         c = *buf;
 245         rbdf->cbd_sc |= BD_SC_EMPTY;
 246
 247         return (c);
 248 }
 249
 250   /*
 251    * SCC callbacks
 252    */
 253
 254 static void scc_init (int scc_index)
 255 {
 256         static int cpm_cr_ch[] = {
 257                 CPM_CR_CH_SCC1,
 258                 CPM_CR_CH_SCC2,
 259                 CPM_CR_CH_SCC3,
 260                 CPM_CR_CH_SCC4,
 261         };
 262
 263         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 264         volatile scc_t *sp;
 265         volatile scc_uart_t *up;
 266         volatile cbd_t *tbdf, *rbdf;
 267         volatile cpm8xx_t *cp = &(im->im_cpm);
 268         uint dpaddr;
 269
 270         /* initialize pointers to SCC */
 271
 272         sp = (scc_t *) & (cp->cp_scc[scc_index]);
 273         up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
 274
 275         /* Disable transmitter/receiver.
 276          */
 277         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 278
 279
 280         /* Allocate space for two buffer descriptors in the DP ram.
 281          */
 282
 283 #ifdef CONFIG_SYS_ALLOC_DPRAM
 284         dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
 285 #else
 286         dpaddr = CPM_POST_BASE;
 287 #endif
 288
 289         /* Enable SDMA.
 290          */
 291         im->im_siu_conf.sc_sdcr = 0x0001;
 292
 293         /* Set the physical address of the host memory buffers in
 294          * the buffer descriptors.
 295          */
 296
 297         rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
 298         rbdf->cbd_bufaddr = (uint) (rbdf + 2);
 299         rbdf->cbd_sc = 0;
 300         tbdf = rbdf + 1;
 301         tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
 302         tbdf->cbd_sc = 0;
 303
 304         /* Set up the baud rate generator.
 305          */
 306         cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
 307         /* no |= needed, since BRG1 is 000 */
 308
 309         cp->cp_brgc1 =
 310                         (((gd->cpu_clk / 16 / gd->baudrate) -
 311                           1) << 1) | CPM_BRG_EN;
 312
 313         /* Set up the uart parameters in the parameter ram.
 314          */
 315         up->scc_genscc.scc_rbase = dpaddr;
 316         up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
 317
 318         /* Initialize Tx/Rx parameters.
 319          */
 320         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 321                 ;
 322         cp->cp_cpcr =
 323                         mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
 324
 325         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 326                 ;
 327
 328         up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
 329         up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
 330
 331         up->scc_genscc.scc_mrblr = 1;   /* Single character receive */
 332         up->scc_maxidl = 0;             /* disable max idle */
 333         up->scc_brkcr = 1;              /* send one break character on stop TX */
 334         up->scc_parec = 0;
 335         up->scc_frmec = 0;
 336         up->scc_nosec = 0;
 337         up->scc_brkec = 0;
 338         up->scc_uaddr1 = 0;
 339         up->scc_uaddr2 = 0;
 340         up->scc_toseq = 0;
 341         up->scc_char1 = 0x8000;
 342         up->scc_char2 = 0x8000;
 343         up->scc_char3 = 0x8000;
 344         up->scc_char4 = 0x8000;
 345         up->scc_char5 = 0x8000;
 346         up->scc_char6 = 0x8000;
 347         up->scc_char7 = 0x8000;
 348         up->scc_char8 = 0x8000;
 349         up->scc_rccm = 0xc0ff;
 350
 351         /* Set low latency / small fifo.
 352          */
 353         sp->scc_gsmrh = SCC_GSMRH_RFW;
 354
 355         /* Set UART mode
 356          */
 357         sp->scc_gsmrl &= ~0xF;
 358         sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
 359
 360         /* Set local loopback mode.
 361          */
 362         sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
 363         sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
 364
 365         /* Set clock divider 16 on Tx and Rx
 366          */
 367         sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
 368
 369         sp->scc_psmr |= SCU_PSMR_CL;
 370
 371         /* Mask all interrupts and remove anything pending.
 372          */
 373         sp->scc_sccm = 0;
 374         sp->scc_scce = 0xffff;
 375         sp->scc_dsr = 0x7e7e;
 376         sp->scc_psmr = 0x3000;
 377
 378         /* Make the first buffer the only buffer.
 379          */
 380         tbdf->cbd_sc |= BD_SC_WRAP;
 381         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 382
 383         /* Enable transmitter/receiver.
 384          */
 385         sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 386 }
 387
 388 static void scc_halt(int scc_index)
 389 {
 390         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 391         volatile cpm8xx_t *cp = &(im->im_cpm);
 392         volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
 393
 394         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
 395 }
 396
 397 static void scc_putc (int scc_index, const char c)
 398 {
 399         volatile cbd_t *tbdf;
 400         volatile char *buf;
 401         volatile scc_uart_t *up;
 402         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 403         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 404
 405         up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
 406
 407         tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
 408
 409         /* Wait for last character to go.
 410          */
 411
 412         buf = (char *) tbdf->cbd_bufaddr;
 413 #if 0
 414         __asm__ ("eieio");
 415         while (tbdf->cbd_sc & BD_SC_READY)
 416                 __asm__ ("eieio");
 417 #endif
 418
 419         *buf = c;
 420         tbdf->cbd_datlen = 1;
 421         tbdf->cbd_sc |= BD_SC_READY;
 422         __asm__ ("eieio");
 423 #if 1
 424         while (tbdf->cbd_sc & BD_SC_READY)
 425                 __asm__ ("eieio");
 426 #endif
 427 }
 428
 429 static int scc_getc (int scc_index)
 430 {
 431         volatile cbd_t *rbdf;
 432         volatile unsigned char *buf;
 433         volatile scc_uart_t *up;
 434         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 435         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 436         unsigned char c;
 437         int i;
 438
 439         up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
 440
 441         rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 442
 443         /* Wait for character to show up.
 444          */
 445         buf = (unsigned char *) rbdf->cbd_bufaddr;
 446 #if 0
 447         while (rbdf->cbd_sc & BD_SC_EMPTY);
 448 #else
 449         for (i = 100; i > 0; i--) {
 450                 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
 451                         break;
 452                 udelay (1000);
 453         }
 454
 455         if (i == 0)
 456                 return -1;
 457 #endif
 458         c = *buf;
 459         rbdf->cbd_sc |= BD_SC_EMPTY;
 460
 461         return (c);
 462 }
 463
 464   /*
 465    * Test routines
 466    */
 467
 468 static int test_ctlr (int ctlr, int index)
 469 {
 470         int res = -1;
 471         char test_str[] = "*** UART Test String ***\r\n";
 472         int i;
 473
 474         ctlr_proc[ctlr].init (index);
 475
 476         for (i = 0; i < sizeof (test_str) - 1; i++) {
 477                 ctlr_proc[ctlr].putc (index, test_str[i]);
 478                 if (ctlr_proc[ctlr].getc (index) != test_str[i])
 479                         goto Done;
 480         }
 481
 482         res = 0;
 483
 484 Done:
 485         ctlr_proc[ctlr].halt (index);
 486
 487         if (res != 0) {
 488                 post_log ("uart %s%d test failed\n",
 489                                 ctlr_name[ctlr], index + 1);
 490         }
 491
 492         return res;
 493 }
 494
 495 int uart_post_test (int flags)
 496 {
 497         int res = 0;
 498         int i;
 499
 500         ctlr_proc[CTLR_SMC].init = smc_init;
 501         ctlr_proc[CTLR_SMC].halt = smc_halt;
 502         ctlr_proc[CTLR_SMC].putc = smc_putc;
 503         ctlr_proc[CTLR_SMC].getc = smc_getc;
 504
 505         ctlr_proc[CTLR_SCC].init = scc_init;
 506         ctlr_proc[CTLR_SCC].halt = scc_halt;
 507         ctlr_proc[CTLR_SCC].putc = scc_putc;
 508         ctlr_proc[CTLR_SCC].getc = scc_getc;
 509
 510         for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
 511                 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
 512                         res = -1;
 513                 }
 514         }
 515
 516 #if !defined(CONFIG_8xx_CONS_NONE)
 517         serial_reinit_all ();
 518 #endif
 519
 520         return res;
 521 }
 522
 523 #endif /* CONFIG_POST & CONFIG_SYS_POST_UART */