post/cpu/mpc8xx/uart.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * UART test
  28  *
  29  * The Serial Management Controllers (SMC) and the Serial Communication
  30  * Controllers (SCC) listed in ctlr_list array below are tested in
  31  * the loopback UART mode.
  32  * The controllers are configured accordingly and several characters
  33  * are transmitted. The configurable test parameters are:
  34  *   MIN_PACKET_LENGTH - minimum size of packet to transmit
  35  *   MAX_PACKET_LENGTH - maximum size of packet to transmit
  36  *   TEST_NUM - number of tests
  37  */
  38
  39 #ifdef CONFIG_POST
  40
  41 #include <post.h>
  42 #if CONFIG_POST & CFG_POST_UART
  43 #if defined(CONFIG_8xx)
  44 #include <commproc.h>
  45 #elif defined(CONFIG_MPC8260)
  46 #include <asm/cpm_8260.h>
  47 #else
  48 #error "Apparently a bad configuration, please fix."
  49 #endif
  50 #include <command.h>
  51 #include <serial.h>
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define CTLR_SMC 0
  56 #define CTLR_SCC 1
  57
  58 /* The list of controllers to test */
  59 #if defined(CONFIG_MPC823)
  60 static int ctlr_list[][2] =
  61                 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
  62 #else
  63 static int ctlr_list[][2] = { };
  64 #endif
  65
  66 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
  67
  68 static struct {
  69         void (*init) (int index);
  70         void (*halt) (int index);
  71         void (*putc) (int index, const char c);
  72         int (*getc) (int index);
  73 } ctlr_proc[2];
  74
  75 static char *ctlr_name[2] = { "SMC", "SCC" };
  76
  77 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
  78 static int proff_scc[] =
  79                 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
  80
  81 /*
  82  * SMC callbacks
  83  */
  84
  85 static void smc_init (int smc_index)
  86 {
  87         static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
  88
  89         volatile immap_t *im = (immap_t *) CFG_IMMR;
  90         volatile smc_t *sp;
  91         volatile smc_uart_t *up;
  92         volatile cbd_t *tbdf, *rbdf;
  93         volatile cpm8xx_t *cp = &(im->im_cpm);
  94         uint dpaddr;
  95
  96         /* initialize pointers to SMC */
  97
  98         sp = (smc_t *) & (cp->cp_smc[smc_index]);
  99         up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
 100
 101         /* Disable transmitter/receiver.
 102          */
 103         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 104
 105         /* Enable SDMA.
 106          */
 107         im->im_siu_conf.sc_sdcr = 1;
 108
 109         /* clear error conditions */
 110 #ifdef  CFG_SDSR
 111         im->im_sdma.sdma_sdsr = CFG_SDSR;
 112 #else
 113         im->im_sdma.sdma_sdsr = 0x83;
 114 #endif
 115
 116         /* clear SDMA interrupt mask */
 117 #ifdef  CFG_SDMR
 118         im->im_sdma.sdma_sdmr = CFG_SDMR;
 119 #else
 120         im->im_sdma.sdma_sdmr = 0x00;
 121 #endif
 122
 123 #if defined(CONFIG_FADS)
 124         /* Enable RS232 */
 125         *((uint *) BCSR1) &=
 126                         ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
 127 #endif
 128
 129 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 130         /* Enable Monitor Port Transceiver */
 131         *((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
 132 #endif
 133
 134         /* Set the physical address of the host memory buffers in
 135          * the buffer descriptors.
 136          */
 137
 138 #ifdef CFG_ALLOC_DPRAM
 139         dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
 140 #else
 141         dpaddr = CPM_POST_BASE;
 142 #endif
 143
 144         /* Allocate space for two buffer descriptors in the DP ram.
 145          * For now, this address seems OK, but it may have to
 146          * change with newer versions of the firmware.
 147          * damm: allocating space after the two buffers for rx/tx data
 148          */
 149
 150         rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
 151         rbdf->cbd_bufaddr = (uint) (rbdf + 2);
 152         rbdf->cbd_sc = 0;
 153         tbdf = rbdf + 1;
 154         tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
 155         tbdf->cbd_sc = 0;
 156
 157         /* Set up the uart parameters in the parameter ram.
 158          */
 159         up->smc_rbase = dpaddr;
 160         up->smc_tbase = dpaddr + sizeof (cbd_t);
 161         up->smc_rfcr = SMC_EB;
 162         up->smc_tfcr = SMC_EB;
 163
 164 #if defined(CONFIG_MBX)
 165         board_serial_init ();
 166 #endif
 167
 168         /* Set UART mode, 8 bit, no parity, one stop.
 169          * Enable receive and transmit.
 170          * Set local loopback mode.
 171          */
 172         sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
 173
 174         /* Mask all interrupts and remove anything pending.
 175          */
 176         sp->smc_smcm = 0;
 177         sp->smc_smce = 0xff;
 178
 179         /* Set up the baud rate generator.
 180          */
 181         cp->cp_simode = 0x00000000;
 182
 183         cp->cp_brgc1 =
 184                         (((gd->cpu_clk / 16 / gd->baudrate) -
 185                           1) << 1) | CPM_BRG_EN;
 186
 187         /* Make the first buffer the only buffer.
 188          */
 189         tbdf->cbd_sc |= BD_SC_WRAP;
 190         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 191
 192         /* Single character receive.
 193          */
 194         up->smc_mrblr = 1;
 195         up->smc_maxidl = 0;
 196
 197         /* Initialize Tx/Rx parameters.
 198          */
 199
 200         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 201                 ;
 202
 203         cp->cp_cpcr =
 204                         mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
 205
 206         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 207                 ;
 208
 209         /* Enable transmitter/receiver.
 210          */
 211         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 212 }
 213
 214 static void smc_halt(int smc_index)
 215 {
 216 }
 217
 218 static void smc_putc (int smc_index, const char c)
 219 {
 220         volatile cbd_t *tbdf;
 221         volatile char *buf;
 222         volatile smc_uart_t *up;
 223         volatile immap_t *im = (immap_t *) CFG_IMMR;
 224         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 225
 226         up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
 227
 228         tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
 229
 230         /* Wait for last character to go.
 231          */
 232
 233         buf = (char *) tbdf->cbd_bufaddr;
 234 #if 0
 235         __asm__ ("eieio");
 236         while (tbdf->cbd_sc & BD_SC_READY)
 237                 __asm__ ("eieio");
 238 #endif
 239
 240         *buf = c;
 241         tbdf->cbd_datlen = 1;
 242         tbdf->cbd_sc |= BD_SC_READY;
 243         __asm__ ("eieio");
 244 #if 1
 245         while (tbdf->cbd_sc & BD_SC_READY)
 246                 __asm__ ("eieio");
 247 #endif
 248 }
 249
 250 static int smc_getc (int smc_index)
 251 {
 252         volatile cbd_t *rbdf;
 253         volatile unsigned char *buf;
 254         volatile smc_uart_t *up;
 255         volatile immap_t *im = (immap_t *) CFG_IMMR;
 256         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 257         unsigned char c;
 258         int i;
 259
 260         up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
 261
 262         rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
 263
 264         /* Wait for character to show up.
 265          */
 266         buf = (unsigned char *) rbdf->cbd_bufaddr;
 267 #if 0
 268         while (rbdf->cbd_sc & BD_SC_EMPTY);
 269 #else
 270         for (i = 100; i > 0; i--) {
 271                 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
 272                         break;
 273                 udelay (1000);
 274         }
 275
 276         if (i == 0)
 277                 return -1;
 278 #endif
 279         c = *buf;
 280         rbdf->cbd_sc |= BD_SC_EMPTY;
 281
 282         return (c);
 283 }
 284
 285   /*
 286    * SCC callbacks
 287    */
 288
 289 static void scc_init (int scc_index)
 290 {
 291         static int cpm_cr_ch[] = {
 292                 CPM_CR_CH_SCC1,
 293                 CPM_CR_CH_SCC2,
 294                 CPM_CR_CH_SCC3,
 295                 CPM_CR_CH_SCC4,
 296         };
 297
 298         volatile immap_t *im = (immap_t *) CFG_IMMR;
 299         volatile scc_t *sp;
 300         volatile scc_uart_t *up;
 301         volatile cbd_t *tbdf, *rbdf;
 302         volatile cpm8xx_t *cp = &(im->im_cpm);
 303         uint dpaddr;
 304
 305         /* initialize pointers to SCC */
 306
 307         sp = (scc_t *) & (cp->cp_scc[scc_index]);
 308         up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
 309
 310         /* Disable transmitter/receiver.
 311          */
 312         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 313
 314
 315         /* Allocate space for two buffer descriptors in the DP ram.
 316          */
 317
 318 #ifdef CFG_ALLOC_DPRAM
 319         dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
 320 #else
 321         dpaddr = CPM_POST_BASE;
 322 #endif
 323
 324         /* Enable SDMA.
 325          */
 326         im->im_siu_conf.sc_sdcr = 0x0001;
 327
 328         /* Set the physical address of the host memory buffers in
 329          * the buffer descriptors.
 330          */
 331
 332         rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
 333         rbdf->cbd_bufaddr = (uint) (rbdf + 2);
 334         rbdf->cbd_sc = 0;
 335         tbdf = rbdf + 1;
 336         tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
 337         tbdf->cbd_sc = 0;
 338
 339         /* Set up the baud rate generator.
 340          */
 341         cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
 342         /* no |= needed, since BRG1 is 000 */
 343
 344         cp->cp_brgc1 =
 345                         (((gd->cpu_clk / 16 / gd->baudrate) -
 346                           1) << 1) | CPM_BRG_EN;
 347
 348         /* Set up the uart parameters in the parameter ram.
 349          */
 350         up->scc_genscc.scc_rbase = dpaddr;
 351         up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
 352
 353         /* Initialize Tx/Rx parameters.
 354          */
 355         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 356                 ;
 357         cp->cp_cpcr =
 358                         mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
 359
 360         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 361                 ;
 362
 363         up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
 364         up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
 365
 366         up->scc_genscc.scc_mrblr = 1;   /* Single character receive */
 367         up->scc_maxidl = 0;             /* disable max idle */
 368         up->scc_brkcr = 1;              /* send one break character on stop TX */
 369         up->scc_parec = 0;
 370         up->scc_frmec = 0;
 371         up->scc_nosec = 0;
 372         up->scc_brkec = 0;
 373         up->scc_uaddr1 = 0;
 374         up->scc_uaddr2 = 0;
 375         up->scc_toseq = 0;
 376         up->scc_char1 = 0x8000;
 377         up->scc_char2 = 0x8000;
 378         up->scc_char3 = 0x8000;
 379         up->scc_char4 = 0x8000;
 380         up->scc_char5 = 0x8000;
 381         up->scc_char6 = 0x8000;
 382         up->scc_char7 = 0x8000;
 383         up->scc_char8 = 0x8000;
 384         up->scc_rccm = 0xc0ff;
 385
 386         /* Set low latency / small fifo.
 387          */
 388         sp->scc_gsmrh = SCC_GSMRH_RFW;
 389
 390         /* Set UART mode
 391          */
 392         sp->scc_gsmrl &= ~0xF;
 393         sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
 394
 395         /* Set local loopback mode.
 396          */
 397         sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
 398         sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
 399
 400         /* Set clock divider 16 on Tx and Rx
 401          */
 402         sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
 403
 404         sp->scc_psmr |= SCU_PSMR_CL;
 405
 406         /* Mask all interrupts and remove anything pending.
 407          */
 408         sp->scc_sccm = 0;
 409         sp->scc_scce = 0xffff;
 410         sp->scc_dsr = 0x7e7e;
 411         sp->scc_psmr = 0x3000;
 412
 413         /* Make the first buffer the only buffer.
 414          */
 415         tbdf->cbd_sc |= BD_SC_WRAP;
 416         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 417
 418         /* Enable transmitter/receiver.
 419          */
 420         sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 421 }
 422
 423 static void scc_halt(int scc_index)
 424 {
 425         volatile immap_t *im = (immap_t *) CFG_IMMR;
 426         volatile cpm8xx_t *cp = &(im->im_cpm);
 427         volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
 428
 429         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
 430 }
 431
 432 static void scc_putc (int scc_index, const char c)
 433 {
 434         volatile cbd_t *tbdf;
 435         volatile char *buf;
 436         volatile scc_uart_t *up;
 437         volatile immap_t *im = (immap_t *) CFG_IMMR;
 438         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 439
 440         up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
 441
 442         tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
 443
 444         /* Wait for last character to go.
 445          */
 446
 447         buf = (char *) tbdf->cbd_bufaddr;
 448 #if 0
 449         __asm__ ("eieio");
 450         while (tbdf->cbd_sc & BD_SC_READY)
 451                 __asm__ ("eieio");
 452 #endif
 453
 454         *buf = c;
 455         tbdf->cbd_datlen = 1;
 456         tbdf->cbd_sc |= BD_SC_READY;
 457         __asm__ ("eieio");
 458 #if 1
 459         while (tbdf->cbd_sc & BD_SC_READY)
 460                 __asm__ ("eieio");
 461 #endif
 462 }
 463
 464 static int scc_getc (int scc_index)
 465 {
 466         volatile cbd_t *rbdf;
 467         volatile unsigned char *buf;
 468         volatile scc_uart_t *up;
 469         volatile immap_t *im = (immap_t *) CFG_IMMR;
 470         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 471         unsigned char c;
 472         int i;
 473
 474         up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
 475
 476         rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 477
 478         /* Wait for character to show up.
 479          */
 480         buf = (unsigned char *) rbdf->cbd_bufaddr;
 481 #if 0
 482         while (rbdf->cbd_sc & BD_SC_EMPTY);
 483 #else
 484         for (i = 100; i > 0; i--) {
 485                 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
 486                         break;
 487                 udelay (1000);
 488         }
 489
 490         if (i == 0)
 491                 return -1;
 492 #endif
 493         c = *buf;
 494         rbdf->cbd_sc |= BD_SC_EMPTY;
 495
 496         return (c);
 497 }
 498
 499   /*
 500    * Test routines
 501    */
 502
 503 static int test_ctlr (int ctlr, int index)
 504 {
 505         int res = -1;
 506         char test_str[] = "*** UART Test String ***\r\n";
 507         int i;
 508
 509         ctlr_proc[ctlr].init (index);
 510
 511         for (i = 0; i < sizeof (test_str) - 1; i++) {
 512                 ctlr_proc[ctlr].putc (index, test_str[i]);
 513                 if (ctlr_proc[ctlr].getc (index) != test_str[i])
 514                         goto Done;
 515         }
 516
 517         res = 0;
 518
 519 Done:
 520         ctlr_proc[ctlr].halt (index);
 521
 522         if (res != 0) {
 523                 post_log ("uart %s%d test failed\n",
 524                                 ctlr_name[ctlr], index + 1);
 525         }
 526
 527         return res;
 528 }
 529
 530 int uart_post_test (int flags)
 531 {
 532         int res = 0;
 533         int i;
 534
 535         ctlr_proc[CTLR_SMC].init = smc_init;
 536         ctlr_proc[CTLR_SMC].halt = smc_halt;
 537         ctlr_proc[CTLR_SMC].putc = smc_putc;
 538         ctlr_proc[CTLR_SMC].getc = smc_getc;
 539
 540         ctlr_proc[CTLR_SCC].init = scc_init;
 541         ctlr_proc[CTLR_SCC].halt = scc_halt;
 542         ctlr_proc[CTLR_SCC].putc = scc_putc;
 543         ctlr_proc[CTLR_SCC].getc = scc_getc;
 544
 545         for (i = 0; i < CTRL_LIST_SIZE; i++) {
 546                 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
 547                         res = -1;
 548                 }
 549         }
 550
 551 #if !defined(CONFIG_8xx_CONS_NONE)
 552         serial_reinit_all ();
 553 #endif
 554
 555         return res;
 556 }
 557
 558 #endif /* CONFIG_POST & CFG_POST_UART */
 559
 560 #endif /* CONFIG_POST */