post/cpu/ppc4xx/cache.c

   1 /*
   2  * (C) Copyright 2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Author: Igor Lisitsin <igor@emcraft.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 /* Cache test
  13  *
  14  * This test verifies the CPU data and instruction cache using
  15  * several test scenarios.
  16  */
  17
  18 #include <post.h>
  19
  20 #if CONFIG_POST & CONFIG_SYS_POST_CACHE
  21
  22 #include <asm/mmu.h>
  23 #include <watchdog.h>
  24
  25 #define CACHE_POST_SIZE 1024
  26
  27 int cache_post_test1 (int tlb, void *p, int size);
  28 int cache_post_test2 (int tlb, void *p, int size);
  29 int cache_post_test3 (int tlb, void *p, int size);
  30 int cache_post_test4 (int tlb, void *p, int size);
  31 int cache_post_test5 (int tlb, void *p, int size);
  32 int cache_post_test6 (int tlb, void *p, int size);
  33
  34 #ifdef CONFIG_440
  35 static unsigned char testarea[CACHE_POST_SIZE]
  36 __attribute__((__aligned__(CACHE_POST_SIZE)));
  37 #endif
  38
  39 int cache_post_test (int flags)
  40 {
  41         void *virt = (void *)CONFIG_SYS_POST_CACHE_ADDR;
  42         int ints;
  43         int res = 0;
  44         int tlb = -1;           /* index to the victim TLB entry */
  45
  46         /*
  47          * All 44x variants deal with cache management differently
  48          * because they have the address translation always enabled.
  49          * The 40x ppc's don't use address translation in U-Boot at all,
  50          * so we have to distinguish here between 40x and 44x.
  51          */
  52 #ifdef CONFIG_440
  53         int word0, i;
  54
  55         /*
  56          * Allocate a new TLB entry, since we are going to modify
  57          * the write-through and caching inhibited storage attributes.
  58          */
  59         program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
  60                     TLB_WORD2_I_ENABLE);
  61
  62         /* Find the TLB entry */
  63         for (i = 0;; i++) {
  64                 if (i >= PPC4XX_TLB_SIZE) {
  65                         printf ("Failed to program tlb entry\n");
  66                         return -1;
  67                 }
  68                 word0 = mftlb1(i);
  69                 if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
  70                         tlb = i;
  71                         break;
  72                 }
  73         }
  74 #endif
  75         ints = disable_interrupts ();
  76
  77         WATCHDOG_RESET ();
  78         if (res == 0)
  79                 res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
  80         WATCHDOG_RESET ();
  81         if (res == 0)
  82                 res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
  83         WATCHDOG_RESET ();
  84         if (res == 0)
  85                 res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
  86         WATCHDOG_RESET ();
  87         if (res == 0)
  88                 res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
  89         WATCHDOG_RESET ();
  90         if (res == 0)
  91                 res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
  92         WATCHDOG_RESET ();
  93         if (res == 0)
  94                 res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
  95
  96         if (ints)
  97                 enable_interrupts ();
  98
  99 #ifdef CONFIG_440
 100         remove_tlb((u32)virt, CACHE_POST_SIZE);
 101 #endif
 102
 103         return res;
 104 }
 105
 106 #endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */