post/cpu/ppc4xx/denali_ecc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Developed for DENX Software Engineering GmbH.
   4  *
   5  * Author: Pavel Kolesnikov <concord@emcraft.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /* define DEBUG for debugging output (obviously ;-)) */
  11 #if 0
  12 #define DEBUG
  13 #endif
  14
  15 #include <common.h>
  16 #include <watchdog.h>
  17
  18 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  19
  20 #include <post.h>
  21
  22 #if CONFIG_POST & CONFIG_SYS_POST_ECC
  23
  24 /*
  25  * MEMORY ECC test
  26  *
  27  * This test performs the checks ECC facility of memory.
  28  */
  29 #include <asm/processor.h>
  30 #include <asm/mmu.h>
  31 #include <asm/io.h>
  32 #include <asm/ppc440.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 const static uint8_t syndrome_codes[] = {
  37         0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
  38         0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
  39         0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
  40         0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
  41         0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
  42         0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
  43         0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
  44         0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
  45         0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
  46 };
  47
  48 #define ECC_START_ADDR          0x10
  49 #define ECC_STOP_ADDR           0x2000
  50 #define ECC_PATTERN             0x01010101
  51 #define ECC_PATTERN_CORR        0x11010101
  52 #define ECC_PATTERN_UNCORR      0x61010101
  53
  54 inline static void disable_ecc(void)
  55 {
  56         uint32_t value;
  57
  58         sync(); /* Wait for any pending memory accesses to complete. */
  59         mfsdram(DDR0_22, value);
  60         mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
  61                 | DDR0_22_CTRL_RAW_ECC_DISABLE);
  62 }
  63
  64 inline static void clear_and_enable_ecc(void)
  65 {
  66         uint32_t value;
  67
  68         sync(); /* Wait for any pending memory accesses to complete. */
  69         mfsdram(DDR0_00, value);
  70         mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
  71         mfsdram(DDR0_22, value);
  72         mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
  73                 | DDR0_22_CTRL_RAW_ECC_ENABLE);
  74 }
  75
  76 static uint32_t get_ecc_status(void)
  77 {
  78         uint32_t int_status;
  79 #if defined(DEBUG)
  80         uint8_t syndrome;
  81         uint32_t hdata, ldata, haddr, laddr;
  82         uint32_t value;
  83 #endif
  84
  85         mfsdram(DDR0_00, int_status);
  86         int_status &= DDR0_00_INT_STATUS_MASK;
  87
  88 #if defined(DEBUG)
  89         if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) {
  90                 mfsdram(DDR0_32, laddr);
  91                 mfsdram(DDR0_33, haddr);
  92                 haddr &= 0x00000001;
  93                 if (int_status & DDR0_00_INT_STATUS_BIT1)
  94                         debug("Multiple accesses");
  95                 else
  96                         debug("A single access");
  97
  98                 debug(" outside the defined physical memory space detected\n"
  99                       "        addr = 0x%01x%08x\n", haddr, laddr);
 100         }
 101         if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) {
 102                 unsigned int bit;
 103
 104                 mfsdram(DDR0_23, value);
 105                 syndrome = (value >> 16) & 0xff;
 106                 for (bit = 0; bit < sizeof(syndrome_codes); bit++)
 107                         if (syndrome_codes[bit] == syndrome)
 108                                 break;
 109
 110                 mfsdram(DDR0_38, laddr);
 111                 mfsdram(DDR0_39, haddr);
 112                 haddr &= 0x00000001;
 113                 mfsdram(DDR0_40, ldata);
 114                 mfsdram(DDR0_41, hdata);
 115                 if (int_status & DDR0_00_INT_STATUS_BIT3)
 116                         debug("Multiple correctable ECC events");
 117                 else
 118                         debug("Single correctable ECC event");
 119
 120                 debug(" detected\n        0x%01x%08x - 0x%08x%08x, bit - %d\n",
 121                       haddr, laddr, hdata, ldata, bit);
 122         }
 123         if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) {
 124                 mfsdram(DDR0_23, value);
 125                 syndrome = (value >> 8) & 0xff;
 126                 mfsdram(DDR0_34, laddr);
 127                 mfsdram(DDR0_35, haddr);
 128                 haddr &= 0x00000001;
 129                 mfsdram(DDR0_36, ldata);
 130                 mfsdram(DDR0_37, hdata);
 131                 if (int_status & DDR0_00_INT_STATUS_BIT5)
 132                         debug("Multiple uncorrectable ECC events");
 133                 else
 134                         debug("Single uncorrectable ECC event");
 135
 136                 debug(" detected\n        0x%01x%08x - 0x%08x%08x, "
 137                       "syndrome - 0x%02x\n",
 138                       haddr, laddr, hdata, ldata, syndrome);
 139         }
 140         if (int_status & DDR0_00_INT_STATUS_BIT6)
 141                 debug("DRAM initialization complete\n");
 142 #endif /* defined(DEBUG) */
 143
 144         return int_status;
 145 }
 146
 147 static int test_ecc(uint32_t ecc_addr)
 148 {
 149         uint32_t value;
 150         volatile uint32_t *const ecc_mem = (volatile uint32_t *)ecc_addr;
 151         int ret = 0;
 152
 153         WATCHDOG_RESET();
 154
 155         debug("Entering test_ecc(0x%08x)\n", ecc_addr);
 156         /* Set up correct ECC in memory */
 157         disable_ecc();
 158         clear_and_enable_ecc();
 159         out_be32(ecc_mem, ECC_PATTERN);
 160         out_be32(ecc_mem + 1, ECC_PATTERN);
 161         ppcDcbf((u32)ecc_mem);
 162
 163         /* Verify no ECC error reading back */
 164         value = in_be32(ecc_mem);
 165         disable_ecc();
 166         if (ECC_PATTERN != value) {
 167                 debug("Data read error (no-error case): "
 168                       "expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
 169                 ret = 1;
 170         }
 171         value = get_ecc_status();
 172         if (0x00000000 != value) {
 173                 /* Expected no ECC status reported */
 174                 debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
 175                       0x00000000, value);
 176                 ret = 1;
 177         }
 178
 179         /* Test for correctable error by creating a one-bit error */
 180         out_be32(ecc_mem, ECC_PATTERN_CORR);
 181         ppcDcbf((u32)ecc_mem);
 182         clear_and_enable_ecc();
 183         value = in_be32(ecc_mem);
 184         disable_ecc();
 185         /* Test that the corrected data was read */
 186         if (ECC_PATTERN != value) {
 187                 debug("Data read error (correctable-error case): "
 188                       "expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
 189                 ret = 1;
 190         }
 191         value = get_ecc_status();
 192         if ((DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT7) != value) {
 193                 /* Expected a single correctable error reported */
 194                 debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
 195                       DDR0_00_INT_STATUS_BIT2, value);
 196                 ret = 1;
 197         }
 198
 199         /* Test for uncorrectable error by creating a two-bit error */
 200         out_be32(ecc_mem, ECC_PATTERN_UNCORR);
 201         ppcDcbf((u32)ecc_mem);
 202         clear_and_enable_ecc();
 203         value = in_be32(ecc_mem);
 204         disable_ecc();
 205         /* Test that the corrected data was read */
 206         if (ECC_PATTERN_UNCORR != value) {
 207                 debug("Data read error (uncorrectable-error case): "
 208                       "expected 0x%08x, read 0x%08x\n", ECC_PATTERN_UNCORR,
 209                       value);
 210                 ret = 1;
 211         }
 212         value = get_ecc_status();
 213         if ((DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT7) != value) {
 214                 /* Expected a single uncorrectable error reported */
 215                 debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
 216                       DDR0_00_INT_STATUS_BIT4, value);
 217                 ret = 1;
 218         }
 219
 220         /* Remove error from SDRAM and enable ECC. */
 221         out_be32(ecc_mem, ECC_PATTERN);
 222         ppcDcbf((u32)ecc_mem);
 223         clear_and_enable_ecc();
 224
 225         return ret;
 226 }
 227
 228 int ecc_post_test(int flags)
 229 {
 230         int ret = 0;
 231         uint32_t value;
 232         uint32_t iaddr;
 233
 234         mfsdram(DDR0_22, value);
 235         if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) {
 236                 debug("SDRAM ECC not enabled, skipping ECC POST.\n");
 237                 return 0;
 238         }
 239
 240         /* Mask all interrupts. */
 241         mfsdram(DDR0_01, value);
 242         mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK)
 243                 | DDR0_01_INT_MASK_ALL_OFF);
 244
 245         for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) {
 246                 ret = test_ecc(iaddr);
 247                 if (ret)
 248                         break;
 249         }
 250         /*
 251          * Clear possible errors resulting from ECC testing.  (If not done, we
 252          * we could get an interrupt later on when exceptions are enabled.)
 253          */
 254         set_mcsr(get_mcsr());
 255         debug("ecc_post_test() returning %d\n", ret);
 256         return ret;
 257 }
 258 #endif /* CONFIG_POST & CONFIG_SYS_POST_ECC */
 259 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */