post/cpu/ppc4xx/ether.c

   1 /*
   2  * (C) Copyright 2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Author: Igor Lisitsin <igor@emcraft.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 /*
  13  * Ethernet test
  14  *
  15  * The Ethernet Media Access Controllers (EMAC) are tested in the
  16  * internal loopback mode.
  17  * The controllers are configured accordingly and several packets
  18  * are transmitted. The configurable test parameters are:
  19  *   MIN_PACKET_LENGTH - minimum size of packet to transmit
  20  *   MAX_PACKET_LENGTH - maximum size of packet to transmit
  21  *   CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
  22  *     is tested with a different frame length. Starting with
  23  *     MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
  24  *     Defaults to 10 and can be overridden in the board config header.
  25  */
  26
  27 #include <post.h>
  28
  29 #if CONFIG_POST & CONFIG_SYS_POST_ETHER
  30
  31 #include <asm/cache.h>
  32 #include <asm/io.h>
  33 #include <asm/processor.h>
  34 #include <asm/ppc4xx-mal.h>
  35 #include <asm/ppc4xx-emac.h>
  36 #include <malloc.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 /*
  41  * Get count of EMAC devices (doesn't have to be the max. possible number
  42  * supported by the cpu)
  43  *
  44  * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
  45  * EMAC count is possible. As it is needed for the Kilauea/Haleakala
  46  * 405EX/405EXr eval board, using the same binary.
  47  */
  48 #if defined(CONFIG_BOARD_EMAC_COUNT)
  49 #define LAST_EMAC_NUM   board_emac_count()
  50 #else /* CONFIG_BOARD_EMAC_COUNT */
  51 #if defined(CONFIG_HAS_ETH3)
  52 #define LAST_EMAC_NUM   4
  53 #elif defined(CONFIG_HAS_ETH2)
  54 #define LAST_EMAC_NUM   3
  55 #elif defined(CONFIG_HAS_ETH1)
  56 #define LAST_EMAC_NUM   2
  57 #else
  58 #define LAST_EMAC_NUM   1
  59 #endif
  60 #endif /* CONFIG_BOARD_EMAC_COUNT */
  61
  62 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  63 #define SDR0_MFR_ETH_CLK_SEL_V(n)       ((0x01<<27) / (n+1))
  64 #endif
  65
  66 #define MIN_PACKET_LENGTH       64
  67 #define MAX_PACKET_LENGTH       1514
  68 #ifndef CONFIG_SYS_POST_ETH_LOOPS
  69 #define CONFIG_SYS_POST_ETH_LOOPS       10
  70 #endif
  71 #define PACKET_INCR     ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
  72                          CONFIG_SYS_POST_ETH_LOOPS)
  73
  74 static volatile mal_desc_t tx __cacheline_aligned;
  75 static volatile mal_desc_t rx __cacheline_aligned;
  76 static char *tx_buf;
  77 static char *rx_buf;
  78
  79 int board_emac_count(void);
  80
  81 static void ether_post_init (int devnum, int hw_addr)
  82 {
  83         int i;
  84 #if defined(CONFIG_440GX) || \
  85     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  86     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  87         unsigned mode_reg;
  88         sys_info_t sysinfo;
  89 #endif
  90 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
  91         unsigned long mfr;
  92 #endif
  93
  94 #if defined(CONFIG_440GX) || \
  95     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  96     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  97         /* Need to get the OPB frequency so we can access the PHY */
  98         get_sys_info (&sysinfo);
  99 #endif
 100
 101 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 102         /* provide clocks for EMAC internal loopback  */
 103         mfsdr (SDR0_MFR, mfr);
 104         mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
 105         mtsdr (SDR0_MFR, mfr);
 106         sync ();
 107 #endif
 108         /* reset emac */
 109         out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
 110         sync ();
 111
 112         for (i = 0;; i++) {
 113                 if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
 114                         break;
 115                 if (i >= 1000) {
 116                         printf ("Timeout resetting EMAC\n");
 117                         break;
 118                 }
 119                 udelay (1000);
 120         }
 121 #if defined(CONFIG_440GX) || \
 122     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 123     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 124         /* Whack the M1 register */
 125         mode_reg = 0x0;
 126         if (sysinfo.freqOPB <= 50000000);
 127         else if (sysinfo.freqOPB <= 66666667)
 128                 mode_reg |= EMAC_MR1_OBCI_66;
 129         else if (sysinfo.freqOPB <= 83333333)
 130                 mode_reg |= EMAC_MR1_OBCI_83;
 131         else if (sysinfo.freqOPB <= 100000000)
 132                 mode_reg |= EMAC_MR1_OBCI_100;
 133         else
 134                 mode_reg |= EMAC_MR1_OBCI_GT100;
 135
 136         out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);
 137
 138 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
 139
 140         /* set the Mal configuration reg */
 141 #if defined(CONFIG_440GX) || \
 142     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 143     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 144         mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
 145                MAL_CR_PLBLT_DEFAULT | 0x00330000);
 146 #else
 147         mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
 148         /* Errata 1.12: MAL_1 -- Disable MAL bursting */
 149         if (get_pvr() == PVR_440GP_RB) {
 150                 mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
 151         }
 152 #endif
 153         /* setup buffer descriptors */
 154         tx.ctrl = MAL_TX_CTRL_WRAP;
 155         tx.data_len = 0;
 156         tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
 157
 158         rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
 159         rx.data_len = 0;
 160         rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
 161         flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
 162         flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
 163
 164         switch (devnum) {
 165         case 1:
 166                 /* setup MAL tx & rx channel pointers */
 167 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
 168                 mtdcr (MAL0_TXCTP2R, &tx);
 169 #else
 170                 mtdcr (MAL0_TXCTP1R, &tx);
 171 #endif
 172 #if defined(CONFIG_440)
 173                 mtdcr (MAL0_TXBADDR, 0x0);
 174                 mtdcr (MAL0_RXBADDR, 0x0);
 175 #endif
 176                 mtdcr (MAL0_RXCTP1R, &rx);
 177                 /* set RX buffer size */
 178                 mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16);
 179                 break;
 180         case 0:
 181         default:
 182                 /* setup MAL tx & rx channel pointers */
 183 #if defined(CONFIG_440)
 184                 mtdcr (MAL0_TXBADDR, 0x0);
 185                 mtdcr (MAL0_RXBADDR, 0x0);
 186 #endif
 187                 mtdcr (MAL0_TXCTP0R, &tx);
 188                 mtdcr (MAL0_RXCTP0R, &rx);
 189                 /* set RX buffer size */
 190                 mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16);
 191                 break;
 192         }
 193
 194         /* Enable MAL transmit and receive channels */
 195 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 196         mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2)));
 197 #else
 198         mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum));
 199 #endif
 200         mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum));
 201
 202         /* set internal loopback mode */
 203 #ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
 204         out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 |
 205                   EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
 206                   EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
 207                   in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
 208 #else
 209         out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE |
 210                   EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
 211                   EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
 212                   in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
 213 #endif
 214
 215         /* set transmit enable & receive enable */
 216         out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE);
 217
 218         /* enable broadcast address */
 219         out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);
 220
 221         /* set transmit request threshold register */
 222         out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000);   /* 256 byte threshold */
 223
 224         /* set receive  low/high water mark register */
 225 #if defined(CONFIG_440)
 226         /* 440s has a 64 byte burst length */
 227         out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
 228 #else
 229         /* 405s have a 16 byte burst length */
 230         out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
 231 #endif /* defined(CONFIG_440) */
 232         out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);
 233
 234         /* Set fifo limit entry in tx mode 0 */
 235         out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
 236         /* Frame gap set */
 237         out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
 238         sync ();
 239 }
 240
 241 static void ether_post_halt (int devnum, int hw_addr)
 242 {
 243         int i = 0;
 244 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 245         unsigned long mfr;
 246 #endif
 247
 248         /* 1st reset MAL channel */
 249         /* Note: writing a 0 to a channel has no effect */
 250 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 251         mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2));
 252 #else
 253         mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum);
 254 #endif
 255         mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum);
 256
 257         /* wait for reset */
 258         while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) {
 259                 if (i++ >= 1000)
 260                         break;
 261                 udelay (1000);
 262         }
 263         /* emac reset */
 264         out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
 265
 266 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 267         /* remove clocks for EMAC internal loopback  */
 268         mfsdr (SDR0_MFR, mfr);
 269         mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
 270         mtsdr (SDR0_MFR, mfr);
 271 #endif
 272 }
 273
 274 static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
 275 {
 276         int i = 0;
 277
 278         while (tx.ctrl & MAL_TX_CTRL_READY) {
 279                 if (i++ > 100) {
 280                         printf ("TX timeout\n");
 281                         return;
 282                 }
 283                 udelay (1000);
 284                 invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
 285         }
 286         tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
 287                 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
 288         tx.data_len = length;
 289         memcpy (tx.data_ptr, packet, length);
 290         flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
 291         flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
 292         sync ();
 293
 294         out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0);
 295         sync ();
 296 }
 297
 298 static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
 299 {
 300         int length;
 301         int i = 0;
 302
 303         while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
 304                 if (i++ > 100) {
 305                         printf ("RX timeout\n");
 306                         return 0;
 307                 }
 308                 udelay (1000);
 309                 invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
 310         }
 311         length = rx.data_len - 4;
 312         if (length <= max_length) {
 313                 invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
 314                 memcpy(packet, rx.data_ptr, length);
 315         }
 316         sync ();
 317
 318         rx.ctrl |= MAL_RX_CTRL_EMPTY;
 319         flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
 320         sync ();
 321
 322         return length;
 323 }
 324
 325   /*
 326    * Test routines
 327    */
 328
 329 static void packet_fill (char *packet, int length)
 330 {
 331         char c = (char) length;
 332         int i;
 333
 334         /* set up ethernet header */
 335         memset (packet, 0xff, 14);
 336
 337         for (i = 14; i < length; i++) {
 338                 packet[i] = c++;
 339         }
 340 }
 341
 342 static int packet_check (char *packet, int length)
 343 {
 344         char c = (char) length;
 345         int i;
 346
 347         for (i = 14; i < length; i++) {
 348                 if (packet[i] != c++)
 349                         return -1;
 350         }
 351
 352         return 0;
 353 }
 354
 355         char packet_send[MAX_PACKET_LENGTH];
 356         char packet_recv[MAX_PACKET_LENGTH];
 357 static int test_ctlr (int devnum, int hw_addr)
 358 {
 359         int res = -1;
 360         int length;
 361         int l;
 362
 363         ether_post_init (devnum, hw_addr);
 364
 365         for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
 366              l -= PACKET_INCR) {
 367                 packet_fill (packet_send, l);
 368
 369                 ether_post_send (devnum, hw_addr, packet_send, l);
 370
 371                 length = ether_post_recv (devnum, hw_addr, packet_recv,
 372                                           sizeof (packet_recv));
 373
 374                 if (length != l || packet_check (packet_recv, length) < 0) {
 375                         goto Done;
 376                 }
 377         }
 378
 379         res = 0;
 380
 381 Done:
 382
 383         ether_post_halt (devnum, hw_addr);
 384
 385         if (res != 0) {
 386                 post_log ("EMAC%d test failed\n", devnum);
 387         }
 388
 389         return res;
 390 }
 391
 392 int ether_post_test (int flags)
 393 {
 394         int res = 0;
 395         int i;
 396
 397         /* Allocate tx & rx packet buffers */
 398         tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
 399         rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
 400
 401         if (!tx_buf || !rx_buf) {
 402                 printf ("Failed to allocate packet buffers\n");
 403                 res = -1;
 404                 goto out_free;
 405         }
 406
 407         for (i = 0; i < LAST_EMAC_NUM; i++) {
 408                 if (test_ctlr (i, i*0x100))
 409                         res = -1;
 410         }
 411
 412 out_free:
 413         free (tx_buf);
 414         free (rx_buf);
 415
 416         return res;
 417 }
 418
 419 #endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */