post/cpu/ppc4xx/ether.c

   1 /*
   2  * (C) Copyright 2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Author: Igor Lisitsin <igor@emcraft.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27
  28 /*
  29  * Ethernet test
  30  *
  31  * The Ethernet Media Access Controllers (EMAC) are tested in the
  32  * internal loopback mode.
  33  * The controllers are configured accordingly and several packets
  34  * are transmitted. The configurable test parameters are:
  35  *   MIN_PACKET_LENGTH - minimum size of packet to transmit
  36  *   MAX_PACKET_LENGTH - maximum size of packet to transmit
  37  *   TEST_NUM - number of tests
  38  */
  39
  40 #ifdef CONFIG_POST
  41
  42 #include <post.h>
  43
  44 #if CONFIG_POST & CFG_POST_ETHER
  45
  46 #include <asm/cache.h>
  47 #include <asm/io.h>
  48 #include <asm/processor.h>
  49 #include <405_mal.h>
  50 #include <ppc4xx_enet.h>
  51 #include <malloc.h>
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  56 #define SDR0_MFR_ETH_CLK_SEL_V(n)       ((0x01<<27) / (n+1))
  57 #endif
  58
  59 #define MIN_PACKET_LENGTH       64
  60 #define MAX_PACKET_LENGTH       256
  61 #define TEST_NUM                1
  62
  63 static volatile mal_desc_t tx __cacheline_aligned;
  64 static volatile mal_desc_t rx __cacheline_aligned;
  65 static char *tx_buf;
  66 static char *rx_buf;
  67
  68 static void ether_post_init (int devnum, int hw_addr)
  69 {
  70         int i;
  71         unsigned mode_reg;
  72 #if defined(CONFIG_440GX) || \
  73     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  74     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  75         sys_info_t sysinfo;
  76 #endif
  77 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
  78         unsigned long mfr;
  79 #endif
  80
  81 #if defined(CONFIG_440GX) || \
  82     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  83     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  84         /* Need to get the OPB frequency so we can access the PHY */
  85         get_sys_info (&sysinfo);
  86 #endif
  87
  88 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  89         /* provide clocks for EMAC internal loopback  */
  90         mfsdr (sdr_mfr, mfr);
  91         mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
  92         mtsdr (sdr_mfr, mfr);
  93         sync ();
  94 #endif
  95         /* reset emac */
  96         out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
  97         sync ();
  98
  99         for (i = 0;; i++) {
 100                 if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
 101                         break;
 102                 if (i >= 1000) {
 103                         printf ("Timeout resetting EMAC\n");
 104                         break;
 105                 }
 106                 udelay (1000);
 107         }
 108 #if defined(CONFIG_440GX) || \
 109     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 110     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 111         /* Whack the M1 register */
 112         mode_reg = 0x0;
 113         if (sysinfo.freqOPB <= 50000000);
 114         else if (sysinfo.freqOPB <= 66666667)
 115                 mode_reg |= EMAC_M1_OBCI_66;
 116         else if (sysinfo.freqOPB <= 83333333)
 117                 mode_reg |= EMAC_M1_OBCI_83;
 118         else if (sysinfo.freqOPB <= 100000000)
 119                 mode_reg |= EMAC_M1_OBCI_100;
 120         else
 121                 mode_reg |= EMAC_M1_OBCI_GT100;
 122
 123         out32 (EMAC_M1 + hw_addr, mode_reg);
 124
 125 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
 126
 127         /* set the Mal configuration reg */
 128 #if defined(CONFIG_440GX) || \
 129     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 130     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 131         mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
 132                MAL_CR_PLBLT_DEFAULT | 0x00330000);
 133 #else
 134         mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
 135         /* Errata 1.12: MAL_1 -- Disable MAL bursting */
 136         if (get_pvr() == PVR_440GP_RB) {
 137                 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
 138         }
 139 #endif
 140         /* setup buffer descriptors */
 141         tx.ctrl = MAL_TX_CTRL_WRAP;
 142         tx.data_len = 0;
 143         tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
 144
 145         rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
 146         rx.data_len = 0;
 147         rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
 148
 149         switch (devnum) {
 150         case 1:
 151                 /* setup MAL tx & rx channel pointers */
 152 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
 153                 mtdcr (maltxctp2r, &tx);
 154 #else
 155                 mtdcr (maltxctp1r, &tx);
 156 #endif
 157 #if defined(CONFIG_440)
 158                 mtdcr (maltxbattr, 0x0);
 159                 mtdcr (malrxbattr, 0x0);
 160 #endif
 161                 mtdcr (malrxctp1r, &rx);
 162                 /* set RX buffer size */
 163                 mtdcr (malrcbs1, PKTSIZE_ALIGN / 16);
 164                 break;
 165         case 0:
 166         default:
 167                 /* setup MAL tx & rx channel pointers */
 168 #if defined(CONFIG_440)
 169                 mtdcr (maltxbattr, 0x0);
 170                 mtdcr (malrxbattr, 0x0);
 171 #endif
 172                 mtdcr (maltxctp0r, &tx);
 173                 mtdcr (malrxctp0r, &rx);
 174                 /* set RX buffer size */
 175                 mtdcr (malrcbs0, PKTSIZE_ALIGN / 16);
 176                 break;
 177         }
 178
 179         /* Enable MAL transmit and receive channels */
 180 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 181         mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2)));
 182 #else
 183         mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum));
 184 #endif
 185         mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
 186
 187         /* set internal loopback mode */
 188         out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
 189                EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
 190                EMAC_M1_MF_100MBPS | EMAC_M1_IST |
 191                in32 (EMAC_M1));
 192
 193         /* set transmit enable & receive enable */
 194         out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
 195
 196         /* enable broadcast address */
 197         out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
 198
 199         /* set transmit request threshold register */
 200         out32 (EMAC_TRTR + hw_addr, 0x18000000);        /* 256 byte threshold */
 201
 202         /* set receive  low/high water mark register */
 203 #if defined(CONFIG_440)
 204         /* 440s has a 64 byte burst length */
 205         out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
 206 #else
 207         /* 405s have a 16 byte burst length */
 208         out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
 209 #endif /* defined(CONFIG_440) */
 210         out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
 211
 212         /* Set fifo limit entry in tx mode 0 */
 213         out32 (EMAC_TXM0 + hw_addr, 0x00000003);
 214         /* Frame gap set */
 215         out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
 216         sync ();
 217 }
 218
 219 static void ether_post_halt (int devnum, int hw_addr)
 220 {
 221         int i = 0;
 222 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 223         unsigned long mfr;
 224 #endif
 225
 226         /* 1st reset MAL channel */
 227         /* Note: writing a 0 to a channel has no effect */
 228 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 229         mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2));
 230 #else
 231         mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum);
 232 #endif
 233         mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum);
 234
 235         /* wait for reset */
 236         while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) {
 237                 if (i++ >= 1000)
 238                         break;
 239                 udelay (1000);
 240         }
 241         /* emac reset */
 242         out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
 243
 244 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 245         /* remove clocks for EMAC internal loopback  */
 246         mfsdr (sdr_mfr, mfr);
 247         mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
 248         mtsdr (sdr_mfr, mfr);
 249 #endif
 250 }
 251
 252 static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
 253 {
 254         int i = 0;
 255
 256         while (tx.ctrl & MAL_TX_CTRL_READY) {
 257                 if (i++ > 100) {
 258                         printf ("TX timeout\n");
 259                         return;
 260                 }
 261                 udelay (1000);
 262         }
 263         tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
 264                 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
 265         tx.data_len = length;
 266         memcpy (tx.data_ptr, packet, length);
 267         sync ();
 268
 269         out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
 270         sync ();
 271 }
 272
 273 static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
 274 {
 275         int length;
 276         int i = 0;
 277
 278         while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
 279                 if (i++ > 100) {
 280                         printf ("RX timeout\n");
 281                         return 0;
 282                 }
 283                 udelay (1000);
 284         }
 285         length = rx.data_len - 4;
 286         if (length <= max_length)
 287                 memcpy(packet, rx.data_ptr, length);
 288         sync ();
 289
 290         rx.ctrl |= MAL_RX_CTRL_EMPTY;
 291         sync ();
 292
 293         return length;
 294 }
 295
 296   /*
 297    * Test routines
 298    */
 299
 300 static void packet_fill (char *packet, int length)
 301 {
 302         char c = (char) length;
 303         int i;
 304
 305         /* set up ethernet header */
 306         memset (packet, 0xff, 14);
 307
 308         for (i = 14; i < length; i++) {
 309                 packet[i] = c++;
 310         }
 311 }
 312
 313 static int packet_check (char *packet, int length)
 314 {
 315         char c = (char) length;
 316         int i;
 317
 318         for (i = 14; i < length; i++) {
 319                 if (packet[i] != c++)
 320                         return -1;
 321         }
 322
 323         return 0;
 324 }
 325
 326 static int test_ctlr (int devnum, int hw_addr)
 327 {
 328         int res = -1;
 329         char packet_send[MAX_PACKET_LENGTH];
 330         char packet_recv[MAX_PACKET_LENGTH];
 331         int length;
 332         int i;
 333         int l;
 334
 335         ether_post_init (devnum, hw_addr);
 336
 337         for (i = 0; i < TEST_NUM; i++) {
 338                 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
 339                         packet_fill (packet_send, l);
 340
 341                         ether_post_send (devnum, hw_addr, packet_send, l);
 342
 343                         length = ether_post_recv (devnum, hw_addr, packet_recv,
 344                                                   sizeof (packet_recv));
 345
 346                         if (length != l || packet_check (packet_recv, length) < 0) {
 347                                 goto Done;
 348                         }
 349                 }
 350         }
 351
 352         res = 0;
 353
 354 Done:
 355
 356         ether_post_halt (devnum, hw_addr);
 357
 358         if (res != 0) {
 359                 post_log ("EMAC%d test failed\n", devnum);
 360         }
 361
 362         return res;
 363 }
 364
 365 int ether_post_test (int flags)
 366 {
 367         int res = 0;
 368
 369         /* Allocate tx & rx packet buffers */
 370         tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
 371         rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
 372
 373         if (!tx_buf || !rx_buf) {
 374                 printf ("Failed to allocate packet buffers\n");
 375                 res = -1;
 376                 goto out_free;
 377         }
 378
 379         /* EMAC0 */
 380         if (test_ctlr (0, 0))
 381                 res = -1;
 382
 383         /* EMAC1 */
 384         if (test_ctlr (1, 0x100))
 385                 res = -1;
 386
 387 out_free:
 388         free (tx_buf);
 389         free (rx_buf);
 390
 391         return res;
 392 }
 393
 394 #endif /* CONFIG_POST & CFG_POST_ETHER */
 395 #endif /* CONFIG_POST */