post/cpu/ppc4xx/ether.c

   1 /*
   2  * (C) Copyright 2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Author: Igor Lisitsin <igor@emcraft.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27
  28 /*
  29  * Ethernet test
  30  *
  31  * The Ethernet Media Access Controllers (EMAC) are tested in the
  32  * internal loopback mode.
  33  * The controllers are configured accordingly and several packets
  34  * are transmitted. The configurable test parameters are:
  35  *   MIN_PACKET_LENGTH - minimum size of packet to transmit
  36  *   MAX_PACKET_LENGTH - maximum size of packet to transmit
  37  *   TEST_NUM - number of tests
  38  */
  39
  40 #ifdef CONFIG_POST
  41
  42 #include <post.h>
  43
  44 #if CONFIG_POST & CFG_POST_ETHER
  45
  46 #include <asm/cache.h>
  47 #include <asm/io.h>
  48 #include <asm/processor.h>
  49 #include <405_mal.h>
  50 #include <ppc4xx_enet.h>
  51 #include <malloc.h>
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 /*
  56  * Get count of EMAC devices (doesn't have to be the max. possible number
  57  * supported by the cpu)
  58  *
  59  * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
  60  * EMAC count is possible. As it is needed for the Kilauea/Haleakala
  61  * 405EX/405EXr eval board, using the same binary.
  62  */
  63 #if defined(CONFIG_BOARD_EMAC_COUNT)
  64 #define LAST_EMAC_NUM   board_emac_count()
  65 #else /* CONFIG_BOARD_EMAC_COUNT */
  66 #if defined(CONFIG_HAS_ETH3)
  67 #define LAST_EMAC_NUM   4
  68 #elif defined(CONFIG_HAS_ETH2)
  69 #define LAST_EMAC_NUM   3
  70 #elif defined(CONFIG_HAS_ETH1)
  71 #define LAST_EMAC_NUM   2
  72 #else
  73 #define LAST_EMAC_NUM   1
  74 #endif
  75 #endif /* CONFIG_BOARD_EMAC_COUNT */
  76
  77 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  78 #define SDR0_MFR_ETH_CLK_SEL_V(n)       ((0x01<<27) / (n+1))
  79 #endif
  80
  81 #define MIN_PACKET_LENGTH       64
  82 #define MAX_PACKET_LENGTH       256
  83 #define TEST_NUM                1
  84
  85 static volatile mal_desc_t tx __cacheline_aligned;
  86 static volatile mal_desc_t rx __cacheline_aligned;
  87 static char *tx_buf;
  88 static char *rx_buf;
  89
  90 int board_emac_count(void);
  91
  92 static void ether_post_init (int devnum, int hw_addr)
  93 {
  94         int i;
  95 #if defined(CONFIG_440GX) || \
  96     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  97     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  98         unsigned mode_reg;
  99         sys_info_t sysinfo;
 100 #endif
 101 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
 102         unsigned long mfr;
 103 #endif
 104
 105 #if defined(CONFIG_440GX) || \
 106     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 107     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 108         /* Need to get the OPB frequency so we can access the PHY */
 109         get_sys_info (&sysinfo);
 110 #endif
 111
 112 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 113         /* provide clocks for EMAC internal loopback  */
 114         mfsdr (sdr_mfr, mfr);
 115         mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
 116         mtsdr (sdr_mfr, mfr);
 117         sync ();
 118 #endif
 119         /* reset emac */
 120         out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
 121         sync ();
 122
 123         for (i = 0;; i++) {
 124                 if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
 125                         break;
 126                 if (i >= 1000) {
 127                         printf ("Timeout resetting EMAC\n");
 128                         break;
 129                 }
 130                 udelay (1000);
 131         }
 132 #if defined(CONFIG_440GX) || \
 133     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 134     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 135         /* Whack the M1 register */
 136         mode_reg = 0x0;
 137         if (sysinfo.freqOPB <= 50000000);
 138         else if (sysinfo.freqOPB <= 66666667)
 139                 mode_reg |= EMAC_M1_OBCI_66;
 140         else if (sysinfo.freqOPB <= 83333333)
 141                 mode_reg |= EMAC_M1_OBCI_83;
 142         else if (sysinfo.freqOPB <= 100000000)
 143                 mode_reg |= EMAC_M1_OBCI_100;
 144         else
 145                 mode_reg |= EMAC_M1_OBCI_GT100;
 146
 147         out32 (EMAC_M1 + hw_addr, mode_reg);
 148
 149 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
 150
 151         /* set the Mal configuration reg */
 152 #if defined(CONFIG_440GX) || \
 153     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 154     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 155         mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
 156                MAL_CR_PLBLT_DEFAULT | 0x00330000);
 157 #else
 158         mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
 159         /* Errata 1.12: MAL_1 -- Disable MAL bursting */
 160         if (get_pvr() == PVR_440GP_RB) {
 161                 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
 162         }
 163 #endif
 164         /* setup buffer descriptors */
 165         tx.ctrl = MAL_TX_CTRL_WRAP;
 166         tx.data_len = 0;
 167         tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
 168
 169         rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
 170         rx.data_len = 0;
 171         rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
 172
 173         switch (devnum) {
 174         case 1:
 175                 /* setup MAL tx & rx channel pointers */
 176 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
 177                 mtdcr (maltxctp2r, &tx);
 178 #else
 179                 mtdcr (maltxctp1r, &tx);
 180 #endif
 181 #if defined(CONFIG_440)
 182                 mtdcr (maltxbattr, 0x0);
 183                 mtdcr (malrxbattr, 0x0);
 184 #endif
 185                 mtdcr (malrxctp1r, &rx);
 186                 /* set RX buffer size */
 187                 mtdcr (malrcbs1, PKTSIZE_ALIGN / 16);
 188                 break;
 189         case 0:
 190         default:
 191                 /* setup MAL tx & rx channel pointers */
 192 #if defined(CONFIG_440)
 193                 mtdcr (maltxbattr, 0x0);
 194                 mtdcr (malrxbattr, 0x0);
 195 #endif
 196                 mtdcr (maltxctp0r, &tx);
 197                 mtdcr (malrxctp0r, &rx);
 198                 /* set RX buffer size */
 199                 mtdcr (malrcbs0, PKTSIZE_ALIGN / 16);
 200                 break;
 201         }
 202
 203         /* Enable MAL transmit and receive channels */
 204 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 205         mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2)));
 206 #else
 207         mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum));
 208 #endif
 209         mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
 210
 211         /* set internal loopback mode */
 212 #ifdef CFG_POST_ETHER_EXT_LOOPBACK
 213         out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
 214                EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
 215                EMAC_M1_MF_100MBPS | EMAC_M1_IST |
 216                in32 (EMAC_M1));
 217 #else
 218         out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
 219                EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
 220                EMAC_M1_MF_100MBPS | EMAC_M1_IST |
 221                in32 (EMAC_M1));
 222 #endif
 223
 224         /* set transmit enable & receive enable */
 225         out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
 226
 227         /* enable broadcast address */
 228         out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
 229
 230         /* set transmit request threshold register */
 231         out32 (EMAC_TRTR + hw_addr, 0x18000000);        /* 256 byte threshold */
 232
 233         /* set receive  low/high water mark register */
 234 #if defined(CONFIG_440)
 235         /* 440s has a 64 byte burst length */
 236         out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
 237 #else
 238         /* 405s have a 16 byte burst length */
 239         out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
 240 #endif /* defined(CONFIG_440) */
 241         out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
 242
 243         /* Set fifo limit entry in tx mode 0 */
 244         out32 (EMAC_TXM0 + hw_addr, 0x00000003);
 245         /* Frame gap set */
 246         out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
 247         sync ();
 248 }
 249
 250 static void ether_post_halt (int devnum, int hw_addr)
 251 {
 252         int i = 0;
 253 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 254         unsigned long mfr;
 255 #endif
 256
 257         /* 1st reset MAL channel */
 258         /* Note: writing a 0 to a channel has no effect */
 259 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 260         mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2));
 261 #else
 262         mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum);
 263 #endif
 264         mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum);
 265
 266         /* wait for reset */
 267         while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) {
 268                 if (i++ >= 1000)
 269                         break;
 270                 udelay (1000);
 271         }
 272         /* emac reset */
 273         out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
 274
 275 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 276         /* remove clocks for EMAC internal loopback  */
 277         mfsdr (sdr_mfr, mfr);
 278         mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
 279         mtsdr (sdr_mfr, mfr);
 280 #endif
 281 }
 282
 283 static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
 284 {
 285         int i = 0;
 286
 287         while (tx.ctrl & MAL_TX_CTRL_READY) {
 288                 if (i++ > 100) {
 289                         printf ("TX timeout\n");
 290                         return;
 291                 }
 292                 udelay (1000);
 293         }
 294         tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
 295                 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
 296         tx.data_len = length;
 297         memcpy (tx.data_ptr, packet, length);
 298         sync ();
 299
 300         out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
 301         sync ();
 302 }
 303
 304 static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
 305 {
 306         int length;
 307         int i = 0;
 308
 309         while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
 310                 if (i++ > 100) {
 311                         printf ("RX timeout\n");
 312                         return 0;
 313                 }
 314                 udelay (1000);
 315         }
 316         length = rx.data_len - 4;
 317         if (length <= max_length)
 318                 memcpy(packet, rx.data_ptr, length);
 319         sync ();
 320
 321         rx.ctrl |= MAL_RX_CTRL_EMPTY;
 322         sync ();
 323
 324         return length;
 325 }
 326
 327   /*
 328    * Test routines
 329    */
 330
 331 static void packet_fill (char *packet, int length)
 332 {
 333         char c = (char) length;
 334         int i;
 335
 336         /* set up ethernet header */
 337         memset (packet, 0xff, 14);
 338
 339         for (i = 14; i < length; i++) {
 340                 packet[i] = c++;
 341         }
 342 }
 343
 344 static int packet_check (char *packet, int length)
 345 {
 346         char c = (char) length;
 347         int i;
 348
 349         for (i = 14; i < length; i++) {
 350                 if (packet[i] != c++)
 351                         return -1;
 352         }
 353
 354         return 0;
 355 }
 356
 357 static int test_ctlr (int devnum, int hw_addr)
 358 {
 359         int res = -1;
 360         char packet_send[MAX_PACKET_LENGTH];
 361         char packet_recv[MAX_PACKET_LENGTH];
 362         int length;
 363         int i;
 364         int l;
 365
 366         ether_post_init (devnum, hw_addr);
 367
 368         for (i = 0; i < TEST_NUM; i++) {
 369                 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
 370                         packet_fill (packet_send, l);
 371
 372                         ether_post_send (devnum, hw_addr, packet_send, l);
 373
 374                         length = ether_post_recv (devnum, hw_addr, packet_recv,
 375                                                   sizeof (packet_recv));
 376
 377                         if (length != l || packet_check (packet_recv, length) < 0) {
 378                                 goto Done;
 379                         }
 380                 }
 381         }
 382
 383         res = 0;
 384
 385 Done:
 386
 387         ether_post_halt (devnum, hw_addr);
 388
 389         if (res != 0) {
 390                 post_log ("EMAC%d test failed\n", devnum);
 391         }
 392
 393         return res;
 394 }
 395
 396 int ether_post_test (int flags)
 397 {
 398         int res = 0;
 399         int i;
 400
 401         /* Allocate tx & rx packet buffers */
 402         tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
 403         rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
 404
 405         if (!tx_buf || !rx_buf) {
 406                 printf ("Failed to allocate packet buffers\n");
 407                 res = -1;
 408                 goto out_free;
 409         }
 410
 411         for (i = 0; i < LAST_EMAC_NUM; i++) {
 412                 if (test_ctlr (i, i*0x100))
 413                         res = -1;
 414         }
 415
 416 out_free:
 417         free (tx_buf);
 418         free (rx_buf);
 419
 420         return res;
 421 }
 422
 423 #endif /* CONFIG_POST & CFG_POST_ETHER */
 424 #endif /* CONFIG_POST */