post/cpu/ppc4xx/ether.c

   1 /*
   2  * (C) Copyright 2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Author: Igor Lisitsin <igor@emcraft.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27
  28 /*
  29  * Ethernet test
  30  *
  31  * The Ethernet Media Access Controllers (EMAC) are tested in the
  32  * internal loopback mode.
  33  * The controllers are configured accordingly and several packets
  34  * are transmitted. The configurable test parameters are:
  35  *   MIN_PACKET_LENGTH - minimum size of packet to transmit
  36  *   MAX_PACKET_LENGTH - maximum size of packet to transmit
  37  *   TEST_NUM - number of tests
  38  */
  39
  40 #ifdef CONFIG_POST
  41
  42 #include <post.h>
  43
  44 #if CONFIG_POST & CFG_POST_ETHER
  45
  46 #include <asm/cache.h>
  47 #include <asm/io.h>
  48 #include <asm/processor.h>
  49 #include <405_mal.h>
  50 #include <ppc4xx_enet.h>
  51 #include <malloc.h>
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 /*
  56  * Get count of EMAC devices (doesn't have to be the max. possible number
  57  * supported by the cpu)
  58  *
  59  * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
  60  * EMAC count is possible. As it is needed for the Kilauea/Haleakala
  61  * 405EX/405EXr eval board, using the same binary.
  62  */
  63 #if defined(CONFIG_BOARD_EMAC_COUNT)
  64 #define LAST_EMAC_NUM   board_emac_count()
  65 #else /* CONFIG_BOARD_EMAC_COUNT */
  66 #if defined(CONFIG_HAS_ETH3)
  67 #define LAST_EMAC_NUM   4
  68 #elif defined(CONFIG_HAS_ETH2)
  69 #define LAST_EMAC_NUM   3
  70 #elif defined(CONFIG_HAS_ETH1)
  71 #define LAST_EMAC_NUM   2
  72 #else
  73 #define LAST_EMAC_NUM   1
  74 #endif
  75 #endif /* CONFIG_BOARD_EMAC_COUNT */
  76
  77 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  78 #define SDR0_MFR_ETH_CLK_SEL_V(n)       ((0x01<<27) / (n+1))
  79 #endif
  80
  81 #define MIN_PACKET_LENGTH       64
  82 #define MAX_PACKET_LENGTH       256
  83 #define TEST_NUM                1
  84
  85 static volatile mal_desc_t tx __cacheline_aligned;
  86 static volatile mal_desc_t rx __cacheline_aligned;
  87 static char *tx_buf;
  88 static char *rx_buf;
  89
  90 int board_emac_count(void);
  91
  92 static void ether_post_init (int devnum, int hw_addr)
  93 {
  94         int i;
  95 #if defined(CONFIG_440GX) || \
  96     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  97     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  98         unsigned mode_reg;
  99         sys_info_t sysinfo;
 100 #endif
 101 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
 102         unsigned long mfr;
 103 #endif
 104
 105 #if defined(CONFIG_440GX) || \
 106     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 107     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 108         /* Need to get the OPB frequency so we can access the PHY */
 109         get_sys_info (&sysinfo);
 110 #endif
 111
 112 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 113         /* provide clocks for EMAC internal loopback  */
 114         mfsdr (sdr_mfr, mfr);
 115         mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
 116         mtsdr (sdr_mfr, mfr);
 117         sync ();
 118 #endif
 119         /* reset emac */
 120         out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
 121         sync ();
 122
 123         for (i = 0;; i++) {
 124                 if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
 125                         break;
 126                 if (i >= 1000) {
 127                         printf ("Timeout resetting EMAC\n");
 128                         break;
 129                 }
 130                 udelay (1000);
 131         }
 132 #if defined(CONFIG_440GX) || \
 133     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 134     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 135         /* Whack the M1 register */
 136         mode_reg = 0x0;
 137         if (sysinfo.freqOPB <= 50000000);
 138         else if (sysinfo.freqOPB <= 66666667)
 139                 mode_reg |= EMAC_M1_OBCI_66;
 140         else if (sysinfo.freqOPB <= 83333333)
 141                 mode_reg |= EMAC_M1_OBCI_83;
 142         else if (sysinfo.freqOPB <= 100000000)
 143                 mode_reg |= EMAC_M1_OBCI_100;
 144         else
 145                 mode_reg |= EMAC_M1_OBCI_GT100;
 146
 147         out32 (EMAC_M1 + hw_addr, mode_reg);
 148
 149 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
 150
 151         /* set the Mal configuration reg */
 152 #if defined(CONFIG_440GX) || \
 153     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 154     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 155         mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
 156                MAL_CR_PLBLT_DEFAULT | 0x00330000);
 157 #else
 158         mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
 159         /* Errata 1.12: MAL_1 -- Disable MAL bursting */
 160         if (get_pvr() == PVR_440GP_RB) {
 161                 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
 162         }
 163 #endif
 164         /* setup buffer descriptors */
 165         tx.ctrl = MAL_TX_CTRL_WRAP;
 166         tx.data_len = 0;
 167         tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
 168
 169         rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
 170         rx.data_len = 0;
 171         rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
 172         flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
 173         flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
 174
 175         switch (devnum) {
 176         case 1:
 177                 /* setup MAL tx & rx channel pointers */
 178 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
 179                 mtdcr (maltxctp2r, &tx);
 180 #else
 181                 mtdcr (maltxctp1r, &tx);
 182 #endif
 183 #if defined(CONFIG_440)
 184                 mtdcr (maltxbattr, 0x0);
 185                 mtdcr (malrxbattr, 0x0);
 186 #endif
 187                 mtdcr (malrxctp1r, &rx);
 188                 /* set RX buffer size */
 189                 mtdcr (malrcbs1, PKTSIZE_ALIGN / 16);
 190                 break;
 191         case 0:
 192         default:
 193                 /* setup MAL tx & rx channel pointers */
 194 #if defined(CONFIG_440)
 195                 mtdcr (maltxbattr, 0x0);
 196                 mtdcr (malrxbattr, 0x0);
 197 #endif
 198                 mtdcr (maltxctp0r, &tx);
 199                 mtdcr (malrxctp0r, &rx);
 200                 /* set RX buffer size */
 201                 mtdcr (malrcbs0, PKTSIZE_ALIGN / 16);
 202                 break;
 203         }
 204
 205         /* Enable MAL transmit and receive channels */
 206 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 207         mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2)));
 208 #else
 209         mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum));
 210 #endif
 211         mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
 212
 213         /* set internal loopback mode */
 214 #ifdef CFG_POST_ETHER_EXT_LOOPBACK
 215         out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
 216                EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
 217                EMAC_M1_MF_100MBPS | EMAC_M1_IST |
 218                in32 (EMAC_M1));
 219 #else
 220         out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
 221                EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
 222                EMAC_M1_MF_100MBPS | EMAC_M1_IST |
 223                in32 (EMAC_M1));
 224 #endif
 225
 226         /* set transmit enable & receive enable */
 227         out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
 228
 229         /* enable broadcast address */
 230         out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
 231
 232         /* set transmit request threshold register */
 233         out32 (EMAC_TRTR + hw_addr, 0x18000000);        /* 256 byte threshold */
 234
 235         /* set receive  low/high water mark register */
 236 #if defined(CONFIG_440)
 237         /* 440s has a 64 byte burst length */
 238         out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
 239 #else
 240         /* 405s have a 16 byte burst length */
 241         out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
 242 #endif /* defined(CONFIG_440) */
 243         out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
 244
 245         /* Set fifo limit entry in tx mode 0 */
 246         out32 (EMAC_TXM0 + hw_addr, 0x00000003);
 247         /* Frame gap set */
 248         out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
 249         sync ();
 250 }
 251
 252 static void ether_post_halt (int devnum, int hw_addr)
 253 {
 254         int i = 0;
 255 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 256         unsigned long mfr;
 257 #endif
 258
 259         /* 1st reset MAL channel */
 260         /* Note: writing a 0 to a channel has no effect */
 261 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 262         mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2));
 263 #else
 264         mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum);
 265 #endif
 266         mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum);
 267
 268         /* wait for reset */
 269         while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) {
 270                 if (i++ >= 1000)
 271                         break;
 272                 udelay (1000);
 273         }
 274         /* emac reset */
 275         out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
 276
 277 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 278         /* remove clocks for EMAC internal loopback  */
 279         mfsdr (sdr_mfr, mfr);
 280         mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
 281         mtsdr (sdr_mfr, mfr);
 282 #endif
 283 }
 284
 285 static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
 286 {
 287         int i = 0;
 288
 289         while (tx.ctrl & MAL_TX_CTRL_READY) {
 290                 if (i++ > 100) {
 291                         printf ("TX timeout\n");
 292                         return;
 293                 }
 294                 udelay (1000);
 295                 invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
 296         }
 297         tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
 298                 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
 299         tx.data_len = length;
 300         memcpy (tx.data_ptr, packet, length);
 301         flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
 302         flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
 303         sync ();
 304
 305         out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
 306         sync ();
 307 }
 308
 309 static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
 310 {
 311         int length;
 312         int i = 0;
 313
 314         while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
 315                 if (i++ > 100) {
 316                         printf ("RX timeout\n");
 317                         return 0;
 318                 }
 319                 udelay (1000);
 320                 invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
 321         }
 322         length = rx.data_len - 4;
 323         if (length <= max_length) {
 324                 invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
 325                 memcpy(packet, rx.data_ptr, length);
 326         }
 327         sync ();
 328
 329         rx.ctrl |= MAL_RX_CTRL_EMPTY;
 330         flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
 331         sync ();
 332
 333         return length;
 334 }
 335
 336   /*
 337    * Test routines
 338    */
 339
 340 static void packet_fill (char *packet, int length)
 341 {
 342         char c = (char) length;
 343         int i;
 344
 345         /* set up ethernet header */
 346         memset (packet, 0xff, 14);
 347
 348         for (i = 14; i < length; i++) {
 349                 packet[i] = c++;
 350         }
 351 }
 352
 353 static int packet_check (char *packet, int length)
 354 {
 355         char c = (char) length;
 356         int i;
 357
 358         for (i = 14; i < length; i++) {
 359                 if (packet[i] != c++)
 360                         return -1;
 361         }
 362
 363         return 0;
 364 }
 365
 366 static int test_ctlr (int devnum, int hw_addr)
 367 {
 368         int res = -1;
 369         char packet_send[MAX_PACKET_LENGTH];
 370         char packet_recv[MAX_PACKET_LENGTH];
 371         int length;
 372         int i;
 373         int l;
 374
 375         ether_post_init (devnum, hw_addr);
 376
 377         for (i = 0; i < TEST_NUM; i++) {
 378                 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
 379                         packet_fill (packet_send, l);
 380
 381                         ether_post_send (devnum, hw_addr, packet_send, l);
 382
 383                         length = ether_post_recv (devnum, hw_addr, packet_recv,
 384                                                   sizeof (packet_recv));
 385
 386                         if (length != l || packet_check (packet_recv, length) < 0) {
 387                                 goto Done;
 388                         }
 389                 }
 390         }
 391
 392         res = 0;
 393
 394 Done:
 395
 396         ether_post_halt (devnum, hw_addr);
 397
 398         if (res != 0) {
 399                 post_log ("EMAC%d test failed\n", devnum);
 400         }
 401
 402         return res;
 403 }
 404
 405 int ether_post_test (int flags)
 406 {
 407         int res = 0;
 408         int i;
 409
 410         /* Allocate tx & rx packet buffers */
 411         tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
 412         rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
 413
 414         if (!tx_buf || !rx_buf) {
 415                 printf ("Failed to allocate packet buffers\n");
 416                 res = -1;
 417                 goto out_free;
 418         }
 419
 420         for (i = 0; i < LAST_EMAC_NUM; i++) {
 421                 if (test_ctlr (i, i*0x100))
 422                         res = -1;
 423         }
 424
 425 out_free:
 426         free (tx_buf);
 427         free (rx_buf);
 428
 429         return res;
 430 }
 431
 432 #endif /* CONFIG_POST & CFG_POST_ETHER */
 433 #endif /* CONFIG_POST */