post/lib_powerpc/cpu.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * CPU test
  28  *
  29  * This test checks the arithmetic logic unit (ALU) of CPU.
  30  * It tests independently various groups of instructions using
  31  * run-time modification of the code to reduce the memory footprint.
  32  * For more details refer to post/cpu/ *.c files.
  33  */
  34
  35 #include <watchdog.h>
  36 #include <post.h>
  37 #include <asm/mmu.h>
  38
  39 #if CONFIG_POST & CONFIG_SYS_POST_CPU
  40
  41 extern int cpu_post_test_cmp (void);
  42 extern int cpu_post_test_cmpi (void);
  43 extern int cpu_post_test_two (void);
  44 extern int cpu_post_test_twox (void);
  45 extern int cpu_post_test_three (void);
  46 extern int cpu_post_test_threex (void);
  47 extern int cpu_post_test_threei (void);
  48 extern int cpu_post_test_andi (void);
  49 extern int cpu_post_test_srawi (void);
  50 extern int cpu_post_test_rlwnm (void);
  51 extern int cpu_post_test_rlwinm (void);
  52 extern int cpu_post_test_rlwimi (void);
  53 extern int cpu_post_test_store (void);
  54 extern int cpu_post_test_load (void);
  55 extern int cpu_post_test_cr (void);
  56 extern int cpu_post_test_b (void);
  57 extern int cpu_post_test_multi (void);
  58 extern int cpu_post_test_string (void);
  59 extern int cpu_post_test_complex (void);
  60
  61 DECLARE_GLOBAL_DATA_PTR;
  62
  63 ulong cpu_post_makecr (long v)
  64 {
  65         ulong cr = 0;
  66
  67         if (v < 0)
  68                 cr |= 0x80000000;
  69         if (v > 0)
  70                 cr |= 0x40000000;
  71         if (v == 0)
  72                 cr |= 0x20000000;
  73
  74         return cr;
  75 }
  76
  77 int cpu_post_test (int flags)
  78 {
  79         int ic = icache_status ();
  80         int ret = 0;
  81
  82         WATCHDOG_RESET();
  83         if (ic)
  84                 icache_disable ();
  85 #ifdef CONFIG_4xx_DCACHE
  86         /* disable cache */
  87         change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
  88 #endif
  89
  90         if (ret == 0)
  91                 ret = cpu_post_test_cmp ();
  92         if (ret == 0)
  93                 ret = cpu_post_test_cmpi ();
  94         if (ret == 0)
  95                 ret = cpu_post_test_two ();
  96         if (ret == 0)
  97                 ret = cpu_post_test_twox ();
  98         WATCHDOG_RESET();
  99         if (ret == 0)
 100                 ret = cpu_post_test_three ();
 101         if (ret == 0)
 102                 ret = cpu_post_test_threex ();
 103         if (ret == 0)
 104                 ret = cpu_post_test_threei ();
 105         if (ret == 0)
 106                 ret = cpu_post_test_andi ();
 107         WATCHDOG_RESET();
 108         if (ret == 0)
 109                 ret = cpu_post_test_srawi ();
 110         if (ret == 0)
 111                 ret = cpu_post_test_rlwnm ();
 112         if (ret == 0)
 113                 ret = cpu_post_test_rlwinm ();
 114         if (ret == 0)
 115                 ret = cpu_post_test_rlwimi ();
 116         WATCHDOG_RESET();
 117         if (ret == 0)
 118                 ret = cpu_post_test_store ();
 119         if (ret == 0)
 120                 ret = cpu_post_test_load ();
 121         if (ret == 0)
 122                 ret = cpu_post_test_cr ();
 123         if (ret == 0)
 124                 ret = cpu_post_test_b ();
 125         WATCHDOG_RESET();
 126         if (ret == 0)
 127                 ret = cpu_post_test_multi ();
 128         WATCHDOG_RESET();
 129         if (ret == 0)
 130                 ret = cpu_post_test_string ();
 131         if (ret == 0)
 132                 ret = cpu_post_test_complex ();
 133         WATCHDOG_RESET();
 134
 135         if (ic)
 136                 icache_enable ();
 137 #ifdef CONFIG_4xx_DCACHE
 138         /* enable cache */
 139         change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
 140 #endif
 141
 142         WATCHDOG_RESET();
 143
 144         return ret;
 145 }
 146
 147 #endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */