post/lib_powerpc/rlwnm.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * CPU test
  28  * Shift instructions:          rlwnm
  29  *
  30  * The test contains a pre-built table of instructions, operands and
  31  * expected results. For each table entry, the test will cyclically use
  32  * different sets of operand registers and result registers.
  33  */
  34
  35 #include <post.h>
  36 #include "cpu_asm.h"
  37
  38 #if CONFIG_POST & CONFIG_SYS_POST_CPU
  39
  40 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  41     ulong op2);
  42 extern ulong cpu_post_makecr (long v);
  43
  44 static struct cpu_post_rlwnm_s
  45 {
  46     ulong cmd;
  47     ulong op1;
  48     ulong op2;
  49     uchar mb;
  50     uchar me;
  51     ulong res;
  52 } cpu_post_rlwnm_table[] =
  53 {
  54    {
  55         OP_RLWNM,
  56         0xffff0000,
  57         24,
  58         16,
  59         23,
  60         0x0000ff00
  61    },
  62 };
  63 static unsigned int cpu_post_rlwnm_size = ARRAY_SIZE(cpu_post_rlwnm_table);
  64
  65 int cpu_post_test_rlwnm (void)
  66 {
  67     int ret = 0;
  68     unsigned int i, reg;
  69     int flag = disable_interrupts();
  70
  71     for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++)
  72     {
  73         struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i;
  74
  75         for (reg = 0; reg < 32 && ret == 0; reg++)
  76         {
  77             unsigned int reg0 = (reg + 0) % 32;
  78             unsigned int reg1 = (reg + 1) % 32;
  79             unsigned int reg2 = (reg + 2) % 32;
  80             unsigned int stk = reg < 16 ? 31 : 15;
  81             unsigned long code[] =
  82             {
  83                 ASM_STW(stk, 1, -4),
  84                 ASM_ADDI(stk, 1, -24),
  85                 ASM_STW(3, stk, 12),
  86                 ASM_STW(4, stk, 16),
  87                 ASM_STW(reg0, stk, 8),
  88                 ASM_STW(reg1, stk, 4),
  89                 ASM_STW(reg2, stk, 0),
  90                 ASM_LWZ(reg1, stk, 12),
  91                 ASM_LWZ(reg0, stk, 16),
  92                 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me),
  93                 ASM_STW(reg2, stk, 12),
  94                 ASM_LWZ(reg2, stk, 0),
  95                 ASM_LWZ(reg1, stk, 4),
  96                 ASM_LWZ(reg0, stk, 8),
  97                 ASM_LWZ(3, stk, 12),
  98                 ASM_ADDI(1, stk, 24),
  99                 ASM_LWZ(stk, 1, -4),
 100                 ASM_BLR,
 101             };
 102             unsigned long codecr[] =
 103             {
 104                 ASM_STW(stk, 1, -4),
 105                 ASM_ADDI(stk, 1, -24),
 106                 ASM_STW(3, stk, 12),
 107                 ASM_STW(4, stk, 16),
 108                 ASM_STW(reg0, stk, 8),
 109                 ASM_STW(reg1, stk, 4),
 110                 ASM_STW(reg2, stk, 0),
 111                 ASM_LWZ(reg1, stk, 12),
 112                 ASM_LWZ(reg0, stk, 16),
 113                 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) |
 114                     BIT_C,
 115                 ASM_STW(reg2, stk, 12),
 116                 ASM_LWZ(reg2, stk, 0),
 117                 ASM_LWZ(reg1, stk, 4),
 118                 ASM_LWZ(reg0, stk, 8),
 119                 ASM_LWZ(3, stk, 12),
 120                 ASM_ADDI(1, stk, 24),
 121                 ASM_LWZ(stk, 1, -4),
 122                 ASM_BLR,
 123             };
 124             ulong res;
 125             ulong cr;
 126
 127             if (ret == 0)
 128             {
 129                 cr = 0;
 130                 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
 131
 132                 ret = res == test->res && cr == 0 ? 0 : -1;
 133
 134                 if (ret != 0)
 135                 {
 136                     post_log ("Error at rlwnm test %d !\n", i);
 137                 }
 138             }
 139
 140             if (ret == 0)
 141             {
 142                 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
 143
 144                 ret = res == test->res &&
 145                       (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 146
 147                 if (ret != 0)
 148                 {
 149                     post_log ("Error at rlwnm test %d !\n", i);
 150                 }
 151             }
 152         }
 153     }
 154
 155     if (flag)
 156         enable_interrupts();
 157
 158     return ret;
 159 }
 160
 161 #endif