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git.ipfire.org Git - people/ms/u-boot.git/blob - post/lib_powerpc/srawi.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 * Shift instructions: srawi
14 * The test contains a pre-built table of instructions, operands and
15 * expected results. For each table entry, the test will cyclically use
16 * different sets of operand registers and result registers.
22 #if CONFIG_POST & CONFIG_SYS_POST_CPU
24 extern void cpu_post_exec_21 (ulong
*code
, ulong
*cr
, ulong
*res
, ulong op
);
25 extern ulong
cpu_post_makecr (long v
);
27 static struct cpu_post_srawi_s
33 } cpu_post_srawi_table
[] =
48 static unsigned int cpu_post_srawi_size
= ARRAY_SIZE(cpu_post_srawi_table
);
50 int cpu_post_test_srawi (void)
54 int flag
= disable_interrupts();
56 for (i
= 0; i
< cpu_post_srawi_size
&& ret
== 0; i
++)
58 struct cpu_post_srawi_s
*test
= cpu_post_srawi_table
+ i
;
60 for (reg
= 0; reg
< 32 && ret
== 0; reg
++)
62 unsigned int reg0
= (reg
+ 0) % 32;
63 unsigned int reg1
= (reg
+ 1) % 32;
64 unsigned int stk
= reg
< 16 ? 31 : 15;
65 unsigned long code
[] =
68 ASM_ADDI(stk
, 1, -16),
70 ASM_STW(reg0
, stk
, 4),
71 ASM_STW(reg1
, stk
, 0),
72 ASM_LWZ(reg0
, stk
, 8),
73 ASM_11S(test
->cmd
, reg1
, reg0
, test
->op2
),
74 ASM_STW(reg1
, stk
, 8),
75 ASM_LWZ(reg1
, stk
, 0),
76 ASM_LWZ(reg0
, stk
, 4),
82 unsigned long codecr
[] =
85 ASM_ADDI(stk
, 1, -16),
87 ASM_STW(reg0
, stk
, 4),
88 ASM_STW(reg1
, stk
, 0),
89 ASM_LWZ(reg0
, stk
, 8),
90 ASM_11S(test
->cmd
, reg1
, reg0
, test
->op2
) | BIT_C
,
91 ASM_STW(reg1
, stk
, 8),
92 ASM_LWZ(reg1
, stk
, 0),
93 ASM_LWZ(reg0
, stk
, 4),
105 cpu_post_exec_21 (code
, & cr
, & res
, test
->op1
);
107 ret
= res
== test
->res
&& cr
== 0 ? 0 : -1;
111 post_log ("Error at srawi test %d !\n", i
);
117 cpu_post_exec_21 (codecr
, & cr
, & res
, test
->op1
);
119 ret
= res
== test
->res
&&
120 (cr
& 0xe0000000) == cpu_post_makecr (res
) ? 0 : -1;
124 post_log ("Error at srawi test %d !\n", i
);