post/lib_powerpc/threei.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9
  10 /*
  11  * CPU test
  12  * Ternary instructions         instr rA,rS,UIMM
  13  *
  14  * Logic instructions:          ori, oris, xori, xoris
  15  *
  16  * The test contains a pre-built table of instructions, operands and
  17  * expected results. For each table entry, the test will cyclically use
  18  * different sets of operand registers and result registers.
  19  */
  20
  21 #include <post.h>
  22 #include "cpu_asm.h"
  23
  24 #if CONFIG_POST & CONFIG_SYS_POST_CPU
  25
  26 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
  27 extern ulong cpu_post_makecr (long v);
  28
  29 static struct cpu_post_threei_s
  30 {
  31     ulong cmd;
  32     ulong op1;
  33     ushort op2;
  34     ulong res;
  35 } cpu_post_threei_table[] =
  36 {
  37     {
  38         OP_ORI,
  39         0x80000000,
  40         0xffff,
  41         0x8000ffff
  42     },
  43     {
  44         OP_ORIS,
  45         0x00008000,
  46         0xffff,
  47         0xffff8000
  48     },
  49     {
  50         OP_XORI,
  51         0x8000ffff,
  52         0xffff,
  53         0x80000000
  54     },
  55     {
  56         OP_XORIS,
  57         0x00008000,
  58         0xffff,
  59         0xffff8000
  60     },
  61 };
  62 static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table);
  63
  64 int cpu_post_test_threei (void)
  65 {
  66     int ret = 0;
  67     unsigned int i, reg;
  68     int flag = disable_interrupts();
  69
  70     for (i = 0; i < cpu_post_threei_size && ret == 0; i++)
  71     {
  72         struct cpu_post_threei_s *test = cpu_post_threei_table + i;
  73
  74         for (reg = 0; reg < 32 && ret == 0; reg++)
  75         {
  76             unsigned int reg0 = (reg + 0) % 32;
  77             unsigned int reg1 = (reg + 1) % 32;
  78             unsigned int stk = reg < 16 ? 31 : 15;
  79             unsigned long code[] =
  80             {
  81                 ASM_STW(stk, 1, -4),
  82                 ASM_ADDI(stk, 1, -16),
  83                 ASM_STW(3, stk, 8),
  84                 ASM_STW(reg0, stk, 4),
  85                 ASM_STW(reg1, stk, 0),
  86                 ASM_LWZ(reg0, stk, 8),
  87                 ASM_11IX(test->cmd, reg1, reg0, test->op2),
  88                 ASM_STW(reg1, stk, 8),
  89                 ASM_LWZ(reg1, stk, 0),
  90                 ASM_LWZ(reg0, stk, 4),
  91                 ASM_LWZ(3, stk, 8),
  92                 ASM_ADDI(1, stk, 16),
  93                 ASM_LWZ(stk, 1, -4),
  94                 ASM_BLR,
  95             };
  96             ulong res;
  97             ulong cr;
  98
  99             cr = 0;
 100             cpu_post_exec_21 (code, & cr, & res, test->op1);
 101
 102             ret = res == test->res && cr == 0 ? 0 : -1;
 103
 104             if (ret != 0)
 105             {
 106                 post_log ("Error at threei test %d !\n", i);
 107             }
 108         }
 109     }
 110
 111     if (flag)
 112         enable_interrupts();
 113
 114     return ret;
 115 }
 116
 117 #endif