post/uart.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * UART test
  28  *
  29  * The Serial Management Controllers (SMC) and the Serial Communication
  30  * Controllers (SCC) listed in ctlr_list array below are tested in
  31  * the loopback UART mode.
  32  * The controllers are configured accordingly and several characters
  33  * are transmitted. The configurable test parameters are:
  34  *   MIN_PACKET_LENGTH - minimum size of packet to transmit
  35  *   MAX_PACKET_LENGTH - maximum size of packet to transmit
  36  *   TEST_NUM - number of tests
  37  */
  38
  39 #ifdef CONFIG_POST
  40
  41 #include <post.h>
  42 #if CONFIG_POST & CFG_POST_UART
  43 #if defined(CONFIG_8xx)
  44 #include <commproc.h>
  45 #elif defined(CONFIG_MPC8260)
  46 #include <asm/cpm_8260.h>
  47 #else
  48 #error "Apparently a bad configuration, please fix."
  49 #endif
  50 #include <command.h>
  51 #include <serial.h>
  52
  53 #define CTLR_SMC 0
  54 #define CTLR_SCC 1
  55
  56 /* The list of controllers to test */
  57 #if defined(CONFIG_MPC823)
  58 static int ctlr_list[][2] =
  59                 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
  60 #else
  61 static int ctlr_list[][2] = { };
  62 #endif
  63
  64 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
  65
  66 static struct {
  67         void (*init) (int index);
  68         void (*halt) (int index);
  69         void (*putc) (int index, const char c);
  70         int (*getc) (int index);
  71 } ctlr_proc[2];
  72
  73 static char *ctlr_name[2] = { "SMC", "SCC" };
  74
  75 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
  76 static int proff_scc[] =
  77                 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
  78
  79 /*
  80  * SMC callbacks
  81  */
  82
  83 static void smc_init (int smc_index)
  84 {
  85         DECLARE_GLOBAL_DATA_PTR;
  86
  87         static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
  88
  89         volatile immap_t *im = (immap_t *) CFG_IMMR;
  90         volatile smc_t *sp;
  91         volatile smc_uart_t *up;
  92         volatile cbd_t *tbdf, *rbdf;
  93         volatile cpm8xx_t *cp = &(im->im_cpm);
  94         uint dpaddr;
  95
  96         /* initialize pointers to SMC */
  97
  98         sp = (smc_t *) & (cp->cp_smc[smc_index]);
  99         up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
 100
 101         /* Disable transmitter/receiver.
 102          */
 103         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 104
 105         /* Enable SDMA.
 106          */
 107         im->im_siu_conf.sc_sdcr = 1;
 108
 109         /* clear error conditions */
 110 #ifdef  CFG_SDSR
 111         im->im_sdma.sdma_sdsr = CFG_SDSR;
 112 #else
 113         im->im_sdma.sdma_sdsr = 0x83;
 114 #endif
 115
 116         /* clear SDMA interrupt mask */
 117 #ifdef  CFG_SDMR
 118         im->im_sdma.sdma_sdmr = CFG_SDMR;
 119 #else
 120         im->im_sdma.sdma_sdmr = 0x00;
 121 #endif
 122
 123 #if defined(CONFIG_FADS)
 124         /* Enable RS232 */
 125         *((uint *) BCSR1) &=
 126                         ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
 127 #endif
 128
 129 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 130         /* Enable Monitor Port Transceiver */
 131         *((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
 132 #endif
 133
 134         /* Set the physical address of the host memory buffers in
 135          * the buffer descriptors.
 136          */
 137
 138 #ifdef CFG_ALLOC_DPRAM
 139         dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
 140 #else
 141         dpaddr = CPM_POST_BASE;
 142 #endif
 143
 144         /* Allocate space for two buffer descriptors in the DP ram.
 145          * For now, this address seems OK, but it may have to
 146          * change with newer versions of the firmware.
 147          * damm: allocating space after the two buffers for rx/tx data
 148          */
 149
 150         rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
 151         rbdf->cbd_bufaddr = (uint) (rbdf + 2);
 152         rbdf->cbd_sc = 0;
 153         tbdf = rbdf + 1;
 154         tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
 155         tbdf->cbd_sc = 0;
 156
 157         /* Set up the uart parameters in the parameter ram.
 158          */
 159         up->smc_rbase = dpaddr;
 160         up->smc_tbase = dpaddr + sizeof (cbd_t);
 161         up->smc_rfcr = SMC_EB;
 162         up->smc_tfcr = SMC_EB;
 163
 164 #if defined(CONFIG_MBX)
 165         board_serial_init ();
 166 #endif
 167
 168         /* Set UART mode, 8 bit, no parity, one stop.
 169          * Enable receive and transmit.
 170          * Set local loopback mode.
 171          */
 172         sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
 173
 174         /* Mask all interrupts and remove anything pending.
 175          */
 176         sp->smc_smcm = 0;
 177         sp->smc_smce = 0xff;
 178
 179         /* Set up the baud rate generator.
 180          */
 181         cp->cp_simode = 0x00000000;
 182
 183         cp->cp_brgc1 =
 184                         (((gd->cpu_clk / 16 / gd->baudrate) -
 185                           1) << 1) | CPM_BRG_EN;
 186
 187         /* Make the first buffer the only buffer.
 188          */
 189         tbdf->cbd_sc |= BD_SC_WRAP;
 190         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 191
 192         /* Single character receive.
 193          */
 194         up->smc_mrblr = 1;
 195         up->smc_maxidl = 0;
 196
 197         /* Initialize Tx/Rx parameters.
 198          */
 199
 200         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 201                 ;
 202
 203         cp->cp_cpcr =
 204                         mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
 205
 206         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 207                 ;
 208
 209         /* Enable transmitter/receiver.
 210          */
 211         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 212 }
 213
 214 static void smc_halt(int smc_index)
 215 {
 216 }
 217
 218 static void smc_putc (int smc_index, const char c)
 219 {
 220         volatile cbd_t *tbdf;
 221         volatile char *buf;
 222         volatile smc_uart_t *up;
 223         volatile immap_t *im = (immap_t *) CFG_IMMR;
 224         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 225
 226         up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
 227
 228         tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
 229
 230         /* Wait for last character to go.
 231          */
 232
 233         buf = (char *) tbdf->cbd_bufaddr;
 234 #if 0
 235         __asm__ ("eieio");
 236         while (tbdf->cbd_sc & BD_SC_READY)
 237                 __asm__ ("eieio");
 238 #endif
 239
 240         *buf = c;
 241         tbdf->cbd_datlen = 1;
 242         tbdf->cbd_sc |= BD_SC_READY;
 243         __asm__ ("eieio");
 244 #if 1
 245         while (tbdf->cbd_sc & BD_SC_READY)
 246                 __asm__ ("eieio");
 247 #endif
 248 }
 249
 250 static int smc_getc (int smc_index)
 251 {
 252         volatile cbd_t *rbdf;
 253         volatile unsigned char *buf;
 254         volatile smc_uart_t *up;
 255         volatile immap_t *im = (immap_t *) CFG_IMMR;
 256         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 257         unsigned char c;
 258         int i;
 259
 260         up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
 261
 262         rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
 263
 264         /* Wait for character to show up.
 265          */
 266         buf = (unsigned char *) rbdf->cbd_bufaddr;
 267 #if 0
 268         while (rbdf->cbd_sc & BD_SC_EMPTY);
 269 #else
 270         for (i = 100; i > 0; i--) {
 271                 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
 272                         break;
 273                 udelay (1000);
 274         }
 275
 276         if (i == 0)
 277                 return -1;
 278 #endif
 279         c = *buf;
 280         rbdf->cbd_sc |= BD_SC_EMPTY;
 281
 282         return (c);
 283 }
 284
 285   /*
 286    * SCC callbacks
 287    */
 288
 289 static void scc_init (int scc_index)
 290 {
 291         DECLARE_GLOBAL_DATA_PTR;
 292
 293         static int cpm_cr_ch[] = {
 294                 CPM_CR_CH_SCC1,
 295                 CPM_CR_CH_SCC2,
 296                 CPM_CR_CH_SCC3,
 297                 CPM_CR_CH_SCC4,
 298         };
 299
 300         volatile immap_t *im = (immap_t *) CFG_IMMR;
 301         volatile scc_t *sp;
 302         volatile scc_uart_t *up;
 303         volatile cbd_t *tbdf, *rbdf;
 304         volatile cpm8xx_t *cp = &(im->im_cpm);
 305         uint dpaddr;
 306
 307         /* initialize pointers to SCC */
 308
 309         sp = (scc_t *) & (cp->cp_scc[scc_index]);
 310         up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
 311
 312         /* Disable transmitter/receiver.
 313          */
 314         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 315
 316
 317         /* Allocate space for two buffer descriptors in the DP ram.
 318          */
 319
 320 #ifdef CFG_ALLOC_DPRAM
 321         dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
 322 #else
 323         dpaddr = CPM_POST_BASE;
 324 #endif
 325
 326         /* Enable SDMA.
 327          */
 328         im->im_siu_conf.sc_sdcr = 0x0001;
 329
 330         /* Set the physical address of the host memory buffers in
 331          * the buffer descriptors.
 332          */
 333
 334         rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
 335         rbdf->cbd_bufaddr = (uint) (rbdf + 2);
 336         rbdf->cbd_sc = 0;
 337         tbdf = rbdf + 1;
 338         tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
 339         tbdf->cbd_sc = 0;
 340
 341         /* Set up the baud rate generator.
 342          */
 343         cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
 344         /* no |= needed, since BRG1 is 000 */
 345
 346         cp->cp_brgc1 =
 347                         (((gd->cpu_clk / 16 / gd->baudrate) -
 348                           1) << 1) | CPM_BRG_EN;
 349
 350         /* Set up the uart parameters in the parameter ram.
 351          */
 352         up->scc_genscc.scc_rbase = dpaddr;
 353         up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
 354
 355         /* Initialize Tx/Rx parameters.
 356          */
 357         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 358                 ;
 359         cp->cp_cpcr =
 360                         mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
 361
 362         while (cp->cp_cpcr & CPM_CR_FLG)        /* wait if cp is busy */
 363                 ;
 364
 365         up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
 366         up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
 367
 368         up->scc_genscc.scc_mrblr = 1;   /* Single character receive */
 369         up->scc_maxidl = 0;             /* disable max idle */
 370         up->scc_brkcr = 1;              /* send one break character on stop TX */
 371         up->scc_parec = 0;
 372         up->scc_frmec = 0;
 373         up->scc_nosec = 0;
 374         up->scc_brkec = 0;
 375         up->scc_uaddr1 = 0;
 376         up->scc_uaddr2 = 0;
 377         up->scc_toseq = 0;
 378         up->scc_char1 = 0x8000;
 379         up->scc_char2 = 0x8000;
 380         up->scc_char3 = 0x8000;
 381         up->scc_char4 = 0x8000;
 382         up->scc_char5 = 0x8000;
 383         up->scc_char6 = 0x8000;
 384         up->scc_char7 = 0x8000;
 385         up->scc_char8 = 0x8000;
 386         up->scc_rccm = 0xc0ff;
 387
 388         /* Set low latency / small fifo.
 389          */
 390         sp->scc_gsmrh = SCC_GSMRH_RFW;
 391
 392         /* Set UART mode
 393          */
 394         sp->scc_gsmrl &= ~0xF;
 395         sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
 396
 397         /* Set local loopback mode.
 398          */
 399         sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
 400         sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
 401
 402         /* Set clock divider 16 on Tx and Rx
 403          */
 404         sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
 405
 406         sp->scc_psmr |= SCU_PSMR_CL;
 407
 408         /* Mask all interrupts and remove anything pending.
 409          */
 410         sp->scc_sccm = 0;
 411         sp->scc_scce = 0xffff;
 412         sp->scc_dsr = 0x7e7e;
 413         sp->scc_psmr = 0x3000;
 414
 415         /* Make the first buffer the only buffer.
 416          */
 417         tbdf->cbd_sc |= BD_SC_WRAP;
 418         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 419
 420         /* Enable transmitter/receiver.
 421          */
 422         sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 423 }
 424
 425 static void scc_halt(int scc_index)
 426 {
 427         volatile immap_t *im = (immap_t *) CFG_IMMR;
 428         volatile cpm8xx_t *cp = &(im->im_cpm);
 429         volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
 430
 431         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
 432 }
 433
 434 static void scc_putc (int scc_index, const char c)
 435 {
 436         volatile cbd_t *tbdf;
 437         volatile char *buf;
 438         volatile scc_uart_t *up;
 439         volatile immap_t *im = (immap_t *) CFG_IMMR;
 440         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 441
 442         up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
 443
 444         tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
 445
 446         /* Wait for last character to go.
 447          */
 448
 449         buf = (char *) tbdf->cbd_bufaddr;
 450 #if 0
 451         __asm__ ("eieio");
 452         while (tbdf->cbd_sc & BD_SC_READY)
 453                 __asm__ ("eieio");
 454 #endif
 455
 456         *buf = c;
 457         tbdf->cbd_datlen = 1;
 458         tbdf->cbd_sc |= BD_SC_READY;
 459         __asm__ ("eieio");
 460 #if 1
 461         while (tbdf->cbd_sc & BD_SC_READY)
 462                 __asm__ ("eieio");
 463 #endif
 464 }
 465
 466 static int scc_getc (int scc_index)
 467 {
 468         volatile cbd_t *rbdf;
 469         volatile unsigned char *buf;
 470         volatile scc_uart_t *up;
 471         volatile immap_t *im = (immap_t *) CFG_IMMR;
 472         volatile cpm8xx_t *cpmp = &(im->im_cpm);
 473         unsigned char c;
 474         int i;
 475
 476         up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
 477
 478         rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 479
 480         /* Wait for character to show up.
 481          */
 482         buf = (unsigned char *) rbdf->cbd_bufaddr;
 483 #if 0
 484         while (rbdf->cbd_sc & BD_SC_EMPTY);
 485 #else
 486         for (i = 100; i > 0; i--) {
 487                 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
 488                         break;
 489                 udelay (1000);
 490         }
 491
 492         if (i == 0)
 493                 return -1;
 494 #endif
 495         c = *buf;
 496         rbdf->cbd_sc |= BD_SC_EMPTY;
 497
 498         return (c);
 499 }
 500
 501   /*
 502    * Test routines
 503    */
 504
 505 static int test_ctlr (int ctlr, int index)
 506 {
 507         int res = -1;
 508         char test_str[] = "*** UART Test String ***\r\n";
 509         int i;
 510
 511         ctlr_proc[ctlr].init (index);
 512
 513         for (i = 0; i < sizeof (test_str) - 1; i++) {
 514                 ctlr_proc[ctlr].putc (index, test_str[i]);
 515                 if (ctlr_proc[ctlr].getc (index) != test_str[i])
 516                         goto Done;
 517         }
 518
 519         res = 0;
 520
 521 Done:
 522         ctlr_proc[ctlr].halt (index);
 523
 524         if (res != 0) {
 525                 post_log ("uart %s%d test failed\n",
 526                                 ctlr_name[ctlr], index + 1);
 527         }
 528
 529         return res;
 530 }
 531
 532 int uart_post_test (int flags)
 533 {
 534         int res = 0;
 535         int i;
 536
 537         ctlr_proc[CTLR_SMC].init = smc_init;
 538         ctlr_proc[CTLR_SMC].halt = smc_halt;
 539         ctlr_proc[CTLR_SMC].putc = smc_putc;
 540         ctlr_proc[CTLR_SMC].getc = smc_getc;
 541
 542         ctlr_proc[CTLR_SCC].init = scc_init;
 543         ctlr_proc[CTLR_SCC].halt = scc_halt;
 544         ctlr_proc[CTLR_SCC].putc = scc_putc;
 545         ctlr_proc[CTLR_SCC].getc = scc_getc;
 546
 547         for (i = 0; i < CTRL_LIST_SIZE; i++) {
 548                 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
 549                         res = -1;
 550                 }
 551         }
 552
 553 #if !defined(CONFIG_8xx_CONS_NONE)
 554         serial_reinit_all ();
 555 #endif
 556
 557         return res;
 558 }
 559
 560 #endif /* CONFIG_POST & CFG_POST_UART */
 561
 562 #endif /* CONFIG_POST */