config: remove platform CONFIG_SYS_HZ definition part 2/2

[people/ms/u-boot.git] / include / configs / omap3_sdp3430.h

diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index b02ec850b7d3a23e772ce3cc7264d61eff0a9d7f..697a3f386c059f653b47330d8c8561cfe682aa37 100644 (file)
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -7,23 +7,7 @@
  *
  * Configuration settings for the 3430 TI SDP3430 board.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -39,6 +23,7 @@
 #define CONFIG_OMAP            1       /* in a TI OMAP core */
 #define CONFIG_OMAP34XX                1       /* which is a 34XX */
 #define CONFIG_OMAP3_3430SDP   1       /* working with SDP Rev2 */
+#define CONFIG_OMAP_COMMON
 
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
@@ -132,8 +117,6 @@
 #define CONFIG_HARD_I2C                        1
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_SYS_I2C_BUS             0
-#define CONFIG_SYS_I2C_BUS_SELECT      1
 #define CONFIG_DRIVER_OMAP34XX_I2C     1
 
 /* OMITTED:  single 1 Gbit MT29F1G NAND flash */
@@ -290,7 +273,6 @@
  */
 #define CONFIG_SYS_TIMERBASE           (OMAP34XX_GPT2)
 #define CONFIG_SYS_PTV                 2       /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ                  1000
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x4020f800