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author	Kever Yang <kever.yang@rock-chips.com>
	Mon, 15 May 2017 12:52:16 +0000 (20:52 +0800)
committer	Simon Glass <sjg@chromium.org>
	Wed, 7 Jun 2017 13:29:20 +0000 (07:29 -0600)
commit	1960b0103420a74ae5b154ed8684785036e2235b
tree	30f953ef8d11259b60f5603cdd4bd4ad4d2a9b71	tree \| snapshot
parent	37943aaeea55011d48a0a492838c50111ba2a37e	commit \| diff

rockchip: clock: rk3036: some fix according TRM

- hclk/pclk_div range　should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

arch/arm/include/asm/arch-rockchip/cru_rk3036.h		diff \| blob \| blame \| history
drivers/clk/rockchip/clk_rk3036.c		diff \| blob \| blame \| history

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