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(parent: 89f99a6) | patch
serial: sh: fix internal clock source on SCIF
authorVladimir Barinov <vladimir.barinov@cogentembedded.com>
Fri, 13 Feb 2015 22:05:18 +0000 (01:05 +0300)
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Wed, 25 Feb 2015 04:53:37 +0000 (13:53 +0900)
commit2cbb17c0e941db629ff2d363c7fef69e47fb7d92
tree3c07f99e7c1b252c0eca29d6a34da9712b008517tree | snapshot
parent89f99a62c1a50d1bad75de315c454c9cf56b2d8dcommit | diff
serial: sh: fix internal clock source on SCIF

The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows:

BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1,
the prescaler is 0 due to SCSMR settings, hence n=0

Also SCSCR must be set to use internal or external clock source.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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