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ddr: altera: Fix scc_mgr_set() argument order
authorMarek Vasut <marex@denx.de>
Mon, 4 Apr 2016 15:28:16 +0000 (17:28 +0200)
committerMarek Vasut <marex@denx.de>
Wed, 20 Apr 2016 09:28:44 +0000 (11:28 +0200)
commit8e9e62c946e295ca8e0b81d07b6b1cc884a70bc1
treeae45e6bcfb09551775df7068f8d94a9406ac087atree | snapshot
parentbba7711092a48ef2af00832213c3cb6c2d5f171ccommit | diff
ddr: altera: Fix scc_mgr_set() argument order

The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
drivers/ddr/altera/sequencer.c diff | blob | blame | history
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