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armv8/ls2080aqds: Update DDR settings for four chip-select case
authorYork Sun <yorksun@freescale.com>
Wed, 4 Nov 2015 18:03:22 +0000 (10:03 -0800)
committerYork Sun <yorksun@freescale.com>
Mon, 14 Dec 2015 02:27:28 +0000 (18:27 -0800)
commitc4243ac9e2713897a63dcdc3a96bf088fdb49866
treeff5766eef6dc2f238791a238bccbc484941373cctree | snapshot
parent6c6e006a2083f2da7b4f66c6bb82ce8b3fb713a3commit | diff
armv8/ls2080aqds: Update DDR settings for four chip-select case

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun <yorksun@freescale.com>
board/freescale/ls2080aqds/ddr.c diff | blob | blame | history
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