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(parent: 2e4ce50) | patch
rockchip: clk: Add SARADC clock support for rk3288
authorDavid Wu <david.wu@rock-chips.com>
Wed, 20 Sep 2017 06:28:19 +0000 (14:28 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sat, 30 Sep 2017 22:33:29 +0000 (00:33 +0200)
commitef4cf5ae393e4adf532f536d6da97c87f88db230
tree57fba8ac99e6c10b3ab505c6e8ded1637e850706tree | snapshot
parent2e4ce50d1aca35d13944f48a7e15d0b63e86eb38commit | diff
rockchip: clk: Add SARADC clock support for rk3288

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
drivers/clk/rockchip/clk_rk3288.c diff | blob | blame | history
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