Simon Glass [Mon, 4 Jul 2016 17:57:54 +0000 (11:57 -0600)]
sandbox: Add a new sandbox_spl board
It is useful to be able to build SPL for sandbox. It provides additional
build coverage and allows SPL features to be tested in sandbox. However
it does not need worthwhile to always create an SPL build. It nearly
doubles the build time and the feature is (so far) seldom used.
So for now, create a separate build target for sandbox SPL. This allows
experimentation with this new feature without impacting existing workflows.
Simon Glass [Mon, 4 Jul 2016 17:57:45 +0000 (11:57 -0600)]
sandbox: Allow chaining from SPL to U-Boot proper
SPL is expected to load and run U-Boot. This needs to work with sandbox also.
Provide a function to locate the U-Boot image, and another to start it. This
allows SPL to function on sandbox as it does on other archs.
Simon Glass [Mon, 4 Jul 2016 17:57:44 +0000 (11:57 -0600)]
Makefile: Allow the SPL final link rule to be overridden
Overriding the final link rule is possible with U-Boot proper. It us used to
create a sandbox image links with host libraries. To build a sandbox SPL
image we need the same feature for SPL.
To support this, update the SPL link rule so sandbox can override it.
Simon Glass [Mon, 4 Jul 2016 17:57:41 +0000 (11:57 -0600)]
sandbox: Don't print a warning for CONFIG_I2C_COMPAT
Sandbox includes this code to provide build coverage. While we retain this
feature we should have sandbox build it. Sandbox does not in fact use the
I2C compatibility mode. Showing a warning for sandbox is just confusing,
since no conversion is expected.
Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.
Currently supported:
- 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
SOM-DB5800.
- 4x USB 2.0 (EHCI)
- Video
- SATA
- Ethernet
- PCIe
- Realtek ALC892 HD Audio
Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
HDA_SDI0 is set in DT to enable HD Audio codec.
Pin defaults for codec pin complexs are not changed.
Not supported:
- Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
- USB 3.0 (XHCI)
- TPM
Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Fri, 17 Jun 2016 09:13:17 +0000 (02:13 -0700)]
x86: baytrail: acpi: Hide internal UART per GNVS setting
If global NVS says internal UART is not enabled, hide it in the ASL
code so that OS won't see it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 17 Jun 2016 09:13:16 +0000 (02:13 -0700)]
x86: acpi: Pack global NVS into ACPI table
Now that platform-specific ACPI global NVS is added, pack it into
ACPI table and get its address fixed up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 17 Jun 2016 09:13:14 +0000 (02:13 -0700)]
x86: baytrail: Introduce ACPI global NVS
This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Wed, 15 Jun 2016 12:15:25 +0000 (14:15 +0200)]
x86: conga-qeval20-qa3: Add support for internal UART
This patch adds support to enable and use the internal BayTrail UART
instead of the one integrated in the Super IO Winbond chip. For this,
a 2nd defconfig file is added.
This is useful for tests done for the congatec SoM used on baseboards
without such a Super IO chip.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 15 Jun 2016 04:33:24 +0000 (21:33 -0700)]
x86: fsp: Wrap setup_internal_uart() call with CONFIG_INTERNAL_UART
For any FSP-enabled boards that want to enable debug UART support,
setup_internal_uart() will be called, but this API is only available
on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 15 Jun 2016 04:33:23 +0000 (21:33 -0700)]
x86: baytrail: Introduce a Kconfig option for the internal UART
There are quite a number of BayTrail boards that uses an external
SuperIO chipset to provide the legacy UART. For such cases, it's
better to have a Kconfig option to enable the internal UART.
So far BayleyBay and MinnowMax boards are using internal UART as
the U-Boot console, enable this on these two boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 14 Jun 2016 09:02:40 +0000 (02:02 -0700)]
pci: Add board_ prefix to should_load_oprom() and make it weak
For consistency with board_should_run_oprom(), do the same to
should_load_oprom(). Board support codes can provide this one
to override the default weak one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 14 Jun 2016 09:02:39 +0000 (02:02 -0700)]
pci: Make load_oprom and run_oprom independent
At present should_load_oprom() calls board_should_run_oprom() to
determine whether oprom should be loaded. But sometimes we just
want to load oprom without running. Make them independent.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Jun 2016 06:24:32 +0000 (23:24 -0700)]
tools: patman: Handle missing 'END' in non-last commit of a series
The following python error:
Traceback (most recent call last):
File "./tools/patman/patman", line 144, in <module>
series = patchstream.FixPatches(series, args)
File "./tools/patman/patchstream.py", line 477, in FixPatches
commit = series.commits[count]
IndexError: list index out of range
is seen when:
- 'END' is missing in those tags
- those tags are put in the last part in a commit message
- the commit is not the last commit of the series
Add testing logic to see if a new commit starts.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Jun 2016 06:24:30 +0000 (23:24 -0700)]
tools: patman: Generate cover letter correctly when 'END' is missing
If 'END' is missing in a 'Cover-letter' section, and that section
happens to show up at the very end of the commit message, and the
commit is the last commit of the series, patman fails to generate
cover letter for us. Handle this in CloseCommit of patchstream.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 27 Jun 2016 06:24:29 +0000 (23:24 -0700)]
tools: patman: Handle tag sections without an 'END'
'Cover-letter', 'Series-notes' and 'Commit-notes' tags require an
'END' to be put at the end of its section. If we forget to put an
'END' in those sections, and these sections are followed by another
patman tag, patman generates incorrect patches. This adds codes to
handle such scenario.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 19 Jun 2016 23:33:15 +0000 (17:33 -0600)]
sandbox: Find keyboard driver using driver model
The cros-ec keyboard is always a child of the cros-ec node. Rather than
searching the device tree, looking at the children. Remove the compat string
which is now unused.
Hamish Martin [Mon, 13 Jun 2016 22:17:05 +0000 (10:17 +1200)]
dm: gpio: MPC85XX GPIO platform data support
Define a platform data structure for the MPC85XX GPIO driver to allow
use of the driver without device tree. Users should define the GPIO
blocks for their platform like this:
struct mpc85xx_gpio_plat gpio_blocks[] = {
{
.addr = 0x130000,
.ngpios = 32,
},
{
.addr = 0x131000,
.ngpios = 32,
},
};
This is intended to build upon the recent submission of the base
MPC85XX driver from Mario Six. We need to use that new driver
without dts support and this patch gives us that flexibility.
This has been tested on a Freescale T2080 CPU, although only the first
GPIO block.
Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Reviewed-by: Mario Six <mario.six@gdsys.cc> Tested-by: Mario Six <mario.six@gdsys.cc> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Jun 2016 05:30:22 +0000 (23:30 -0600)]
dm: mmc: Add a way to use driver model for MMC operations
The driver model conversion for MMC has moved in small steps. The first step
was to have an MMC device (CONFIG_DM_MMC). The second was to use a child
block device (CONFIG_BLK). The final one is to use driver model for MMC
operations (CONFIG_DM_MMC_OP). Add support for this.
The immediate priority is to make all boards that use DM_MMC also use those
other two options. This will allow them to be removed.
Simon Glass [Mon, 13 Jun 2016 05:30:14 +0000 (23:30 -0600)]
rockchip: Use 'select' instead of defaults in Kconfig
Rockchip uses driver model for all subsystems. Specify this in the arm
Kconfig rather than as defaults in the Rockchip Kconfig. This means that
boards cannot turn these options off, which seems correct.
Andre Przywara [Fri, 8 Jul 2016 14:25:23 +0000 (15:25 +0100)]
doc: ARMv8: add README.pine64
Since we lack information about the DRAM initialization for the
Allwinner A64 SoC, booting any A64 based board like the Pine64 is a bit
involved at the moment.
Add a README file to explain the process.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Move to board/sunxi/ from doc/] Signed-off-by: Tom Rini <trini@konsulko.com>
Vignesh R [Wed, 6 Jul 2016 04:34:28 +0000 (10:04 +0530)]
dm: spi: Read default speed and mode values from DT
In case of DT boot, don't read default speed and mode for SPI from
CONFIG_*, instead read from DT node. This will make sure that boards
with multiple SPI/QSPI controllers can be probed at different
bus frequencies and SPI modes.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:56:03 +0000 (10:26 +0530)]
ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:50:57 +0000 (10:20 +0530)]
ARM: dts: K2G: Add support for QSPI controller
K2G SoC has a Cadence QSPI controller to communicate with NOR flash
devices. Add DT nodes to support the same.
Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor
flash slave node for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:50:56 +0000 (10:20 +0530)]
spi: cadence_quadspi: Enable QUAD mode based on DT data
Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine
whether to enable or disable QUAD mode. This is necessary to support
muliple SPI controllers where one of them may not support QUAD mode.
Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:50:55 +0000 (10:20 +0530)]
spi: cadence_qspi_apb: Support 32 bit AHB address
AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.
Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:29:05 +0000 (09:59 +0530)]
ARM: dts: k2g: add support for Davinci SPI controller
K2G SoC has 4 SPI instances that are compatible with davinci_spi
controller(present on previous generation of Keystone2 devices). Add DT
nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on
SPI-1. Add DT bindings for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:29:03 +0000 (09:59 +0530)]
ARM: dts: k2l: Enable Davinci SPI controller
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:29:01 +0000 (09:59 +0530)]
ARM: dts: k2e: Enable Davinci SPI controller
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:28:59 +0000 (09:58 +0530)]
ARM: dts: k2hk: Enable Davinci SPI controller
Now that davinci_spi driver has been converted to DM framework, enable
the same in DT. Also add "spi-flash" as compatible property to
n25q128a11 node as it is required for flash device to be probed in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Wed, 6 Jul 2016 04:28:55 +0000 (09:58 +0530)]
dm: core: implement dev_map_physmem()
This API helps to map physical register addresss pace of device to
virtual address space easily. Its just a wrapper around map_physmem()
with MAP_NOCACHE flag.
Signed-off-by: Vignesh R <vigneshr@ti.com> Suggested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
Mingkai Hu [Thu, 7 Jul 2016 04:22:12 +0000 (12:22 +0800)]
armv8: Enable CPUECTLR.SMPEN for coherency
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
test/py: support 'memstart =' in u_boot_utils.find_ram_base()
Some archs like MIPS or PPC have a different 'bdinfo' output
than ARM regarding the memory configuration. Also support
'memstart = 0x*' in u_boot_utils.find_ram_base() to make
all tests requiring the RAM base working on those archs.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Wed, 6 Jul 2016 16:34:30 +0000 (10:34 -0600)]
test/py: strip VT100 codes from match buffer
Prior to this patch, any VT100 codes emitted by U-Boot are considered part
of a command's output, which often causes tests to fail. For example,
test_env_echo_exists executes printenv, and then considers any text on a
line before an = sign as a valid U-Boot environment variable name. This
includes any VT100 codes emitted. When the test later attempts to use that
variable, the name would be invalid since it includes the VT100 codes.
Solve this by stripping VT100 codes from the match buffer, so they are
never seen by higher level test code.
The codes are still logged unmodified, so that users can expect U-Boot's
exact output without interference. This does clutter the log file a bit.
However, it allows users to see exactly what U-Boot emitted rather than a
modified version, which hopefully is better for debugging. It's also much
simpler to implement, since logging happens as soon as text is received,
and so stripping the VT100 codes from the log would require handling
reception and stripping of partial VT100 codes.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Alexander Graf [Tue, 5 Jul 2016 18:37:17 +0000 (20:37 +0200)]
arm: Fix setjmp (again)
Commit e677724 (arm: Fix setjmp) added code to fix compilation of the setjmp
code path with thumv1. Unfortunately it missed a constraint that the adr
instruction can only refer to 4 byte aligned offsets.
So this patch adds the required alignment hooks to make compilation
work again even when setjmp doesn't happen to be 4 byte aligned.
Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Tom Rini <trini@konsulko.com>
Andre Przywara [Fri, 8 Jul 2016 14:18:35 +0000 (15:18 +0100)]
SPL: tiny-printf: avoid any BSS usage
As printf calls may be executed quite early, we should avoid using any
BSS stored variables, since some boards put BSS in DRAM, which may not
have been initialised yet.
Explicitly mark those "static global" variables as belonging to the
.data section, to keep tiny-printf clear of any BSS usage.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Stephen Warren [Wed, 6 Jul 2016 15:04:08 +0000 (09:04 -0600)]
test/py: fix CONFIG_ tests
Some CONFIG_ variables were recently renamed, but test/py wasn't updated
to match. This causes some tests to be skipped. Fix test/py so the tests
are run.
Fixes: 11636258981a ("Rename reset to sysreset") Fixes: f1f9d4fac527 ("hush: complete renaming CONFIG_SYS_HUSH_PARSER to CONFIG_HUSH_PARSER") Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
York Sun [Wed, 6 Jul 2016 23:39:51 +0000 (16:39 -0700)]
powerpc: mpc85xx: kmp204x: Fix compiling error for usb errata
Commit 9262367 moves USB errata workaround into a C file. This
causes compiling error for kmcoge4 and kmlion1. To enable the
errata workaround, define CONFIG_USB_EHCI_FSL in common header.
Signed-off-by: York Sun <york.sun@nxp.com> Cc: Marek Vasut <marex@denx.de> Cc: Ed Swarthout <Ed.Swarthout@nxp.com> Cc: Sriram Dash <sriram.dash@nxp.com> Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")
net: rtl8169: Fix return value for rtl_send_common
Return value of rtl_send_common propogates unmodified all the way
up to eth_send and further to API consumer if CONFIG_API is enabled.
Previously rtl_send_common returned number of bytes sent on success
which was erroneouly detected as error condition by API consumers
that checked for operation success by comparing return value with 0.
Switch rtl_send_common to use common convention: return 0 on success
and negative value for failure.
Cc: Stephen Warren <swarren@nvidia.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
projects / people / ms / u-boot.git / log
