Masahiro Yamada [Fri, 13 Mar 2015 09:08:55 +0000 (18:08 +0900)]
kbuild: remove scripts/multiconfig.sh
We have switched to the single .config configuration system,
the same one as used in Linux Kernel.
The necessary glue code is small enough now, so move it to the
top-level Makefile and scripts/kconfig/Makefile, and then delete
scripts/multiconfig.sh.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Fri, 13 Mar 2015 09:08:54 +0000 (18:08 +0900)]
kbuild: remove "*_felconfig" target
This target was added by commit cbdd9a9737cc (sunxi: kconfig: Add
%_felconfig rule to enable FEL build of sunxi platforms.).
At that time, U-Boot used separate .config files for U-Boot proper
and SPL. I understood the pain to modify both .config and
spl/.config.
Now, we have switched to single .config configuration.
It seems acceptable to run "make menuconfig" or friends to enable
CONFIG_SPL_FEL, as we do for other CONFIGs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Iain Paton [Wed, 25 Mar 2015 16:03:26 +0000 (16:03 +0000)]
sunxi: axp209: fix incorrect limits on ldo3
board/sunxi/board.c tries to set ldo3 to 2.8v however drivers/power/axp209.c
contains an incorrect limit on ldo3 of 2.275v
The origin of the incorrect limit seems likely due to some inconsistencies
in the axp209 datasheet. ldo3 is described with different limits in
different sections. register 0x29 uses 7 bits for voltage configuration
while the 2.275v limit would apply if only 6 bits were used.
Probably this is a cut&paste error from register 0x23
The linux kernel driver has the correct limit and operation up to the 2.8v
required by my board has been physically verified with a multimeter.
Signed-off-by: Iain Paton <ipaton0@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Ian Campbell [Wed, 25 Mar 2015 13:39:05 +0000 (13:39 +0000)]
sunxi: set GMAC TX delay = 0x1 on Cubietruck.
Of 4 boards in our automated test system 2 do not have reliable
networking with the default TX delay of 0x0. Increasing to 0x1 seems
to make things reliable on all 4 boards.
Some previous ad-hpoc tests with tx delay set to 0, 1, 2 and 3 on one
of the problematic boards showed:
0: mw.l 0x1c20164 0x006 1 -- t/o in 4/5 tftp runs
1: mw.l 0x1c20164 0x406 1 -- t/o in 1/5 tftp runs
2: mw.l 0x1c20164 0x806 1 -- t/o in 1/5 tftp runs
3: mw.l 0x1c20164 0xc06 1 -- t/o many times in first tftp run
For 0, 1 and 2 "t/o" means one or two "T" glitches in the download,
but it did complete. For 3 those were basically continuous and it
couldn't complete.
tftp was of a 16M initrd.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Masahiro Yamada [Fri, 20 Mar 2015 04:24:45 +0000 (13:24 +0900)]
dm: serial: remove bogus include <ns16550.h>
Serial-uclass should be generically implemented without depending
a particular hardware. Fortunately, nothing in include/ns16550.h is
referenced from drivers/serial/serial-uclass.c, so remove this bogus
include.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
Sjoerd Simons [Wed, 25 Feb 2015 22:23:52 +0000 (23:23 +0100)]
config_distro_bootcmd.h: Prefer booting from bootable paritions
List bootable partitions and only scan those for bootable files, falling
back to partition 1 if there are no bootable partitions
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Sjoerd Simons [Wed, 25 Feb 2015 22:23:51 +0000 (23:23 +0100)]
config_cmd_default.h: Add 'env exists' command
env exists allows scripts to query whether an environment variable
exists. Enable by default as it adds only a trivial amount of code and
can be useful in scripts.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Bin Meng [Thu, 12 Mar 2015 05:08:46 +0000 (13:08 +0800)]
x86: Add ramboot and nfsboot commands in x86-common.h
It is very common in the debug stage to test U-Boot loading a linux
kernel. The commands to boot linux kernel with ramdisk and nfs as the
root are common to all x86 targets, so it makes sense to add them as
the U-Boot default environment in x86-common.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chroimum.org>
Bin Meng [Fri, 20 Mar 2015 09:12:20 +0000 (17:12 +0800)]
net: Add Intel Topcliff GMAC driver
Add a new driver for the Gigabit Ethernet MAC found on Intel Topcliff
Platform Controller Hub. Tested under 10/100 half/full duplex and 1000
full duplex modes using ping and tftpboot commands.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Bin Meng [Fri, 20 Mar 2015 09:12:18 +0000 (17:12 +0800)]
net: Add ethernet FCS length macro in net.h
Some ethernet drivers use their own version of ethernet FCS length
macro which is really common. We define ETH_FCS_LEN in net.h and
replace those custom versions in various places.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Bin Meng [Wed, 11 Mar 2015 03:25:56 +0000 (11:25 +0800)]
x86: quark: Enable on-chip ethernet controllers
Intel Quark SoC integrates two 10/100 ethernet controllers which can
be connected to an external RMII PHY. The MAC IP is from Designware.
Enable this support with the existing U-Boot Designware MAC driver
so that the ethernet port on Intel Galileo board can be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 5 Mar 2015 03:21:03 +0000 (11:21 +0800)]
x86: Add queensbay fsp patch information in README.x86
The FSP release version 001 for Intel Queensbay has a bug which
could cause random endless loop during the FspInit call. This bug
was published by Intel although Intel did not describe any details.
Describe this information in the x86 doc so that U-Boot Queensbay
support is invulnerable.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 19 Feb 2015 11:58:57 +0000 (06:58 -0500)]
arch/x86/cpu/quark/mrc.c: Switch to U_BOOT_DATE / U_BOOT_TIME
Using __DATE__ and __TIME__ results in an error due to -Werror=date-time
with gcc-4.9 (__DATE__ / __TIME__ might prevent reproducible builds) so
switch these over to U_BOOT_DATE / U_BOOT_TIME
Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 10 Mar 2015 10:31:20 +0000 (18:31 +0800)]
x86: quark: MRC codes clean up
This patch cleans up the quark MRC codes coding style by:
- Remove BIT0/1../31 defines from mrc_util.h
- Create names for the documented BITs and use them
- For undocumented single BITs, use (1 << n) directly
- For undocumented ORed BITs, use the hex number directly
- Remove redundancy parenthesis all over the codes
- Replace to use lower case hex numbers
Stephen Warren [Tue, 24 Mar 2015 05:00:25 +0000 (23:00 -0600)]
ARM: rpi: fix RPi1 board rev detection for warranty bit
Apparently the firmware's board rev response includes both the board
revision and some other data even on the RPi1. In particular, the
"warranty bit" is bit 24. We need to mask that out when looking up the
board ID.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
The callee (arch/arm/lib/cache-cp15.c) has a #ifdef
CONFIG_SYS_DCACHE_OFF conditional. The same conditional in the
caller (arch/arm/mach-uniphier/cache_uniphier.c) is redundant.
Masahiro Yamada [Sun, 22 Mar 2015 15:07:32 +0000 (00:07 +0900)]
ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot proper
The L2 cache is used as a temporary SRAM on SPL.
Now the secondary CPUs store the necessary code for jumping to
Linux on their L1 I-caches. So, the L2 cache can be disabled
much earlier, at the very entry of U-Boot proper (lowlevel_init).
This makes the boot sequence clearer.
Also, as the L1 cache has been disabled by the start.S,
enable_caches() does not need to do it again.
Currently, the secondary CPU(s) are kicked three times:
Boot ROM ---(kick)--> SPL ---(kick)--> U-boot ---(kick)--> Linux.
It makes the boot sequence very complicated.
This commit merges the first and the second kicks, so the secondary
CPU(s) can directly jump from SPL to Linux.
arch/arm/mach-uniphier/smp.S is no longer necessary.
Masahiro Yamada [Sun, 22 Mar 2015 15:07:25 +0000 (00:07 +0900)]
ARM: UniPhier: enable Driver Model and UART on SPL
Enable CONFIG_SPL_DM and CONFIG_SPL_SERIAL_SUPPORT, which provide
Driver Model UART support on SPL.
CONFIG_SYS_SPL_MALLOC_{START,SIZE} should be dropped because simple
malloc is preferred on SPL. Dlmalloc requires some static variables
on .data section that is not available yet for NOR boot mode etc.
Masahiro Yamada [Sun, 22 Mar 2015 15:07:21 +0000 (00:07 +0900)]
ARM: UniPhier: include PH1-LD4 Makefile from PH1-sLD8
The two Makefiles arch/arm/mach-uniphier/{ph1-ld4,ph1-sld8}/Makefile
are completely the same. We can improve the maintainability by
having one to include the other.
Masahiro Yamada [Mon, 16 Mar 2015 04:46:07 +0000 (13:46 +0900)]
ARM: UniPhier: remove unnecessary CONFIG_SYS_SOC
Since commit a86ac9540e20 (ARM: UniPhier: include <mach/*.h> instead
of <asm/arch/*.h>), UniPhier platform does not need the symbolic
link arch/arm/include/asm. This option is not necessary either.
Bo Shen [Wed, 4 Mar 2015 05:35:16 +0000 (13:35 +0800)]
Net: macb: reset GBE bit when fallback checking
If the GBE bit is set, when do next time autonegotiation,
if the result is not 1000Mbps, it will fallback to 100Mbps
checking. So, we need to clear the GBE bit.
Stefan Roese [Wed, 18 Mar 2015 08:30:54 +0000 (09:30 +0100)]
i2c: mvtwsi: Fix problem with baud rate calculation
The current implementation for baudrate calculation is incorrect.
This part from the formula:
"2 ^ (n + 1)" is not equivalent to (1 << n) but to (2 << n)!
This patch fixes this and moves this calculation to a function instead of using a macro.
This new function is taken from the Linux kernel.
This was detected and tested on the Marvell Armada A38x DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Heiko Schocher <hs@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com>
Matt Reimer [Mon, 23 Feb 2015 21:56:58 +0000 (14:56 -0700)]
mmc: sdhci: don't clobber adjacent registers
SDHCI_HOST_CONTROL is a byte-sized register, so don't write to it
as if it were a long, as that would result in clobbering the three
registers following.
Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
Masahiro Yamada [Thu, 12 Mar 2015 04:24:39 +0000 (13:24 +0900)]
kconfig: remove meaningless prefixes in defconfig files
Since commit e02ee2548afe (kconfig: switch to single .config
configuration), the prefixes in defconfig files such as "+S:",
"+ST:", etc., are meaningless.
This commit was generated by the following command:
find configs -name '*_defconfig' | xargs sed -i 's/^+*S*T*://'
Masahiro Yamada [Wed, 11 Mar 2015 08:34:25 +0000 (17:34 +0900)]
README: remove description about driver model configuration options (again)
The Driver Model description in README was removed by commit 65eb659e56fa (README: remove description about driver model
configuration options), and was revived by mistake by commit b79dadf846e5 when resolving the conflict.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Tue, 10 Mar 2015 21:40:58 +0000 (15:40 -0600)]
config_distro_bootcmd.h: add note on error handling
This should make it more clear why there appear to be C pre-processor
symbols in the file that contain mixed case. They're really error
messages.
Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Nishanth Menon [Mon, 9 Mar 2015 22:12:09 +0000 (17:12 -0500)]
ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
RX51 has a secure logic which uses different parameters compared to
traditional implementation. So, make the generic secure acr write
over-ride-able by board file and refactor rx51 code to use this.
While at it, enable the OMAP3 specific errata code for 454179, 430973,
621766.
Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Praveen Rao [Mon, 9 Mar 2015 22:12:06 +0000 (17:12 -0500)]
ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.
Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:12:03 +0000 (17:12 -0500)]
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.
While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:12:02 +0000 (17:12 -0500)]
ARM: Introduce erratum workaround for 621766
621766: Under a specific set of conditions, executing a sequence of
NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:12:01 +0000 (17:12 -0500)]
ARM: Introduce erratum workaround for 430973
430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:12:00 +0000 (17:12 -0500)]
ARM: Introduce erratum workaround for 454179
454179: Stale prediction may inhibit target address misprediction on
next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Mon, 9 Mar 2015 22:11:59 +0000 (17:11 -0500)]
ARM: Introduce erratum workaround for 798870
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 9 Mar 2015 16:40:36 +0000 (12:40 -0400)]
am335x_evm_usbspl: Remove other SPL modes
The purpose of this build target is to do SPL over USB RNDIS. We remove
YMODEM, MMC and NAND (and re-set ENV to be built-in) as when those are needed
we can use the other build targets. This brings us well under size limit again.
projects / people / ms / u-boot.git / log
