Jagan Teki [Fri, 25 Nov 2016 17:47:28 +0000 (23:17 +0530)]
MAINTAINERS: Fix ALTERA SOCFPGA Files
Replace arch/arm/cpu/armv7/socfpga/ path with
arch/arm/mach-socfpga/ and removed board file path
since board/altera has different boards with relevant
board maintainers.
Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@openedev.com>
Bill Randle [Sat, 19 Nov 2016 04:23:33 +0000 (20:23 -0800)]
qts-filter.sh: strip DOS line endings and handle continuation lines
Some Altera Quartus generated files have long lines that are split with a '\' at
the end of the line. It also wOn Windows, rites files in DOS format, which can
confuse some of the processing scripts in this file. This patch solves both issues.
Signed-off-by: Bill Randle <bill.randle@gmail.com> Cc: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 16 Nov 2016 16:20:23 +0000 (17:20 +0100)]
ARM: socfpga: Add boot0 hook to prevent SPL corruption
Valid Altera SoCFPGA preloader image must contain special data at
offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or
0x50. These addresses are by default used by U-Boot's vector table
and a piece of reset handler, thus a valid preloader corrupts those
addresses slightly. While this works most of the time, this can and
does prevent the board from rebooting sometimes and triggering this
issue may even depend on compiler.
The problem is that when SoCFPGA performs warm reset, it checks the
addresses 0x40..0x4b in SRAM for a valid preloader signature and
header checksum. If those are found, it jumps to address 0x4c or
0x50 (this is unclear). These addresses are populated by the first
few instructions of arch/arm/cpu/armv7/start.S:
Without this patch, the CPU will enter the code at 0xffff004c or
0xffff0050 , at which point the value of r0 and r1 registers is
undefined. Moreover, jumping directly to the preloader entry point
at address 0xffff0000 will also fail, because address 0xffff004.
is invalid and contains the preloader magic.
Add BOOT0 hook which reserves the area at offset 0x40..0x5f and
populates offset 0x50 with jump to the entry point. This way, the
preloader signature is stored in reserved space and can not corrupt
the SPL code.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Shengzhou Liu [Mon, 21 Nov 2016 03:36:48 +0000 (11:36 +0800)]
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
Stefan Roese [Thu, 1 Dec 2016 12:52:08 +0000 (13:52 +0100)]
travis-ci: Build mvebu boards (arm & aarch64) in separate job
Its easier to watch the output of the build process when the platforms
specific boards are grouped in a separate job. This patch adds a job
for all mvebu boards (arm and aarch64).
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
The LCDC controller on the lcdk board has high memory throughput
requirements. Even with the kernel-side tweaks to master peripheral
and peripheral bus burst priorities, the default PLL0 frquency of
300 MHz is not enough to service the LCD controller and causes
DMA FIFO underflows.
Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of
456 MHz - the same value that downstream reference u-boot from Texas
Instruments uses.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Yegor Yefremov [Thu, 1 Dec 2016 11:52:17 +0000 (12:52 +0100)]
arm: baltos: active mPCIe slot
Baltos devices provide a mPCIe slot, whose power is turned off by
default. This patch activates mPCIe slot in U-Boot, so that for example
GSM modem can be already available in user space.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
ARM: DRA7: AMxx: Make sure that the SPL always reads the configuration EEPROM
The bootrom may corrupt the area of SRAM used to store the ti_common_eeprom
structure. This patch makes sure that it's always read after a reset, even
if a valid MAGIC number is found in the SRAM.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Michal Simek [Thu, 1 Dec 2016 10:09:01 +0000 (11:09 +0100)]
dm: spl: mmc: Fix EXT SPL support
The patch
"dm: spl: mmc: Support CONFIG_BLK in SPL MMC"
(sha1: 87bce4e5c0b55452d70830928b2d7b98fa24d4e3)
converted FAT part of spl_mmc_do_fs_boot() but forget to update also EXT
part by 's/&mmc->block_dev/mmc_get_blk_desc(mmc)/'.
This patch is fixing compilation error when CONFIG_SPL_EXT_SUPPORT
is enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 11 Nov 2016 07:18:44 +0000 (08:18 +0100)]
arm64: mvebu: Restrict memory size to a usable maximum
Not all memory is mapped in the MMU. So we need to restrict the memory
size so that U-Boot does not try to access it. Also, the internal
registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB
are mapped for system memory. This is what we pass to the U-Boot
subsystem here.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
This patch adds PCI support to the Marvell Armada-8K devel board.
Additionally the Intel E1000 ethernet driver is enabled so that
network support is available on this board, even without the
internal network interfaces being supported (yet).
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 16:16:25 +0000 (18:16 +0200)]
drivers/phy: marvell: Add support for the slave CP COMPHY device
With the support for the Armada 8k, a 2nd COMPHY controller now needs
to get supported from the CP110 slave controller. This patch adds support
for this 2nd contoller in the COMPHY driver.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 16:12:40 +0000 (18:12 +0200)]
arm64: mvebu: Init COMPHY from the slave-CP on the A8k
The Armada8k implements 2 CPs (communication processors) and the 2nd
CP also is equipped with a COMPHY controller. This patch now loops
over all enabled MISC devices (CP110) enabled in the DT to initialize
all CPs.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 16:11:44 +0000 (18:11 +0200)]
arm64: mvebu: armada-8040-db.dts: Add I2C and SPI aliases
Add I2C and SPI aliases to enable usage in U-Boot. Otherwise U-Boot will
not be able to use the SPI NOR chip for environment storage and use
"i2c dev 0" to select this I2C bus.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
Since the cp110 slave also has comphy DT nodes, the names need to be
renamed to avoid a name clash. Lets use the common naming scheme:
"cpm_xxx" for master and "cps_xxx" for slave.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 09:47:51 +0000 (11:47 +0200)]
arm64: mvebu: Add support for the DB-88F8040 Armada 8k devel board
This patch adds the necessary files to support the Marvell Armada 8k
devel board. Most board specfic files are shared with the Armada 7k
boards under the name "armada-8k*". So only minimal changes are
necessary to add this basic board support (except the DT files of
course).
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 10:41:45 +0000 (12:41 +0200)]
arm64: mvebu: armada-8k: Only configure xHCI power on DB-88F7040 board
This patch uses of_machine_is_compatible() to detect the board at runtime
and only configured the I2C IO expander for the xHCI power / reset on
the DB-88F7040 board. As this code will be used by other Armada-7k/8k
ports, its necessary to use this runtime detection here.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
Stefan Roese [Tue, 25 Oct 2016 08:56:19 +0000 (10:56 +0200)]
arm64: mvebu: Rename db-88f7040 files to armada-8k
This moves some of the Armada DB-88F7040 board specific files to a more
generic name: armada-8k. This is in preparation for the Armada-8k
support which will be added soon. And since both platforms share
most devices, lets also share most source files to not duplicate
the code here.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
Simon Glass [Wed, 23 Nov 2016 13:34:43 +0000 (06:34 -0700)]
samsung: i2c: Split the high-speed I2C code into a new driver
Now that driver model is used for I2C on all boards, we can split the
high-speed code into its own driver. There is virtually no common code,
and this significantly reduces confusion.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 23 Nov 2016 13:34:40 +0000 (06:34 -0700)]
arm: exynos: i2c: Convert exynos boards to use DM_I2C
Three boards are still not converting to use DM_I2C. They are also using
the old PMIC framework. Rather than removing them, add #ifdefs to allow
them to continue to build. This will give the maintainers a little more
time to decide whether to convert them or not.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
Vignesh R [Tue, 22 Nov 2016 09:12:56 +0000 (14:42 +0530)]
defconfig: am43xx_evm: Enable DM_SPI and DM_SPI_FLASH
Commit 4c4e3b37750f3("ARM: AM43xx: Enable FIT") accidentally disabled
DM_SPI and DM_SPI_FLASH. Add back DM_SPI and DM_SPI_FLASH to
am43xx_evm_defconfig in order to make use of DM framework for QSPI.
Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Andrew F. Davis [Mon, 21 Nov 2016 20:37:09 +0000 (14:37 -0600)]
common: image: Remove FIT header update from image post-processing
After an image is selected out of a FIT blob for further processing we
run an optional, platform specific, post-processing function on this
component. This post-processing may modify the position and size of the
image, so after post-processing we update the location and size for this
image in the FIT header. This can cause problems as the position of
subsequent components in the FIT blob are only referenced by relative
position to the end of the last component. When we resize or move a
component the following components position will be calculated
incorrectly. To fix this, we do not update the FIT header but instead
only update our local understanding of the image data. This also allows
us to re-run post-processing steps if needed.
Signed-off-by: Andrew F. Davis <afd@ti.com> Tested-by: Carlos Hernandez <ceh@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Andre Przywara [Wed, 16 Nov 2016 00:50:10 +0000 (00:50 +0000)]
marvell: comphy_a3700: fix bitmask
Obviously the mask for the rx and tx select field cannot be right,
as it would overlap in one and exceed the 32-bit register in the other
case. From looking at the neighbouring bits it looks like the mask
should be really 4 bits wide instead of 8.
Pointed out by a GCC 6.2 (default) warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
Andre Przywara [Wed, 16 Nov 2016 00:50:06 +0000 (00:50 +0000)]
mtd: cfi_flash: fix indentation
The indentation is misleading here and suggests that the write command
will be only executed in the else clause.
It seems like this is not intended, so fix the indentation to avoid
both compiler warnings and puzzled readers.
Pointed out by GCC 6.2's -Wmisleading-indentation warning.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefan Roese <sr@denx.de>
Lokesh Vutla [Fri, 25 Nov 2016 05:44:26 +0000 (11:14 +0530)]
ti_armv7_common: env: Increase IO buffer size
There are certain environment variables whose length is greater than
the defined IO buffer size. So, increase the IO buffer size to print the
entire variables.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Steve Kipisz [Fri, 25 Nov 2016 05:44:24 +0000 (11:14 +0530)]
board: ti: am57xx: Add support for the am571x idk
The AM571x Industrial Development Kit (IDK) is a board based on TI's
AM571x SoC which has a single core 1.5GHz Cortex-A15processor. This
board is a development platform for the Industrial Market with:
- 1GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector
The PRU/ICSS will be supported by 3rd party software for EtherCat,
Profibus, and other Industrial protocols.
The link to the data sheet and TRM can be found here:
http://www.ti.com/product/AM5718
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Fri, 25 Nov 2016 05:44:23 +0000 (11:14 +0530)]
board: ti: am572x-idk: Update pinmux using latest PMT
Update the board pinmux for AM572x-IDK board using latest PMT[1] and the
board files named am572x_idk_v1p3b_sr2p0 that were autogenerated on
20th October, 2016 by "Steve Kipisz <s-kipisz2@ti.com>" and
"Tom Johnson <thjohnson@ti.com>".
Nishanth Menon [Fri, 25 Nov 2016 05:44:22 +0000 (11:14 +0530)]
board: ti: am572x: Add pinmux for X15/GPEVM SR2.0 using latest PMT
Update the board pinmux for AM572x-IDK board using latest PMT[1] and the
board files named am572x_gp_evm_A3a_sr2p0 that were autogenerated on
19th October, 2016 by "Ahmad Rashed<a-rashed@ti.com>".
Lokesh Vutla [Fri, 25 Nov 2016 05:44:20 +0000 (11:14 +0530)]
board: ti: am57xx: Add support for detection of X15 revb1
BeagleBoard-X15 Rev B1 with SR1.1 platform have incompatible changes for HDMI
GPIO requiring new dtb support. This implies we have to properly identify
the platform now as well. Hence provide a different board name for the
Rev B1 variants.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Fri, 25 Nov 2016 05:44:19 +0000 (11:14 +0530)]
board: ti: am57xx: Add support for detection of reva3 variations for GPEVM
AM57xx evm Rev A3 with SR2.0 platform have incompatible changes for HDMI
GPIO requiring new dtb support. This implies we have to properly identify
the platform now as well. Hence provide a different board name for the
Rev A3 variations.
Lokesh Vutla [Wed, 23 Nov 2016 07:55:28 +0000 (13:25 +0530)]
ARM: OMAP4+: Add support for getting pbias info from board
Palmas driver assumes it is always TPS659xx regulator on all DRA7xx based
boards to enable mmc regulator. This is not true always like in case of
DRA71x-evm. So get this information based on the board.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Delete omap4_vmmc_pbias_config from omap_hsmmc.c] Signed-off-by: Tom Rini <trini@konsulko.com>
Keerthy [Wed, 23 Nov 2016 07:55:27 +0000 (13:25 +0530)]
board: ti: dra71x-evm: Add PMIC support
Add the pmic_data for LP873x PMIC which is used to power
up dra71x-evm.
Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating
the efuse registers only to use OPP_NOM irrespective of any
CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined.
Nishanth Menon [Wed, 23 Nov 2016 07:55:26 +0000 (13:25 +0530)]
board: ti: dra72: Introduce optimization for rgmii timing for rev C
Rev C version of EVM does require IODelay to be configured for RGMII
pins in MANUAL_1 configuration. Update the same based on PG2.0 initial
simulation values.
Data based on PCT_DRA72x_SR2.0_SR1.0_v1.3.0.7
Lokesh Vutla [Wed, 23 Nov 2016 07:55:24 +0000 (13:25 +0530)]
board: ti: dra71x-evm: Add epprom support
The dra71x-evm is a board based on TI's DRA718 processor targeting BOM-optimized
entry infotainment systems such as display audio and is a software compatible
derivative of the highly successful DRA74 and DRA72 processor families.
More information can be found here[1].
Add epprom detection for dra71-evm.
[1] http://www.ti.com/product/dra718
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Suman Anna [Wed, 23 Nov 2016 07:24:41 +0000 (12:54 +0530)]
ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP
This patch adds support to update the device-tree blob to adjust the
DSP and IVA DPLL clocks pertinent to the selected OPP choice, with
the default being OPP_NOM. The voltage settings are done in u-boot,
but the actual clock configuration itself is done in kernel because
of the following reasons:
1. SoC definition constraints us to NOT to do dynamic voltage
scaling ever after the initial avs0 setting in bootloader
- so the voltage must be set in bootloader.
2. The voltage level must be set even if the IP blocks like
GPU/DSP are unused.
3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality,
and similar DPLL clock configuration code has been cleaned up in
v2014.10 u-boot release. See commit, 02c41535b6a4 ("ARM: OMAP4/5:
Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL").
The non-essential DPLLs are configured within the kernel during
the clock init step when parsing the device tree and creating
the clock devices. This approach meets both the u-boot and kernel
needs.
Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Subhajit Paul <subhajit_paul@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Suman Anna [Wed, 23 Nov 2016 07:24:40 +0000 (12:54 +0530)]
ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig
Redefine the macros used to define the voltage values and the
efuse register offsets based on OPP for all the voltage domains.
This is done using Kconfig macros that can be set in a defconfig
or selected during a config step. This allows a voltage domain
to be configured/set to a corresponding voltage value depending
on the OPP selection choice.
The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
voltage domains, with the MPU domain restricted to OPP_NOM. The
OPP_OD and OPP_HIGH options will be added when the support for
configuring the MPU clock frequency is added. The clock
configuration for other voltage domains is out of scope in
u-boot code.
The CORE voltage domain does not have separate voltage values
and efuse register offset at different OPPs, while the MPU
voltage domain only has different efuse register offsets for
different OPPs, but uses the same voltage value. Any different
choices of OPPs for voltage domains on common ganged-rails
is automatically taken care to select the corresponding
highest OPP voltage value.
Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Wed, 23 Nov 2016 07:24:39 +0000 (12:54 +0530)]
ARM: OMAP4+: Add support for dynamically selecting OPPs
It can be expected that different paper spins of a SoC can have
different definitions for OPP and can have their own constraints
on the boot up OPP for each voltage rail. In order to have this
flexibility, add support for dynamically selecting the OPP voltage
based on the board to handle any such exceptions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Yann E. MORIN [Sun, 13 Nov 2016 20:59:52 +0000 (21:59 +0100)]
cmd: move CMD_PXE to Kconfig
Currently, CMD_PXE is forcibly enabled in config_distro_defaults.h, so
that general purpose distributions can rely on it being defined. This
header is included, under conditions or not, by various archs or
famillies of archs / SoCs.
However, it is very possible that boards based on those SoCs will not
have a physical ethernet connector at all, even if the have a MAC; for
example, the Nanopi Neo AIR (sunxi H3) does not. It is also possible
that network booting is absolutely not necessary for a device.
However, it is not possible to disable the PXE command, as it is
forcibly enabled and is non-configurable.
But it turns out we already have a config option to build a distro-ready
image, in the name of DISTRO_DEFAULTS.
Move CMD_PXE out of the hard-coded config_distro_defaults.h into a
Kconfig option, that gets selected by DISTRO_DEFAULTS when it is set.
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Joe Hershberger <joe.hershberger@ni.com>
[trini: Make it select MENU, run moveconfig.py] Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 29 Nov 2016 14:14:57 +0000 (09:14 -0500)]
Enable DISTRO_DEFAULT on platforms that missed it before
A number of platforms had been using the distro default feature before
it was moved to Kconfig but did not enable the new Kconfig option when
it was enabled. This caused a regression in terms of features and this
introduces breakage when more things move to Kconfig.
secure_tee_install is used to install and initialize a secure TEE OS such as
Linaro OP-TEE into the secure world. This function takes in the address
where the signed TEE image is loaded as an argument. The signed TEE image
consists of a header (struct tee_header), TEE code+data followed by the
signature generated using image signing tool from TI security development
package (SECDEV). Refer to README.ti-secure for more information.
This function uses 2 new secure APIs.
1. PPA_SERV_HAL_TEE_LOAD_MASTER - Must be called on CPU Core 0. Protected
memory for TEE must be reserved before calling this function. This API
needs arguments filled into struct ppa_tee_load_info. The TEE image is
authenticated and if there are no errors, the control passes to the TEE
entry point.
2. PPA_SERV_HAL_TEE_LOAD_SLAVE - Called on other CPU cores only after
a TEE_LOAD_MASTER call. Takes no arguments. Checks if TEE was
successfully loaded (on core 0) and transfers control to the same TEE
entry point.
The code at TEE entry point is expected perform OS initialization steps
and return back to non-secure world (U-Boot).
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
arm: omap5: Add function to make an SMC call on cpu1
On DRA7xx platform, CPU Core 1 is not used in u-boot. However, in some
cases it is need to make secure API calls from Core 1. This patch adds
an assembly function to make a secure (SMC) call from CPU Core #1.
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Andrew F. Davis [Tue, 29 Nov 2016 22:33:20 +0000 (16:33 -0600)]
image: Add FIT image loadable section custom processing
To help automate the loading of custom image types we add the ability
to define custom handlers for the loadable section types. When we find
a compatible type while loading a "loadable" image from a FIT image we
run its associated handlers to perform any additional steps needed for
loading this image.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / people / ms / u-boot.git / log
