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(parent: c4f97b1) | patch
drivers/ddr/fsl: Fix timing_cfg_2 register
authorYork Sun <york.sun@nxp.com>
Thu, 19 May 2016 04:11:19 +0000 (21:11 -0700)
committerYork Sun <york.sun@nxp.com>
Fri, 3 Jun 2016 21:12:06 +0000 (14:12 -0700)
commit5605dc6135f6f26560ef3b0c6ebc5141c531179a
tree261ba20afcda83bd9e50ea82f9981eac9b151752tree | snapshot
parentc4f97b1f53a48ab52efc221b73a235797375fbfbcommit | diff
drivers/ddr/fsl: Fix timing_cfg_2 register

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.

Signed-off-by: York Sun <york.sun@nxp.com>
drivers/ddr/fsl/ctrl_regs.c diff | blob | blame | history
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