projects / people / pmueller / ipfire-2.x.git / blame
| Commit | Line | Data |
|---|---|---|
| 2cb7cef9 BS |
1 | Subject: xen3 x86 build fixes. |
| 2 | From: jbeulich@novell.com | |
| 3 | Patch-mainline: obsolete | |
| 4 | ||
| 82094b55 AF |
5 | --- sle11-2009-10-16.orig/arch/x86/kdb/kdba_bt.c 2009-10-16 14:48:16.000000000 +0200 |
| 6 | +++ sle11-2009-10-16/arch/x86/kdb/kdba_bt.c 2009-06-04 10:19:52.000000000 +0200 | |
| 2cb7cef9 BS |
7 | @@ -3196,6 +3196,9 @@ bb_usage_mov(const struct bb_operand *sr |
| 8 | bb_is_int_reg(dst->base_rc) && | |
| 9 | full_register_dst) { | |
| 10 | #ifdef CONFIG_X86_32 | |
| 11 | +#ifndef TSS_sysenter_sp0 | |
| 12 | +#define TSS_sysenter_sp0 SYSENTER_stack_sp0 | |
| 13 | +#endif | |
| 14 | /* mov from TSS_sysenter_sp0+offset to esp to fix up the | |
| 15 | * sysenter stack, it leaves esp well defined. mov | |
| 16 | * TSS_ysenter_sp0+offset(%esp),%esp is followed by up to 5 | |
| 82094b55 AF |
17 | --- sle11-2009-10-16.orig/arch/x86/kernel/cpu/intel_cacheinfo.c 2008-10-10 00:13:53.000000000 +0200 |
| 18 | +++ sle11-2009-10-16/arch/x86/kernel/cpu/intel_cacheinfo.c 2009-10-16 14:50:37.000000000 +0200 | |
| 19 | @@ -455,7 +455,7 @@ unsigned int __cpuinit init_intel_cachei | |
| 20 | static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info); | |
| 21 | #define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y])) | |
| 22 | ||
| 23 | -#ifdef CONFIG_SMP | |
| 24 | +#if defined(CONFIG_SMP) && !defined(CONFIG_XEN) | |
| 25 | static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index) | |
| 26 | { | |
| 27 | struct _cpuid4_info *this_leaf, *sibling_leaf; | |
| 28 | --- sle11-2009-10-16.orig/arch/x86/power/Makefile 2009-10-16 14:48:16.000000000 +0200 | |
| 29 | +++ sle11-2009-10-16/arch/x86/power/Makefile 2009-06-04 10:19:52.000000000 +0200 | |
| 2cb7cef9 BS |
30 | @@ -1,2 +1,4 @@ |
| 31 | obj-$(CONFIG_PM_SLEEP) += cpu_$(BITS).o | |
| 32 | obj-$(CONFIG_HIBERNATION) += hibernate_$(BITS).o hibernate_asm_$(BITS).o | |
| 33 | + | |
| 34 | +disabled-obj-$(CONFIG_XEN) := cpu_$(BITS).o | |
| 82094b55 AF |
35 | --- sle11-2009-10-16.orig/arch/x86/power/cpu_64.c 2008-11-25 12:35:54.000000000 +0100 |
| 36 | +++ sle11-2009-10-16/arch/x86/power/cpu_64.c 2009-06-04 10:19:52.000000000 +0200 | |
| 2cb7cef9 BS |
37 | @@ -135,7 +135,6 @@ void restore_processor_state(void) |
| 38 | ||
| 39 | static void fix_processor_context(void) | |
| 40 | { | |
| 41 | -#ifndef CONFIG_X86_NO_TSS | |
| 42 | int cpu = smp_processor_id(); | |
| 43 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
| 44 | ||
| 45 | @@ -147,7 +146,6 @@ static void fix_processor_context(void) | |
| 46 | set_tss_desc(cpu, t); | |
| 47 | ||
| 48 | get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9; | |
| 49 | -#endif | |
| 50 | ||
| 51 | syscall_init(); /* This sets MSR_*STAR and related */ | |
| 52 | load_TR_desc(); /* This does ltr */ |