d4cebf48395c982d97fa76bc2437fb730d01c0c8
[people/pmueller/ipfire-2.x.git] / src / r8101 / r8101.c
1 /*
2 * r8101.c: RealTek 8101 ethernet driver.
3 *
4 * This driver based on r8169 from Kernel 2.6.27.31
5 * All pciids except for 8101 are removed becaue we want use
6 * original realtek drivers except for 8101 because the
7 * vendors r8101 produce a kernel panic.
8 *
9 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
10 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
11 * Copyright (c) 2009 Arne Fitzenreiter <arne_f@ipfire.org>
12 * Copyright (c) a lot of people too. Please respect their work.
13 *
14 * See MAINTAINERS file for support contact information.
15 */
16
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/delay.h>
23 #include <linux/ethtool.h>
24 #include <linux/mii.h>
25 #include <linux/if_vlan.h>
26 #include <linux/crc32.h>
27 #include <linux/in.h>
28 #include <linux/ip.h>
29 #include <linux/tcp.h>
30 #include <linux/init.h>
31 #include <linux/dma-mapping.h>
32
33 #include <asm/system.h>
34 #include <asm/io.h>
35 #include <asm/irq.h>
36
37 #define RTL8101_VERSION "2.3LK-NAPI"
38 #define MODULENAME "r8101"
39 #define PFX MODULENAME ": "
40
41 #ifdef RTL8101_DEBUG
42 #define assert(expr) \
43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
47 #define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
49 #else
50 #define assert(expr) do {} while (0)
51 #define dprintk(fmt, args...) do {} while (0)
52 #endif /* RTL8101_DEBUG */
53
54 #define R8101_MSG_DEFAULT \
55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
56
57 #define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59
60 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
61 static const int max_interrupt_work = 20;
62
63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
65 static const int multicast_filter_limit = 32;
66
67 /* MAC address length */
68 #define MAC_ADDR_LEN 6
69
70 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
71 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
72 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77 #define R8101_REGS_SIZE 256
78 #define R8101_NAPI_WEIGHT 64
79 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
82 #define R8101_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8101_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85 #define RTL8101_TX_TIMEOUT (6*HZ)
86 #define RTL8101_PHY_TIMEOUT (10*HZ)
87
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
95
96 enum mac_version {
97 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
98 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
99 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
100 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
101 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
102 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
113 };
114
115 #define _R(NAME,MAC,MASK) \
116 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
117
118 static const struct {
119 const char *name;
120 u8 mac_version;
121 u32 RxConfigMask; /* Clears the bits supported by this chip */
122 } rtl_chip_info[] = {
123 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
124 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
125 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
126 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
127 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8169SCd
128 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8169SCe
129 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
130 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
131 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
132 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
133 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
134 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
135 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
136 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
137 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
138 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
139 };
140 #undef _R
141
142 enum cfg_version {
143 RTL_CFG_0 = 0x00,
144 RTL_CFG_1,
145 RTL_CFG_2
146 };
147
148 static void rtl_hw_start_8169(struct net_device *);
149 static void rtl_hw_start_8168(struct net_device *);
150 static void rtl_hw_start_8101(struct net_device *);
151
152 static struct pci_device_id rtl8101_pci_tbl[] = {
153 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
154 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
155 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
156 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
157 // { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
158 // { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
159 // { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
160 // { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
161 // { PCI_VENDOR_ID_LINKSYS, 0x1032,
162 // PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
163 { 0x0001, 0x8168,
164 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
165 {0,},
166 };
167
168 MODULE_DEVICE_TABLE(pci, rtl8101_pci_tbl);
169
170 static int rx_copybreak = 200;
171 static int use_dac;
172 static struct {
173 u32 msg_enable;
174 } debug = { -1 };
175
176 enum rtl_registers {
177 MAC0 = 0, /* Ethernet hardware address. */
178 MAC4 = 4,
179 MAR0 = 8, /* Multicast filter. */
180 CounterAddrLow = 0x10,
181 CounterAddrHigh = 0x14,
182 TxDescStartAddrLow = 0x20,
183 TxDescStartAddrHigh = 0x24,
184 TxHDescStartAddrLow = 0x28,
185 TxHDescStartAddrHigh = 0x2c,
186 FLASH = 0x30,
187 ERSR = 0x36,
188 ChipCmd = 0x37,
189 TxPoll = 0x38,
190 IntrMask = 0x3c,
191 IntrStatus = 0x3e,
192 TxConfig = 0x40,
193 RxConfig = 0x44,
194 RxMissed = 0x4c,
195 Cfg9346 = 0x50,
196 Config0 = 0x51,
197 Config1 = 0x52,
198 Config2 = 0x53,
199 Config3 = 0x54,
200 Config4 = 0x55,
201 Config5 = 0x56,
202 MultiIntr = 0x5c,
203 PHYAR = 0x60,
204 TBICSR = 0x64,
205 TBI_ANAR = 0x68,
206 TBI_LPAR = 0x6a,
207 PHYstatus = 0x6c,
208 RxMaxSize = 0xda,
209 CPlusCmd = 0xe0,
210 IntrMitigate = 0xe2,
211 RxDescAddrLow = 0xe4,
212 RxDescAddrHigh = 0xe8,
213 EarlyTxThres = 0xec,
214 FuncEvent = 0xf0,
215 FuncEventMask = 0xf4,
216 FuncPresetState = 0xf8,
217 FuncForceEvent = 0xfc,
218 };
219
220 enum rtl_register_content {
221 /* InterruptStatusBits */
222 SYSErr = 0x8000,
223 PCSTimeout = 0x4000,
224 SWInt = 0x0100,
225 TxDescUnavail = 0x0080,
226 RxFIFOOver = 0x0040,
227 LinkChg = 0x0020,
228 RxOverflow = 0x0010,
229 TxErr = 0x0008,
230 TxOK = 0x0004,
231 RxErr = 0x0002,
232 RxOK = 0x0001,
233
234 /* RxStatusDesc */
235 RxFOVF = (1 << 23),
236 RxRWT = (1 << 22),
237 RxRES = (1 << 21),
238 RxRUNT = (1 << 20),
239 RxCRC = (1 << 19),
240
241 /* ChipCmdBits */
242 CmdReset = 0x10,
243 CmdRxEnb = 0x08,
244 CmdTxEnb = 0x04,
245 RxBufEmpty = 0x01,
246
247 /* TXPoll register p.5 */
248 HPQ = 0x80, /* Poll cmd on the high prio queue */
249 NPQ = 0x40, /* Poll cmd on the low prio queue */
250 FSWInt = 0x01, /* Forced software interrupt */
251
252 /* Cfg9346Bits */
253 Cfg9346_Lock = 0x00,
254 Cfg9346_Unlock = 0xc0,
255
256 /* rx_mode_bits */
257 AcceptErr = 0x20,
258 AcceptRunt = 0x10,
259 AcceptBroadcast = 0x08,
260 AcceptMulticast = 0x04,
261 AcceptMyPhys = 0x02,
262 AcceptAllPhys = 0x01,
263
264 /* RxConfigBits */
265 RxCfgFIFOShift = 13,
266 RxCfgDMAShift = 8,
267
268 /* TxConfigBits */
269 TxInterFrameGapShift = 24,
270 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
271
272 /* Config1 register p.24 */
273 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
274 PMEnable = (1 << 0), /* Power Management Enable */
275
276 /* Config2 register p. 25 */
277 PCI_Clock_66MHz = 0x01,
278 PCI_Clock_33MHz = 0x00,
279
280 /* Config3 register p.25 */
281 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
282 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
283
284 /* Config5 register p.27 */
285 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
286 MWF = (1 << 5), /* Accept Multicast wakeup frame */
287 UWF = (1 << 4), /* Accept Unicast wakeup frame */
288 LanWake = (1 << 1), /* LanWake enable/disable */
289 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
290
291 /* TBICSR p.28 */
292 TBIReset = 0x80000000,
293 TBILoopback = 0x40000000,
294 TBINwEnable = 0x20000000,
295 TBINwRestart = 0x10000000,
296 TBILinkOk = 0x02000000,
297 TBINwComplete = 0x01000000,
298
299 /* CPlusCmd p.31 */
300 PktCntrDisable = (1 << 7), // 8168
301 RxVlan = (1 << 6),
302 RxChkSum = (1 << 5),
303 PCIDAC = (1 << 4),
304 PCIMulRW = (1 << 3),
305 INTT_0 = 0x0000, // 8168
306 INTT_1 = 0x0001, // 8168
307 INTT_2 = 0x0002, // 8168
308 INTT_3 = 0x0003, // 8168
309
310 /* rtl8101_PHYstatus */
311 TBI_Enable = 0x80,
312 TxFlowCtrl = 0x40,
313 RxFlowCtrl = 0x20,
314 _1000bpsF = 0x10,
315 _100bps = 0x08,
316 _10bps = 0x04,
317 LinkStatus = 0x02,
318 FullDup = 0x01,
319
320 /* _TBICSRBit */
321 TBILinkOK = 0x02000000,
322
323 /* DumpCounterCommand */
324 CounterDump = 0x8,
325 };
326
327 enum desc_status_bit {
328 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
329 RingEnd = (1 << 30), /* End of descriptor ring */
330 FirstFrag = (1 << 29), /* First segment of a packet */
331 LastFrag = (1 << 28), /* Final segment of a packet */
332
333 /* Tx private */
334 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
335 MSSShift = 16, /* MSS value position */
336 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
337 IPCS = (1 << 18), /* Calculate IP checksum */
338 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
339 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
340 TxVlanTag = (1 << 17), /* Add VLAN tag */
341
342 /* Rx private */
343 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
344 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
345
346 #define RxProtoUDP (PID1)
347 #define RxProtoTCP (PID0)
348 #define RxProtoIP (PID1 | PID0)
349 #define RxProtoMask RxProtoIP
350
351 IPFail = (1 << 16), /* IP checksum failed */
352 UDPFail = (1 << 15), /* UDP/IP checksum failed */
353 TCPFail = (1 << 14), /* TCP/IP checksum failed */
354 RxVlanTag = (1 << 16), /* VLAN tag available */
355 };
356
357 #define RsvdMask 0x3fffc000
358
359 struct TxDesc {
360 __le32 opts1;
361 __le32 opts2;
362 __le64 addr;
363 };
364
365 struct RxDesc {
366 __le32 opts1;
367 __le32 opts2;
368 __le64 addr;
369 };
370
371 struct ring_info {
372 struct sk_buff *skb;
373 u32 len;
374 u8 __pad[sizeof(void *) - sizeof(u32)];
375 };
376
377 enum features {
378 RTL_FEATURE_WOL = (1 << 0),
379 RTL_FEATURE_MSI = (1 << 1),
380 RTL_FEATURE_GMII = (1 << 2),
381 };
382
383 struct rtl8101_counters {
384 __le64 tx_packets;
385 __le64 rx_packets;
386 __le64 tx_errors;
387 __le32 rx_errors;
388 __le16 rx_missed;
389 __le16 align_errors;
390 __le32 tx_one_collision;
391 __le32 tx_multi_collision;
392 __le64 rx_unicast;
393 __le64 rx_broadcast;
394 __le32 rx_multicast;
395 __le16 tx_aborted;
396 __le16 tx_underun;
397 };
398
399 struct rtl8101_private {
400 void __iomem *mmio_addr; /* memory map physical address */
401 struct pci_dev *pci_dev; /* Index of PCI device */
402 struct net_device *dev;
403 struct napi_struct napi;
404 spinlock_t lock; /* spin lock flag */
405 u32 msg_enable;
406 int chipset;
407 int mac_version;
408 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
409 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
410 u32 dirty_rx;
411 u32 dirty_tx;
412 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
413 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
414 dma_addr_t TxPhyAddr;
415 dma_addr_t RxPhyAddr;
416 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
417 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
418 unsigned align;
419 unsigned rx_buf_sz;
420 struct timer_list timer;
421 u16 cp_cmd;
422 u16 intr_event;
423 u16 napi_event;
424 u16 intr_mask;
425 int phy_auto_nego_reg;
426 int phy_1000_ctrl_reg;
427 #ifdef CONFIG_R8101_VLAN
428 struct vlan_group *vlgrp;
429 #endif
430 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
431 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
432 void (*phy_reset_enable)(void __iomem *);
433 void (*hw_start)(struct net_device *);
434 unsigned int (*phy_reset_pending)(void __iomem *);
435 unsigned int (*link_ok)(void __iomem *);
436 struct delayed_work task;
437 unsigned features;
438
439 struct mii_if_info mii;
440 struct rtl8101_counters counters;
441 };
442
443 MODULE_AUTHOR("Realtek,the Linux r8169 crew & Arne Fitzenreiter <arne_f@ipfire.org>");
444 MODULE_DESCRIPTION("RealTek RTL-8101 Fast Ethernet driver");
445 module_param(rx_copybreak, int, 0);
446 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
447 module_param(use_dac, int, 0);
448 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
449 module_param_named(debug, debug.msg_enable, int, 0);
450 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
451 MODULE_LICENSE("GPL");
452 MODULE_VERSION(RTL8101_VERSION);
453
454 static int rtl8101_open(struct net_device *dev);
455 static int rtl8101_start_xmit(struct sk_buff *skb, struct net_device *dev);
456 static irqreturn_t rtl8101_interrupt(int irq, void *dev_instance);
457 static int rtl8101_init_ring(struct net_device *dev);
458 static void rtl_hw_start(struct net_device *dev);
459 static int rtl8101_close(struct net_device *dev);
460 static void rtl_set_rx_mode(struct net_device *dev);
461 static void rtl8101_tx_timeout(struct net_device *dev);
462 static struct net_device_stats *rtl8101_get_stats(struct net_device *dev);
463 static int rtl8101_rx_interrupt(struct net_device *, struct rtl8101_private *,
464 void __iomem *, u32 budget);
465 static int rtl8101_change_mtu(struct net_device *dev, int new_mtu);
466 static void rtl8101_down(struct net_device *dev);
467 static void rtl8101_rx_clear(struct rtl8101_private *tp);
468 static int rtl8101_poll(struct napi_struct *napi, int budget);
469
470 static const unsigned int rtl8101_rx_config =
471 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
472
473 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
474 {
475 int i;
476
477 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
478
479 for (i = 20; i > 0; i--) {
480 /*
481 * Check if the RTL8101 has completed writing to the specified
482 * MII register.
483 */
484 if (!(RTL_R32(PHYAR) & 0x80000000))
485 break;
486 udelay(25);
487 }
488 }
489
490 static int mdio_read(void __iomem *ioaddr, int reg_addr)
491 {
492 int i, value = -1;
493
494 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
495
496 for (i = 20; i > 0; i--) {
497 /*
498 * Check if the RTL8101 has completed retrieving data from
499 * the specified MII register.
500 */
501 if (RTL_R32(PHYAR) & 0x80000000) {
502 value = RTL_R32(PHYAR) & 0xffff;
503 break;
504 }
505 udelay(25);
506 }
507 return value;
508 }
509
510 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
511 int val)
512 {
513 struct rtl8101_private *tp = netdev_priv(dev);
514 void __iomem *ioaddr = tp->mmio_addr;
515
516 mdio_write(ioaddr, location, val);
517 }
518
519 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
520 {
521 struct rtl8101_private *tp = netdev_priv(dev);
522 void __iomem *ioaddr = tp->mmio_addr;
523
524 return mdio_read(ioaddr, location);
525 }
526
527 static void rtl8101_irq_mask_and_ack(void __iomem *ioaddr)
528 {
529 RTL_W16(IntrMask, 0x0000);
530
531 RTL_W16(IntrStatus, 0xffff);
532 }
533
534 static void rtl8101_asic_down(void __iomem *ioaddr)
535 {
536 RTL_W8(ChipCmd, 0x00);
537 rtl8101_irq_mask_and_ack(ioaddr);
538 RTL_R16(CPlusCmd);
539 }
540
541 static unsigned int rtl8101_tbi_reset_pending(void __iomem *ioaddr)
542 {
543 return RTL_R32(TBICSR) & TBIReset;
544 }
545
546 static unsigned int rtl8101_xmii_reset_pending(void __iomem *ioaddr)
547 {
548 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
549 }
550
551 static unsigned int rtl8101_tbi_link_ok(void __iomem *ioaddr)
552 {
553 return RTL_R32(TBICSR) & TBILinkOk;
554 }
555
556 static unsigned int rtl8101_xmii_link_ok(void __iomem *ioaddr)
557 {
558 return RTL_R8(PHYstatus) & LinkStatus;
559 }
560
561 static void rtl8101_tbi_reset_enable(void __iomem *ioaddr)
562 {
563 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
564 }
565
566 static void rtl8101_xmii_reset_enable(void __iomem *ioaddr)
567 {
568 unsigned int val;
569
570 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
571 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
572 }
573
574 static void rtl8101_check_link_status(struct net_device *dev,
575 struct rtl8101_private *tp,
576 void __iomem *ioaddr)
577 {
578 unsigned long flags;
579
580 spin_lock_irqsave(&tp->lock, flags);
581 if (tp->link_ok(ioaddr)) {
582 netif_carrier_on(dev);
583 if (netif_msg_ifup(tp))
584 printk(KERN_INFO PFX "%s: link up\n", dev->name);
585 } else {
586 if (netif_msg_ifdown(tp))
587 printk(KERN_INFO PFX "%s: link down\n", dev->name);
588 netif_carrier_off(dev);
589 }
590 spin_unlock_irqrestore(&tp->lock, flags);
591 }
592
593 static void rtl8101_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
594 {
595 struct rtl8101_private *tp = netdev_priv(dev);
596 void __iomem *ioaddr = tp->mmio_addr;
597 u8 options;
598
599 wol->wolopts = 0;
600
601 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
602 wol->supported = WAKE_ANY;
603
604 spin_lock_irq(&tp->lock);
605
606 options = RTL_R8(Config1);
607 if (!(options & PMEnable))
608 goto out_unlock;
609
610 options = RTL_R8(Config3);
611 if (options & LinkUp)
612 wol->wolopts |= WAKE_PHY;
613 if (options & MagicPacket)
614 wol->wolopts |= WAKE_MAGIC;
615
616 options = RTL_R8(Config5);
617 if (options & UWF)
618 wol->wolopts |= WAKE_UCAST;
619 if (options & BWF)
620 wol->wolopts |= WAKE_BCAST;
621 if (options & MWF)
622 wol->wolopts |= WAKE_MCAST;
623
624 out_unlock:
625 spin_unlock_irq(&tp->lock);
626 }
627
628 static int rtl8101_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
629 {
630 struct rtl8101_private *tp = netdev_priv(dev);
631 void __iomem *ioaddr = tp->mmio_addr;
632 unsigned int i;
633 static struct {
634 u32 opt;
635 u16 reg;
636 u8 mask;
637 } cfg[] = {
638 { WAKE_ANY, Config1, PMEnable },
639 { WAKE_PHY, Config3, LinkUp },
640 { WAKE_MAGIC, Config3, MagicPacket },
641 { WAKE_UCAST, Config5, UWF },
642 { WAKE_BCAST, Config5, BWF },
643 { WAKE_MCAST, Config5, MWF },
644 { WAKE_ANY, Config5, LanWake }
645 };
646
647 spin_lock_irq(&tp->lock);
648
649 RTL_W8(Cfg9346, Cfg9346_Unlock);
650
651 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
652 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
653 if (wol->wolopts & cfg[i].opt)
654 options |= cfg[i].mask;
655 RTL_W8(cfg[i].reg, options);
656 }
657
658 RTL_W8(Cfg9346, Cfg9346_Lock);
659
660 if (wol->wolopts)
661 tp->features |= RTL_FEATURE_WOL;
662 else
663 tp->features &= ~RTL_FEATURE_WOL;
664
665 spin_unlock_irq(&tp->lock);
666
667 return 0;
668 }
669
670 static void rtl8101_get_drvinfo(struct net_device *dev,
671 struct ethtool_drvinfo *info)
672 {
673 struct rtl8101_private *tp = netdev_priv(dev);
674
675 strcpy(info->driver, MODULENAME);
676 strcpy(info->version, RTL8101_VERSION);
677 strcpy(info->bus_info, pci_name(tp->pci_dev));
678 }
679
680 static int rtl8101_get_regs_len(struct net_device *dev)
681 {
682 return R8101_REGS_SIZE;
683 }
684
685 static int rtl8101_set_speed_tbi(struct net_device *dev,
686 u8 autoneg, u16 speed, u8 duplex)
687 {
688 struct rtl8101_private *tp = netdev_priv(dev);
689 void __iomem *ioaddr = tp->mmio_addr;
690 int ret = 0;
691 u32 reg;
692
693 reg = RTL_R32(TBICSR);
694 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
695 (duplex == DUPLEX_FULL)) {
696 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
697 } else if (autoneg == AUTONEG_ENABLE)
698 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
699 else {
700 if (netif_msg_link(tp)) {
701 printk(KERN_WARNING "%s: "
702 "incorrect speed setting refused in TBI mode\n",
703 dev->name);
704 }
705 ret = -EOPNOTSUPP;
706 }
707
708 return ret;
709 }
710
711 static int rtl8101_set_speed_xmii(struct net_device *dev,
712 u8 autoneg, u16 speed, u8 duplex)
713 {
714 struct rtl8101_private *tp = netdev_priv(dev);
715 void __iomem *ioaddr = tp->mmio_addr;
716 int auto_nego, giga_ctrl;
717
718 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
719 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
720 ADVERTISE_100HALF | ADVERTISE_100FULL);
721 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
722 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
723
724 if (autoneg == AUTONEG_ENABLE) {
725 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
726 ADVERTISE_100HALF | ADVERTISE_100FULL);
727 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
728 } else {
729 if (speed == SPEED_10)
730 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
731 else if (speed == SPEED_100)
732 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
733 else if (speed == SPEED_1000)
734 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
735
736 if (duplex == DUPLEX_HALF)
737 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
738
739 if (duplex == DUPLEX_FULL)
740 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
741
742 /* This tweak comes straight from Realtek's driver. */
743 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
744 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
745 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
746 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
747 }
748 }
749
750 /* The 8100e/8101e do Fast Ethernet only. */
751 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
752 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
753 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
754 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
755 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
756 netif_msg_link(tp)) {
757 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
758 dev->name);
759 }
760 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
761 }
762
763 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
764
765 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
766 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
767 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
768 /*
769 * Wake up the PHY.
770 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
771 */
772 mdio_write(ioaddr, 0x1f, 0x0000);
773 mdio_write(ioaddr, 0x0e, 0x0000);
774 }
775
776 tp->phy_auto_nego_reg = auto_nego;
777 tp->phy_1000_ctrl_reg = giga_ctrl;
778
779 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
780 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
781 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
782 return 0;
783 }
784
785 static int rtl8101_set_speed(struct net_device *dev,
786 u8 autoneg, u16 speed, u8 duplex)
787 {
788 struct rtl8101_private *tp = netdev_priv(dev);
789 int ret;
790
791 ret = tp->set_speed(dev, autoneg, speed, duplex);
792
793 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
794 mod_timer(&tp->timer, jiffies + RTL8101_PHY_TIMEOUT);
795
796 return ret;
797 }
798
799 static int rtl8101_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
800 {
801 struct rtl8101_private *tp = netdev_priv(dev);
802 unsigned long flags;
803 int ret;
804
805 spin_lock_irqsave(&tp->lock, flags);
806 ret = rtl8101_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
807 spin_unlock_irqrestore(&tp->lock, flags);
808
809 return ret;
810 }
811
812 static u32 rtl8101_get_rx_csum(struct net_device *dev)
813 {
814 struct rtl8101_private *tp = netdev_priv(dev);
815
816 return tp->cp_cmd & RxChkSum;
817 }
818
819 static int rtl8101_set_rx_csum(struct net_device *dev, u32 data)
820 {
821 struct rtl8101_private *tp = netdev_priv(dev);
822 void __iomem *ioaddr = tp->mmio_addr;
823 unsigned long flags;
824
825 spin_lock_irqsave(&tp->lock, flags);
826
827 if (data)
828 tp->cp_cmd |= RxChkSum;
829 else
830 tp->cp_cmd &= ~RxChkSum;
831
832 RTL_W16(CPlusCmd, tp->cp_cmd);
833 RTL_R16(CPlusCmd);
834
835 spin_unlock_irqrestore(&tp->lock, flags);
836
837 return 0;
838 }
839
840 #ifdef CONFIG_R8101_VLAN
841
842 static inline u32 rtl8101_tx_vlan_tag(struct rtl8101_private *tp,
843 struct sk_buff *skb)
844 {
845 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
846 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
847 }
848
849 static void rtl8101_vlan_rx_register(struct net_device *dev,
850 struct vlan_group *grp)
851 {
852 struct rtl8101_private *tp = netdev_priv(dev);
853 void __iomem *ioaddr = tp->mmio_addr;
854 unsigned long flags;
855
856 spin_lock_irqsave(&tp->lock, flags);
857 tp->vlgrp = grp;
858 if (tp->vlgrp)
859 tp->cp_cmd |= RxVlan;
860 else
861 tp->cp_cmd &= ~RxVlan;
862 RTL_W16(CPlusCmd, tp->cp_cmd);
863 RTL_R16(CPlusCmd);
864 spin_unlock_irqrestore(&tp->lock, flags);
865 }
866
867 static int rtl8101_rx_vlan_skb(struct rtl8101_private *tp, struct RxDesc *desc,
868 struct sk_buff *skb)
869 {
870 u32 opts2 = le32_to_cpu(desc->opts2);
871 struct vlan_group *vlgrp = tp->vlgrp;
872 int ret;
873
874 if (vlgrp && (opts2 & RxVlanTag)) {
875 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
876 ret = 0;
877 } else
878 ret = -1;
879 desc->opts2 = 0;
880 return ret;
881 }
882
883 #else /* !CONFIG_R8101_VLAN */
884
885 static inline u32 rtl8101_tx_vlan_tag(struct rtl8101_private *tp,
886 struct sk_buff *skb)
887 {
888 return 0;
889 }
890
891 static int rtl8101_rx_vlan_skb(struct rtl8101_private *tp, struct RxDesc *desc,
892 struct sk_buff *skb)
893 {
894 return -1;
895 }
896
897 #endif
898
899 static int rtl8101_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
900 {
901 struct rtl8101_private *tp = netdev_priv(dev);
902 void __iomem *ioaddr = tp->mmio_addr;
903 u32 status;
904
905 cmd->supported =
906 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
907 cmd->port = PORT_FIBRE;
908 cmd->transceiver = XCVR_INTERNAL;
909
910 status = RTL_R32(TBICSR);
911 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
912 cmd->autoneg = !!(status & TBINwEnable);
913
914 cmd->speed = SPEED_1000;
915 cmd->duplex = DUPLEX_FULL; /* Always set */
916
917 return 0;
918 }
919
920 static int rtl8101_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
921 {
922 struct rtl8101_private *tp = netdev_priv(dev);
923
924 return mii_ethtool_gset(&tp->mii, cmd);
925 }
926
927 static int rtl8101_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
928 {
929 struct rtl8101_private *tp = netdev_priv(dev);
930 unsigned long flags;
931 int rc;
932
933 spin_lock_irqsave(&tp->lock, flags);
934
935 rc = tp->get_settings(dev, cmd);
936
937 spin_unlock_irqrestore(&tp->lock, flags);
938 return rc;
939 }
940
941 static void rtl8101_get_regs(struct net_device *dev, struct ethtool_regs *regs,
942 void *p)
943 {
944 struct rtl8101_private *tp = netdev_priv(dev);
945 unsigned long flags;
946
947 if (regs->len > R8101_REGS_SIZE)
948 regs->len = R8101_REGS_SIZE;
949
950 spin_lock_irqsave(&tp->lock, flags);
951 memcpy_fromio(p, tp->mmio_addr, regs->len);
952 spin_unlock_irqrestore(&tp->lock, flags);
953 }
954
955 static u32 rtl8101_get_msglevel(struct net_device *dev)
956 {
957 struct rtl8101_private *tp = netdev_priv(dev);
958
959 return tp->msg_enable;
960 }
961
962 static void rtl8101_set_msglevel(struct net_device *dev, u32 value)
963 {
964 struct rtl8101_private *tp = netdev_priv(dev);
965
966 tp->msg_enable = value;
967 }
968
969 static const char rtl8101_gstrings[][ETH_GSTRING_LEN] = {
970 "tx_packets",
971 "rx_packets",
972 "tx_errors",
973 "rx_errors",
974 "rx_missed",
975 "align_errors",
976 "tx_single_collisions",
977 "tx_multi_collisions",
978 "unicast",
979 "broadcast",
980 "multicast",
981 "tx_aborted",
982 "tx_underrun",
983 };
984
985 static int rtl8101_get_sset_count(struct net_device *dev, int sset)
986 {
987 switch (sset) {
988 case ETH_SS_STATS:
989 return ARRAY_SIZE(rtl8101_gstrings);
990 default:
991 return -EOPNOTSUPP;
992 }
993 }
994
995 static void rtl8101_update_counters(struct net_device *dev)
996 {
997 struct rtl8101_private *tp = netdev_priv(dev);
998 void __iomem *ioaddr = tp->mmio_addr;
999 struct rtl8101_counters *counters;
1000 dma_addr_t paddr;
1001 u32 cmd;
1002 int wait = 1000;
1003
1004 /*
1005 * Some chips are unable to dump tally counters when the receiver
1006 * is disabled.
1007 */
1008 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1009 return;
1010
1011 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1012 if (!counters)
1013 return;
1014
1015 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1016 cmd = (u64)paddr & DMA_32BIT_MASK;
1017 RTL_W32(CounterAddrLow, cmd);
1018 RTL_W32(CounterAddrLow, cmd | CounterDump);
1019
1020 while (wait--) {
1021 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1022 /* copy updated counters */
1023 memcpy(&tp->counters, counters, sizeof(*counters));
1024 break;
1025 }
1026 udelay(10);
1027 }
1028
1029 RTL_W32(CounterAddrLow, 0);
1030 RTL_W32(CounterAddrHigh, 0);
1031
1032 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1033 }
1034
1035 static void rtl8101_get_ethtool_stats(struct net_device *dev,
1036 struct ethtool_stats *stats, u64 *data)
1037 {
1038 struct rtl8101_private *tp = netdev_priv(dev);
1039
1040 ASSERT_RTNL();
1041
1042 rtl8101_update_counters(dev);
1043
1044 data[0] = le64_to_cpu(tp->counters.tx_packets);
1045 data[1] = le64_to_cpu(tp->counters.rx_packets);
1046 data[2] = le64_to_cpu(tp->counters.tx_errors);
1047 data[3] = le32_to_cpu(tp->counters.rx_errors);
1048 data[4] = le16_to_cpu(tp->counters.rx_missed);
1049 data[5] = le16_to_cpu(tp->counters.align_errors);
1050 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1051 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1052 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1053 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1054 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1055 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1056 data[12] = le16_to_cpu(tp->counters.tx_underun);
1057 }
1058
1059 static void rtl8101_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1060 {
1061 switch(stringset) {
1062 case ETH_SS_STATS:
1063 memcpy(data, *rtl8101_gstrings, sizeof(rtl8101_gstrings));
1064 break;
1065 }
1066 }
1067
1068 static const struct ethtool_ops rtl8101_ethtool_ops = {
1069 .get_drvinfo = rtl8101_get_drvinfo,
1070 .get_regs_len = rtl8101_get_regs_len,
1071 .get_link = ethtool_op_get_link,
1072 .get_settings = rtl8101_get_settings,
1073 .set_settings = rtl8101_set_settings,
1074 .get_msglevel = rtl8101_get_msglevel,
1075 .set_msglevel = rtl8101_set_msglevel,
1076 .get_rx_csum = rtl8101_get_rx_csum,
1077 .set_rx_csum = rtl8101_set_rx_csum,
1078 .set_tx_csum = ethtool_op_set_tx_csum,
1079 .set_sg = ethtool_op_set_sg,
1080 .set_tso = ethtool_op_set_tso,
1081 .get_regs = rtl8101_get_regs,
1082 .get_wol = rtl8101_get_wol,
1083 .set_wol = rtl8101_set_wol,
1084 .get_strings = rtl8101_get_strings,
1085 .get_sset_count = rtl8101_get_sset_count,
1086 .get_ethtool_stats = rtl8101_get_ethtool_stats,
1087 };
1088
1089 static void rtl8101_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1090 int bitnum, int bitval)
1091 {
1092 int val;
1093
1094 val = mdio_read(ioaddr, reg);
1095 val = (bitval == 1) ?
1096 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1097 mdio_write(ioaddr, reg, val & 0xffff);
1098 }
1099
1100 static void rtl8101_get_mac_version(struct rtl8101_private *tp,
1101 void __iomem *ioaddr)
1102 {
1103 /*
1104 * The driver currently handles the 8168Bf and the 8168Be identically
1105 * but they can be identified more specifically through the test below
1106 * if needed:
1107 *
1108 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1109 *
1110 * Same thing for the 8101Eb and the 8101Ec:
1111 *
1112 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1113 */
1114 const struct {
1115 u32 mask;
1116 u32 val;
1117 int mac_version;
1118 } mac_info[] = {
1119 /* 8168B family. */
1120 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1121 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1122 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1123 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1124
1125 /* 8168B family. */
1126 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1127 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1128 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1129 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1130
1131 /* 8101 family. */
1132 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1133 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1134 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1135 /* FIXME: where did these entries come from ? -- FR */
1136 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1137 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1138
1139 /* 8110 family. */
1140 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1141 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1142 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1143 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1144 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1145 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1146
1147 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1148 }, *p = mac_info;
1149 u32 reg;
1150
1151 reg = RTL_R32(TxConfig);
1152 while ((reg & p->mask) != p->val)
1153 p++;
1154 tp->mac_version = p->mac_version;
1155
1156 if (p->mask == 0x00000000) {
1157 struct pci_dev *pdev = tp->pci_dev;
1158
1159 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1160 }
1161 }
1162
1163 static void rtl8101_print_mac_version(struct rtl8101_private *tp)
1164 {
1165 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1166 }
1167
1168 struct phy_reg {
1169 u16 reg;
1170 u16 val;
1171 };
1172
1173 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1174 {
1175 while (len-- > 0) {
1176 mdio_write(ioaddr, regs->reg, regs->val);
1177 regs++;
1178 }
1179 }
1180
1181 static void rtl8101s_hw_phy_config(void __iomem *ioaddr)
1182 {
1183 struct {
1184 u16 regs[5]; /* Beware of bit-sign propagation */
1185 } phy_magic[5] = { {
1186 { 0x0000, //w 4 15 12 0
1187 0x00a1, //w 3 15 0 00a1
1188 0x0008, //w 2 15 0 0008
1189 0x1020, //w 1 15 0 1020
1190 0x1000 } },{ //w 0 15 0 1000
1191 { 0x7000, //w 4 15 12 7
1192 0xff41, //w 3 15 0 ff41
1193 0xde60, //w 2 15 0 de60
1194 0x0140, //w 1 15 0 0140
1195 0x0077 } },{ //w 0 15 0 0077
1196 { 0xa000, //w 4 15 12 a
1197 0xdf01, //w 3 15 0 df01
1198 0xdf20, //w 2 15 0 df20
1199 0xff95, //w 1 15 0 ff95
1200 0xfa00 } },{ //w 0 15 0 fa00
1201 { 0xb000, //w 4 15 12 b
1202 0xff41, //w 3 15 0 ff41
1203 0xde20, //w 2 15 0 de20
1204 0x0140, //w 1 15 0 0140
1205 0x00bb } },{ //w 0 15 0 00bb
1206 { 0xf000, //w 4 15 12 f
1207 0xdf01, //w 3 15 0 df01
1208 0xdf20, //w 2 15 0 df20
1209 0xff95, //w 1 15 0 ff95
1210 0xbf00 } //w 0 15 0 bf00
1211 }
1212 }, *p = phy_magic;
1213 unsigned int i;
1214
1215 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1216 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1217 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1218 rtl8101_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1219
1220 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1221 int val, pos = 4;
1222
1223 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1224 mdio_write(ioaddr, pos, val);
1225 while (--pos >= 0)
1226 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1227 rtl8101_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1228 rtl8101_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1229 }
1230 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1231 }
1232
1233 static void rtl8101sb_hw_phy_config(void __iomem *ioaddr)
1234 {
1235 struct phy_reg phy_reg_init[] = {
1236 { 0x1f, 0x0002 },
1237 { 0x01, 0x90d0 },
1238 { 0x1f, 0x0000 }
1239 };
1240
1241 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1242 }
1243
1244 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1245 {
1246 struct phy_reg phy_reg_init[] = {
1247 { 0x1f, 0x0000 },
1248 { 0x1d, 0x0f00 },
1249 { 0x1f, 0x0002 },
1250 { 0x0c, 0x1ec8 },
1251 { 0x1f, 0x0000 }
1252 };
1253
1254 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1255 }
1256
1257 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1258 {
1259 struct phy_reg phy_reg_init[] = {
1260 { 0x1f, 0x0001 },
1261 { 0x12, 0x2300 },
1262 { 0x1f, 0x0002 },
1263 { 0x00, 0x88d4 },
1264 { 0x01, 0x82b1 },
1265 { 0x03, 0x7002 },
1266 { 0x08, 0x9e30 },
1267 { 0x09, 0x01f0 },
1268 { 0x0a, 0x5500 },
1269 { 0x0c, 0x00c8 },
1270 { 0x1f, 0x0003 },
1271 { 0x12, 0xc096 },
1272 { 0x16, 0x000a },
1273 { 0x1f, 0x0000 }
1274 };
1275
1276 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1277 }
1278
1279 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1280 {
1281 struct phy_reg phy_reg_init[] = {
1282 { 0x1f, 0x0000 },
1283 { 0x12, 0x2300 },
1284 { 0x1f, 0x0003 },
1285 { 0x16, 0x0f0a },
1286 { 0x1f, 0x0000 },
1287 { 0x1f, 0x0002 },
1288 { 0x0c, 0x7eb8 },
1289 { 0x1f, 0x0000 }
1290 };
1291
1292 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1293 }
1294
1295 static void rtl_hw_phy_config(struct net_device *dev)
1296 {
1297 struct rtl8101_private *tp = netdev_priv(dev);
1298 void __iomem *ioaddr = tp->mmio_addr;
1299
1300 rtl8101_print_mac_version(tp);
1301
1302 switch (tp->mac_version) {
1303 case RTL_GIGA_MAC_VER_01:
1304 break;
1305 case RTL_GIGA_MAC_VER_02:
1306 case RTL_GIGA_MAC_VER_03:
1307 rtl8101s_hw_phy_config(ioaddr);
1308 break;
1309 case RTL_GIGA_MAC_VER_04:
1310 rtl8101sb_hw_phy_config(ioaddr);
1311 break;
1312 case RTL_GIGA_MAC_VER_18:
1313 rtl8168cp_hw_phy_config(ioaddr);
1314 break;
1315 case RTL_GIGA_MAC_VER_19:
1316 rtl8168c_hw_phy_config(ioaddr);
1317 break;
1318 case RTL_GIGA_MAC_VER_20:
1319 rtl8168cx_hw_phy_config(ioaddr);
1320 break;
1321 default:
1322 break;
1323 }
1324 }
1325
1326 static void rtl8101_phy_timer(unsigned long __opaque)
1327 {
1328 struct net_device *dev = (struct net_device *)__opaque;
1329 struct rtl8101_private *tp = netdev_priv(dev);
1330 struct timer_list *timer = &tp->timer;
1331 void __iomem *ioaddr = tp->mmio_addr;
1332 unsigned long timeout = RTL8101_PHY_TIMEOUT;
1333
1334 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1335
1336 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1337 return;
1338
1339 spin_lock_irq(&tp->lock);
1340
1341 if (tp->phy_reset_pending(ioaddr)) {
1342 /*
1343 * A busy loop could burn quite a few cycles on nowadays CPU.
1344 * Let's delay the execution of the timer for a few ticks.
1345 */
1346 timeout = HZ/10;
1347 goto out_mod_timer;
1348 }
1349
1350 if (tp->link_ok(ioaddr))
1351 goto out_unlock;
1352
1353 if (netif_msg_link(tp))
1354 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1355
1356 tp->phy_reset_enable(ioaddr);
1357
1358 out_mod_timer:
1359 mod_timer(timer, jiffies + timeout);
1360 out_unlock:
1361 spin_unlock_irq(&tp->lock);
1362 }
1363
1364 static inline void rtl8101_delete_timer(struct net_device *dev)
1365 {
1366 struct rtl8101_private *tp = netdev_priv(dev);
1367 struct timer_list *timer = &tp->timer;
1368
1369 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1370 return;
1371
1372 del_timer_sync(timer);
1373 }
1374
1375 static inline void rtl8101_request_timer(struct net_device *dev)
1376 {
1377 struct rtl8101_private *tp = netdev_priv(dev);
1378 struct timer_list *timer = &tp->timer;
1379
1380 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1381 return;
1382
1383 mod_timer(timer, jiffies + RTL8101_PHY_TIMEOUT);
1384 }
1385
1386 #ifdef CONFIG_NET_POLL_CONTROLLER
1387 /*
1388 * Polling 'interrupt' - used by things like netconsole to send skbs
1389 * without having to re-enable interrupts. It's not called while
1390 * the interrupt routine is executing.
1391 */
1392 static void rtl8101_netpoll(struct net_device *dev)
1393 {
1394 struct rtl8101_private *tp = netdev_priv(dev);
1395 struct pci_dev *pdev = tp->pci_dev;
1396
1397 disable_irq(pdev->irq);
1398 rtl8101_interrupt(pdev->irq, dev);
1399 enable_irq(pdev->irq);
1400 }
1401 #endif
1402
1403 static void rtl8101_release_board(struct pci_dev *pdev, struct net_device *dev,
1404 void __iomem *ioaddr)
1405 {
1406 iounmap(ioaddr);
1407 pci_release_regions(pdev);
1408 pci_disable_device(pdev);
1409 free_netdev(dev);
1410 }
1411
1412 static void rtl8101_phy_reset(struct net_device *dev,
1413 struct rtl8101_private *tp)
1414 {
1415 void __iomem *ioaddr = tp->mmio_addr;
1416 unsigned int i;
1417
1418 tp->phy_reset_enable(ioaddr);
1419 for (i = 0; i < 100; i++) {
1420 if (!tp->phy_reset_pending(ioaddr))
1421 return;
1422 msleep(1);
1423 }
1424 if (netif_msg_link(tp))
1425 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1426 }
1427
1428 static void rtl8101_init_phy(struct net_device *dev, struct rtl8101_private *tp)
1429 {
1430 void __iomem *ioaddr = tp->mmio_addr;
1431
1432 rtl_hw_phy_config(dev);
1433
1434 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1435 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1436 RTL_W8(0x82, 0x01);
1437 }
1438
1439 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1440
1441 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1442 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1443
1444 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1445 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1446 RTL_W8(0x82, 0x01);
1447 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1448 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1449 }
1450
1451 rtl8101_phy_reset(dev, tp);
1452
1453 /*
1454 * rtl8101_set_speed_xmii takes good care of the Fast Ethernet
1455 * only 8101. Don't panic.
1456 */
1457 rtl8101_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1458
1459 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1460 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1461 }
1462
1463 static void rtl_rar_set(struct rtl8101_private *tp, u8 *addr)
1464 {
1465 void __iomem *ioaddr = tp->mmio_addr;
1466 u32 high;
1467 u32 low;
1468
1469 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1470 high = addr[4] | (addr[5] << 8);
1471
1472 spin_lock_irq(&tp->lock);
1473
1474 RTL_W8(Cfg9346, Cfg9346_Unlock);
1475 RTL_W32(MAC0, low);
1476 RTL_W32(MAC4, high);
1477 RTL_W8(Cfg9346, Cfg9346_Lock);
1478
1479 spin_unlock_irq(&tp->lock);
1480 }
1481
1482 static int rtl_set_mac_address(struct net_device *dev, void *p)
1483 {
1484 struct rtl8101_private *tp = netdev_priv(dev);
1485 struct sockaddr *addr = p;
1486
1487 if (!is_valid_ether_addr(addr->sa_data))
1488 return -EADDRNOTAVAIL;
1489
1490 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1491
1492 rtl_rar_set(tp, dev->dev_addr);
1493
1494 return 0;
1495 }
1496
1497 static int rtl8101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1498 {
1499 struct rtl8101_private *tp = netdev_priv(dev);
1500 struct mii_ioctl_data *data = if_mii(ifr);
1501
1502 if (!netif_running(dev))
1503 return -ENODEV;
1504
1505 switch (cmd) {
1506 case SIOCGMIIPHY:
1507 data->phy_id = 32; /* Internal PHY */
1508 return 0;
1509
1510 case SIOCGMIIREG:
1511 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1512 return 0;
1513
1514 case SIOCSMIIREG:
1515 if (!capable(CAP_NET_ADMIN))
1516 return -EPERM;
1517 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1518 return 0;
1519 }
1520 return -EOPNOTSUPP;
1521 }
1522
1523 static const struct rtl_cfg_info {
1524 void (*hw_start)(struct net_device *);
1525 unsigned int region;
1526 unsigned int align;
1527 u16 intr_event;
1528 u16 napi_event;
1529 unsigned features;
1530 } rtl_cfg_infos [] = {
1531 [RTL_CFG_0] = {
1532 .hw_start = rtl_hw_start_8169,
1533 .region = 1,
1534 .align = 0,
1535 .intr_event = SYSErr | LinkChg | RxOverflow |
1536 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1537 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1538 .features = RTL_FEATURE_GMII
1539 },
1540 [RTL_CFG_1] = {
1541 .hw_start = rtl_hw_start_8168,
1542 .region = 2,
1543 .align = 8,
1544 .intr_event = SYSErr | LinkChg | RxOverflow |
1545 TxErr | TxOK | RxOK | RxErr,
1546 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1547 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1548 },
1549 [RTL_CFG_2] = {
1550 .hw_start = rtl_hw_start_8101,
1551 .region = 2,
1552 .align = 8,
1553 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1554 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1555 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1556 .features = RTL_FEATURE_MSI
1557 }
1558 };
1559
1560 /* Cfg9346_Unlock assumed. */
1561 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1562 const struct rtl_cfg_info *cfg)
1563 {
1564 unsigned msi = 0;
1565 u8 cfg2;
1566
1567 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1568 if (cfg->features & RTL_FEATURE_MSI) {
1569 if (pci_enable_msi(pdev)) {
1570 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1571 } else {
1572 cfg2 |= MSIEnable;
1573 msi = RTL_FEATURE_MSI;
1574 }
1575 }
1576 RTL_W8(Config2, cfg2);
1577 return msi;
1578 }
1579
1580 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8101_private *tp)
1581 {
1582 if (tp->features & RTL_FEATURE_MSI) {
1583 pci_disable_msi(pdev);
1584 tp->features &= ~RTL_FEATURE_MSI;
1585 }
1586 }
1587
1588 static int __devinit
1589 rtl8101_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1590 {
1591 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1592 const unsigned int region = cfg->region;
1593 struct rtl8101_private *tp;
1594 struct mii_if_info *mii;
1595 struct net_device *dev;
1596 void __iomem *ioaddr;
1597 unsigned int i;
1598 int rc;
1599
1600 if (netif_msg_drv(&debug)) {
1601 printk(KERN_INFO "%s Fast Ethernet driver %s loaded\n",
1602 MODULENAME, RTL8101_VERSION);
1603 }
1604
1605 dev = alloc_etherdev(sizeof (*tp));
1606 if (!dev) {
1607 if (netif_msg_drv(&debug))
1608 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1609 rc = -ENOMEM;
1610 goto out;
1611 }
1612
1613 SET_NETDEV_DEV(dev, &pdev->dev);
1614 tp = netdev_priv(dev);
1615 tp->dev = dev;
1616 tp->pci_dev = pdev;
1617 tp->msg_enable = netif_msg_init(debug.msg_enable, R8101_MSG_DEFAULT);
1618
1619 mii = &tp->mii;
1620 mii->dev = dev;
1621 mii->mdio_read = rtl_mdio_read;
1622 mii->mdio_write = rtl_mdio_write;
1623 mii->phy_id_mask = 0x1f;
1624 mii->reg_num_mask = 0x1f;
1625 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1626
1627 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1628 rc = pci_enable_device(pdev);
1629 if (rc < 0) {
1630 if (netif_msg_probe(tp))
1631 dev_err(&pdev->dev, "enable failure\n");
1632 goto err_out_free_dev_1;
1633 }
1634
1635 rc = pci_set_mwi(pdev);
1636 if (rc < 0)
1637 goto err_out_disable_2;
1638
1639 /* make sure PCI base addr 1 is MMIO */
1640 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1641 if (netif_msg_probe(tp)) {
1642 dev_err(&pdev->dev,
1643 "region #%d not an MMIO resource, aborting\n",
1644 region);
1645 }
1646 rc = -ENODEV;
1647 goto err_out_mwi_3;
1648 }
1649
1650 /* check for weird/broken PCI region reporting */
1651 if (pci_resource_len(pdev, region) < R8101_REGS_SIZE) {
1652 if (netif_msg_probe(tp)) {
1653 dev_err(&pdev->dev,
1654 "Invalid PCI region size(s), aborting\n");
1655 }
1656 rc = -ENODEV;
1657 goto err_out_mwi_3;
1658 }
1659
1660 rc = pci_request_regions(pdev, MODULENAME);
1661 if (rc < 0) {
1662 if (netif_msg_probe(tp))
1663 dev_err(&pdev->dev, "could not request regions.\n");
1664 goto err_out_mwi_3;
1665 }
1666
1667 tp->cp_cmd = PCIMulRW | RxChkSum;
1668
1669 if ((sizeof(dma_addr_t) > 4) &&
1670 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1671 tp->cp_cmd |= PCIDAC;
1672 dev->features |= NETIF_F_HIGHDMA;
1673 } else {
1674 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1675 if (rc < 0) {
1676 if (netif_msg_probe(tp)) {
1677 dev_err(&pdev->dev,
1678 "DMA configuration failed.\n");
1679 }
1680 goto err_out_free_res_4;
1681 }
1682 }
1683
1684 pci_set_master(pdev);
1685
1686 /* ioremap MMIO region */
1687 ioaddr = ioremap(pci_resource_start(pdev, region), R8101_REGS_SIZE);
1688 if (!ioaddr) {
1689 if (netif_msg_probe(tp))
1690 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1691 rc = -EIO;
1692 goto err_out_free_res_4;
1693 }
1694
1695 RTL_W16(IntrMask, 0x0000);
1696
1697 /* Soft reset the chip. */
1698 RTL_W8(ChipCmd, CmdReset);
1699
1700 /* Check that the chip has finished the reset. */
1701 for (i = 0; i < 100; i++) {
1702 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1703 break;
1704 msleep_interruptible(1);
1705 }
1706
1707 RTL_W16(IntrStatus, 0xffff);
1708
1709 /* Identify chip attached to board */
1710 rtl8101_get_mac_version(tp, ioaddr);
1711
1712 rtl8101_print_mac_version(tp);
1713
1714 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1715 if (tp->mac_version == rtl_chip_info[i].mac_version)
1716 break;
1717 }
1718 if (i == ARRAY_SIZE(rtl_chip_info)) {
1719 /* Unknown chip: assume array element #0, original RTL-8101 */
1720 if (netif_msg_probe(tp)) {
1721 dev_printk(KERN_DEBUG, &pdev->dev,
1722 "unknown chip version, assuming %s\n",
1723 rtl_chip_info[0].name);
1724 }
1725 i = 0;
1726 }
1727 tp->chipset = i;
1728
1729 RTL_W8(Cfg9346, Cfg9346_Unlock);
1730 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1731 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1732 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1733 RTL_W8(Cfg9346, Cfg9346_Lock);
1734
1735 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1736 (RTL_R8(PHYstatus) & TBI_Enable)) {
1737 tp->set_speed = rtl8101_set_speed_tbi;
1738 tp->get_settings = rtl8101_gset_tbi;
1739 tp->phy_reset_enable = rtl8101_tbi_reset_enable;
1740 tp->phy_reset_pending = rtl8101_tbi_reset_pending;
1741 tp->link_ok = rtl8101_tbi_link_ok;
1742
1743 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1744 } else {
1745 tp->set_speed = rtl8101_set_speed_xmii;
1746 tp->get_settings = rtl8101_gset_xmii;
1747 tp->phy_reset_enable = rtl8101_xmii_reset_enable;
1748 tp->phy_reset_pending = rtl8101_xmii_reset_pending;
1749 tp->link_ok = rtl8101_xmii_link_ok;
1750
1751 dev->do_ioctl = rtl8101_ioctl;
1752 }
1753
1754 /* Get MAC address. FIXME: read EEPROM */
1755 for (i = 0; i < MAC_ADDR_LEN; i++)
1756 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1757 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1758
1759 dev->open = rtl8101_open;
1760 dev->hard_start_xmit = rtl8101_start_xmit;
1761 dev->get_stats = rtl8101_get_stats;
1762 SET_ETHTOOL_OPS(dev, &rtl8101_ethtool_ops);
1763 dev->stop = rtl8101_close;
1764 dev->tx_timeout = rtl8101_tx_timeout;
1765 dev->set_multicast_list = rtl_set_rx_mode;
1766 dev->watchdog_timeo = RTL8101_TX_TIMEOUT;
1767 dev->irq = pdev->irq;
1768 dev->base_addr = (unsigned long) ioaddr;
1769 dev->change_mtu = rtl8101_change_mtu;
1770 dev->set_mac_address = rtl_set_mac_address;
1771
1772 netif_napi_add(dev, &tp->napi, rtl8101_poll, R8101_NAPI_WEIGHT);
1773
1774 #ifdef CONFIG_R8101_VLAN
1775 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1776 dev->vlan_rx_register = rtl8101_vlan_rx_register;
1777 #endif
1778
1779 #ifdef CONFIG_NET_POLL_CONTROLLER
1780 dev->poll_controller = rtl8101_netpoll;
1781 #endif
1782
1783 tp->intr_mask = 0xffff;
1784 tp->mmio_addr = ioaddr;
1785 tp->align = cfg->align;
1786 tp->hw_start = cfg->hw_start;
1787 tp->intr_event = cfg->intr_event;
1788 tp->napi_event = cfg->napi_event;
1789
1790 init_timer(&tp->timer);
1791 tp->timer.data = (unsigned long) dev;
1792 tp->timer.function = rtl8101_phy_timer;
1793
1794 spin_lock_init(&tp->lock);
1795
1796 rc = register_netdev(dev);
1797 if (rc < 0)
1798 goto err_out_msi_5;
1799
1800 pci_set_drvdata(pdev, dev);
1801
1802 if (netif_msg_probe(tp)) {
1803 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1804
1805 printk(KERN_INFO "%s: %s at 0x%lx, "
1806 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1807 "XID %08x IRQ %d\n",
1808 dev->name,
1809 rtl_chip_info[tp->chipset].name,
1810 dev->base_addr,
1811 dev->dev_addr[0], dev->dev_addr[1],
1812 dev->dev_addr[2], dev->dev_addr[3],
1813 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1814 }
1815
1816 rtl8101_init_phy(dev, tp);
1817
1818 out:
1819 return rc;
1820
1821 err_out_msi_5:
1822 rtl_disable_msi(pdev, tp);
1823 iounmap(ioaddr);
1824 err_out_free_res_4:
1825 pci_release_regions(pdev);
1826 err_out_mwi_3:
1827 pci_clear_mwi(pdev);
1828 err_out_disable_2:
1829 pci_disable_device(pdev);
1830 err_out_free_dev_1:
1831 free_netdev(dev);
1832 goto out;
1833 }
1834
1835 static void __devexit rtl8101_remove_one(struct pci_dev *pdev)
1836 {
1837 struct net_device *dev = pci_get_drvdata(pdev);
1838 struct rtl8101_private *tp = netdev_priv(dev);
1839
1840 flush_scheduled_work();
1841
1842 unregister_netdev(dev);
1843 rtl_disable_msi(pdev, tp);
1844 rtl8101_release_board(pdev, dev, tp->mmio_addr);
1845 pci_set_drvdata(pdev, NULL);
1846 }
1847
1848 static void rtl8101_set_rxbufsize(struct rtl8101_private *tp,
1849 struct net_device *dev)
1850 {
1851 unsigned int mtu = dev->mtu;
1852
1853 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1854 }
1855
1856 static int rtl8101_open(struct net_device *dev)
1857 {
1858 struct rtl8101_private *tp = netdev_priv(dev);
1859 struct pci_dev *pdev = tp->pci_dev;
1860 int retval = -ENOMEM;
1861
1862
1863 rtl8101_set_rxbufsize(tp, dev);
1864
1865 /*
1866 * Rx and Tx desscriptors needs 256 bytes alignment.
1867 * pci_alloc_consistent provides more.
1868 */
1869 tp->TxDescArray = pci_alloc_consistent(pdev, R8101_TX_RING_BYTES,
1870 &tp->TxPhyAddr);
1871 if (!tp->TxDescArray)
1872 goto out;
1873
1874 tp->RxDescArray = pci_alloc_consistent(pdev, R8101_RX_RING_BYTES,
1875 &tp->RxPhyAddr);
1876 if (!tp->RxDescArray)
1877 goto err_free_tx_0;
1878
1879 retval = rtl8101_init_ring(dev);
1880 if (retval < 0)
1881 goto err_free_rx_1;
1882
1883 INIT_DELAYED_WORK(&tp->task, NULL);
1884
1885 smp_mb();
1886
1887 retval = request_irq(dev->irq, rtl8101_interrupt,
1888 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
1889 dev->name, dev);
1890 if (retval < 0)
1891 goto err_release_ring_2;
1892
1893 napi_enable(&tp->napi);
1894
1895 rtl_hw_start(dev);
1896
1897 rtl8101_request_timer(dev);
1898
1899 rtl8101_check_link_status(dev, tp, tp->mmio_addr);
1900 out:
1901 return retval;
1902
1903 err_release_ring_2:
1904 rtl8101_rx_clear(tp);
1905 err_free_rx_1:
1906 pci_free_consistent(pdev, R8101_RX_RING_BYTES, tp->RxDescArray,
1907 tp->RxPhyAddr);
1908 err_free_tx_0:
1909 pci_free_consistent(pdev, R8101_TX_RING_BYTES, tp->TxDescArray,
1910 tp->TxPhyAddr);
1911 goto out;
1912 }
1913
1914 static void rtl8101_hw_reset(void __iomem *ioaddr)
1915 {
1916 /* Disable interrupts */
1917 rtl8101_irq_mask_and_ack(ioaddr);
1918
1919 /* Reset the chipset */
1920 RTL_W8(ChipCmd, CmdReset);
1921
1922 /* PCI commit */
1923 RTL_R8(ChipCmd);
1924 }
1925
1926 static void rtl_set_rx_tx_config_registers(struct rtl8101_private *tp)
1927 {
1928 void __iomem *ioaddr = tp->mmio_addr;
1929 u32 cfg = rtl8101_rx_config;
1930
1931 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1932 RTL_W32(RxConfig, cfg);
1933
1934 /* Set DMA burst size and Interframe Gap Time */
1935 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1936 (InterFrameGap << TxInterFrameGapShift));
1937 }
1938
1939 static void rtl_hw_start(struct net_device *dev)
1940 {
1941 struct rtl8101_private *tp = netdev_priv(dev);
1942 void __iomem *ioaddr = tp->mmio_addr;
1943 unsigned int i;
1944
1945 /* Soft reset the chip. */
1946 RTL_W8(ChipCmd, CmdReset);
1947
1948 /* Check that the chip has finished the reset. */
1949 for (i = 0; i < 100; i++) {
1950 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1951 break;
1952 msleep_interruptible(1);
1953 }
1954
1955 tp->hw_start(dev);
1956
1957 netif_start_queue(dev);
1958 }
1959
1960
1961 static void rtl_set_rx_tx_desc_registers(struct rtl8101_private *tp,
1962 void __iomem *ioaddr)
1963 {
1964 /*
1965 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1966 * register to be written before TxDescAddrLow to work.
1967 * Switching from MMIO to I/O access fixes the issue as well.
1968 */
1969 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1970 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1971 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1972 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1973 }
1974
1975 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1976 {
1977 u16 cmd;
1978
1979 cmd = RTL_R16(CPlusCmd);
1980 RTL_W16(CPlusCmd, cmd);
1981 return cmd;
1982 }
1983
1984 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
1985 {
1986 /* Low hurts. Let's disable the filtering. */
1987 RTL_W16(RxMaxSize, rx_buf_sz);
1988 }
1989
1990 static void rtl8101_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1991 {
1992 struct {
1993 u32 mac_version;
1994 u32 clk;
1995 u32 val;
1996 } cfg2_info [] = {
1997 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1998 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1999 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2000 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2001 }, *p = cfg2_info;
2002 unsigned int i;
2003 u32 clk;
2004
2005 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2006 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2007 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2008 RTL_W32(0x7c, p->val);
2009 break;
2010 }
2011 }
2012 }
2013
2014 static void rtl_hw_start_8169(struct net_device *dev)
2015 {
2016 struct rtl8101_private *tp = netdev_priv(dev);
2017 void __iomem *ioaddr = tp->mmio_addr;
2018 struct pci_dev *pdev = tp->pci_dev;
2019
2020 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2021 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2022 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2023 }
2024
2025 RTL_W8(Cfg9346, Cfg9346_Unlock);
2026 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2027 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2028 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2029 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2030 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2031
2032 RTL_W8(EarlyTxThres, EarlyTxThld);
2033
2034 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2035
2036 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2037 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2038 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2039 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2040 rtl_set_rx_tx_config_registers(tp);
2041
2042 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2043
2044 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2045 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2046 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2047 "Bit-3 and bit-14 MUST be 1\n");
2048 tp->cp_cmd |= (1 << 14);
2049 }
2050
2051 RTL_W16(CPlusCmd, tp->cp_cmd);
2052
2053 rtl8101_set_magic_reg(ioaddr, tp->mac_version);
2054
2055 /*
2056 * Undocumented corner. Supposedly:
2057 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2058 */
2059 RTL_W16(IntrMitigate, 0x0000);
2060
2061 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2062
2063 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2064 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2065 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2066 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2067 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2068 rtl_set_rx_tx_config_registers(tp);
2069 }
2070
2071 RTL_W8(Cfg9346, Cfg9346_Lock);
2072
2073 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2074 RTL_R8(IntrMask);
2075
2076 RTL_W32(RxMissed, 0);
2077
2078 rtl_set_rx_mode(dev);
2079
2080 /* no early-rx interrupts */
2081 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2082
2083 /* Enable all known interrupts by setting the interrupt mask. */
2084 RTL_W16(IntrMask, tp->intr_event);
2085 }
2086
2087 static void rtl_hw_start_8168(struct net_device *dev)
2088 {
2089 struct rtl8101_private *tp = netdev_priv(dev);
2090 void __iomem *ioaddr = tp->mmio_addr;
2091 struct pci_dev *pdev = tp->pci_dev;
2092 u8 ctl;
2093
2094 RTL_W8(Cfg9346, Cfg9346_Unlock);
2095
2096 RTL_W8(EarlyTxThres, EarlyTxThld);
2097
2098 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2099
2100 rtl_set_rx_tx_config_registers(tp);
2101
2102 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2103
2104 RTL_W16(CPlusCmd, tp->cp_cmd);
2105
2106 /* Tx performance tweak. */
2107 pci_read_config_byte(pdev, 0x69, &ctl);
2108 ctl = (ctl & ~0x70) | 0x50;
2109 pci_write_config_byte(pdev, 0x69, ctl);
2110
2111 RTL_W16(IntrMitigate, 0x5151);
2112
2113 /* Work around for RxFIFO overflow. */
2114 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2115 tp->intr_event |= RxFIFOOver | PCSTimeout;
2116 tp->intr_event &= ~RxOverflow;
2117 }
2118
2119 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2120
2121 RTL_W8(Cfg9346, Cfg9346_Lock);
2122
2123 RTL_R8(IntrMask);
2124
2125 rtl_set_rx_mode(dev);
2126
2127 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2128
2129 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2130
2131 RTL_W16(IntrMask, tp->intr_event);
2132 }
2133
2134 static void rtl_hw_start_8101(struct net_device *dev)
2135 {
2136 struct rtl8101_private *tp = netdev_priv(dev);
2137 void __iomem *ioaddr = tp->mmio_addr;
2138 struct pci_dev *pdev = tp->pci_dev;
2139
2140 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2141 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2142 pci_write_config_word(pdev, 0x68, 0x00);
2143 pci_write_config_word(pdev, 0x69, 0x08);
2144 }
2145
2146 RTL_W8(Cfg9346, Cfg9346_Unlock);
2147
2148 RTL_W8(EarlyTxThres, EarlyTxThld);
2149
2150 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2151
2152 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2153
2154 RTL_W16(CPlusCmd, tp->cp_cmd);
2155
2156 RTL_W16(IntrMitigate, 0x0000);
2157
2158 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2159
2160 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2161 rtl_set_rx_tx_config_registers(tp);
2162
2163 RTL_W8(Cfg9346, Cfg9346_Lock);
2164
2165 RTL_R8(IntrMask);
2166
2167 rtl_set_rx_mode(dev);
2168
2169 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2170
2171 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2172
2173 RTL_W16(IntrMask, tp->intr_event);
2174 }
2175
2176 static int rtl8101_change_mtu(struct net_device *dev, int new_mtu)
2177 {
2178 struct rtl8101_private *tp = netdev_priv(dev);
2179 int ret = 0;
2180
2181 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2182 return -EINVAL;
2183
2184 dev->mtu = new_mtu;
2185
2186 if (!netif_running(dev))
2187 goto out;
2188
2189 rtl8101_down(dev);
2190
2191 rtl8101_set_rxbufsize(tp, dev);
2192
2193 ret = rtl8101_init_ring(dev);
2194 if (ret < 0)
2195 goto out;
2196
2197 napi_enable(&tp->napi);
2198
2199 rtl_hw_start(dev);
2200
2201 rtl8101_request_timer(dev);
2202
2203 out:
2204 return ret;
2205 }
2206
2207 static inline void rtl8101_make_unusable_by_asic(struct RxDesc *desc)
2208 {
2209 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2210 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2211 }
2212
2213 static void rtl8101_free_rx_skb(struct rtl8101_private *tp,
2214 struct sk_buff **sk_buff, struct RxDesc *desc)
2215 {
2216 struct pci_dev *pdev = tp->pci_dev;
2217
2218 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2219 PCI_DMA_FROMDEVICE);
2220 dev_kfree_skb(*sk_buff);
2221 *sk_buff = NULL;
2222 rtl8101_make_unusable_by_asic(desc);
2223 }
2224
2225 static inline void rtl8101_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2226 {
2227 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2228
2229 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2230 }
2231
2232 static inline void rtl8101_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2233 u32 rx_buf_sz)
2234 {
2235 desc->addr = cpu_to_le64(mapping);
2236 wmb();
2237 rtl8101_mark_to_asic(desc, rx_buf_sz);
2238 }
2239
2240 static struct sk_buff *rtl8101_alloc_rx_skb(struct pci_dev *pdev,
2241 struct net_device *dev,
2242 struct RxDesc *desc, int rx_buf_sz,
2243 unsigned int align)
2244 {
2245 struct sk_buff *skb;
2246 dma_addr_t mapping;
2247 unsigned int pad;
2248
2249 pad = align ? align : NET_IP_ALIGN;
2250
2251 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2252 if (!skb)
2253 goto err_out;
2254
2255 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2256
2257 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2258 PCI_DMA_FROMDEVICE);
2259
2260 rtl8101_map_to_asic(desc, mapping, rx_buf_sz);
2261 out:
2262 return skb;
2263
2264 err_out:
2265 rtl8101_make_unusable_by_asic(desc);
2266 goto out;
2267 }
2268
2269 static void rtl8101_rx_clear(struct rtl8101_private *tp)
2270 {
2271 unsigned int i;
2272
2273 for (i = 0; i < NUM_RX_DESC; i++) {
2274 if (tp->Rx_skbuff[i]) {
2275 rtl8101_free_rx_skb(tp, tp->Rx_skbuff + i,
2276 tp->RxDescArray + i);
2277 }
2278 }
2279 }
2280
2281 static u32 rtl8101_rx_fill(struct rtl8101_private *tp, struct net_device *dev,
2282 u32 start, u32 end)
2283 {
2284 u32 cur;
2285
2286 for (cur = start; end - cur != 0; cur++) {
2287 struct sk_buff *skb;
2288 unsigned int i = cur % NUM_RX_DESC;
2289
2290 WARN_ON((s32)(end - cur) < 0);
2291
2292 if (tp->Rx_skbuff[i])
2293 continue;
2294
2295 skb = rtl8101_alloc_rx_skb(tp->pci_dev, dev,
2296 tp->RxDescArray + i,
2297 tp->rx_buf_sz, tp->align);
2298 if (!skb)
2299 break;
2300
2301 tp->Rx_skbuff[i] = skb;
2302 }
2303 return cur - start;
2304 }
2305
2306 static inline void rtl8101_mark_as_last_descriptor(struct RxDesc *desc)
2307 {
2308 desc->opts1 |= cpu_to_le32(RingEnd);
2309 }
2310
2311 static void rtl8101_init_ring_indexes(struct rtl8101_private *tp)
2312 {
2313 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2314 }
2315
2316 static int rtl8101_init_ring(struct net_device *dev)
2317 {
2318 struct rtl8101_private *tp = netdev_priv(dev);
2319
2320 rtl8101_init_ring_indexes(tp);
2321
2322 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2323 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2324
2325 if (rtl8101_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2326 goto err_out;
2327
2328 rtl8101_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2329
2330 return 0;
2331
2332 err_out:
2333 rtl8101_rx_clear(tp);
2334 return -ENOMEM;
2335 }
2336
2337 static void rtl8101_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2338 struct TxDesc *desc)
2339 {
2340 unsigned int len = tx_skb->len;
2341
2342 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2343 desc->opts1 = 0x00;
2344 desc->opts2 = 0x00;
2345 desc->addr = 0x00;
2346 tx_skb->len = 0;
2347 }
2348
2349 static void rtl8101_tx_clear(struct rtl8101_private *tp)
2350 {
2351 unsigned int i;
2352
2353 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2354 unsigned int entry = i % NUM_TX_DESC;
2355 struct ring_info *tx_skb = tp->tx_skb + entry;
2356 unsigned int len = tx_skb->len;
2357
2358 if (len) {
2359 struct sk_buff *skb = tx_skb->skb;
2360
2361 rtl8101_unmap_tx_skb(tp->pci_dev, tx_skb,
2362 tp->TxDescArray + entry);
2363 if (skb) {
2364 dev_kfree_skb(skb);
2365 tx_skb->skb = NULL;
2366 }
2367 tp->dev->stats.tx_dropped++;
2368 }
2369 }
2370 tp->cur_tx = tp->dirty_tx = 0;
2371 }
2372
2373 static void rtl8101_schedule_work(struct net_device *dev, work_func_t task)
2374 {
2375 struct rtl8101_private *tp = netdev_priv(dev);
2376
2377 PREPARE_DELAYED_WORK(&tp->task, task);
2378 schedule_delayed_work(&tp->task, 4);
2379 }
2380
2381 static void rtl8101_wait_for_quiescence(struct net_device *dev)
2382 {
2383 struct rtl8101_private *tp = netdev_priv(dev);
2384 void __iomem *ioaddr = tp->mmio_addr;
2385
2386 synchronize_irq(dev->irq);
2387
2388 /* Wait for any pending NAPI task to complete */
2389 napi_disable(&tp->napi);
2390
2391 rtl8101_irq_mask_and_ack(ioaddr);
2392
2393 tp->intr_mask = 0xffff;
2394 RTL_W16(IntrMask, tp->intr_event);
2395 napi_enable(&tp->napi);
2396 }
2397
2398 static void rtl8101_reinit_task(struct work_struct *work)
2399 {
2400 struct rtl8101_private *tp =
2401 container_of(work, struct rtl8101_private, task.work);
2402 struct net_device *dev = tp->dev;
2403 int ret;
2404
2405 rtnl_lock();
2406
2407 if (!netif_running(dev))
2408 goto out_unlock;
2409
2410 rtl8101_wait_for_quiescence(dev);
2411 rtl8101_close(dev);
2412
2413 ret = rtl8101_open(dev);
2414 if (unlikely(ret < 0)) {
2415 if (net_ratelimit() && netif_msg_drv(tp)) {
2416 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2417 " Rescheduling.\n", dev->name, ret);
2418 }
2419 rtl8101_schedule_work(dev, rtl8101_reinit_task);
2420 }
2421
2422 out_unlock:
2423 rtnl_unlock();
2424 }
2425
2426 static void rtl8101_reset_task(struct work_struct *work)
2427 {
2428 struct rtl8101_private *tp =
2429 container_of(work, struct rtl8101_private, task.work);
2430 struct net_device *dev = tp->dev;
2431
2432 rtnl_lock();
2433
2434 if (!netif_running(dev))
2435 goto out_unlock;
2436
2437 rtl8101_wait_for_quiescence(dev);
2438
2439 rtl8101_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2440 rtl8101_tx_clear(tp);
2441
2442 if (tp->dirty_rx == tp->cur_rx) {
2443 rtl8101_init_ring_indexes(tp);
2444 rtl_hw_start(dev);
2445 netif_wake_queue(dev);
2446 rtl8101_check_link_status(dev, tp, tp->mmio_addr);
2447 } else {
2448 if (net_ratelimit() && netif_msg_intr(tp)) {
2449 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2450 dev->name);
2451 }
2452 rtl8101_schedule_work(dev, rtl8101_reset_task);
2453 }
2454
2455 out_unlock:
2456 rtnl_unlock();
2457 }
2458
2459 static void rtl8101_tx_timeout(struct net_device *dev)
2460 {
2461 struct rtl8101_private *tp = netdev_priv(dev);
2462
2463 rtl8101_hw_reset(tp->mmio_addr);
2464
2465 /* Let's wait a bit while any (async) irq lands on */
2466 rtl8101_schedule_work(dev, rtl8101_reset_task);
2467 }
2468
2469 static int rtl8101_xmit_frags(struct rtl8101_private *tp, struct sk_buff *skb,
2470 u32 opts1)
2471 {
2472 struct skb_shared_info *info = skb_shinfo(skb);
2473 unsigned int cur_frag, entry;
2474 struct TxDesc * uninitialized_var(txd);
2475
2476 entry = tp->cur_tx;
2477 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2478 skb_frag_t *frag = info->frags + cur_frag;
2479 dma_addr_t mapping;
2480 u32 status, len;
2481 void *addr;
2482
2483 entry = (entry + 1) % NUM_TX_DESC;
2484
2485 txd = tp->TxDescArray + entry;
2486 len = frag->size;
2487 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2488 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2489
2490 /* anti gcc 2.95.3 bugware (sic) */
2491 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2492
2493 txd->opts1 = cpu_to_le32(status);
2494 txd->addr = cpu_to_le64(mapping);
2495
2496 tp->tx_skb[entry].len = len;
2497 }
2498
2499 if (cur_frag) {
2500 tp->tx_skb[entry].skb = skb;
2501 txd->opts1 |= cpu_to_le32(LastFrag);
2502 }
2503
2504 return cur_frag;
2505 }
2506
2507 static inline u32 rtl8101_tso_csum(struct sk_buff *skb, struct net_device *dev)
2508 {
2509 if (dev->features & NETIF_F_TSO) {
2510 u32 mss = skb_shinfo(skb)->gso_size;
2511
2512 if (mss)
2513 return LargeSend | ((mss & MSSMask) << MSSShift);
2514 }
2515 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2516 const struct iphdr *ip = ip_hdr(skb);
2517
2518 if (ip->protocol == IPPROTO_TCP)
2519 return IPCS | TCPCS;
2520 else if (ip->protocol == IPPROTO_UDP)
2521 return IPCS | UDPCS;
2522 WARN_ON(1); /* we need a WARN() */
2523 }
2524 return 0;
2525 }
2526
2527 static int rtl8101_start_xmit(struct sk_buff *skb, struct net_device *dev)
2528 {
2529 struct rtl8101_private *tp = netdev_priv(dev);
2530 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2531 struct TxDesc *txd = tp->TxDescArray + entry;
2532 void __iomem *ioaddr = tp->mmio_addr;
2533 dma_addr_t mapping;
2534 u32 status, len;
2535 u32 opts1;
2536 int ret = NETDEV_TX_OK;
2537
2538 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2539 if (netif_msg_drv(tp)) {
2540 printk(KERN_ERR
2541 "%s: BUG! Tx Ring full when queue awake!\n",
2542 dev->name);
2543 }
2544 goto err_stop;
2545 }
2546
2547 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2548 goto err_stop;
2549
2550 opts1 = DescOwn | rtl8101_tso_csum(skb, dev);
2551
2552 frags = rtl8101_xmit_frags(tp, skb, opts1);
2553 if (frags) {
2554 len = skb_headlen(skb);
2555 opts1 |= FirstFrag;
2556 } else {
2557 len = skb->len;
2558 opts1 |= FirstFrag | LastFrag;
2559 tp->tx_skb[entry].skb = skb;
2560 }
2561
2562 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2563
2564 tp->tx_skb[entry].len = len;
2565 txd->addr = cpu_to_le64(mapping);
2566 txd->opts2 = cpu_to_le32(rtl8101_tx_vlan_tag(tp, skb));
2567
2568 wmb();
2569
2570 /* anti gcc 2.95.3 bugware (sic) */
2571 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2572 txd->opts1 = cpu_to_le32(status);
2573
2574 dev->trans_start = jiffies;
2575
2576 tp->cur_tx += frags + 1;
2577
2578 smp_wmb();
2579
2580 RTL_W8(TxPoll, NPQ); /* set polling bit */
2581
2582 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2583 netif_stop_queue(dev);
2584 smp_rmb();
2585 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2586 netif_wake_queue(dev);
2587 }
2588
2589 out:
2590 return ret;
2591
2592 err_stop:
2593 netif_stop_queue(dev);
2594 ret = NETDEV_TX_BUSY;
2595 dev->stats.tx_dropped++;
2596 goto out;
2597 }
2598
2599 static void rtl8101_pcierr_interrupt(struct net_device *dev)
2600 {
2601 struct rtl8101_private *tp = netdev_priv(dev);
2602 struct pci_dev *pdev = tp->pci_dev;
2603 void __iomem *ioaddr = tp->mmio_addr;
2604 u16 pci_status, pci_cmd;
2605
2606 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2607 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2608
2609 if (netif_msg_intr(tp)) {
2610 printk(KERN_ERR
2611 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2612 dev->name, pci_cmd, pci_status);
2613 }
2614
2615 /*
2616 * The recovery sequence below admits a very elaborated explanation:
2617 * - it seems to work;
2618 * - I did not see what else could be done;
2619 * - it makes iop3xx happy.
2620 *
2621 * Feel free to adjust to your needs.
2622 */
2623 if (pdev->broken_parity_status)
2624 pci_cmd &= ~PCI_COMMAND_PARITY;
2625 else
2626 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2627
2628 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2629
2630 pci_write_config_word(pdev, PCI_STATUS,
2631 pci_status & (PCI_STATUS_DETECTED_PARITY |
2632 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2633 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2634
2635 /* The infamous DAC f*ckup only happens at boot time */
2636 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2637 if (netif_msg_intr(tp))
2638 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2639 tp->cp_cmd &= ~PCIDAC;
2640 RTL_W16(CPlusCmd, tp->cp_cmd);
2641 dev->features &= ~NETIF_F_HIGHDMA;
2642 }
2643
2644 rtl8101_hw_reset(ioaddr);
2645
2646 rtl8101_schedule_work(dev, rtl8101_reinit_task);
2647 }
2648
2649 static void rtl8101_tx_interrupt(struct net_device *dev,
2650 struct rtl8101_private *tp,
2651 void __iomem *ioaddr)
2652 {
2653 unsigned int dirty_tx, tx_left;
2654
2655 dirty_tx = tp->dirty_tx;
2656 smp_rmb();
2657 tx_left = tp->cur_tx - dirty_tx;
2658
2659 while (tx_left > 0) {
2660 unsigned int entry = dirty_tx % NUM_TX_DESC;
2661 struct ring_info *tx_skb = tp->tx_skb + entry;
2662 u32 len = tx_skb->len;
2663 u32 status;
2664
2665 rmb();
2666 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2667 if (status & DescOwn)
2668 break;
2669
2670 dev->stats.tx_bytes += len;
2671 dev->stats.tx_packets++;
2672
2673 rtl8101_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2674
2675 if (status & LastFrag) {
2676 dev_kfree_skb_irq(tx_skb->skb);
2677 tx_skb->skb = NULL;
2678 }
2679 dirty_tx++;
2680 tx_left--;
2681 }
2682
2683 if (tp->dirty_tx != dirty_tx) {
2684 tp->dirty_tx = dirty_tx;
2685 smp_wmb();
2686 if (netif_queue_stopped(dev) &&
2687 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2688 netif_wake_queue(dev);
2689 }
2690 /*
2691 * 8168 hack: TxPoll requests are lost when the Tx packets are
2692 * too close. Let's kick an extra TxPoll request when a burst
2693 * of start_xmit activity is detected (if it is not detected,
2694 * it is slow enough). -- FR
2695 */
2696 smp_rmb();
2697 if (tp->cur_tx != dirty_tx)
2698 RTL_W8(TxPoll, NPQ);
2699 }
2700 }
2701
2702 static inline int rtl8101_fragmented_frame(u32 status)
2703 {
2704 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2705 }
2706
2707 static inline void rtl8101_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2708 {
2709 u32 opts1 = le32_to_cpu(desc->opts1);
2710 u32 status = opts1 & RxProtoMask;
2711
2712 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2713 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2714 ((status == RxProtoIP) && !(opts1 & IPFail)))
2715 skb->ip_summed = CHECKSUM_UNNECESSARY;
2716 else
2717 skb->ip_summed = CHECKSUM_NONE;
2718 }
2719
2720 static inline bool rtl8101_try_rx_copy(struct sk_buff **sk_buff,
2721 struct rtl8101_private *tp, int pkt_size,
2722 dma_addr_t addr)
2723 {
2724 struct sk_buff *skb;
2725 bool done = false;
2726
2727 if (pkt_size >= rx_copybreak)
2728 goto out;
2729
2730 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2731 if (!skb)
2732 goto out;
2733
2734 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2735 PCI_DMA_FROMDEVICE);
2736 skb_reserve(skb, NET_IP_ALIGN);
2737 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2738 *sk_buff = skb;
2739 done = true;
2740 out:
2741 return done;
2742 }
2743
2744 static int rtl8101_rx_interrupt(struct net_device *dev,
2745 struct rtl8101_private *tp,
2746 void __iomem *ioaddr, u32 budget)
2747 {
2748 unsigned int cur_rx, rx_left;
2749 unsigned int delta, count;
2750
2751 cur_rx = tp->cur_rx;
2752 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2753 rx_left = min(rx_left, budget);
2754
2755 for (; rx_left > 0; rx_left--, cur_rx++) {
2756 unsigned int entry = cur_rx % NUM_RX_DESC;
2757 struct RxDesc *desc = tp->RxDescArray + entry;
2758 u32 status;
2759
2760 rmb();
2761 status = le32_to_cpu(desc->opts1);
2762
2763 if (status & DescOwn)
2764 break;
2765 if (unlikely(status & RxRES)) {
2766 if (netif_msg_rx_err(tp)) {
2767 printk(KERN_INFO
2768 "%s: Rx ERROR. status = %08x\n",
2769 dev->name, status);
2770 }
2771 dev->stats.rx_errors++;
2772 if (status & (RxRWT | RxRUNT))
2773 dev->stats.rx_length_errors++;
2774 if (status & RxCRC)
2775 dev->stats.rx_crc_errors++;
2776 if (status & RxFOVF) {
2777 rtl8101_schedule_work(dev, rtl8101_reset_task);
2778 dev->stats.rx_fifo_errors++;
2779 }
2780 rtl8101_mark_to_asic(desc, tp->rx_buf_sz);
2781 } else {
2782 struct sk_buff *skb = tp->Rx_skbuff[entry];
2783 dma_addr_t addr = le64_to_cpu(desc->addr);
2784 int pkt_size = (status & 0x00001FFF) - 4;
2785 struct pci_dev *pdev = tp->pci_dev;
2786
2787 /*
2788 * The driver does not support incoming fragmented
2789 * frames. They are seen as a symptom of over-mtu
2790 * sized frames.
2791 */
2792 if (unlikely(rtl8101_fragmented_frame(status))) {
2793 dev->stats.rx_dropped++;
2794 dev->stats.rx_length_errors++;
2795 rtl8101_mark_to_asic(desc, tp->rx_buf_sz);
2796 continue;
2797 }
2798
2799 rtl8101_rx_csum(skb, desc);
2800
2801 if (rtl8101_try_rx_copy(&skb, tp, pkt_size, addr)) {
2802 pci_dma_sync_single_for_device(pdev, addr,
2803 pkt_size, PCI_DMA_FROMDEVICE);
2804 rtl8101_mark_to_asic(desc, tp->rx_buf_sz);
2805 } else {
2806 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
2807 PCI_DMA_FROMDEVICE);
2808 tp->Rx_skbuff[entry] = NULL;
2809 }
2810
2811 skb_put(skb, pkt_size);
2812 skb->protocol = eth_type_trans(skb, dev);
2813
2814 if (rtl8101_rx_vlan_skb(tp, desc, skb) < 0)
2815 netif_receive_skb(skb);
2816
2817 dev->last_rx = jiffies;
2818 dev->stats.rx_bytes += pkt_size;
2819 dev->stats.rx_packets++;
2820 }
2821
2822 /* Work around for AMD plateform. */
2823 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
2824 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2825 desc->opts2 = 0;
2826 cur_rx++;
2827 }
2828 }
2829
2830 count = cur_rx - tp->cur_rx;
2831 tp->cur_rx = cur_rx;
2832
2833 delta = rtl8101_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2834 if (!delta && count && netif_msg_intr(tp))
2835 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2836 tp->dirty_rx += delta;
2837
2838 /*
2839 * FIXME: until there is periodic timer to try and refill the ring,
2840 * a temporary shortage may definitely kill the Rx process.
2841 * - disable the asic to try and avoid an overflow and kick it again
2842 * after refill ?
2843 * - how do others driver handle this condition (Uh oh...).
2844 */
2845 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2846 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2847
2848 return count;
2849 }
2850
2851 static irqreturn_t rtl8101_interrupt(int irq, void *dev_instance)
2852 {
2853 struct net_device *dev = dev_instance;
2854 struct rtl8101_private *tp = netdev_priv(dev);
2855 void __iomem *ioaddr = tp->mmio_addr;
2856 int handled = 0;
2857 int status;
2858
2859 /* loop handling interrupts until we have no new ones or
2860 * we hit a invalid/hotplug case.
2861 */
2862 status = RTL_R16(IntrStatus);
2863 while (status && status != 0xffff) {
2864 handled = 1;
2865
2866 /* Handle all of the error cases first. These will reset
2867 * the chip, so just exit the loop.
2868 */
2869 if (unlikely(!netif_running(dev))) {
2870 rtl8101_asic_down(ioaddr);
2871 break;
2872 }
2873
2874 /* Work around for rx fifo overflow */
2875 if (unlikely(status & RxFIFOOver) &&
2876 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2877 netif_stop_queue(dev);
2878 rtl8101_tx_timeout(dev);
2879 break;
2880 }
2881
2882 if (unlikely(status & SYSErr)) {
2883 rtl8101_pcierr_interrupt(dev);
2884 break;
2885 }
2886
2887 if (status & LinkChg)
2888 rtl8101_check_link_status(dev, tp, ioaddr);
2889
2890 /* We need to see the lastest version of tp->intr_mask to
2891 * avoid ignoring an MSI interrupt and having to wait for
2892 * another event which may never come.
2893 */
2894 smp_rmb();
2895 if (status & tp->intr_mask & tp->napi_event) {
2896 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2897 tp->intr_mask = ~tp->napi_event;
2898
2899 if (likely(napi_schedule_prep(&tp->napi)))
2900 __napi_schedule(&tp->napi);
2901 else if (netif_msg_intr(tp)) {
2902 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2903 dev->name, status);
2904 }
2905 }
2906
2907 /* We only get a new MSI interrupt when all active irq
2908 * sources on the chip have been acknowledged. So, ack
2909 * everything we've seen and check if new sources have become
2910 * active to avoid blocking all interrupts from the chip.
2911 */
2912 RTL_W16(IntrStatus,
2913 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2914 status = RTL_R16(IntrStatus);
2915 }
2916
2917 return IRQ_RETVAL(handled);
2918 }
2919
2920 static int rtl8101_poll(struct napi_struct *napi, int budget)
2921 {
2922 struct rtl8101_private *tp = container_of(napi, struct rtl8101_private, napi);
2923 struct net_device *dev = tp->dev;
2924 void __iomem *ioaddr = tp->mmio_addr;
2925 int work_done;
2926
2927 work_done = rtl8101_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2928 rtl8101_tx_interrupt(dev, tp, ioaddr);
2929
2930 if (work_done < budget) {
2931 netif_rx_complete(dev, napi);
2932
2933 /* We need for force the visibility of tp->intr_mask
2934 * for other CPUs, as we can loose an MSI interrupt
2935 * and potentially wait for a retransmit timeout if we don't.
2936 * The posted write to IntrMask is safe, as it will
2937 * eventually make it to the chip and we won't loose anything
2938 * until it does.
2939 */
2940 tp->intr_mask = 0xffff;
2941 smp_wmb();
2942 RTL_W16(IntrMask, tp->intr_event);
2943 }
2944
2945 return work_done;
2946 }
2947
2948 static void rtl8101_rx_missed(struct net_device *dev, void __iomem *ioaddr)
2949 {
2950 struct rtl8101_private *tp = netdev_priv(dev);
2951
2952 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
2953 return;
2954
2955 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
2956 RTL_W32(RxMissed, 0);
2957 }
2958
2959 static void rtl8101_down(struct net_device *dev)
2960 {
2961 struct rtl8101_private *tp = netdev_priv(dev);
2962 void __iomem *ioaddr = tp->mmio_addr;
2963 unsigned int intrmask;
2964
2965 rtl8101_delete_timer(dev);
2966
2967 netif_stop_queue(dev);
2968
2969 napi_disable(&tp->napi);
2970
2971 core_down:
2972 spin_lock_irq(&tp->lock);
2973
2974 rtl8101_asic_down(ioaddr);
2975
2976 rtl8101_rx_missed(dev, ioaddr);
2977
2978 spin_unlock_irq(&tp->lock);
2979
2980 synchronize_irq(dev->irq);
2981
2982 /* Give a racing hard_start_xmit a few cycles to complete. */
2983 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2984
2985 /*
2986 * And now for the 50k$ question: are IRQ disabled or not ?
2987 *
2988 * Two paths lead here:
2989 * 1) dev->close
2990 * -> netif_running() is available to sync the current code and the
2991 * IRQ handler. See rtl8101_interrupt for details.
2992 * 2) dev->change_mtu
2993 * -> rtl8101_poll can not be issued again and re-enable the
2994 * interruptions. Let's simply issue the IRQ down sequence again.
2995 *
2996 * No loop if hotpluged or major error (0xffff).
2997 */
2998 intrmask = RTL_R16(IntrMask);
2999 if (intrmask && (intrmask != 0xffff))
3000 goto core_down;
3001
3002 rtl8101_tx_clear(tp);
3003
3004 rtl8101_rx_clear(tp);
3005 }
3006
3007 static int rtl8101_close(struct net_device *dev)
3008 {
3009 struct rtl8101_private *tp = netdev_priv(dev);
3010 struct pci_dev *pdev = tp->pci_dev;
3011
3012 /* update counters before going down */
3013 rtl8101_update_counters(dev);
3014
3015 rtl8101_down(dev);
3016
3017 free_irq(dev->irq, dev);
3018
3019 pci_free_consistent(pdev, R8101_RX_RING_BYTES, tp->RxDescArray,
3020 tp->RxPhyAddr);
3021 pci_free_consistent(pdev, R8101_TX_RING_BYTES, tp->TxDescArray,
3022 tp->TxPhyAddr);
3023 tp->TxDescArray = NULL;
3024 tp->RxDescArray = NULL;
3025
3026 return 0;
3027 }
3028
3029 static void rtl_set_rx_mode(struct net_device *dev)
3030 {
3031 struct rtl8101_private *tp = netdev_priv(dev);
3032 void __iomem *ioaddr = tp->mmio_addr;
3033 unsigned long flags;
3034 u32 mc_filter[2]; /* Multicast hash filter */
3035 int rx_mode;
3036 u32 tmp = 0;
3037
3038 if (dev->flags & IFF_PROMISC) {
3039 /* Unconditionally log net taps. */
3040 if (netif_msg_link(tp)) {
3041 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3042 dev->name);
3043 }
3044 rx_mode =
3045 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3046 AcceptAllPhys;
3047 mc_filter[1] = mc_filter[0] = 0xffffffff;
3048 } else if ((dev->mc_count > multicast_filter_limit)
3049 || (dev->flags & IFF_ALLMULTI)) {
3050 /* Too many to filter perfectly -- accept all multicasts. */
3051 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3052 mc_filter[1] = mc_filter[0] = 0xffffffff;
3053 } else {
3054 struct dev_mc_list *mclist;
3055 unsigned int i;
3056
3057 rx_mode = AcceptBroadcast | AcceptMyPhys;
3058 mc_filter[1] = mc_filter[0] = 0;
3059 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3060 i++, mclist = mclist->next) {
3061 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3062 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3063 rx_mode |= AcceptMulticast;
3064 }
3065 }
3066
3067 spin_lock_irqsave(&tp->lock, flags);
3068
3069 tmp = rtl8101_rx_config | rx_mode |
3070 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3071
3072 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3073 u32 data = mc_filter[0];
3074
3075 mc_filter[0] = swab32(mc_filter[1]);
3076 mc_filter[1] = swab32(data);
3077 }
3078
3079 RTL_W32(MAR0 + 0, mc_filter[0]);
3080 RTL_W32(MAR0 + 4, mc_filter[1]);
3081
3082 RTL_W32(RxConfig, tmp);
3083
3084 spin_unlock_irqrestore(&tp->lock, flags);
3085 }
3086
3087 /**
3088 * rtl8101_get_stats - Get rtl8101 read/write statistics
3089 * @dev: The Ethernet Device to get statistics for
3090 *
3091 * Get TX/RX statistics for rtl8101
3092 */
3093 static struct net_device_stats *rtl8101_get_stats(struct net_device *dev)
3094 {
3095 struct rtl8101_private *tp = netdev_priv(dev);
3096 void __iomem *ioaddr = tp->mmio_addr;
3097 unsigned long flags;
3098
3099 if (netif_running(dev)) {
3100 spin_lock_irqsave(&tp->lock, flags);
3101 rtl8101_rx_missed(dev, ioaddr);
3102 spin_unlock_irqrestore(&tp->lock, flags);
3103 }
3104
3105 return &dev->stats;
3106 }
3107
3108 #ifdef CONFIG_PM
3109
3110 static int rtl8101_suspend(struct pci_dev *pdev, pm_message_t state)
3111 {
3112 struct net_device *dev = pci_get_drvdata(pdev);
3113 struct rtl8101_private *tp = netdev_priv(dev);
3114 void __iomem *ioaddr = tp->mmio_addr;
3115
3116 if (!netif_running(dev))
3117 goto out_pci_suspend;
3118
3119 netif_device_detach(dev);
3120 netif_stop_queue(dev);
3121
3122 spin_lock_irq(&tp->lock);
3123
3124 rtl8101_asic_down(ioaddr);
3125
3126 rtl8101_rx_missed(dev, ioaddr);
3127
3128 spin_unlock_irq(&tp->lock);
3129
3130 out_pci_suspend:
3131 pci_save_state(pdev);
3132 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3133 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3134 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3135
3136 return 0;
3137 }
3138
3139 static int rtl8101_resume(struct pci_dev *pdev)
3140 {
3141 struct net_device *dev = pci_get_drvdata(pdev);
3142
3143 pci_set_power_state(pdev, PCI_D0);
3144 pci_restore_state(pdev);
3145 pci_enable_wake(pdev, PCI_D0, 0);
3146
3147 if (!netif_running(dev))
3148 goto out;
3149
3150 netif_device_attach(dev);
3151
3152 rtl8101_schedule_work(dev, rtl8101_reset_task);
3153 out:
3154 return 0;
3155 }
3156
3157 #endif /* CONFIG_PM */
3158
3159 static struct pci_driver rtl8101_pci_driver = {
3160 .name = MODULENAME,
3161 .id_table = rtl8101_pci_tbl,
3162 .probe = rtl8101_init_one,
3163 .remove = __devexit_p(rtl8101_remove_one),
3164 #ifdef CONFIG_PM
3165 .suspend = rtl8101_suspend,
3166 .resume = rtl8101_resume,
3167 #endif
3168 };
3169
3170 static int __init rtl8101_init_module(void)
3171 {
3172 return pci_register_driver(&rtl8101_pci_driver);
3173 }
3174
3175 static void __exit rtl8101_cleanup_module(void)
3176 {
3177 pci_unregister_driver(&rtl8101_pci_driver);
3178 }
3179
3180 module_init(rtl8101_init_module);
3181 module_exit(rtl8101_cleanup_module);