u-boot: add OrangePi R1 Plus LTS

Signed-off-by: Arne Fitzenreiter <arne_f@ipfire.org>

diff --git a/config/rootfiles/common/aarch64/u-boot b/config/rootfiles/common/aarch64/u-boot
index 4b2dcd4fd5ba8ba62ca8fda5deeb45bead40e1ef..a9b9ed435398893346844ff0d20431326afde2d2 100644 (file)
--- a/config/rootfiles/common/aarch64/u-boot
+++ b/config/rootfiles/common/aarch64/u-boot
@@ -12,6 +12,8 @@ usr/share/u-boot/nanopi_r2c/u-boot-rockchip.bin
 usr/share/u-boot/nanopi_r2s/u-boot-rockchip.bin
 #usr/share/u-boot/nanopi_r4s
 usr/share/u-boot/nanopi_r4s/u-boot-rockchip.bin
+#usr/share/u-boot/orangepi_r1_plus_lts
+usr/share/u-boot/orangepi_r1_plus_lts/u-boot-rockchip.bin
 #usr/share/u-boot/orangepi_zero_plus
 usr/share/u-boot/orangepi_zero_plus/u-boot-sunxi-with-spl.bin
 #usr/share/u-boot/rpi

diff --git a/lfs/u-boot b/lfs/u-boot
index cea74e64cd8ade380bc3b995ba6dad99cf47aaa9..2ad92df059f8f4d112645a4c405d27194e7a67f6 100644 (file)
--- a/lfs/u-boot
+++ b/lfs/u-boot
@@ -138,7 +138,7 @@ ifneq "$(MKIMAGE)" "1"
        cd $(DIR_APP) && make distclean
 
        # Nanopi R2C
-       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/u-boot/rockchip/add_nanopi-r2c.patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/u-boot/rockchip/add-nanopi-r2c-and-orangepi-r1-plus-lts.patch
        cd $(DIR_APP) && rm -rf arm-trusted-firmware-$(ATF_VER)
        cd $(DIR_APP) && tar axf $(DIR_DL)/arm-trusted-firmware-$(ATF_VER).tar.gz
        cd $(DIR_APP)/arm-trusted-firmware-$(ATF_VER) && make PLAT=rk3328 ARCH=aarch64 DEBUG=0 bl31 LDFLAGS="$(LDFLAGS)"
@@ -156,6 +156,23 @@ ifneq "$(MKIMAGE)" "1"
                /usr/share/u-boot/nanopi_r2c/u-boot-rockchip.bin
        cd $(DIR_APP) && make distclean
 
+       # Orangepi R1 plus lts
+       cd $(DIR_APP) && rm -rf arm-trusted-firmware-$(ATF_VER)
+       cd $(DIR_APP) && tar axf $(DIR_DL)/arm-trusted-firmware-$(ATF_VER).tar.gz
+       cd $(DIR_APP)/arm-trusted-firmware-$(ATF_VER) && make PLAT=rk3328 ARCH=aarch64 DEBUG=0 bl31 LDFLAGS="$(LDFLAGS)"
+       cd $(DIR_APP) && cp arm-trusted-firmware-$(ATF_VER)/build/rk3328/release/bl31/bl31.elf bl31.elf
+       cd $(DIR_APP) && rm -rf arm-trusted-firmware-$(ATF_VER)
+       -mkdir -pv /usr/share/u-boot/orangepi_r1_plus_lts
+
+       cd $(DIR_APP) && make CROSS_COMPILE="" orangepi-r1-plus-lts-rk3328_config
+       cd $(DIR_APP) && sed -i -e 's!^CONFIG_IDENT_STRING=.*!CONFIG_IDENT_STRING=" OrangePi R1 plus lts - IPFire.org"!' .config
+       cd $(DIR_APP) && sed -i -e 's!^CONFIG_BOOTCOMMAND=.*!CONFIG_BOOTCOMMAND="console=ttyS2,115200n8;run distro_bootcmd"!' .config
+       cd $(DIR_APP) && sed -i -e 's!^CONFIG_BAUDRATE=.*!CONFIG_BAUDRATE=115200!' .config
+       cd $(DIR_APP) && sed -i -e 's!.*CONFIG_ENV_OVERWRITE.*!CONFIG_ENV_OVERWRITE=y!' .config
+       cd $(DIR_APP) && make CROSS_COMPILE="" HOSTCC="gcc $(CFLAGS)"
+       cd $(DIR_APP) && install -v -m 644 u-boot-rockchip.bin \
+               /usr/share/u-boot/orangepi_r1_plus_lts/u-boot-rockchip.bin
+       cd $(DIR_APP) && make distclean
 
        # Nanopi R4S
        # arm trusted firmware for rk3399 cannot build without cortex m0 gcc crosscompiler

diff --git a/src/patches/u-boot/rockchip/add_nanopi-r2c.patch b/src/patches/u-boot/rockchip/add-nanopi-r2c-and-orangepi-r1-plus-lts.patch
similarity index 52%
rename from src/patches/u-boot/rockchip/add_nanopi-r2c.patch
rename to src/patches/u-boot/rockchip/add-nanopi-r2c-and-orangepi-r1-plus-lts.patch
index 9e330041f2700c0dc1e9700a6f66437b0db3e2ef..99712be038621f9548bf5c87b6a8b02796b09432 100644 (file)
--- a/src/patches/u-boot/rockchip/add_nanopi-r2c.patch
+++ b/src/patches/u-boot/rockchip/add-nanopi-r2c-and-orangepi-r1-plus-lts.patch
@@ -1,14 +1,16 @@
 diff -Naur u-boot-2022.10.org/arch/arm/dts/Makefile u-boot-2022.10/arch/arm/dts/Makefile
 --- u-boot-2022.10.org/arch/arm/dts/Makefile   2022-10-03 19:25:32.000000000 +0000
-+++ u-boot-2022.10/arch/arm/dts/Makefile       2023-04-22 15:02:25.945603949 +0000
-@@ -124,6 +124,7 @@
++++ u-boot-2022.10/arch/arm/dts/Makefile       2023-04-27 16:16:35.697116372 +0000
+@@ -124,7 +124,9 @@
  
  dtb-$(CONFIG_ROCKCHIP_RK3328) += \
        rk3328-evb.dtb \
 +      rk3328-nanopi-r2c.dtb \
        rk3328-nanopi-r2s.dtb \
++      rk3328-orangepi-r1-plus-lts.dtb \
        rk3328-roc-cc.dtb \
        rk3328-rock64.dtb \
+       rk3328-rock-pi-e.dtb
 diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
 --- u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi      1970-01-01 00:00:00.000000000 +0000
 +++ u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi  2023-04-22 15:07:54.544953841 +0000
@@ -51,6 +53,32 @@ diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c.dts u-boot-2022.10/
 +      vqmmc-supply = <&vcc18_emmc>;
 +      status = "okay";
 +};
+diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi u-boot-2022.10/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+--- u-boot-2022.10.org/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi    1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2022.10/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi        2023-04-27 16:12:50.320850145 +0000
+@@ -0,0 +1,6 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ */
++
++#include "rk3328-nanopi-r2s-u-boot.dtsi"
++#include "rk3328-sdram-lpddr3-666.dtsi"
+diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts u-boot-2022.10/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
+--- u-boot-2022.10.org/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts    1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2022.10/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts        2023-04-27 16:14:56.582755127 +0000
+@@ -0,0 +1,12 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ */
++
++/dts-v1/;
++#include "rk3328-nanopi-r2s.dts"
++
++/ {
++      model = "Xunlong Orange Pi R1 Plus";
++      compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
++};
++
 diff -Naur u-boot-2022.10.org/configs/nanopi-r2c-rk3328_defconfig u-boot-2022.10/configs/nanopi-r2c-rk3328_defconfig
 --- u-boot-2022.10.org/configs/nanopi-r2c-rk3328_defconfig     1970-01-01 00:00:00.000000000 +0000
 +++ u-boot-2022.10/configs/nanopi-r2c-rk3328_defconfig 2023-04-22 15:09:20.843584447 +0000
@@ -167,3 +195,119 @@ diff -Naur u-boot-2022.10.org/configs/nanopi-r2c-rk3328_defconfig u-boot-2022.10
 +CONFIG_SPL_TINY_MEMSET=y
 +CONFIG_TPL_TINY_MEMSET=y
 +CONFIG_ERRNO_STR=y
+diff -Naur u-boot-2022.10.org/configs/orangepi-r1-plus-lts-rk3328_defconfig u-boot-2022.10/configs/orangepi-r1-plus-lts-rk3328_defconfig
+--- u-boot-2022.10.org/configs/orangepi-r1-plus-lts-rk3328_defconfig   1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2022.10/configs/orangepi-r1-plus-lts-rk3328_defconfig       2023-04-27 16:19:41.122065498 +0000
+@@ -0,0 +1,112 @@
++CONFIG_ARM=y
++CONFIG_SKIP_LOWLEVEL_INIT=y
++CONFIG_COUNTER_FREQUENCY=24000000
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_TEXT_BASE=0x00200000
++CONFIG_SPL_GPIO=y
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
++CONFIG_ROCKCHIP_RK3328=y
++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
++CONFIG_TPL_LIBCOMMON_SUPPORT=y
++CONFIG_TPL_LIBGENERIC_SUPPORT=y
++CONFIG_SPL_DRIVERS_MISC=y
++CONFIG_SPL_STACK_R_ADDR=0x600000
++CONFIG_DEBUG_UART_BASE=0xFF130000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_SYS_LOAD_ADDR=0x800800
++CONFIG_DEBUG_UART=y
++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++CONFIG_MISC_INIT_R=y
++CONFIG_SPL_MAX_SIZE=0x40000
++CONFIG_SPL_PAD_TO=0x7f8000
++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
++CONFIG_SPL_BSS_START_ADDR=0x2000000
++CONFIG_SPL_BSS_MAX_SIZE=0x2000
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
++CONFIG_SPL_STACK=0x400000
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_I2C=y
++CONFIG_SPL_POWER=y
++CONFIG_SPL_ATF=y
++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
++CONFIG_CMD_BOOTZ=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_TPL_OF_CONTROL=y
++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_TPL_OF_PLATDATA=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_SYS_MMC_ENV_DEV=1
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_TPL_DM=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_TPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_TPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_FASTBOOT_BUF_ADDR=0x800800
++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_SF_DEFAULT_SPEED=20000000
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PINCTRL=y
++CONFIG_SPL_PINCTRL=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_SPL_PMIC_RK8XX=y
++CONFIG_SPL_DM_REGULATOR=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_SPL_DM_REGULATOR_FIXED=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_TPL_RAM=y
++CONFIG_DM_RESET=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYSINFO=y
++CONFIG_SYSRESET=y
++# CONFIG_TPL_SYSRESET is not set
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_GENERIC=y
++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
++CONFIG_USB_DWC2=y
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_GADGET is not set
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_SPL_TINY_MEMSET=y
++CONFIG_TPL_TINY_MEMSET=y
++CONFIG_ERRNO_STR=y