kernel: r8169 disable PCIe L23 modes.

diff --git a/lfs/linux b/lfs/linux
index c6ca7742b2a4eb2d551f91bede788c0027322390..d92bdfee301be269b2a6ac49af3ad877dd868363 100644 (file)
--- a/lfs/linux
+++ b/lfs/linux
@@ -161,6 +161,9 @@ endif
        cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/linux-3.2.33_ipg-fix-driver-name.patch
        cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/linux-2.6.32.27_mcs7830-fix-driver-name.patch
 
+       # r8169 L23 patch
+       cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/linux-3.14.32-r8169_disable_L23.patch
+
 ifeq "$(KCFG)" "-kirkwood"
        cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/linux-3.10.10-mv_cesa_disable_failing_hmac_sha1.patch
        cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/linux-3.14.22-kirkwood_legacy_boot.patch

diff --git a/src/patches/linux-3.14.32-r8169_disable_L23.patch b/src/patches/linux-3.14.32-r8169_disable_L23.patch
new file mode 100644 (file)
index 0000000..dbb58d6
--- /dev/null
+++ b/src/patches/linux-3.14.32-r8169_disable_L23.patch
@@ -0,0 +1,100 @@
+From 77e3b7f055f824e4d6587faa73bd4aacd0c307e8 Mon Sep 17 00:00:00 2001
+From: hayeswang <hayeswang@realtek.com>
+Date: Wed, 9 Jul 2014 14:52:51 +0800
+Subject: [PATCH] r8169: disable L23
+
+For RTL8411, RTL8111G, RTL8402, RTL8105, and RTL8106, disable the feature
+of entering the L2/L3 link state of the PCIe. When the nic starts the process
+of entering the L2/L3 link state and the PCI reset occurs before the work
+is finished, the work would be queued and continue after the next the PCI
+reset occurs. This causes the device stays in L2/L3 link state, and the system
+couldn't find the device.
+
+Signed-off-by: Hayes Wang <hayeswang@realtek.com>
+Acked-by: Francois Romieu <romieu@fr.zoreil.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/realtek/r8169.c | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
+index 3ff7bc3..b94f658 100644
+--- a/drivers/net/ethernet/realtek/r8169.c
++++ b/drivers/net/ethernet/realtek/r8169.c
+@@ -538,6 +538,7 @@ enum rtl_register_content {
+       MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
+       LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
+       Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
++      Rdy_to_L23      = (1 << 1),     /* L23 Enable */
+       Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
+ 
+       /* Config4 register */
+@@ -4897,6 +4898,21 @@ static void rtl_enable_clock_request(struct pci_dev *pdev)
+                                PCI_EXP_LNKCTL_CLKREQ_EN);
+ }
+ 
++static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
++{
++      void __iomem *ioaddr = tp->mmio_addr;
++      u8 data;
++
++      data = RTL_R8(Config3);
++
++      if (enable)
++              data |= Rdy_to_L23;
++      else
++              data &= ~Rdy_to_L23;
++
++      RTL_W8(Config3, data);
++}
++
+ #define R8168_CPCMD_QUIRK_MASK (\
+       EnableBist | \
+       Mac_dbgo_oe | \
+@@ -5246,6 +5262,7 @@ static void rtl_hw_start_8411(struct rtl8169_private *tp)
+       };
+ 
+       rtl_hw_start_8168f(tp);
++      rtl_pcie_state_l2l3_enable(tp, false);
+ 
+       rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
+ 
+@@ -5284,6 +5301,8 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
+ 
+       rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
+       rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
++
++      rtl_pcie_state_l2l3_enable(tp, false);
+ }
+ 
+ static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
+@@ -5536,6 +5555,8 @@ static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
+       RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
+ 
+       rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
++
++      rtl_pcie_state_l2l3_enable(tp, false);
+ }
+ 
+ static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
+@@ -5571,6 +5592,8 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp)
+       rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+       rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+       rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
++
++      rtl_pcie_state_l2l3_enable(tp, false);
+ }
+ 
+ static void rtl_hw_start_8106(struct rtl8169_private *tp)
+@@ -5583,6 +5606,8 @@ static void rtl_hw_start_8106(struct rtl8169_private *tp)
+       RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
+       RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
+       RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
++
++      rtl_pcie_state_l2l3_enable(tp, false);
+ }
+ 
+ static void rtl_hw_start_8101(struct net_device *dev)
+-- 
+1.8.5.2
+