projects / people / teissler / ipfire-2.x.git / blame
| Commit | Line | Data |
|---|---|---|
| 12788f63 MT |
1 | 2011-03-22 Ulrich Drepper <drepper@gmail.com> |
| 2 | ||
| 3 | * sysdeps/unix/sysv/linux/i386/sysconf.c (intel_check_word): Increment | |
| 4 | round counter. | |
| 5 | * sysdeps/x86_64/cacheinfo.c (intel_check_word): Likewise. | |
| 6 | ||
| 7 | 2011-03-20 Ulrich Drepper <drepper@gmail.com> | |
| 8 | ||
| 9 | [BZ #12587] | |
| 10 | * sysdeps/unix/sysv/linux/i386/sysconf.c (intel_check_word): | |
| 11 | Handle cache information in CPU leaf 4. | |
| 12 | * sysdeps/x86_64/cacheinfo.c (intel_check_word): Likewise. | |
| 13 | ||
| 14 | Index: glibc-2.12-2-gc4ccff1/sysdeps/unix/sysv/linux/i386/sysconf.c | |
| 15 | =================================================================== | |
| 16 | --- glibc-2.12-2-gc4ccff1.orig/sysdeps/unix/sysv/linux/i386/sysconf.c | |
| 17 | +++ glibc-2.12-2-gc4ccff1/sysdeps/unix/sysv/linux/i386/sysconf.c | |
| 18 | @@ -186,6 +186,57 @@ intel_check_word (int name, unsigned int | |
| 19 | /* No need to look further. */ | |
| 20 | break; | |
| 21 | } | |
| 22 | + else if (byte == 0xff) | |
| 23 | + { | |
| 24 | + /* CPUID leaf 0x4 contains all the information. We need to | |
| 25 | + iterate over it. */ | |
| 26 | + unsigned int eax; | |
| 27 | + unsigned int ebx; | |
| 28 | + unsigned int ecx; | |
| 29 | + unsigned int edx; | |
| 30 | + | |
| 31 | + unsigned int round = 0; | |
| 32 | + while (1) | |
| 33 | + { | |
| 34 | + asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1" | |
| 35 | + : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx) | |
| 36 | + : "0" (4), "2" (round)); | |
| 37 | + | |
| 38 | + enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f; | |
| 39 | + if (type == null) | |
| 40 | + /* That was the end. */ | |
| 41 | + break; | |
| 42 | + | |
| 43 | + unsigned int level = (eax >> 5) & 0x7; | |
| 44 | + | |
| 45 | + if ((level == 1 && type == data | |
| 46 | + && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE)) | |
| 47 | + || (level == 1 && type == inst | |
| 48 | + && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE)) | |
| 49 | + || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE)) | |
| 50 | + || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE)) | |
| 51 | + || (level == 4 && folded_rel_name == M(_SC_LEVEL4_CACHE_SIZE))) | |
| 52 | + { | |
| 53 | + unsigned int offset = M(name) - folded_rel_name; | |
| 54 | + | |
| 55 | + if (offset == 0) | |
| 56 | + /* Cache size. */ | |
| 57 | + return (((ebx >> 22) + 1) | |
| 58 | + * (((ebx >> 12) & 0x3ff) + 1) | |
| 59 | + * ((ebx & 0xfff) + 1) | |
| 60 | + * (ecx + 1)); | |
| 61 | + if (offset == 1) | |
| 62 | + return (ebx >> 22) + 1; | |
| 63 | + | |
| 64 | + assert (offset == 2); | |
| 65 | + return (ebx & 0xfff) + 1; | |
| 66 | + } | |
| 67 | + | |
| 68 | + ++round; | |
| 69 | + } | |
| 70 | + /* There is no other cache information anywhere else. */ | |
| 71 | + break; | |
| 72 | + } | |
| 73 | else | |
| 74 | { | |
| 75 | if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE)) | |
| 76 | Index: glibc-2.12-2-gc4ccff1/sysdeps/x86_64/cacheinfo.c | |
| 77 | =================================================================== | |
| 78 | --- glibc-2.12-2-gc4ccff1.orig/sysdeps/x86_64/cacheinfo.c | |
| 79 | +++ glibc-2.12-2-gc4ccff1/sysdeps/x86_64/cacheinfo.c | |
| 80 | @@ -181,6 +181,57 @@ intel_check_word (int name, unsigned int | |
| 81 | /* No need to look further. */ | |
| 82 | break; | |
| 83 | } | |
| 84 | + else if (byte == 0xff) | |
| 85 | + { | |
| 86 | + /* CPUID leaf 0x4 contains all the information. We need to | |
| 87 | + iterate over it. */ | |
| 88 | + unsigned int eax; | |
| 89 | + unsigned int ebx; | |
| 90 | + unsigned int ecx; | |
| 91 | + unsigned int edx; | |
| 92 | + | |
| 93 | + unsigned int round = 0; | |
| 94 | + while (1) | |
| 95 | + { | |
| 96 | + asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1" | |
| 97 | + : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx) | |
| 98 | + : "0" (4), "2" (round)); | |
| 99 | + | |
| 100 | + enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f; | |
| 101 | + if (type == null) | |
| 102 | + /* That was the end. */ | |
| 103 | + break; | |
| 104 | + | |
| 105 | + unsigned int level = (eax >> 5) & 0x7; | |
| 106 | + | |
| 107 | + if ((level == 1 && type == data | |
| 108 | + && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE)) | |
| 109 | + || (level == 1 && type == inst | |
| 110 | + && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE)) | |
| 111 | + || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE)) | |
| 112 | + || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE)) | |
| 113 | + || (level == 4 && folded_rel_name == M(_SC_LEVEL4_CACHE_SIZE))) | |
| 114 | + { | |
| 115 | + unsigned int offset = M(name) - folded_rel_name; | |
| 116 | + | |
| 117 | + if (offset == 0) | |
| 118 | + /* Cache size. */ | |
| 119 | + return (((ebx >> 22) + 1) | |
| 120 | + * (((ebx >> 12) & 0x3ff) + 1) | |
| 121 | + * ((ebx & 0xfff) + 1) | |
| 122 | + * (ecx + 1)); | |
| 123 | + if (offset == 1) | |
| 124 | + return (ebx >> 22) + 1; | |
| 125 | + | |
| 126 | + assert (offset == 2); | |
| 127 | + return (ebx & 0xfff) + 1; | |
| 128 | + } | |
| 129 | + | |
| 130 | + ++round; | |
| 131 | + } | |
| 132 | + /* There is no other cache information anywhere else. */ | |
| 133 | + break; | |
| 134 | + } | |
| 135 | else | |
| 136 | { | |
| 137 | if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE)) |