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[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28 #include "as.h"
29 #include "safe-ctype.h"
30 #include "subsegs.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
35
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
38 #endif
39
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
42 #endif
43
44 #ifndef DEFAULT_ARCH
45 #define DEFAULT_ARCH "i386"
46 #endif
47
48 #ifndef INLINE
49 #if __GNUC__ >= 2
50 #define INLINE __inline__
51 #else
52 #define INLINE
53 #endif
54 #endif
55
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
61 #define WAIT_PREFIX 0
62 #define SEG_PREFIX 1
63 #define ADDR_PREFIX 2
64 #define DATA_PREFIX 3
65 #define REP_PREFIX 4
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91 #define END_OF_INSN '\0'
92
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100 typedef struct
101 {
102 const insn_template *start;
103 const insn_template *end;
104 }
105 templates;
106
107 /* 386 operand encoding bytes: see 386 book for details of this. */
108 typedef struct
109 {
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113 }
114 modrm_byte;
115
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
118
119 /* 386 opcode byte to code indirect addressing. */
120 typedef struct
121 {
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125 }
126 sib_byte;
127
128 /* x86 arch names, types and features */
129 typedef struct
130 {
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 }
137 arch_entry;
138
139 /* Used to turn off indicated flags. */
140 typedef struct
141 {
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145 }
146 noarch_entry;
147
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
156 #ifdef TE_PE
157 static void pe_directive_secrel (int);
158 #endif
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
189 #ifndef I386COFF
190 static void s_bss (int);
191 #endif
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
194 #endif
195
196 static const char *default_arch = DEFAULT_ARCH;
197
198 /* This struct describes rounding control and SAE in the instruction. */
199 struct RC_Operation
200 {
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210 };
211
212 static struct RC_Operation rc_op;
213
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
218 {
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223 };
224
225 static struct Mask_Operation mask_op;
226
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229 struct Broadcast_Operation
230 {
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236 };
237
238 static struct Broadcast_Operation broadcast_op;
239
240 /* VEX prefix. */
241 typedef struct
242 {
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248 } vex_prefix;
249
250 /* 'md_assemble ()' gathers together information and puts it into a
251 i386_insn. */
252
253 union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
260 enum i386_error
261 {
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
271 unsupported,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
285 };
286
287 struct _i386_insn
288 {
289 /* TM holds the template for the insn were currently assembling. */
290 insn_template tm;
291
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
294 char suffix;
295
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
301 operands. */
302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types[MAX_OPERANDS];
307
308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
311
312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314 #define Operand_PCrel 1
315
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
318
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry *seg[2];
328
329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
338 addressing modes of this insn are encoded. */
339 modrm_byte rm;
340 rex_byte rex;
341 rex_byte vrex;
342 sib_byte sib;
343 vex_prefix vex;
344
345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
357 /* Prefer load or store in encoding. */
358 enum
359 {
360 dir_encoding_default = 0,
361 dir_encoding_load,
362 dir_encoding_store
363 } dir_encoding;
364
365 /* Prefer 8bit or 32bit displacement in encoding. */
366 enum
367 {
368 disp_encoding_default = 0,
369 disp_encoding_8bit,
370 disp_encoding_32bit
371 } disp_encoding;
372
373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
382 /* REP prefix. */
383 const char *rep_prefix;
384
385 /* HLE prefix. */
386 const char *hle_prefix;
387
388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
393
394 /* Error message. */
395 enum i386_error error;
396 };
397
398 typedef struct _i386_insn i386_insn;
399
400 /* Link RC type with corresponding string, that'll be looked for in
401 asm. */
402 struct RC_name
403 {
404 enum rc_type type;
405 const char *name;
406 unsigned int len;
407 };
408
409 static const struct RC_name RC_NamesTable[] =
410 {
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
416 };
417
418 /* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
420 const char extra_symbol_chars[] = "*%-([{}"
421 #ifdef LEX_AT
422 "@"
423 #endif
424 #ifdef LEX_QM
425 "?"
426 #endif
427 ;
428
429 #if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
431 && !defined (TE_GNU) \
432 && !defined (TE_LINUX) \
433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
435 && !defined (TE_FreeBSD) \
436 && !defined (TE_DragonFly) \
437 && !defined (TE_NetBSD)))
438 /* This array holds the chars that always start a comment. If the
439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441 const char *i386_comment_chars = "#/";
442 #define SVR4_COMMENT_CHARS 1
443 #define PREFIX_SEPARATOR '\\'
444
445 #else
446 const char *i386_comment_chars = "#";
447 #define PREFIX_SEPARATOR '/'
448 #endif
449
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
457 '/' isn't otherwise defined. */
458 const char line_comment_chars[] = "#/";
459
460 const char line_separator_chars[] = ";";
461
462 /* Chars that can be used to separate mant from exp in floating point
463 nums. */
464 const char EXP_CHARS[] = "eE";
465
466 /* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
469 const char FLT_CHARS[] = "fFdDxX";
470
471 /* Tables for lexical analysis. */
472 static char mnemonic_chars[256];
473 static char register_chars[256];
474 static char operand_chars[256];
475 static char identifier_chars[256];
476 static char digit_chars[256];
477
478 /* Lexical macros. */
479 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480 #define is_operand_char(x) (operand_chars[(unsigned char) x])
481 #define is_register_char(x) (register_chars[(unsigned char) x])
482 #define is_space_char(x) ((x) == ' ')
483 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484 #define is_digit_char(x) (digit_chars[(unsigned char) x])
485
486 /* All non-digit non-letter characters that may occur in an operand. */
487 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489 /* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
492 assembler instruction). */
493 static char save_stack[32];
494 static char *save_stack_p;
495 #define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497 #define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
500 /* The instruction we're assembling. */
501 static i386_insn i;
502
503 /* Possible templates for current insn. */
504 static const templates *current_templates;
505
506 /* Per instruction expressionS buffers: max displacements & immediates. */
507 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
509
510 /* Current operand we are working on. */
511 static int this_operand = -1;
512
513 /* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516 enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521 static enum flag_code flag_code;
522 static unsigned int object_64bit;
523 static unsigned int disallow_64bit_reloc;
524 static int use_rela_relocations = 0;
525
526 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
530 /* The ELF ABI to use. */
531 enum x86_elf_abi
532 {
533 I386_ABI,
534 X86_64_ABI,
535 X86_64_X32_ABI
536 };
537
538 static enum x86_elf_abi x86_elf_abi = I386_ABI;
539 #endif
540
541 #if defined (TE_PE) || defined (TE_PEP)
542 /* Use big object file format. */
543 static int use_big_obj = 0;
544 #endif
545
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 /* 1 if generating code for a shared library. */
548 static int shared = 0;
549 #endif
550
551 /* 1 for intel syntax,
552 0 if att syntax. */
553 static int intel_syntax = 0;
554
555 /* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557 static int intel64;
558
559 /* 1 for intel mnemonic,
560 0 if att mnemonic. */
561 static int intel_mnemonic = !SYSV386_COMPAT;
562
563 /* 1 if support old (<= 2.8.1) versions of gcc. */
564 static int old_gcc = OLDGCC_COMPAT;
565
566 /* 1 if pseudo registers are permitted. */
567 static int allow_pseudo_reg = 0;
568
569 /* 1 if register prefix % not required. */
570 static int allow_naked_reg = 0;
571
572 /* 1 if the assembler should add BND prefix for all control-transferring
573 instructions supporting it, even if this prefix wasn't specified
574 explicitly. */
575 static int add_bnd_prefix = 0;
576
577 /* 1 if pseudo index register, eiz/riz, is allowed . */
578 static int allow_index_reg = 0;
579
580 /* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582 static int omit_lock_prefix = 0;
583
584 /* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586 static int avoid_fence = 0;
587
588 /* 1 if the assembler should generate relax relocations. */
589
590 static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592
593 static enum check_kind
594 {
595 check_none = 0,
596 check_warning,
597 check_error
598 }
599 sse_check, operand_check = check_warning;
600
601 /* Register prefix used for error message. */
602 static const char *register_prefix = "%";
603
604 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607 static char stackop_size = '\0';
608
609 /* Non-zero to optimize code alignment. */
610 int optimize_align_code = 1;
611
612 /* Non-zero to quieten some warnings. */
613 static int quiet_warnings = 0;
614
615 /* CPU name. */
616 static const char *cpu_arch_name = NULL;
617 static char *cpu_sub_arch_name = NULL;
618
619 /* CPU feature flags. */
620 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
621
622 /* If we have selected a cpu we are generating instructions for. */
623 static int cpu_arch_tune_set = 0;
624
625 /* Cpu we are generating instructions for. */
626 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
627
628 /* CPU feature flags of cpu we are generating instructions for. */
629 static i386_cpu_flags cpu_arch_tune_flags;
630
631 /* CPU instruction set architecture used. */
632 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
633
634 /* CPU feature flags of instruction set architecture used. */
635 i386_cpu_flags cpu_arch_isa_flags;
636
637 /* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639 static unsigned int no_cond_jump_promotion = 0;
640
641 /* Encode SSE instructions with VEX prefix. */
642 static unsigned int sse2avx;
643
644 /* Encode scalar AVX instructions with specific vector length. */
645 static enum
646 {
647 vex128 = 0,
648 vex256
649 } avxscalar;
650
651 /* Encode scalar EVEX LIG instructions with specific vector length. */
652 static enum
653 {
654 evexl128 = 0,
655 evexl256,
656 evexl512
657 } evexlig;
658
659 /* Encode EVEX WIG instructions with specific evex.w. */
660 static enum
661 {
662 evexw0 = 0,
663 evexw1
664 } evexwig;
665
666 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
667 static enum rc_type evexrcig = rne;
668
669 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
670 static symbolS *GOT_symbol;
671
672 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
673 unsigned int x86_dwarf2_return_column;
674
675 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676 int x86_cie_data_alignment;
677
678 /* Interface to relax_segment.
679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
682
683 /* Types. */
684 #define UNCOND_JUMP 0
685 #define COND_JUMP 1
686 #define COND_JUMP86 2
687
688 /* Sizes. */
689 #define CODE16 1
690 #define SMALL 0
691 #define SMALL16 (SMALL | CODE16)
692 #define BIG 2
693 #define BIG16 (BIG | CODE16)
694
695 #ifndef INLINE
696 #ifdef __GNUC__
697 #define INLINE __inline__
698 #else
699 #define INLINE
700 #endif
701 #endif
702
703 #define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705 #define TYPE_FROM_RELAX_STATE(s) \
706 ((s) >> 2)
707 #define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
709
710 /* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
717
718 const relax_typeS md_relax_table[] =
719 {
720 /* The fields are:
721 1) most positive reach of this state,
722 2) most negative reach of this state,
723 3) how many bytes this mode will have in the variable part of the frag
724 4) which index into the table to try if we can't fit into this one. */
725
726 /* UNCOND_JUMP states. */
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
731 {0, 0, 4, 0},
732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
734 {0, 0, 2, 0},
735
736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
741 {0, 0, 5, 0},
742 /* word conditionals add 3 bytes to frag:
743 1 extra opcode byte, 2 displacement bytes. */
744 {0, 0, 3, 0},
745
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
751 {0, 0, 5, 0},
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
754 {0, 0, 4, 0}
755 };
756
757 static const arch_entry cpu_arch[] =
758 {
759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
762 CPU_GENERIC32_FLAGS, 0 },
763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
764 CPU_GENERIC64_FLAGS, 0 },
765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
766 CPU_NONE_FLAGS, 0 },
767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
768 CPU_I186_FLAGS, 0 },
769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
770 CPU_I286_FLAGS, 0 },
771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
772 CPU_I386_FLAGS, 0 },
773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
774 CPU_I486_FLAGS, 0 },
775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
776 CPU_I586_FLAGS, 0 },
777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
778 CPU_I686_FLAGS, 0 },
779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
780 CPU_I586_FLAGS, 0 },
781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
782 CPU_PENTIUMPRO_FLAGS, 0 },
783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
784 CPU_P2_FLAGS, 0 },
785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
786 CPU_P3_FLAGS, 0 },
787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
788 CPU_P4_FLAGS, 0 },
789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
790 CPU_CORE_FLAGS, 0 },
791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
792 CPU_NOCONA_FLAGS, 0 },
793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
794 CPU_CORE_FLAGS, 1 },
795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
796 CPU_CORE_FLAGS, 0 },
797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
798 CPU_CORE2_FLAGS, 1 },
799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
800 CPU_CORE2_FLAGS, 0 },
801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
802 CPU_COREI7_FLAGS, 0 },
803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
804 CPU_L1OM_FLAGS, 0 },
805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
806 CPU_K1OM_FLAGS, 0 },
807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
808 CPU_IAMCU_FLAGS, 0 },
809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
810 CPU_K6_FLAGS, 0 },
811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
812 CPU_K6_2_FLAGS, 0 },
813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
814 CPU_ATHLON_FLAGS, 0 },
815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
816 CPU_K8_FLAGS, 1 },
817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
818 CPU_K8_FLAGS, 0 },
819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
820 CPU_K8_FLAGS, 0 },
821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
822 CPU_AMDFAM10_FLAGS, 0 },
823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
824 CPU_BDVER1_FLAGS, 0 },
825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
826 CPU_BDVER2_FLAGS, 0 },
827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
828 CPU_BDVER3_FLAGS, 0 },
829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
830 CPU_BDVER4_FLAGS, 0 },
831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
832 CPU_ZNVER1_FLAGS, 0 },
833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
834 CPU_BTVER1_FLAGS, 0 },
835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
836 CPU_BTVER2_FLAGS, 0 },
837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
838 CPU_8087_FLAGS, 0 },
839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
840 CPU_287_FLAGS, 0 },
841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
842 CPU_387_FLAGS, 0 },
843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
844 CPU_687_FLAGS, 0 },
845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
846 CPU_MMX_FLAGS, 0 },
847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
848 CPU_SSE_FLAGS, 0 },
849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
850 CPU_SSE2_FLAGS, 0 },
851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
852 CPU_SSE3_FLAGS, 0 },
853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
854 CPU_SSSE3_FLAGS, 0 },
855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
856 CPU_SSE4_1_FLAGS, 0 },
857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
858 CPU_SSE4_2_FLAGS, 0 },
859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
860 CPU_SSE4_2_FLAGS, 0 },
861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
862 CPU_AVX_FLAGS, 0 },
863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
864 CPU_AVX2_FLAGS, 0 },
865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
866 CPU_AVX512F_FLAGS, 0 },
867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
868 CPU_AVX512CD_FLAGS, 0 },
869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
870 CPU_AVX512ER_FLAGS, 0 },
871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
872 CPU_AVX512PF_FLAGS, 0 },
873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
874 CPU_AVX512DQ_FLAGS, 0 },
875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
876 CPU_AVX512BW_FLAGS, 0 },
877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
878 CPU_AVX512VL_FLAGS, 0 },
879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
880 CPU_VMX_FLAGS, 0 },
881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
882 CPU_VMFUNC_FLAGS, 0 },
883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
884 CPU_SMX_FLAGS, 0 },
885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
886 CPU_XSAVE_FLAGS, 0 },
887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
888 CPU_XSAVEOPT_FLAGS, 0 },
889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
890 CPU_XSAVEC_FLAGS, 0 },
891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
892 CPU_XSAVES_FLAGS, 0 },
893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
894 CPU_AES_FLAGS, 0 },
895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
896 CPU_PCLMUL_FLAGS, 0 },
897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
898 CPU_PCLMUL_FLAGS, 1 },
899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
900 CPU_FSGSBASE_FLAGS, 0 },
901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
902 CPU_RDRND_FLAGS, 0 },
903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
904 CPU_F16C_FLAGS, 0 },
905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
906 CPU_BMI2_FLAGS, 0 },
907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
908 CPU_FMA_FLAGS, 0 },
909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
910 CPU_FMA4_FLAGS, 0 },
911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
912 CPU_XOP_FLAGS, 0 },
913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
914 CPU_LWP_FLAGS, 0 },
915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
916 CPU_MOVBE_FLAGS, 0 },
917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
918 CPU_CX16_FLAGS, 0 },
919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
920 CPU_EPT_FLAGS, 0 },
921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
922 CPU_LZCNT_FLAGS, 0 },
923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
924 CPU_HLE_FLAGS, 0 },
925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
926 CPU_RTM_FLAGS, 0 },
927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
928 CPU_INVPCID_FLAGS, 0 },
929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
930 CPU_CLFLUSH_FLAGS, 0 },
931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
932 CPU_NOP_FLAGS, 0 },
933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
934 CPU_SYSCALL_FLAGS, 0 },
935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
936 CPU_RDTSCP_FLAGS, 0 },
937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
938 CPU_3DNOW_FLAGS, 0 },
939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
940 CPU_3DNOWA_FLAGS, 0 },
941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
942 CPU_PADLOCK_FLAGS, 0 },
943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
944 CPU_SVME_FLAGS, 1 },
945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
946 CPU_SVME_FLAGS, 0 },
947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
948 CPU_SSE4A_FLAGS, 0 },
949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
950 CPU_ABM_FLAGS, 0 },
951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
952 CPU_BMI_FLAGS, 0 },
953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
954 CPU_TBM_FLAGS, 0 },
955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
956 CPU_ADX_FLAGS, 0 },
957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
958 CPU_RDSEED_FLAGS, 0 },
959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
960 CPU_PRFCHW_FLAGS, 0 },
961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
962 CPU_SMAP_FLAGS, 0 },
963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
964 CPU_MPX_FLAGS, 0 },
965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
966 CPU_SHA_FLAGS, 0 },
967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
968 CPU_CLFLUSHOPT_FLAGS, 0 },
969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
970 CPU_PREFETCHWT1_FLAGS, 0 },
971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
972 CPU_SE1_FLAGS, 0 },
973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
974 CPU_CLWB_FLAGS, 0 },
975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
976 CPU_AVX512IFMA_FLAGS, 0 },
977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
978 CPU_AVX512VBMI_FLAGS, 0 },
979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
980 CPU_AVX512_4FMAPS_FLAGS, 0 },
981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
982 CPU_AVX512_4VNNIW_FLAGS, 0 },
983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
984 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
985 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
986 CPU_AVX512_VBMI2_FLAGS, 0 },
987 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
988 CPU_AVX512_VNNI_FLAGS, 0 },
989 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
990 CPU_AVX512_BITALG_FLAGS, 0 },
991 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
992 CPU_CLZERO_FLAGS, 0 },
993 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
994 CPU_MWAITX_FLAGS, 0 },
995 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
996 CPU_OSPKE_FLAGS, 0 },
997 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
998 CPU_RDPID_FLAGS, 0 },
999 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1000 CPU_PTWRITE_FLAGS, 0 },
1001 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
1002 CPU_CET_FLAGS, 0 },
1003 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1004 CPU_GFNI_FLAGS, 0 },
1005 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1006 CPU_VAES_FLAGS, 0 },
1007 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1008 CPU_VPCLMULQDQ_FLAGS, 0 },
1009 };
1010
1011 static const noarch_entry cpu_noarch[] =
1012 {
1013 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1014 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1015 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1016 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1017 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1018 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1019 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1020 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1021 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1022 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1023 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1024 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1025 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1026 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1027 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1035 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1036 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1037 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1038 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1039 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1040 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1041 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1042 };
1043
1044 #ifdef I386COFF
1045 /* Like s_lcomm_internal in gas/read.c but the alignment string
1046 is allowed to be optional. */
1047
1048 static symbolS *
1049 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1050 {
1051 addressT align = 0;
1052
1053 SKIP_WHITESPACE ();
1054
1055 if (needs_align
1056 && *input_line_pointer == ',')
1057 {
1058 align = parse_align (needs_align - 1);
1059
1060 if (align == (addressT) -1)
1061 return NULL;
1062 }
1063 else
1064 {
1065 if (size >= 8)
1066 align = 3;
1067 else if (size >= 4)
1068 align = 2;
1069 else if (size >= 2)
1070 align = 1;
1071 else
1072 align = 0;
1073 }
1074
1075 bss_alloc (symbolP, size, align);
1076 return symbolP;
1077 }
1078
1079 static void
1080 pe_lcomm (int needs_align)
1081 {
1082 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1083 }
1084 #endif
1085
1086 const pseudo_typeS md_pseudo_table[] =
1087 {
1088 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1089 {"align", s_align_bytes, 0},
1090 #else
1091 {"align", s_align_ptwo, 0},
1092 #endif
1093 {"arch", set_cpu_arch, 0},
1094 #ifndef I386COFF
1095 {"bss", s_bss, 0},
1096 #else
1097 {"lcomm", pe_lcomm, 1},
1098 #endif
1099 {"ffloat", float_cons, 'f'},
1100 {"dfloat", float_cons, 'd'},
1101 {"tfloat", float_cons, 'x'},
1102 {"value", cons, 2},
1103 {"slong", signed_cons, 4},
1104 {"noopt", s_ignore, 0},
1105 {"optim", s_ignore, 0},
1106 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1107 {"code16", set_code_flag, CODE_16BIT},
1108 {"code32", set_code_flag, CODE_32BIT},
1109 #ifdef BFD64
1110 {"code64", set_code_flag, CODE_64BIT},
1111 #endif
1112 {"intel_syntax", set_intel_syntax, 1},
1113 {"att_syntax", set_intel_syntax, 0},
1114 {"intel_mnemonic", set_intel_mnemonic, 1},
1115 {"att_mnemonic", set_intel_mnemonic, 0},
1116 {"allow_index_reg", set_allow_index_reg, 1},
1117 {"disallow_index_reg", set_allow_index_reg, 0},
1118 {"sse_check", set_check, 0},
1119 {"operand_check", set_check, 1},
1120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1121 {"largecomm", handle_large_common, 0},
1122 #else
1123 {"file", (void (*) (int)) dwarf2_directive_file, 0},
1124 {"loc", dwarf2_directive_loc, 0},
1125 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1126 #endif
1127 #ifdef TE_PE
1128 {"secrel32", pe_directive_secrel, 0},
1129 #endif
1130 {0, 0, 0}
1131 };
1132
1133 /* For interface with expression (). */
1134 extern char *input_line_pointer;
1135
1136 /* Hash table for instruction mnemonic lookup. */
1137 static struct hash_control *op_hash;
1138
1139 /* Hash table for register lookup. */
1140 static struct hash_control *reg_hash;
1141 \f
1142 void
1143 i386_align_code (fragS *fragP, int count)
1144 {
1145 /* Various efficient no-op patterns for aligning code labels.
1146 Note: Don't try to assemble the instructions in the comments.
1147 0L and 0w are not legal. */
1148 static const unsigned char f32_1[] =
1149 {0x90}; /* nop */
1150 static const unsigned char f32_2[] =
1151 {0x66,0x90}; /* xchg %ax,%ax */
1152 static const unsigned char f32_3[] =
1153 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1154 static const unsigned char f32_4[] =
1155 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1156 static const unsigned char f32_5[] =
1157 {0x90, /* nop */
1158 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1159 static const unsigned char f32_6[] =
1160 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1161 static const unsigned char f32_7[] =
1162 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1163 static const unsigned char f32_8[] =
1164 {0x90, /* nop */
1165 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1166 static const unsigned char f32_9[] =
1167 {0x89,0xf6, /* movl %esi,%esi */
1168 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1169 static const unsigned char f32_10[] =
1170 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1171 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1172 static const unsigned char f32_11[] =
1173 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1174 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1175 static const unsigned char f32_12[] =
1176 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1177 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1178 static const unsigned char f32_13[] =
1179 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1180 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1181 static const unsigned char f32_14[] =
1182 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1183 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1184 static const unsigned char f16_3[] =
1185 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1186 static const unsigned char f16_4[] =
1187 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1188 static const unsigned char f16_5[] =
1189 {0x90, /* nop */
1190 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1191 static const unsigned char f16_6[] =
1192 {0x89,0xf6, /* mov %si,%si */
1193 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1194 static const unsigned char f16_7[] =
1195 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1196 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1197 static const unsigned char f16_8[] =
1198 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1199 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1200 static const unsigned char jump_31[] =
1201 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1203 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1204 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1205 static const unsigned char *const f32_patt[] = {
1206 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1207 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1208 };
1209 static const unsigned char *const f16_patt[] = {
1210 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1211 };
1212 /* nopl (%[re]ax) */
1213 static const unsigned char alt_3[] =
1214 {0x0f,0x1f,0x00};
1215 /* nopl 0(%[re]ax) */
1216 static const unsigned char alt_4[] =
1217 {0x0f,0x1f,0x40,0x00};
1218 /* nopl 0(%[re]ax,%[re]ax,1) */
1219 static const unsigned char alt_5[] =
1220 {0x0f,0x1f,0x44,0x00,0x00};
1221 /* nopw 0(%[re]ax,%[re]ax,1) */
1222 static const unsigned char alt_6[] =
1223 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1224 /* nopl 0L(%[re]ax) */
1225 static const unsigned char alt_7[] =
1226 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1227 /* nopl 0L(%[re]ax,%[re]ax,1) */
1228 static const unsigned char alt_8[] =
1229 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1230 /* nopw 0L(%[re]ax,%[re]ax,1) */
1231 static const unsigned char alt_9[] =
1232 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1233 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1234 static const unsigned char alt_10[] =
1235 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1236 static const unsigned char *const alt_patt[] = {
1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1238 alt_9, alt_10
1239 };
1240
1241 /* Only align for at least a positive non-zero boundary. */
1242 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1243 return;
1244
1245 /* We need to decide which NOP sequence to use for 32bit and
1246 64bit. When -mtune= is used:
1247
1248 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1249 PROCESSOR_GENERIC32, f32_patt will be used.
1250 2. For the rest, alt_patt will be used.
1251
1252 When -mtune= isn't used, alt_patt will be used if
1253 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1254 be used.
1255
1256 When -march= or .arch is used, we can't use anything beyond
1257 cpu_arch_isa_flags. */
1258
1259 if (flag_code == CODE_16BIT)
1260 {
1261 if (count > 8)
1262 {
1263 memcpy (fragP->fr_literal + fragP->fr_fix,
1264 jump_31, count);
1265 /* Adjust jump offset. */
1266 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1267 }
1268 else
1269 memcpy (fragP->fr_literal + fragP->fr_fix,
1270 f16_patt[count - 1], count);
1271 }
1272 else
1273 {
1274 const unsigned char *const *patt = NULL;
1275
1276 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1277 {
1278 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1279 switch (cpu_arch_tune)
1280 {
1281 case PROCESSOR_UNKNOWN:
1282 /* We use cpu_arch_isa_flags to check if we SHOULD
1283 optimize with nops. */
1284 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1285 patt = alt_patt;
1286 else
1287 patt = f32_patt;
1288 break;
1289 case PROCESSOR_PENTIUM4:
1290 case PROCESSOR_NOCONA:
1291 case PROCESSOR_CORE:
1292 case PROCESSOR_CORE2:
1293 case PROCESSOR_COREI7:
1294 case PROCESSOR_L1OM:
1295 case PROCESSOR_K1OM:
1296 case PROCESSOR_GENERIC64:
1297 case PROCESSOR_K6:
1298 case PROCESSOR_ATHLON:
1299 case PROCESSOR_K8:
1300 case PROCESSOR_AMDFAM10:
1301 case PROCESSOR_BD:
1302 case PROCESSOR_ZNVER:
1303 case PROCESSOR_BT:
1304 patt = alt_patt;
1305 break;
1306 case PROCESSOR_I386:
1307 case PROCESSOR_I486:
1308 case PROCESSOR_PENTIUM:
1309 case PROCESSOR_PENTIUMPRO:
1310 case PROCESSOR_IAMCU:
1311 case PROCESSOR_GENERIC32:
1312 patt = f32_patt;
1313 break;
1314 }
1315 }
1316 else
1317 {
1318 switch (fragP->tc_frag_data.tune)
1319 {
1320 case PROCESSOR_UNKNOWN:
1321 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1322 PROCESSOR_UNKNOWN. */
1323 abort ();
1324 break;
1325
1326 case PROCESSOR_I386:
1327 case PROCESSOR_I486:
1328 case PROCESSOR_PENTIUM:
1329 case PROCESSOR_IAMCU:
1330 case PROCESSOR_K6:
1331 case PROCESSOR_ATHLON:
1332 case PROCESSOR_K8:
1333 case PROCESSOR_AMDFAM10:
1334 case PROCESSOR_BD:
1335 case PROCESSOR_ZNVER:
1336 case PROCESSOR_BT:
1337 case PROCESSOR_GENERIC32:
1338 /* We use cpu_arch_isa_flags to check if we CAN optimize
1339 with nops. */
1340 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1341 patt = alt_patt;
1342 else
1343 patt = f32_patt;
1344 break;
1345 case PROCESSOR_PENTIUMPRO:
1346 case PROCESSOR_PENTIUM4:
1347 case PROCESSOR_NOCONA:
1348 case PROCESSOR_CORE:
1349 case PROCESSOR_CORE2:
1350 case PROCESSOR_COREI7:
1351 case PROCESSOR_L1OM:
1352 case PROCESSOR_K1OM:
1353 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1354 patt = alt_patt;
1355 else
1356 patt = f32_patt;
1357 break;
1358 case PROCESSOR_GENERIC64:
1359 patt = alt_patt;
1360 break;
1361 }
1362 }
1363
1364 if (patt == f32_patt)
1365 {
1366 /* If the padding is less than 15 bytes, we use the normal
1367 ones. Otherwise, we use a jump instruction and adjust
1368 its offset. */
1369 int limit;
1370
1371 /* For 64bit, the limit is 3 bytes. */
1372 if (flag_code == CODE_64BIT
1373 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1374 limit = 3;
1375 else
1376 limit = 15;
1377 if (count < limit)
1378 memcpy (fragP->fr_literal + fragP->fr_fix,
1379 patt[count - 1], count);
1380 else
1381 {
1382 memcpy (fragP->fr_literal + fragP->fr_fix,
1383 jump_31, count);
1384 /* Adjust jump offset. */
1385 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1386 }
1387 }
1388 else
1389 {
1390 /* Maximum length of an instruction is 10 byte. If the
1391 padding is greater than 10 bytes and we don't use jump,
1392 we have to break it into smaller pieces. */
1393 int padding = count;
1394 while (padding > 10)
1395 {
1396 padding -= 10;
1397 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1398 patt [9], 10);
1399 }
1400
1401 if (padding)
1402 memcpy (fragP->fr_literal + fragP->fr_fix,
1403 patt [padding - 1], padding);
1404 }
1405 }
1406 fragP->fr_var = count;
1407 }
1408
1409 static INLINE int
1410 operand_type_all_zero (const union i386_operand_type *x)
1411 {
1412 switch (ARRAY_SIZE(x->array))
1413 {
1414 case 3:
1415 if (x->array[2])
1416 return 0;
1417 /* Fall through. */
1418 case 2:
1419 if (x->array[1])
1420 return 0;
1421 /* Fall through. */
1422 case 1:
1423 return !x->array[0];
1424 default:
1425 abort ();
1426 }
1427 }
1428
1429 static INLINE void
1430 operand_type_set (union i386_operand_type *x, unsigned int v)
1431 {
1432 switch (ARRAY_SIZE(x->array))
1433 {
1434 case 3:
1435 x->array[2] = v;
1436 /* Fall through. */
1437 case 2:
1438 x->array[1] = v;
1439 /* Fall through. */
1440 case 1:
1441 x->array[0] = v;
1442 /* Fall through. */
1443 break;
1444 default:
1445 abort ();
1446 }
1447 }
1448
1449 static INLINE int
1450 operand_type_equal (const union i386_operand_type *x,
1451 const union i386_operand_type *y)
1452 {
1453 switch (ARRAY_SIZE(x->array))
1454 {
1455 case 3:
1456 if (x->array[2] != y->array[2])
1457 return 0;
1458 /* Fall through. */
1459 case 2:
1460 if (x->array[1] != y->array[1])
1461 return 0;
1462 /* Fall through. */
1463 case 1:
1464 return x->array[0] == y->array[0];
1465 break;
1466 default:
1467 abort ();
1468 }
1469 }
1470
1471 static INLINE int
1472 cpu_flags_all_zero (const union i386_cpu_flags *x)
1473 {
1474 switch (ARRAY_SIZE(x->array))
1475 {
1476 case 4:
1477 if (x->array[3])
1478 return 0;
1479 /* Fall through. */
1480 case 3:
1481 if (x->array[2])
1482 return 0;
1483 /* Fall through. */
1484 case 2:
1485 if (x->array[1])
1486 return 0;
1487 /* Fall through. */
1488 case 1:
1489 return !x->array[0];
1490 default:
1491 abort ();
1492 }
1493 }
1494
1495 static INLINE int
1496 cpu_flags_equal (const union i386_cpu_flags *x,
1497 const union i386_cpu_flags *y)
1498 {
1499 switch (ARRAY_SIZE(x->array))
1500 {
1501 case 4:
1502 if (x->array[3] != y->array[3])
1503 return 0;
1504 /* Fall through. */
1505 case 3:
1506 if (x->array[2] != y->array[2])
1507 return 0;
1508 /* Fall through. */
1509 case 2:
1510 if (x->array[1] != y->array[1])
1511 return 0;
1512 /* Fall through. */
1513 case 1:
1514 return x->array[0] == y->array[0];
1515 break;
1516 default:
1517 abort ();
1518 }
1519 }
1520
1521 static INLINE int
1522 cpu_flags_check_cpu64 (i386_cpu_flags f)
1523 {
1524 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1525 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1526 }
1527
1528 static INLINE i386_cpu_flags
1529 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1530 {
1531 switch (ARRAY_SIZE (x.array))
1532 {
1533 case 4:
1534 x.array [3] &= y.array [3];
1535 /* Fall through. */
1536 case 3:
1537 x.array [2] &= y.array [2];
1538 /* Fall through. */
1539 case 2:
1540 x.array [1] &= y.array [1];
1541 /* Fall through. */
1542 case 1:
1543 x.array [0] &= y.array [0];
1544 break;
1545 default:
1546 abort ();
1547 }
1548 return x;
1549 }
1550
1551 static INLINE i386_cpu_flags
1552 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1553 {
1554 switch (ARRAY_SIZE (x.array))
1555 {
1556 case 4:
1557 x.array [3] |= y.array [3];
1558 /* Fall through. */
1559 case 3:
1560 x.array [2] |= y.array [2];
1561 /* Fall through. */
1562 case 2:
1563 x.array [1] |= y.array [1];
1564 /* Fall through. */
1565 case 1:
1566 x.array [0] |= y.array [0];
1567 break;
1568 default:
1569 abort ();
1570 }
1571 return x;
1572 }
1573
1574 static INLINE i386_cpu_flags
1575 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1576 {
1577 switch (ARRAY_SIZE (x.array))
1578 {
1579 case 4:
1580 x.array [3] &= ~y.array [3];
1581 /* Fall through. */
1582 case 3:
1583 x.array [2] &= ~y.array [2];
1584 /* Fall through. */
1585 case 2:
1586 x.array [1] &= ~y.array [1];
1587 /* Fall through. */
1588 case 1:
1589 x.array [0] &= ~y.array [0];
1590 break;
1591 default:
1592 abort ();
1593 }
1594 return x;
1595 }
1596
1597 #define CPU_FLAGS_ARCH_MATCH 0x1
1598 #define CPU_FLAGS_64BIT_MATCH 0x2
1599 #define CPU_FLAGS_AES_MATCH 0x4
1600 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1601 #define CPU_FLAGS_AVX_MATCH 0x10
1602
1603 #define CPU_FLAGS_32BIT_MATCH \
1604 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1605 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1606 #define CPU_FLAGS_PERFECT_MATCH \
1607 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1608
1609 /* Return CPU flags match bits. */
1610
1611 static int
1612 cpu_flags_match (const insn_template *t)
1613 {
1614 i386_cpu_flags x = t->cpu_flags;
1615 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1616
1617 x.bitfield.cpu64 = 0;
1618 x.bitfield.cpuno64 = 0;
1619
1620 if (cpu_flags_all_zero (&x))
1621 {
1622 /* This instruction is available on all archs. */
1623 match |= CPU_FLAGS_32BIT_MATCH;
1624 }
1625 else
1626 {
1627 /* This instruction is available only on some archs. */
1628 i386_cpu_flags cpu = cpu_arch_flags;
1629
1630 cpu = cpu_flags_and (x, cpu);
1631 if (!cpu_flags_all_zero (&cpu))
1632 {
1633 if (x.bitfield.cpuavx)
1634 {
1635 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1636 if (cpu.bitfield.cpuavx)
1637 {
1638 /* Check SSE2AVX. */
1639 if (!t->opcode_modifier.sse2avx|| sse2avx)
1640 {
1641 match |= (CPU_FLAGS_ARCH_MATCH
1642 | CPU_FLAGS_AVX_MATCH);
1643 /* Check AES. */
1644 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1645 match |= CPU_FLAGS_AES_MATCH;
1646 /* Check PCLMUL. */
1647 if (!x.bitfield.cpupclmul
1648 || cpu.bitfield.cpupclmul)
1649 match |= CPU_FLAGS_PCLMUL_MATCH;
1650 }
1651 }
1652 else
1653 match |= CPU_FLAGS_ARCH_MATCH;
1654 }
1655 else if (x.bitfield.cpuavx512vl)
1656 {
1657 /* Match AVX512VL. */
1658 if (cpu.bitfield.cpuavx512vl)
1659 {
1660 /* Need another match. */
1661 cpu.bitfield.cpuavx512vl = 0;
1662 if (!cpu_flags_all_zero (&cpu))
1663 match |= CPU_FLAGS_32BIT_MATCH;
1664 else
1665 match |= CPU_FLAGS_ARCH_MATCH;
1666 }
1667 else
1668 match |= CPU_FLAGS_ARCH_MATCH;
1669 }
1670 else
1671 match |= CPU_FLAGS_32BIT_MATCH;
1672 }
1673 }
1674 return match;
1675 }
1676
1677 static INLINE i386_operand_type
1678 operand_type_and (i386_operand_type x, i386_operand_type y)
1679 {
1680 switch (ARRAY_SIZE (x.array))
1681 {
1682 case 3:
1683 x.array [2] &= y.array [2];
1684 /* Fall through. */
1685 case 2:
1686 x.array [1] &= y.array [1];
1687 /* Fall through. */
1688 case 1:
1689 x.array [0] &= y.array [0];
1690 break;
1691 default:
1692 abort ();
1693 }
1694 return x;
1695 }
1696
1697 static INLINE i386_operand_type
1698 operand_type_or (i386_operand_type x, i386_operand_type y)
1699 {
1700 switch (ARRAY_SIZE (x.array))
1701 {
1702 case 3:
1703 x.array [2] |= y.array [2];
1704 /* Fall through. */
1705 case 2:
1706 x.array [1] |= y.array [1];
1707 /* Fall through. */
1708 case 1:
1709 x.array [0] |= y.array [0];
1710 break;
1711 default:
1712 abort ();
1713 }
1714 return x;
1715 }
1716
1717 static INLINE i386_operand_type
1718 operand_type_xor (i386_operand_type x, i386_operand_type y)
1719 {
1720 switch (ARRAY_SIZE (x.array))
1721 {
1722 case 3:
1723 x.array [2] ^= y.array [2];
1724 /* Fall through. */
1725 case 2:
1726 x.array [1] ^= y.array [1];
1727 /* Fall through. */
1728 case 1:
1729 x.array [0] ^= y.array [0];
1730 break;
1731 default:
1732 abort ();
1733 }
1734 return x;
1735 }
1736
1737 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1738 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1739 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1740 static const i386_operand_type inoutportreg
1741 = OPERAND_TYPE_INOUTPORTREG;
1742 static const i386_operand_type reg16_inoutportreg
1743 = OPERAND_TYPE_REG16_INOUTPORTREG;
1744 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1745 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1746 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1747 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1748 static const i386_operand_type anydisp
1749 = OPERAND_TYPE_ANYDISP;
1750 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1751 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1752 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1753 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1754 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1755 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1756 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1757 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1758 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1759 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1760 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1761 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1762 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1763 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1764
1765 enum operand_type
1766 {
1767 reg,
1768 imm,
1769 disp,
1770 anymem
1771 };
1772
1773 static INLINE int
1774 operand_type_check (i386_operand_type t, enum operand_type c)
1775 {
1776 switch (c)
1777 {
1778 case reg:
1779 return (t.bitfield.reg8
1780 || t.bitfield.reg16
1781 || t.bitfield.reg32
1782 || t.bitfield.reg64);
1783
1784 case imm:
1785 return (t.bitfield.imm8
1786 || t.bitfield.imm8s
1787 || t.bitfield.imm16
1788 || t.bitfield.imm32
1789 || t.bitfield.imm32s
1790 || t.bitfield.imm64);
1791
1792 case disp:
1793 return (t.bitfield.disp8
1794 || t.bitfield.disp16
1795 || t.bitfield.disp32
1796 || t.bitfield.disp32s
1797 || t.bitfield.disp64);
1798
1799 case anymem:
1800 return (t.bitfield.disp8
1801 || t.bitfield.disp16
1802 || t.bitfield.disp32
1803 || t.bitfield.disp32s
1804 || t.bitfield.disp64
1805 || t.bitfield.baseindex);
1806
1807 default:
1808 abort ();
1809 }
1810
1811 return 0;
1812 }
1813
1814 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1815 operand J for instruction template T. */
1816
1817 static INLINE int
1818 match_reg_size (const insn_template *t, unsigned int j)
1819 {
1820 return !((i.types[j].bitfield.byte
1821 && !t->operand_types[j].bitfield.byte)
1822 || (i.types[j].bitfield.word
1823 && !t->operand_types[j].bitfield.word)
1824 || (i.types[j].bitfield.dword
1825 && !t->operand_types[j].bitfield.dword)
1826 || (i.types[j].bitfield.qword
1827 && !t->operand_types[j].bitfield.qword));
1828 }
1829
1830 /* Return 1 if there is no conflict in any size on operand J for
1831 instruction template T. */
1832
1833 static INLINE int
1834 match_mem_size (const insn_template *t, unsigned int j)
1835 {
1836 return (match_reg_size (t, j)
1837 && !((i.types[j].bitfield.unspecified
1838 && !i.broadcast
1839 && !t->operand_types[j].bitfield.unspecified)
1840 || (i.types[j].bitfield.fword
1841 && !t->operand_types[j].bitfield.fword)
1842 || (i.types[j].bitfield.tbyte
1843 && !t->operand_types[j].bitfield.tbyte)
1844 || (i.types[j].bitfield.xmmword
1845 && !t->operand_types[j].bitfield.xmmword)
1846 || (i.types[j].bitfield.ymmword
1847 && !t->operand_types[j].bitfield.ymmword)
1848 || (i.types[j].bitfield.zmmword
1849 && !t->operand_types[j].bitfield.zmmword)));
1850 }
1851
1852 /* Return 1 if there is no size conflict on any operands for
1853 instruction template T. */
1854
1855 static INLINE int
1856 operand_size_match (const insn_template *t)
1857 {
1858 unsigned int j;
1859 int match = 1;
1860
1861 /* Don't check jump instructions. */
1862 if (t->opcode_modifier.jump
1863 || t->opcode_modifier.jumpbyte
1864 || t->opcode_modifier.jumpdword
1865 || t->opcode_modifier.jumpintersegment)
1866 return match;
1867
1868 /* Check memory and accumulator operand size. */
1869 for (j = 0; j < i.operands; j++)
1870 {
1871 if (t->operand_types[j].bitfield.anysize)
1872 continue;
1873
1874 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1875 {
1876 match = 0;
1877 break;
1878 }
1879
1880 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1881 {
1882 match = 0;
1883 break;
1884 }
1885 }
1886
1887 if (match)
1888 return match;
1889 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1890 {
1891 mismatch:
1892 i.error = operand_size_mismatch;
1893 return 0;
1894 }
1895
1896 /* Check reverse. */
1897 gas_assert (i.operands == 2);
1898
1899 match = 1;
1900 for (j = 0; j < 2; j++)
1901 {
1902 if (t->operand_types[j].bitfield.acc
1903 && !match_reg_size (t, j ? 0 : 1))
1904 goto mismatch;
1905
1906 if (i.types[j].bitfield.mem
1907 && !match_mem_size (t, j ? 0 : 1))
1908 goto mismatch;
1909 }
1910
1911 return match;
1912 }
1913
1914 static INLINE int
1915 operand_type_match (i386_operand_type overlap,
1916 i386_operand_type given)
1917 {
1918 i386_operand_type temp = overlap;
1919
1920 temp.bitfield.jumpabsolute = 0;
1921 temp.bitfield.unspecified = 0;
1922 temp.bitfield.byte = 0;
1923 temp.bitfield.word = 0;
1924 temp.bitfield.dword = 0;
1925 temp.bitfield.fword = 0;
1926 temp.bitfield.qword = 0;
1927 temp.bitfield.tbyte = 0;
1928 temp.bitfield.xmmword = 0;
1929 temp.bitfield.ymmword = 0;
1930 temp.bitfield.zmmword = 0;
1931 if (operand_type_all_zero (&temp))
1932 goto mismatch;
1933
1934 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1935 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1936 return 1;
1937
1938 mismatch:
1939 i.error = operand_type_mismatch;
1940 return 0;
1941 }
1942
1943 /* If given types g0 and g1 are registers they must be of the same type
1944 unless the expected operand type register overlap is null.
1945 Note that Acc in a template matches every size of reg. */
1946
1947 static INLINE int
1948 operand_type_register_match (i386_operand_type m0,
1949 i386_operand_type g0,
1950 i386_operand_type t0,
1951 i386_operand_type m1,
1952 i386_operand_type g1,
1953 i386_operand_type t1)
1954 {
1955 if (!operand_type_check (g0, reg))
1956 return 1;
1957
1958 if (!operand_type_check (g1, reg))
1959 return 1;
1960
1961 if (g0.bitfield.reg8 == g1.bitfield.reg8
1962 && g0.bitfield.reg16 == g1.bitfield.reg16
1963 && g0.bitfield.reg32 == g1.bitfield.reg32
1964 && g0.bitfield.reg64 == g1.bitfield.reg64)
1965 return 1;
1966
1967 if (m0.bitfield.acc)
1968 {
1969 t0.bitfield.reg8 = 1;
1970 t0.bitfield.reg16 = 1;
1971 t0.bitfield.reg32 = 1;
1972 t0.bitfield.reg64 = 1;
1973 }
1974
1975 if (m1.bitfield.acc)
1976 {
1977 t1.bitfield.reg8 = 1;
1978 t1.bitfield.reg16 = 1;
1979 t1.bitfield.reg32 = 1;
1980 t1.bitfield.reg64 = 1;
1981 }
1982
1983 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1984 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1985 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1986 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1987 return 1;
1988
1989 i.error = register_type_mismatch;
1990
1991 return 0;
1992 }
1993
1994 static INLINE unsigned int
1995 register_number (const reg_entry *r)
1996 {
1997 unsigned int nr = r->reg_num;
1998
1999 if (r->reg_flags & RegRex)
2000 nr += 8;
2001
2002 if (r->reg_flags & RegVRex)
2003 nr += 16;
2004
2005 return nr;
2006 }
2007
2008 static INLINE unsigned int
2009 mode_from_disp_size (i386_operand_type t)
2010 {
2011 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
2012 return 1;
2013 else if (t.bitfield.disp16
2014 || t.bitfield.disp32
2015 || t.bitfield.disp32s)
2016 return 2;
2017 else
2018 return 0;
2019 }
2020
2021 static INLINE int
2022 fits_in_signed_byte (addressT num)
2023 {
2024 return num + 0x80 <= 0xff;
2025 }
2026
2027 static INLINE int
2028 fits_in_unsigned_byte (addressT num)
2029 {
2030 return num <= 0xff;
2031 }
2032
2033 static INLINE int
2034 fits_in_unsigned_word (addressT num)
2035 {
2036 return num <= 0xffff;
2037 }
2038
2039 static INLINE int
2040 fits_in_signed_word (addressT num)
2041 {
2042 return num + 0x8000 <= 0xffff;
2043 }
2044
2045 static INLINE int
2046 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2047 {
2048 #ifndef BFD64
2049 return 1;
2050 #else
2051 return num + 0x80000000 <= 0xffffffff;
2052 #endif
2053 } /* fits_in_signed_long() */
2054
2055 static INLINE int
2056 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2057 {
2058 #ifndef BFD64
2059 return 1;
2060 #else
2061 return num <= 0xffffffff;
2062 #endif
2063 } /* fits_in_unsigned_long() */
2064
2065 static INLINE int
2066 fits_in_vec_disp8 (offsetT num)
2067 {
2068 int shift = i.memshift;
2069 unsigned int mask;
2070
2071 if (shift == -1)
2072 abort ();
2073
2074 mask = (1 << shift) - 1;
2075
2076 /* Return 0 if NUM isn't properly aligned. */
2077 if ((num & mask))
2078 return 0;
2079
2080 /* Check if NUM will fit in 8bit after shift. */
2081 return fits_in_signed_byte (num >> shift);
2082 }
2083
2084 static INLINE int
2085 fits_in_imm4 (offsetT num)
2086 {
2087 return (num & 0xf) == num;
2088 }
2089
2090 static i386_operand_type
2091 smallest_imm_type (offsetT num)
2092 {
2093 i386_operand_type t;
2094
2095 operand_type_set (&t, 0);
2096 t.bitfield.imm64 = 1;
2097
2098 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2099 {
2100 /* This code is disabled on the 486 because all the Imm1 forms
2101 in the opcode table are slower on the i486. They're the
2102 versions with the implicitly specified single-position
2103 displacement, which has another syntax if you really want to
2104 use that form. */
2105 t.bitfield.imm1 = 1;
2106 t.bitfield.imm8 = 1;
2107 t.bitfield.imm8s = 1;
2108 t.bitfield.imm16 = 1;
2109 t.bitfield.imm32 = 1;
2110 t.bitfield.imm32s = 1;
2111 }
2112 else if (fits_in_signed_byte (num))
2113 {
2114 t.bitfield.imm8 = 1;
2115 t.bitfield.imm8s = 1;
2116 t.bitfield.imm16 = 1;
2117 t.bitfield.imm32 = 1;
2118 t.bitfield.imm32s = 1;
2119 }
2120 else if (fits_in_unsigned_byte (num))
2121 {
2122 t.bitfield.imm8 = 1;
2123 t.bitfield.imm16 = 1;
2124 t.bitfield.imm32 = 1;
2125 t.bitfield.imm32s = 1;
2126 }
2127 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2128 {
2129 t.bitfield.imm16 = 1;
2130 t.bitfield.imm32 = 1;
2131 t.bitfield.imm32s = 1;
2132 }
2133 else if (fits_in_signed_long (num))
2134 {
2135 t.bitfield.imm32 = 1;
2136 t.bitfield.imm32s = 1;
2137 }
2138 else if (fits_in_unsigned_long (num))
2139 t.bitfield.imm32 = 1;
2140
2141 return t;
2142 }
2143
2144 static offsetT
2145 offset_in_range (offsetT val, int size)
2146 {
2147 addressT mask;
2148
2149 switch (size)
2150 {
2151 case 1: mask = ((addressT) 1 << 8) - 1; break;
2152 case 2: mask = ((addressT) 1 << 16) - 1; break;
2153 case 4: mask = ((addressT) 2 << 31) - 1; break;
2154 #ifdef BFD64
2155 case 8: mask = ((addressT) 2 << 63) - 1; break;
2156 #endif
2157 default: abort ();
2158 }
2159
2160 #ifdef BFD64
2161 /* If BFD64, sign extend val for 32bit address mode. */
2162 if (flag_code != CODE_64BIT
2163 || i.prefix[ADDR_PREFIX])
2164 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2165 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2166 #endif
2167
2168 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2169 {
2170 char buf1[40], buf2[40];
2171
2172 sprint_value (buf1, val);
2173 sprint_value (buf2, val & mask);
2174 as_warn (_("%s shortened to %s"), buf1, buf2);
2175 }
2176 return val & mask;
2177 }
2178
2179 enum PREFIX_GROUP
2180 {
2181 PREFIX_EXIST = 0,
2182 PREFIX_LOCK,
2183 PREFIX_REP,
2184 PREFIX_DS,
2185 PREFIX_OTHER
2186 };
2187
2188 /* Returns
2189 a. PREFIX_EXIST if attempting to add a prefix where one from the
2190 same class already exists.
2191 b. PREFIX_LOCK if lock prefix is added.
2192 c. PREFIX_REP if rep/repne prefix is added.
2193 d. PREFIX_DS if ds prefix is added.
2194 e. PREFIX_OTHER if other prefix is added.
2195 */
2196
2197 static enum PREFIX_GROUP
2198 add_prefix (unsigned int prefix)
2199 {
2200 enum PREFIX_GROUP ret = PREFIX_OTHER;
2201 unsigned int q;
2202
2203 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2204 && flag_code == CODE_64BIT)
2205 {
2206 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2207 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2208 && (prefix & (REX_R | REX_X | REX_B))))
2209 ret = PREFIX_EXIST;
2210 q = REX_PREFIX;
2211 }
2212 else
2213 {
2214 switch (prefix)
2215 {
2216 default:
2217 abort ();
2218
2219 case DS_PREFIX_OPCODE:
2220 ret = PREFIX_DS;
2221 /* Fall through. */
2222 case CS_PREFIX_OPCODE:
2223 case ES_PREFIX_OPCODE:
2224 case FS_PREFIX_OPCODE:
2225 case GS_PREFIX_OPCODE:
2226 case SS_PREFIX_OPCODE:
2227 q = SEG_PREFIX;
2228 break;
2229
2230 case REPNE_PREFIX_OPCODE:
2231 case REPE_PREFIX_OPCODE:
2232 q = REP_PREFIX;
2233 ret = PREFIX_REP;
2234 break;
2235
2236 case LOCK_PREFIX_OPCODE:
2237 q = LOCK_PREFIX;
2238 ret = PREFIX_LOCK;
2239 break;
2240
2241 case FWAIT_OPCODE:
2242 q = WAIT_PREFIX;
2243 break;
2244
2245 case ADDR_PREFIX_OPCODE:
2246 q = ADDR_PREFIX;
2247 break;
2248
2249 case DATA_PREFIX_OPCODE:
2250 q = DATA_PREFIX;
2251 break;
2252 }
2253 if (i.prefix[q] != 0)
2254 ret = PREFIX_EXIST;
2255 }
2256
2257 if (ret)
2258 {
2259 if (!i.prefix[q])
2260 ++i.prefixes;
2261 i.prefix[q] |= prefix;
2262 }
2263 else
2264 as_bad (_("same type of prefix used twice"));
2265
2266 return ret;
2267 }
2268
2269 static void
2270 update_code_flag (int value, int check)
2271 {
2272 PRINTF_LIKE ((*as_error));
2273
2274 flag_code = (enum flag_code) value;
2275 if (flag_code == CODE_64BIT)
2276 {
2277 cpu_arch_flags.bitfield.cpu64 = 1;
2278 cpu_arch_flags.bitfield.cpuno64 = 0;
2279 }
2280 else
2281 {
2282 cpu_arch_flags.bitfield.cpu64 = 0;
2283 cpu_arch_flags.bitfield.cpuno64 = 1;
2284 }
2285 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2286 {
2287 if (check)
2288 as_error = as_fatal;
2289 else
2290 as_error = as_bad;
2291 (*as_error) (_("64bit mode not supported on `%s'."),
2292 cpu_arch_name ? cpu_arch_name : default_arch);
2293 }
2294 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2295 {
2296 if (check)
2297 as_error = as_fatal;
2298 else
2299 as_error = as_bad;
2300 (*as_error) (_("32bit mode not supported on `%s'."),
2301 cpu_arch_name ? cpu_arch_name : default_arch);
2302 }
2303 stackop_size = '\0';
2304 }
2305
2306 static void
2307 set_code_flag (int value)
2308 {
2309 update_code_flag (value, 0);
2310 }
2311
2312 static void
2313 set_16bit_gcc_code_flag (int new_code_flag)
2314 {
2315 flag_code = (enum flag_code) new_code_flag;
2316 if (flag_code != CODE_16BIT)
2317 abort ();
2318 cpu_arch_flags.bitfield.cpu64 = 0;
2319 cpu_arch_flags.bitfield.cpuno64 = 1;
2320 stackop_size = LONG_MNEM_SUFFIX;
2321 }
2322
2323 static void
2324 set_intel_syntax (int syntax_flag)
2325 {
2326 /* Find out if register prefixing is specified. */
2327 int ask_naked_reg = 0;
2328
2329 SKIP_WHITESPACE ();
2330 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2331 {
2332 char *string;
2333 int e = get_symbol_name (&string);
2334
2335 if (strcmp (string, "prefix") == 0)
2336 ask_naked_reg = 1;
2337 else if (strcmp (string, "noprefix") == 0)
2338 ask_naked_reg = -1;
2339 else
2340 as_bad (_("bad argument to syntax directive."));
2341 (void) restore_line_pointer (e);
2342 }
2343 demand_empty_rest_of_line ();
2344
2345 intel_syntax = syntax_flag;
2346
2347 if (ask_naked_reg == 0)
2348 allow_naked_reg = (intel_syntax
2349 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2350 else
2351 allow_naked_reg = (ask_naked_reg < 0);
2352
2353 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2354
2355 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2356 identifier_chars['$'] = intel_syntax ? '$' : 0;
2357 register_prefix = allow_naked_reg ? "" : "%";
2358 }
2359
2360 static void
2361 set_intel_mnemonic (int mnemonic_flag)
2362 {
2363 intel_mnemonic = mnemonic_flag;
2364 }
2365
2366 static void
2367 set_allow_index_reg (int flag)
2368 {
2369 allow_index_reg = flag;
2370 }
2371
2372 static void
2373 set_check (int what)
2374 {
2375 enum check_kind *kind;
2376 const char *str;
2377
2378 if (what)
2379 {
2380 kind = &operand_check;
2381 str = "operand";
2382 }
2383 else
2384 {
2385 kind = &sse_check;
2386 str = "sse";
2387 }
2388
2389 SKIP_WHITESPACE ();
2390
2391 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2392 {
2393 char *string;
2394 int e = get_symbol_name (&string);
2395
2396 if (strcmp (string, "none") == 0)
2397 *kind = check_none;
2398 else if (strcmp (string, "warning") == 0)
2399 *kind = check_warning;
2400 else if (strcmp (string, "error") == 0)
2401 *kind = check_error;
2402 else
2403 as_bad (_("bad argument to %s_check directive."), str);
2404 (void) restore_line_pointer (e);
2405 }
2406 else
2407 as_bad (_("missing argument for %s_check directive"), str);
2408
2409 demand_empty_rest_of_line ();
2410 }
2411
2412 static void
2413 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2414 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2415 {
2416 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2417 static const char *arch;
2418
2419 /* Intel LIOM is only supported on ELF. */
2420 if (!IS_ELF)
2421 return;
2422
2423 if (!arch)
2424 {
2425 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2426 use default_arch. */
2427 arch = cpu_arch_name;
2428 if (!arch)
2429 arch = default_arch;
2430 }
2431
2432 /* If we are targeting Intel MCU, we must enable it. */
2433 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2434 || new_flag.bitfield.cpuiamcu)
2435 return;
2436
2437 /* If we are targeting Intel L1OM, we must enable it. */
2438 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2439 || new_flag.bitfield.cpul1om)
2440 return;
2441
2442 /* If we are targeting Intel K1OM, we must enable it. */
2443 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2444 || new_flag.bitfield.cpuk1om)
2445 return;
2446
2447 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2448 #endif
2449 }
2450
2451 static void
2452 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2453 {
2454 SKIP_WHITESPACE ();
2455
2456 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2457 {
2458 char *string;
2459 int e = get_symbol_name (&string);
2460 unsigned int j;
2461 i386_cpu_flags flags;
2462
2463 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2464 {
2465 if (strcmp (string, cpu_arch[j].name) == 0)
2466 {
2467 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2468
2469 if (*string != '.')
2470 {
2471 cpu_arch_name = cpu_arch[j].name;
2472 cpu_sub_arch_name = NULL;
2473 cpu_arch_flags = cpu_arch[j].flags;
2474 if (flag_code == CODE_64BIT)
2475 {
2476 cpu_arch_flags.bitfield.cpu64 = 1;
2477 cpu_arch_flags.bitfield.cpuno64 = 0;
2478 }
2479 else
2480 {
2481 cpu_arch_flags.bitfield.cpu64 = 0;
2482 cpu_arch_flags.bitfield.cpuno64 = 1;
2483 }
2484 cpu_arch_isa = cpu_arch[j].type;
2485 cpu_arch_isa_flags = cpu_arch[j].flags;
2486 if (!cpu_arch_tune_set)
2487 {
2488 cpu_arch_tune = cpu_arch_isa;
2489 cpu_arch_tune_flags = cpu_arch_isa_flags;
2490 }
2491 break;
2492 }
2493
2494 flags = cpu_flags_or (cpu_arch_flags,
2495 cpu_arch[j].flags);
2496
2497 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2498 {
2499 if (cpu_sub_arch_name)
2500 {
2501 char *name = cpu_sub_arch_name;
2502 cpu_sub_arch_name = concat (name,
2503 cpu_arch[j].name,
2504 (const char *) NULL);
2505 free (name);
2506 }
2507 else
2508 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2509 cpu_arch_flags = flags;
2510 cpu_arch_isa_flags = flags;
2511 }
2512 (void) restore_line_pointer (e);
2513 demand_empty_rest_of_line ();
2514 return;
2515 }
2516 }
2517
2518 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2519 {
2520 /* Disable an ISA extension. */
2521 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2522 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2523 {
2524 flags = cpu_flags_and_not (cpu_arch_flags,
2525 cpu_noarch[j].flags);
2526 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2527 {
2528 if (cpu_sub_arch_name)
2529 {
2530 char *name = cpu_sub_arch_name;
2531 cpu_sub_arch_name = concat (name, string,
2532 (const char *) NULL);
2533 free (name);
2534 }
2535 else
2536 cpu_sub_arch_name = xstrdup (string);
2537 cpu_arch_flags = flags;
2538 cpu_arch_isa_flags = flags;
2539 }
2540 (void) restore_line_pointer (e);
2541 demand_empty_rest_of_line ();
2542 return;
2543 }
2544
2545 j = ARRAY_SIZE (cpu_arch);
2546 }
2547
2548 if (j >= ARRAY_SIZE (cpu_arch))
2549 as_bad (_("no such architecture: `%s'"), string);
2550
2551 *input_line_pointer = e;
2552 }
2553 else
2554 as_bad (_("missing cpu architecture"));
2555
2556 no_cond_jump_promotion = 0;
2557 if (*input_line_pointer == ','
2558 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2559 {
2560 char *string;
2561 char e;
2562
2563 ++input_line_pointer;
2564 e = get_symbol_name (&string);
2565
2566 if (strcmp (string, "nojumps") == 0)
2567 no_cond_jump_promotion = 1;
2568 else if (strcmp (string, "jumps") == 0)
2569 ;
2570 else
2571 as_bad (_("no such architecture modifier: `%s'"), string);
2572
2573 (void) restore_line_pointer (e);
2574 }
2575
2576 demand_empty_rest_of_line ();
2577 }
2578
2579 enum bfd_architecture
2580 i386_arch (void)
2581 {
2582 if (cpu_arch_isa == PROCESSOR_L1OM)
2583 {
2584 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2585 || flag_code != CODE_64BIT)
2586 as_fatal (_("Intel L1OM is 64bit ELF only"));
2587 return bfd_arch_l1om;
2588 }
2589 else if (cpu_arch_isa == PROCESSOR_K1OM)
2590 {
2591 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2592 || flag_code != CODE_64BIT)
2593 as_fatal (_("Intel K1OM is 64bit ELF only"));
2594 return bfd_arch_k1om;
2595 }
2596 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2597 {
2598 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2599 || flag_code == CODE_64BIT)
2600 as_fatal (_("Intel MCU is 32bit ELF only"));
2601 return bfd_arch_iamcu;
2602 }
2603 else
2604 return bfd_arch_i386;
2605 }
2606
2607 unsigned long
2608 i386_mach (void)
2609 {
2610 if (!strncmp (default_arch, "x86_64", 6))
2611 {
2612 if (cpu_arch_isa == PROCESSOR_L1OM)
2613 {
2614 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2615 || default_arch[6] != '\0')
2616 as_fatal (_("Intel L1OM is 64bit ELF only"));
2617 return bfd_mach_l1om;
2618 }
2619 else if (cpu_arch_isa == PROCESSOR_K1OM)
2620 {
2621 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2622 || default_arch[6] != '\0')
2623 as_fatal (_("Intel K1OM is 64bit ELF only"));
2624 return bfd_mach_k1om;
2625 }
2626 else if (default_arch[6] == '\0')
2627 return bfd_mach_x86_64;
2628 else
2629 return bfd_mach_x64_32;
2630 }
2631 else if (!strcmp (default_arch, "i386")
2632 || !strcmp (default_arch, "iamcu"))
2633 {
2634 if (cpu_arch_isa == PROCESSOR_IAMCU)
2635 {
2636 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2637 as_fatal (_("Intel MCU is 32bit ELF only"));
2638 return bfd_mach_i386_iamcu;
2639 }
2640 else
2641 return bfd_mach_i386_i386;
2642 }
2643 else
2644 as_fatal (_("unknown architecture"));
2645 }
2646 \f
2647 void
2648 md_begin (void)
2649 {
2650 const char *hash_err;
2651
2652 /* Support pseudo prefixes like {disp32}. */
2653 lex_type ['{'] = LEX_BEGIN_NAME;
2654
2655 /* Initialize op_hash hash table. */
2656 op_hash = hash_new ();
2657
2658 {
2659 const insn_template *optab;
2660 templates *core_optab;
2661
2662 /* Setup for loop. */
2663 optab = i386_optab;
2664 core_optab = XNEW (templates);
2665 core_optab->start = optab;
2666
2667 while (1)
2668 {
2669 ++optab;
2670 if (optab->name == NULL
2671 || strcmp (optab->name, (optab - 1)->name) != 0)
2672 {
2673 /* different name --> ship out current template list;
2674 add to hash table; & begin anew. */
2675 core_optab->end = optab;
2676 hash_err = hash_insert (op_hash,
2677 (optab - 1)->name,
2678 (void *) core_optab);
2679 if (hash_err)
2680 {
2681 as_fatal (_("can't hash %s: %s"),
2682 (optab - 1)->name,
2683 hash_err);
2684 }
2685 if (optab->name == NULL)
2686 break;
2687 core_optab = XNEW (templates);
2688 core_optab->start = optab;
2689 }
2690 }
2691 }
2692
2693 /* Initialize reg_hash hash table. */
2694 reg_hash = hash_new ();
2695 {
2696 const reg_entry *regtab;
2697 unsigned int regtab_size = i386_regtab_size;
2698
2699 for (regtab = i386_regtab; regtab_size--; regtab++)
2700 {
2701 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2702 if (hash_err)
2703 as_fatal (_("can't hash %s: %s"),
2704 regtab->reg_name,
2705 hash_err);
2706 }
2707 }
2708
2709 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2710 {
2711 int c;
2712 char *p;
2713
2714 for (c = 0; c < 256; c++)
2715 {
2716 if (ISDIGIT (c))
2717 {
2718 digit_chars[c] = c;
2719 mnemonic_chars[c] = c;
2720 register_chars[c] = c;
2721 operand_chars[c] = c;
2722 }
2723 else if (ISLOWER (c))
2724 {
2725 mnemonic_chars[c] = c;
2726 register_chars[c] = c;
2727 operand_chars[c] = c;
2728 }
2729 else if (ISUPPER (c))
2730 {
2731 mnemonic_chars[c] = TOLOWER (c);
2732 register_chars[c] = mnemonic_chars[c];
2733 operand_chars[c] = c;
2734 }
2735 else if (c == '{' || c == '}')
2736 {
2737 mnemonic_chars[c] = c;
2738 operand_chars[c] = c;
2739 }
2740
2741 if (ISALPHA (c) || ISDIGIT (c))
2742 identifier_chars[c] = c;
2743 else if (c >= 128)
2744 {
2745 identifier_chars[c] = c;
2746 operand_chars[c] = c;
2747 }
2748 }
2749
2750 #ifdef LEX_AT
2751 identifier_chars['@'] = '@';
2752 #endif
2753 #ifdef LEX_QM
2754 identifier_chars['?'] = '?';
2755 operand_chars['?'] = '?';
2756 #endif
2757 digit_chars['-'] = '-';
2758 mnemonic_chars['_'] = '_';
2759 mnemonic_chars['-'] = '-';
2760 mnemonic_chars['.'] = '.';
2761 identifier_chars['_'] = '_';
2762 identifier_chars['.'] = '.';
2763
2764 for (p = operand_special_chars; *p != '\0'; p++)
2765 operand_chars[(unsigned char) *p] = *p;
2766 }
2767
2768 if (flag_code == CODE_64BIT)
2769 {
2770 #if defined (OBJ_COFF) && defined (TE_PE)
2771 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2772 ? 32 : 16);
2773 #else
2774 x86_dwarf2_return_column = 16;
2775 #endif
2776 x86_cie_data_alignment = -8;
2777 }
2778 else
2779 {
2780 x86_dwarf2_return_column = 8;
2781 x86_cie_data_alignment = -4;
2782 }
2783 }
2784
2785 void
2786 i386_print_statistics (FILE *file)
2787 {
2788 hash_print_statistics (file, "i386 opcode", op_hash);
2789 hash_print_statistics (file, "i386 register", reg_hash);
2790 }
2791 \f
2792 #ifdef DEBUG386
2793
2794 /* Debugging routines for md_assemble. */
2795 static void pte (insn_template *);
2796 static void pt (i386_operand_type);
2797 static void pe (expressionS *);
2798 static void ps (symbolS *);
2799
2800 static void
2801 pi (char *line, i386_insn *x)
2802 {
2803 unsigned int j;
2804
2805 fprintf (stdout, "%s: template ", line);
2806 pte (&x->tm);
2807 fprintf (stdout, " address: base %s index %s scale %x\n",
2808 x->base_reg ? x->base_reg->reg_name : "none",
2809 x->index_reg ? x->index_reg->reg_name : "none",
2810 x->log2_scale_factor);
2811 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2812 x->rm.mode, x->rm.reg, x->rm.regmem);
2813 fprintf (stdout, " sib: base %x index %x scale %x\n",
2814 x->sib.base, x->sib.index, x->sib.scale);
2815 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2816 (x->rex & REX_W) != 0,
2817 (x->rex & REX_R) != 0,
2818 (x->rex & REX_X) != 0,
2819 (x->rex & REX_B) != 0);
2820 for (j = 0; j < x->operands; j++)
2821 {
2822 fprintf (stdout, " #%d: ", j + 1);
2823 pt (x->types[j]);
2824 fprintf (stdout, "\n");
2825 if (x->types[j].bitfield.reg8
2826 || x->types[j].bitfield.reg16
2827 || x->types[j].bitfield.reg32
2828 || x->types[j].bitfield.reg64
2829 || x->types[j].bitfield.regmmx
2830 || x->types[j].bitfield.regxmm
2831 || x->types[j].bitfield.regymm
2832 || x->types[j].bitfield.regzmm
2833 || x->types[j].bitfield.sreg2
2834 || x->types[j].bitfield.sreg3
2835 || x->types[j].bitfield.control
2836 || x->types[j].bitfield.debug
2837 || x->types[j].bitfield.test)
2838 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2839 if (operand_type_check (x->types[j], imm))
2840 pe (x->op[j].imms);
2841 if (operand_type_check (x->types[j], disp))
2842 pe (x->op[j].disps);
2843 }
2844 }
2845
2846 static void
2847 pte (insn_template *t)
2848 {
2849 unsigned int j;
2850 fprintf (stdout, " %d operands ", t->operands);
2851 fprintf (stdout, "opcode %x ", t->base_opcode);
2852 if (t->extension_opcode != None)
2853 fprintf (stdout, "ext %x ", t->extension_opcode);
2854 if (t->opcode_modifier.d)
2855 fprintf (stdout, "D");
2856 if (t->opcode_modifier.w)
2857 fprintf (stdout, "W");
2858 fprintf (stdout, "\n");
2859 for (j = 0; j < t->operands; j++)
2860 {
2861 fprintf (stdout, " #%d type ", j + 1);
2862 pt (t->operand_types[j]);
2863 fprintf (stdout, "\n");
2864 }
2865 }
2866
2867 static void
2868 pe (expressionS *e)
2869 {
2870 fprintf (stdout, " operation %d\n", e->X_op);
2871 fprintf (stdout, " add_number %ld (%lx)\n",
2872 (long) e->X_add_number, (long) e->X_add_number);
2873 if (e->X_add_symbol)
2874 {
2875 fprintf (stdout, " add_symbol ");
2876 ps (e->X_add_symbol);
2877 fprintf (stdout, "\n");
2878 }
2879 if (e->X_op_symbol)
2880 {
2881 fprintf (stdout, " op_symbol ");
2882 ps (e->X_op_symbol);
2883 fprintf (stdout, "\n");
2884 }
2885 }
2886
2887 static void
2888 ps (symbolS *s)
2889 {
2890 fprintf (stdout, "%s type %s%s",
2891 S_GET_NAME (s),
2892 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2893 segment_name (S_GET_SEGMENT (s)));
2894 }
2895
2896 static struct type_name
2897 {
2898 i386_operand_type mask;
2899 const char *name;
2900 }
2901 const type_names[] =
2902 {
2903 { OPERAND_TYPE_REG8, "r8" },
2904 { OPERAND_TYPE_REG16, "r16" },
2905 { OPERAND_TYPE_REG32, "r32" },
2906 { OPERAND_TYPE_REG64, "r64" },
2907 { OPERAND_TYPE_IMM8, "i8" },
2908 { OPERAND_TYPE_IMM8, "i8s" },
2909 { OPERAND_TYPE_IMM16, "i16" },
2910 { OPERAND_TYPE_IMM32, "i32" },
2911 { OPERAND_TYPE_IMM32S, "i32s" },
2912 { OPERAND_TYPE_IMM64, "i64" },
2913 { OPERAND_TYPE_IMM1, "i1" },
2914 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2915 { OPERAND_TYPE_DISP8, "d8" },
2916 { OPERAND_TYPE_DISP16, "d16" },
2917 { OPERAND_TYPE_DISP32, "d32" },
2918 { OPERAND_TYPE_DISP32S, "d32s" },
2919 { OPERAND_TYPE_DISP64, "d64" },
2920 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
2921 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2922 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2923 { OPERAND_TYPE_CONTROL, "control reg" },
2924 { OPERAND_TYPE_TEST, "test reg" },
2925 { OPERAND_TYPE_DEBUG, "debug reg" },
2926 { OPERAND_TYPE_FLOATREG, "FReg" },
2927 { OPERAND_TYPE_FLOATACC, "FAcc" },
2928 { OPERAND_TYPE_SREG2, "SReg2" },
2929 { OPERAND_TYPE_SREG3, "SReg3" },
2930 { OPERAND_TYPE_ACC, "Acc" },
2931 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2932 { OPERAND_TYPE_REGMMX, "rMMX" },
2933 { OPERAND_TYPE_REGXMM, "rXMM" },
2934 { OPERAND_TYPE_REGYMM, "rYMM" },
2935 { OPERAND_TYPE_REGZMM, "rZMM" },
2936 { OPERAND_TYPE_REGMASK, "Mask reg" },
2937 { OPERAND_TYPE_ESSEG, "es" },
2938 };
2939
2940 static void
2941 pt (i386_operand_type t)
2942 {
2943 unsigned int j;
2944 i386_operand_type a;
2945
2946 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2947 {
2948 a = operand_type_and (t, type_names[j].mask);
2949 if (!operand_type_all_zero (&a))
2950 fprintf (stdout, "%s, ", type_names[j].name);
2951 }
2952 fflush (stdout);
2953 }
2954
2955 #endif /* DEBUG386 */
2956 \f
2957 static bfd_reloc_code_real_type
2958 reloc (unsigned int size,
2959 int pcrel,
2960 int sign,
2961 bfd_reloc_code_real_type other)
2962 {
2963 if (other != NO_RELOC)
2964 {
2965 reloc_howto_type *rel;
2966
2967 if (size == 8)
2968 switch (other)
2969 {
2970 case BFD_RELOC_X86_64_GOT32:
2971 return BFD_RELOC_X86_64_GOT64;
2972 break;
2973 case BFD_RELOC_X86_64_GOTPLT64:
2974 return BFD_RELOC_X86_64_GOTPLT64;
2975 break;
2976 case BFD_RELOC_X86_64_PLTOFF64:
2977 return BFD_RELOC_X86_64_PLTOFF64;
2978 break;
2979 case BFD_RELOC_X86_64_GOTPC32:
2980 other = BFD_RELOC_X86_64_GOTPC64;
2981 break;
2982 case BFD_RELOC_X86_64_GOTPCREL:
2983 other = BFD_RELOC_X86_64_GOTPCREL64;
2984 break;
2985 case BFD_RELOC_X86_64_TPOFF32:
2986 other = BFD_RELOC_X86_64_TPOFF64;
2987 break;
2988 case BFD_RELOC_X86_64_DTPOFF32:
2989 other = BFD_RELOC_X86_64_DTPOFF64;
2990 break;
2991 default:
2992 break;
2993 }
2994
2995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2996 if (other == BFD_RELOC_SIZE32)
2997 {
2998 if (size == 8)
2999 other = BFD_RELOC_SIZE64;
3000 if (pcrel)
3001 {
3002 as_bad (_("there are no pc-relative size relocations"));
3003 return NO_RELOC;
3004 }
3005 }
3006 #endif
3007
3008 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3009 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3010 sign = -1;
3011
3012 rel = bfd_reloc_type_lookup (stdoutput, other);
3013 if (!rel)
3014 as_bad (_("unknown relocation (%u)"), other);
3015 else if (size != bfd_get_reloc_size (rel))
3016 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3017 bfd_get_reloc_size (rel),
3018 size);
3019 else if (pcrel && !rel->pc_relative)
3020 as_bad (_("non-pc-relative relocation for pc-relative field"));
3021 else if ((rel->complain_on_overflow == complain_overflow_signed
3022 && !sign)
3023 || (rel->complain_on_overflow == complain_overflow_unsigned
3024 && sign > 0))
3025 as_bad (_("relocated field and relocation type differ in signedness"));
3026 else
3027 return other;
3028 return NO_RELOC;
3029 }
3030
3031 if (pcrel)
3032 {
3033 if (!sign)
3034 as_bad (_("there are no unsigned pc-relative relocations"));
3035 switch (size)
3036 {
3037 case 1: return BFD_RELOC_8_PCREL;
3038 case 2: return BFD_RELOC_16_PCREL;
3039 case 4: return BFD_RELOC_32_PCREL;
3040 case 8: return BFD_RELOC_64_PCREL;
3041 }
3042 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3043 }
3044 else
3045 {
3046 if (sign > 0)
3047 switch (size)
3048 {
3049 case 4: return BFD_RELOC_X86_64_32S;
3050 }
3051 else
3052 switch (size)
3053 {
3054 case 1: return BFD_RELOC_8;
3055 case 2: return BFD_RELOC_16;
3056 case 4: return BFD_RELOC_32;
3057 case 8: return BFD_RELOC_64;
3058 }
3059 as_bad (_("cannot do %s %u byte relocation"),
3060 sign > 0 ? "signed" : "unsigned", size);
3061 }
3062
3063 return NO_RELOC;
3064 }
3065
3066 /* Here we decide which fixups can be adjusted to make them relative to
3067 the beginning of the section instead of the symbol. Basically we need
3068 to make sure that the dynamic relocations are done correctly, so in
3069 some cases we force the original symbol to be used. */
3070
3071 int
3072 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3073 {
3074 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3075 if (!IS_ELF)
3076 return 1;
3077
3078 /* Don't adjust pc-relative references to merge sections in 64-bit
3079 mode. */
3080 if (use_rela_relocations
3081 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3082 && fixP->fx_pcrel)
3083 return 0;
3084
3085 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3086 and changed later by validate_fix. */
3087 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3088 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3089 return 0;
3090
3091 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3092 for size relocations. */
3093 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3094 || fixP->fx_r_type == BFD_RELOC_SIZE64
3095 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3096 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3097 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3098 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3099 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3100 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3101 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3102 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3103 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3104 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3105 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3106 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3107 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3108 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3109 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3110 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3111 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3112 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3113 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3114 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3115 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3116 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3117 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3118 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3119 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3120 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3121 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3122 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3123 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3124 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3125 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3126 return 0;
3127 #endif
3128 return 1;
3129 }
3130
3131 static int
3132 intel_float_operand (const char *mnemonic)
3133 {
3134 /* Note that the value returned is meaningful only for opcodes with (memory)
3135 operands, hence the code here is free to improperly handle opcodes that
3136 have no operands (for better performance and smaller code). */
3137
3138 if (mnemonic[0] != 'f')
3139 return 0; /* non-math */
3140
3141 switch (mnemonic[1])
3142 {
3143 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3144 the fs segment override prefix not currently handled because no
3145 call path can make opcodes without operands get here */
3146 case 'i':
3147 return 2 /* integer op */;
3148 case 'l':
3149 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3150 return 3; /* fldcw/fldenv */
3151 break;
3152 case 'n':
3153 if (mnemonic[2] != 'o' /* fnop */)
3154 return 3; /* non-waiting control op */
3155 break;
3156 case 'r':
3157 if (mnemonic[2] == 's')
3158 return 3; /* frstor/frstpm */
3159 break;
3160 case 's':
3161 if (mnemonic[2] == 'a')
3162 return 3; /* fsave */
3163 if (mnemonic[2] == 't')
3164 {
3165 switch (mnemonic[3])
3166 {
3167 case 'c': /* fstcw */
3168 case 'd': /* fstdw */
3169 case 'e': /* fstenv */
3170 case 's': /* fsts[gw] */
3171 return 3;
3172 }
3173 }
3174 break;
3175 case 'x':
3176 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3177 return 0; /* fxsave/fxrstor are not really math ops */
3178 break;
3179 }
3180
3181 return 1;
3182 }
3183
3184 /* Build the VEX prefix. */
3185
3186 static void
3187 build_vex_prefix (const insn_template *t)
3188 {
3189 unsigned int register_specifier;
3190 unsigned int implied_prefix;
3191 unsigned int vector_length;
3192
3193 /* Check register specifier. */
3194 if (i.vex.register_specifier)
3195 {
3196 register_specifier =
3197 ~register_number (i.vex.register_specifier) & 0xf;
3198 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3199 }
3200 else
3201 register_specifier = 0xf;
3202
3203 /* Use 2-byte VEX prefix by swapping destination and source
3204 operand. */
3205 if (i.vec_encoding != vex_encoding_vex3
3206 && i.dir_encoding == dir_encoding_default
3207 && i.operands == i.reg_operands
3208 && i.tm.opcode_modifier.vexopcode == VEX0F
3209 && i.tm.opcode_modifier.load
3210 && i.rex == REX_B)
3211 {
3212 unsigned int xchg = i.operands - 1;
3213 union i386_op temp_op;
3214 i386_operand_type temp_type;
3215
3216 temp_type = i.types[xchg];
3217 i.types[xchg] = i.types[0];
3218 i.types[0] = temp_type;
3219 temp_op = i.op[xchg];
3220 i.op[xchg] = i.op[0];
3221 i.op[0] = temp_op;
3222
3223 gas_assert (i.rm.mode == 3);
3224
3225 i.rex = REX_R;
3226 xchg = i.rm.regmem;
3227 i.rm.regmem = i.rm.reg;
3228 i.rm.reg = xchg;
3229
3230 /* Use the next insn. */
3231 i.tm = t[1];
3232 }
3233
3234 if (i.tm.opcode_modifier.vex == VEXScalar)
3235 vector_length = avxscalar;
3236 else
3237 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3238
3239 switch ((i.tm.base_opcode >> 8) & 0xff)
3240 {
3241 case 0:
3242 implied_prefix = 0;
3243 break;
3244 case DATA_PREFIX_OPCODE:
3245 implied_prefix = 1;
3246 break;
3247 case REPE_PREFIX_OPCODE:
3248 implied_prefix = 2;
3249 break;
3250 case REPNE_PREFIX_OPCODE:
3251 implied_prefix = 3;
3252 break;
3253 default:
3254 abort ();
3255 }
3256
3257 /* Use 2-byte VEX prefix if possible. */
3258 if (i.vec_encoding != vex_encoding_vex3
3259 && i.tm.opcode_modifier.vexopcode == VEX0F
3260 && i.tm.opcode_modifier.vexw != VEXW1
3261 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3262 {
3263 /* 2-byte VEX prefix. */
3264 unsigned int r;
3265
3266 i.vex.length = 2;
3267 i.vex.bytes[0] = 0xc5;
3268
3269 /* Check the REX.R bit. */
3270 r = (i.rex & REX_R) ? 0 : 1;
3271 i.vex.bytes[1] = (r << 7
3272 | register_specifier << 3
3273 | vector_length << 2
3274 | implied_prefix);
3275 }
3276 else
3277 {
3278 /* 3-byte VEX prefix. */
3279 unsigned int m, w;
3280
3281 i.vex.length = 3;
3282
3283 switch (i.tm.opcode_modifier.vexopcode)
3284 {
3285 case VEX0F:
3286 m = 0x1;
3287 i.vex.bytes[0] = 0xc4;
3288 break;
3289 case VEX0F38:
3290 m = 0x2;
3291 i.vex.bytes[0] = 0xc4;
3292 break;
3293 case VEX0F3A:
3294 m = 0x3;
3295 i.vex.bytes[0] = 0xc4;
3296 break;
3297 case XOP08:
3298 m = 0x8;
3299 i.vex.bytes[0] = 0x8f;
3300 break;
3301 case XOP09:
3302 m = 0x9;
3303 i.vex.bytes[0] = 0x8f;
3304 break;
3305 case XOP0A:
3306 m = 0xa;
3307 i.vex.bytes[0] = 0x8f;
3308 break;
3309 default:
3310 abort ();
3311 }
3312
3313 /* The high 3 bits of the second VEX byte are 1's compliment
3314 of RXB bits from REX. */
3315 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3316
3317 /* Check the REX.W bit. */
3318 w = (i.rex & REX_W) ? 1 : 0;
3319 if (i.tm.opcode_modifier.vexw == VEXW1)
3320 w = 1;
3321
3322 i.vex.bytes[2] = (w << 7
3323 | register_specifier << 3
3324 | vector_length << 2
3325 | implied_prefix);
3326 }
3327 }
3328
3329 /* Build the EVEX prefix. */
3330
3331 static void
3332 build_evex_prefix (void)
3333 {
3334 unsigned int register_specifier;
3335 unsigned int implied_prefix;
3336 unsigned int m, w;
3337 rex_byte vrex_used = 0;
3338
3339 /* Check register specifier. */
3340 if (i.vex.register_specifier)
3341 {
3342 gas_assert ((i.vrex & REX_X) == 0);
3343
3344 register_specifier = i.vex.register_specifier->reg_num;
3345 if ((i.vex.register_specifier->reg_flags & RegRex))
3346 register_specifier += 8;
3347 /* The upper 16 registers are encoded in the fourth byte of the
3348 EVEX prefix. */
3349 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3350 i.vex.bytes[3] = 0x8;
3351 register_specifier = ~register_specifier & 0xf;
3352 }
3353 else
3354 {
3355 register_specifier = 0xf;
3356
3357 /* Encode upper 16 vector index register in the fourth byte of
3358 the EVEX prefix. */
3359 if (!(i.vrex & REX_X))
3360 i.vex.bytes[3] = 0x8;
3361 else
3362 vrex_used |= REX_X;
3363 }
3364
3365 switch ((i.tm.base_opcode >> 8) & 0xff)
3366 {
3367 case 0:
3368 implied_prefix = 0;
3369 break;
3370 case DATA_PREFIX_OPCODE:
3371 implied_prefix = 1;
3372 break;
3373 case REPE_PREFIX_OPCODE:
3374 implied_prefix = 2;
3375 break;
3376 case REPNE_PREFIX_OPCODE:
3377 implied_prefix = 3;
3378 break;
3379 default:
3380 abort ();
3381 }
3382
3383 /* 4 byte EVEX prefix. */
3384 i.vex.length = 4;
3385 i.vex.bytes[0] = 0x62;
3386
3387 /* mmmm bits. */
3388 switch (i.tm.opcode_modifier.vexopcode)
3389 {
3390 case VEX0F:
3391 m = 1;
3392 break;
3393 case VEX0F38:
3394 m = 2;
3395 break;
3396 case VEX0F3A:
3397 m = 3;
3398 break;
3399 default:
3400 abort ();
3401 break;
3402 }
3403
3404 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3405 bits from REX. */
3406 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3407
3408 /* The fifth bit of the second EVEX byte is 1's compliment of the
3409 REX_R bit in VREX. */
3410 if (!(i.vrex & REX_R))
3411 i.vex.bytes[1] |= 0x10;
3412 else
3413 vrex_used |= REX_R;
3414
3415 if ((i.reg_operands + i.imm_operands) == i.operands)
3416 {
3417 /* When all operands are registers, the REX_X bit in REX is not
3418 used. We reuse it to encode the upper 16 registers, which is
3419 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3420 as 1's compliment. */
3421 if ((i.vrex & REX_B))
3422 {
3423 vrex_used |= REX_B;
3424 i.vex.bytes[1] &= ~0x40;
3425 }
3426 }
3427
3428 /* EVEX instructions shouldn't need the REX prefix. */
3429 i.vrex &= ~vrex_used;
3430 gas_assert (i.vrex == 0);
3431
3432 /* Check the REX.W bit. */
3433 w = (i.rex & REX_W) ? 1 : 0;
3434 if (i.tm.opcode_modifier.vexw)
3435 {
3436 if (i.tm.opcode_modifier.vexw == VEXW1)
3437 w = 1;
3438 }
3439 /* If w is not set it means we are dealing with WIG instruction. */
3440 else if (!w)
3441 {
3442 if (evexwig == evexw1)
3443 w = 1;
3444 }
3445
3446 /* Encode the U bit. */
3447 implied_prefix |= 0x4;
3448
3449 /* The third byte of the EVEX prefix. */
3450 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3451
3452 /* The fourth byte of the EVEX prefix. */
3453 /* The zeroing-masking bit. */
3454 if (i.mask && i.mask->zeroing)
3455 i.vex.bytes[3] |= 0x80;
3456
3457 /* Don't always set the broadcast bit if there is no RC. */
3458 if (!i.rounding)
3459 {
3460 /* Encode the vector length. */
3461 unsigned int vec_length;
3462
3463 switch (i.tm.opcode_modifier.evex)
3464 {
3465 case EVEXLIG: /* LL' is ignored */
3466 vec_length = evexlig << 5;
3467 break;
3468 case EVEX128:
3469 vec_length = 0 << 5;
3470 break;
3471 case EVEX256:
3472 vec_length = 1 << 5;
3473 break;
3474 case EVEX512:
3475 vec_length = 2 << 5;
3476 break;
3477 default:
3478 abort ();
3479 break;
3480 }
3481 i.vex.bytes[3] |= vec_length;
3482 /* Encode the broadcast bit. */
3483 if (i.broadcast)
3484 i.vex.bytes[3] |= 0x10;
3485 }
3486 else
3487 {
3488 if (i.rounding->type != saeonly)
3489 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3490 else
3491 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3492 }
3493
3494 if (i.mask && i.mask->mask)
3495 i.vex.bytes[3] |= i.mask->mask->reg_num;
3496 }
3497
3498 static void
3499 process_immext (void)
3500 {
3501 expressionS *exp;
3502
3503 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3504 && i.operands > 0)
3505 {
3506 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3507 with an opcode suffix which is coded in the same place as an
3508 8-bit immediate field would be.
3509 Here we check those operands and remove them afterwards. */
3510 unsigned int x;
3511
3512 for (x = 0; x < i.operands; x++)
3513 if (register_number (i.op[x].regs) != x)
3514 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3515 register_prefix, i.op[x].regs->reg_name, x + 1,
3516 i.tm.name);
3517
3518 i.operands = 0;
3519 }
3520
3521 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3522 {
3523 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3524 suffix which is coded in the same place as an 8-bit immediate
3525 field would be.
3526 Here we check those operands and remove them afterwards. */
3527 unsigned int x;
3528
3529 if (i.operands != 3)
3530 abort();
3531
3532 for (x = 0; x < 2; x++)
3533 if (register_number (i.op[x].regs) != x)
3534 goto bad_register_operand;
3535
3536 /* Check for third operand for mwaitx/monitorx insn. */
3537 if (register_number (i.op[x].regs)
3538 != (x + (i.tm.extension_opcode == 0xfb)))
3539 {
3540 bad_register_operand:
3541 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3542 register_prefix, i.op[x].regs->reg_name, x+1,
3543 i.tm.name);
3544 }
3545
3546 i.operands = 0;
3547 }
3548
3549 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3550 which is coded in the same place as an 8-bit immediate field
3551 would be. Here we fake an 8-bit immediate operand from the
3552 opcode suffix stored in tm.extension_opcode.
3553
3554 AVX instructions also use this encoding, for some of
3555 3 argument instructions. */
3556
3557 gas_assert (i.imm_operands <= 1
3558 && (i.operands <= 2
3559 || ((i.tm.opcode_modifier.vex
3560 || i.tm.opcode_modifier.evex)
3561 && i.operands <= 4)));
3562
3563 exp = &im_expressions[i.imm_operands++];
3564 i.op[i.operands].imms = exp;
3565 i.types[i.operands] = imm8;
3566 i.operands++;
3567 exp->X_op = O_constant;
3568 exp->X_add_number = i.tm.extension_opcode;
3569 i.tm.extension_opcode = None;
3570 }
3571
3572
3573 static int
3574 check_hle (void)
3575 {
3576 switch (i.tm.opcode_modifier.hleprefixok)
3577 {
3578 default:
3579 abort ();
3580 case HLEPrefixNone:
3581 as_bad (_("invalid instruction `%s' after `%s'"),
3582 i.tm.name, i.hle_prefix);
3583 return 0;
3584 case HLEPrefixLock:
3585 if (i.prefix[LOCK_PREFIX])
3586 return 1;
3587 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3588 return 0;
3589 case HLEPrefixAny:
3590 return 1;
3591 case HLEPrefixRelease:
3592 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3593 {
3594 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3595 i.tm.name);
3596 return 0;
3597 }
3598 if (i.mem_operands == 0
3599 || !operand_type_check (i.types[i.operands - 1], anymem))
3600 {
3601 as_bad (_("memory destination needed for instruction `%s'"
3602 " after `xrelease'"), i.tm.name);
3603 return 0;
3604 }
3605 return 1;
3606 }
3607 }
3608
3609 /* This is the guts of the machine-dependent assembler. LINE points to a
3610 machine dependent instruction. This function is supposed to emit
3611 the frags/bytes it assembles to. */
3612
3613 void
3614 md_assemble (char *line)
3615 {
3616 unsigned int j;
3617 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3618 const insn_template *t;
3619
3620 /* Initialize globals. */
3621 memset (&i, '\0', sizeof (i));
3622 for (j = 0; j < MAX_OPERANDS; j++)
3623 i.reloc[j] = NO_RELOC;
3624 memset (disp_expressions, '\0', sizeof (disp_expressions));
3625 memset (im_expressions, '\0', sizeof (im_expressions));
3626 save_stack_p = save_stack;
3627
3628 /* First parse an instruction mnemonic & call i386_operand for the operands.
3629 We assume that the scrubber has arranged it so that line[0] is the valid
3630 start of a (possibly prefixed) mnemonic. */
3631
3632 line = parse_insn (line, mnemonic);
3633 if (line == NULL)
3634 return;
3635 mnem_suffix = i.suffix;
3636
3637 line = parse_operands (line, mnemonic);
3638 this_operand = -1;
3639 xfree (i.memop1_string);
3640 i.memop1_string = NULL;
3641 if (line == NULL)
3642 return;
3643
3644 /* Now we've parsed the mnemonic into a set of templates, and have the
3645 operands at hand. */
3646
3647 /* All intel opcodes have reversed operands except for "bound" and
3648 "enter". We also don't reverse intersegment "jmp" and "call"
3649 instructions with 2 immediate operands so that the immediate segment
3650 precedes the offset, as it does when in AT&T mode. */
3651 if (intel_syntax
3652 && i.operands > 1
3653 && (strcmp (mnemonic, "bound") != 0)
3654 && (strcmp (mnemonic, "invlpga") != 0)
3655 && !(operand_type_check (i.types[0], imm)
3656 && operand_type_check (i.types[1], imm)))
3657 swap_operands ();
3658
3659 /* The order of the immediates should be reversed
3660 for 2 immediates extrq and insertq instructions */
3661 if (i.imm_operands == 2
3662 && (strcmp (mnemonic, "extrq") == 0
3663 || strcmp (mnemonic, "insertq") == 0))
3664 swap_2_operands (0, 1);
3665
3666 if (i.imm_operands)
3667 optimize_imm ();
3668
3669 /* Don't optimize displacement for movabs since it only takes 64bit
3670 displacement. */
3671 if (i.disp_operands
3672 && i.disp_encoding != disp_encoding_32bit
3673 && (flag_code != CODE_64BIT
3674 || strcmp (mnemonic, "movabs") != 0))
3675 optimize_disp ();
3676
3677 /* Next, we find a template that matches the given insn,
3678 making sure the overlap of the given operands types is consistent
3679 with the template operand types. */
3680
3681 if (!(t = match_template (mnem_suffix)))
3682 return;
3683
3684 if (sse_check != check_none
3685 && !i.tm.opcode_modifier.noavx
3686 && (i.tm.cpu_flags.bitfield.cpusse
3687 || i.tm.cpu_flags.bitfield.cpusse2
3688 || i.tm.cpu_flags.bitfield.cpusse3
3689 || i.tm.cpu_flags.bitfield.cpussse3
3690 || i.tm.cpu_flags.bitfield.cpusse4_1
3691 || i.tm.cpu_flags.bitfield.cpusse4_2))
3692 {
3693 (sse_check == check_warning
3694 ? as_warn
3695 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3696 }
3697
3698 /* Zap movzx and movsx suffix. The suffix has been set from
3699 "word ptr" or "byte ptr" on the source operand in Intel syntax
3700 or extracted from mnemonic in AT&T syntax. But we'll use
3701 the destination register to choose the suffix for encoding. */
3702 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3703 {
3704 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3705 there is no suffix, the default will be byte extension. */
3706 if (i.reg_operands != 2
3707 && !i.suffix
3708 && intel_syntax)
3709 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3710
3711 i.suffix = 0;
3712 }
3713
3714 if (i.tm.opcode_modifier.fwait)
3715 if (!add_prefix (FWAIT_OPCODE))
3716 return;
3717
3718 /* Check if REP prefix is OK. */
3719 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3720 {
3721 as_bad (_("invalid instruction `%s' after `%s'"),
3722 i.tm.name, i.rep_prefix);
3723 return;
3724 }
3725
3726 /* Check for lock without a lockable instruction. Destination operand
3727 must be memory unless it is xchg (0x86). */
3728 if (i.prefix[LOCK_PREFIX]
3729 && (!i.tm.opcode_modifier.islockable
3730 || i.mem_operands == 0
3731 || (i.tm.base_opcode != 0x86
3732 && !operand_type_check (i.types[i.operands - 1], anymem))))
3733 {
3734 as_bad (_("expecting lockable instruction after `lock'"));
3735 return;
3736 }
3737
3738 /* Check if HLE prefix is OK. */
3739 if (i.hle_prefix && !check_hle ())
3740 return;
3741
3742 /* Check BND prefix. */
3743 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3744 as_bad (_("expecting valid branch instruction after `bnd'"));
3745
3746 /* Check NOTRACK prefix. */
3747 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3748 as_bad (_("expecting indirect branch instruction after `notrack'"));
3749
3750 if (i.tm.cpu_flags.bitfield.cpumpx)
3751 {
3752 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3753 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3754 else if (flag_code != CODE_16BIT
3755 ? i.prefix[ADDR_PREFIX]
3756 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3757 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3758 }
3759
3760 /* Insert BND prefix. */
3761 if (add_bnd_prefix
3762 && i.tm.opcode_modifier.bndprefixok
3763 && !i.prefix[BND_PREFIX])
3764 add_prefix (BND_PREFIX_OPCODE);
3765
3766 /* Check string instruction segment overrides. */
3767 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3768 {
3769 if (!check_string ())
3770 return;
3771 i.disp_operands = 0;
3772 }
3773
3774 if (!process_suffix ())
3775 return;
3776
3777 /* Update operand types. */
3778 for (j = 0; j < i.operands; j++)
3779 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3780
3781 /* Make still unresolved immediate matches conform to size of immediate
3782 given in i.suffix. */
3783 if (!finalize_imm ())
3784 return;
3785
3786 if (i.types[0].bitfield.imm1)
3787 i.imm_operands = 0; /* kludge for shift insns. */
3788
3789 /* We only need to check those implicit registers for instructions
3790 with 3 operands or less. */
3791 if (i.operands <= 3)
3792 for (j = 0; j < i.operands; j++)
3793 if (i.types[j].bitfield.inoutportreg
3794 || i.types[j].bitfield.shiftcount
3795 || i.types[j].bitfield.acc
3796 || i.types[j].bitfield.floatacc)
3797 i.reg_operands--;
3798
3799 /* ImmExt should be processed after SSE2AVX. */
3800 if (!i.tm.opcode_modifier.sse2avx
3801 && i.tm.opcode_modifier.immext)
3802 process_immext ();
3803
3804 /* For insns with operands there are more diddles to do to the opcode. */
3805 if (i.operands)
3806 {
3807 if (!process_operands ())
3808 return;
3809 }
3810 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3811 {
3812 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3813 as_warn (_("translating to `%sp'"), i.tm.name);
3814 }
3815
3816 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3817 {
3818 if (flag_code == CODE_16BIT)
3819 {
3820 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3821 i.tm.name);
3822 return;
3823 }
3824
3825 if (i.tm.opcode_modifier.vex)
3826 build_vex_prefix (t);
3827 else
3828 build_evex_prefix ();
3829 }
3830
3831 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3832 instructions may define INT_OPCODE as well, so avoid this corner
3833 case for those instructions that use MODRM. */
3834 if (i.tm.base_opcode == INT_OPCODE
3835 && !i.tm.opcode_modifier.modrm
3836 && i.op[0].imms->X_add_number == 3)
3837 {
3838 i.tm.base_opcode = INT3_OPCODE;
3839 i.imm_operands = 0;
3840 }
3841
3842 if ((i.tm.opcode_modifier.jump
3843 || i.tm.opcode_modifier.jumpbyte
3844 || i.tm.opcode_modifier.jumpdword)
3845 && i.op[0].disps->X_op == O_constant)
3846 {
3847 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3848 the absolute address given by the constant. Since ix86 jumps and
3849 calls are pc relative, we need to generate a reloc. */
3850 i.op[0].disps->X_add_symbol = &abs_symbol;
3851 i.op[0].disps->X_op = O_symbol;
3852 }
3853
3854 if (i.tm.opcode_modifier.rex64)
3855 i.rex |= REX_W;
3856
3857 /* For 8 bit registers we need an empty rex prefix. Also if the
3858 instruction already has a prefix, we need to convert old
3859 registers to new ones. */
3860
3861 if ((i.types[0].bitfield.reg8
3862 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3863 || (i.types[1].bitfield.reg8
3864 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3865 || ((i.types[0].bitfield.reg8
3866 || i.types[1].bitfield.reg8)
3867 && i.rex != 0))
3868 {
3869 int x;
3870
3871 i.rex |= REX_OPCODE;
3872 for (x = 0; x < 2; x++)
3873 {
3874 /* Look for 8 bit operand that uses old registers. */
3875 if (i.types[x].bitfield.reg8
3876 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3877 {
3878 /* In case it is "hi" register, give up. */
3879 if (i.op[x].regs->reg_num > 3)
3880 as_bad (_("can't encode register '%s%s' in an "
3881 "instruction requiring REX prefix."),
3882 register_prefix, i.op[x].regs->reg_name);
3883
3884 /* Otherwise it is equivalent to the extended register.
3885 Since the encoding doesn't change this is merely
3886 cosmetic cleanup for debug output. */
3887
3888 i.op[x].regs = i.op[x].regs + 8;
3889 }
3890 }
3891 }
3892
3893 if (i.rex != 0)
3894 add_prefix (REX_OPCODE | i.rex);
3895
3896 /* We are ready to output the insn. */
3897 output_insn ();
3898 }
3899
3900 static char *
3901 parse_insn (char *line, char *mnemonic)
3902 {
3903 char *l = line;
3904 char *token_start = l;
3905 char *mnem_p;
3906 int supported;
3907 const insn_template *t;
3908 char *dot_p = NULL;
3909
3910 while (1)
3911 {
3912 mnem_p = mnemonic;
3913 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3914 {
3915 if (*mnem_p == '.')
3916 dot_p = mnem_p;
3917 mnem_p++;
3918 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3919 {
3920 as_bad (_("no such instruction: `%s'"), token_start);
3921 return NULL;
3922 }
3923 l++;
3924 }
3925 if (!is_space_char (*l)
3926 && *l != END_OF_INSN
3927 && (intel_syntax
3928 || (*l != PREFIX_SEPARATOR
3929 && *l != ',')))
3930 {
3931 as_bad (_("invalid character %s in mnemonic"),
3932 output_invalid (*l));
3933 return NULL;
3934 }
3935 if (token_start == l)
3936 {
3937 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3938 as_bad (_("expecting prefix; got nothing"));
3939 else
3940 as_bad (_("expecting mnemonic; got nothing"));
3941 return NULL;
3942 }
3943
3944 /* Look up instruction (or prefix) via hash table. */
3945 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3946
3947 if (*l != END_OF_INSN
3948 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3949 && current_templates
3950 && current_templates->start->opcode_modifier.isprefix)
3951 {
3952 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3953 {
3954 as_bad ((flag_code != CODE_64BIT
3955 ? _("`%s' is only supported in 64-bit mode")
3956 : _("`%s' is not supported in 64-bit mode")),
3957 current_templates->start->name);
3958 return NULL;
3959 }
3960 /* If we are in 16-bit mode, do not allow addr16 or data16.
3961 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3962 if ((current_templates->start->opcode_modifier.size16
3963 || current_templates->start->opcode_modifier.size32)
3964 && flag_code != CODE_64BIT
3965 && (current_templates->start->opcode_modifier.size32
3966 ^ (flag_code == CODE_16BIT)))
3967 {
3968 as_bad (_("redundant %s prefix"),
3969 current_templates->start->name);
3970 return NULL;
3971 }
3972 if (current_templates->start->opcode_length == 0)
3973 {
3974 /* Handle pseudo prefixes. */
3975 switch (current_templates->start->base_opcode)
3976 {
3977 case 0x0:
3978 /* {disp8} */
3979 i.disp_encoding = disp_encoding_8bit;
3980 break;
3981 case 0x1:
3982 /* {disp32} */
3983 i.disp_encoding = disp_encoding_32bit;
3984 break;
3985 case 0x2:
3986 /* {load} */
3987 i.dir_encoding = dir_encoding_load;
3988 break;
3989 case 0x3:
3990 /* {store} */
3991 i.dir_encoding = dir_encoding_store;
3992 break;
3993 case 0x4:
3994 /* {vex2} */
3995 i.vec_encoding = vex_encoding_vex2;
3996 break;
3997 case 0x5:
3998 /* {vex3} */
3999 i.vec_encoding = vex_encoding_vex3;
4000 break;
4001 case 0x6:
4002 /* {evex} */
4003 i.vec_encoding = vex_encoding_evex;
4004 break;
4005 default:
4006 abort ();
4007 }
4008 }
4009 else
4010 {
4011 /* Add prefix, checking for repeated prefixes. */
4012 switch (add_prefix (current_templates->start->base_opcode))
4013 {
4014 case PREFIX_EXIST:
4015 return NULL;
4016 case PREFIX_DS:
4017 if (current_templates->start->cpu_flags.bitfield.cpucet)
4018 i.notrack_prefix = current_templates->start->name;
4019 break;
4020 case PREFIX_REP:
4021 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4022 i.hle_prefix = current_templates->start->name;
4023 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4024 i.bnd_prefix = current_templates->start->name;
4025 else
4026 i.rep_prefix = current_templates->start->name;
4027 break;
4028 default:
4029 break;
4030 }
4031 }
4032 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4033 token_start = ++l;
4034 }
4035 else
4036 break;
4037 }
4038
4039 if (!current_templates)
4040 {
4041 /* Check if we should swap operand or force 32bit displacement in
4042 encoding. */
4043 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4044 i.dir_encoding = dir_encoding_store;
4045 else if (mnem_p - 3 == dot_p
4046 && dot_p[1] == 'd'
4047 && dot_p[2] == '8')
4048 i.disp_encoding = disp_encoding_8bit;
4049 else if (mnem_p - 4 == dot_p
4050 && dot_p[1] == 'd'
4051 && dot_p[2] == '3'
4052 && dot_p[3] == '2')
4053 i.disp_encoding = disp_encoding_32bit;
4054 else
4055 goto check_suffix;
4056 mnem_p = dot_p;
4057 *dot_p = '\0';
4058 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4059 }
4060
4061 if (!current_templates)
4062 {
4063 check_suffix:
4064 /* See if we can get a match by trimming off a suffix. */
4065 switch (mnem_p[-1])
4066 {
4067 case WORD_MNEM_SUFFIX:
4068 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4069 i.suffix = SHORT_MNEM_SUFFIX;
4070 else
4071 /* Fall through. */
4072 case BYTE_MNEM_SUFFIX:
4073 case QWORD_MNEM_SUFFIX:
4074 i.suffix = mnem_p[-1];
4075 mnem_p[-1] = '\0';
4076 current_templates = (const templates *) hash_find (op_hash,
4077 mnemonic);
4078 break;
4079 case SHORT_MNEM_SUFFIX:
4080 case LONG_MNEM_SUFFIX:
4081 if (!intel_syntax)
4082 {
4083 i.suffix = mnem_p[-1];
4084 mnem_p[-1] = '\0';
4085 current_templates = (const templates *) hash_find (op_hash,
4086 mnemonic);
4087 }
4088 break;
4089
4090 /* Intel Syntax. */
4091 case 'd':
4092 if (intel_syntax)
4093 {
4094 if (intel_float_operand (mnemonic) == 1)
4095 i.suffix = SHORT_MNEM_SUFFIX;
4096 else
4097 i.suffix = LONG_MNEM_SUFFIX;
4098 mnem_p[-1] = '\0';
4099 current_templates = (const templates *) hash_find (op_hash,
4100 mnemonic);
4101 }
4102 break;
4103 }
4104 if (!current_templates)
4105 {
4106 as_bad (_("no such instruction: `%s'"), token_start);
4107 return NULL;
4108 }
4109 }
4110
4111 if (current_templates->start->opcode_modifier.jump
4112 || current_templates->start->opcode_modifier.jumpbyte)
4113 {
4114 /* Check for a branch hint. We allow ",pt" and ",pn" for
4115 predict taken and predict not taken respectively.
4116 I'm not sure that branch hints actually do anything on loop
4117 and jcxz insns (JumpByte) for current Pentium4 chips. They
4118 may work in the future and it doesn't hurt to accept them
4119 now. */
4120 if (l[0] == ',' && l[1] == 'p')
4121 {
4122 if (l[2] == 't')
4123 {
4124 if (!add_prefix (DS_PREFIX_OPCODE))
4125 return NULL;
4126 l += 3;
4127 }
4128 else if (l[2] == 'n')
4129 {
4130 if (!add_prefix (CS_PREFIX_OPCODE))
4131 return NULL;
4132 l += 3;
4133 }
4134 }
4135 }
4136 /* Any other comma loses. */
4137 if (*l == ',')
4138 {
4139 as_bad (_("invalid character %s in mnemonic"),
4140 output_invalid (*l));
4141 return NULL;
4142 }
4143
4144 /* Check if instruction is supported on specified architecture. */
4145 supported = 0;
4146 for (t = current_templates->start; t < current_templates->end; ++t)
4147 {
4148 supported |= cpu_flags_match (t);
4149 if (supported == CPU_FLAGS_PERFECT_MATCH)
4150 goto skip;
4151 }
4152
4153 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4154 {
4155 as_bad (flag_code == CODE_64BIT
4156 ? _("`%s' is not supported in 64-bit mode")
4157 : _("`%s' is only supported in 64-bit mode"),
4158 current_templates->start->name);
4159 return NULL;
4160 }
4161 if (supported != CPU_FLAGS_PERFECT_MATCH)
4162 {
4163 as_bad (_("`%s' is not supported on `%s%s'"),
4164 current_templates->start->name,
4165 cpu_arch_name ? cpu_arch_name : default_arch,
4166 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4167 return NULL;
4168 }
4169
4170 skip:
4171 if (!cpu_arch_flags.bitfield.cpui386
4172 && (flag_code != CODE_16BIT))
4173 {
4174 as_warn (_("use .code16 to ensure correct addressing mode"));
4175 }
4176
4177 return l;
4178 }
4179
4180 static char *
4181 parse_operands (char *l, const char *mnemonic)
4182 {
4183 char *token_start;
4184
4185 /* 1 if operand is pending after ','. */
4186 unsigned int expecting_operand = 0;
4187
4188 /* Non-zero if operand parens not balanced. */
4189 unsigned int paren_not_balanced;
4190
4191 while (*l != END_OF_INSN)
4192 {
4193 /* Skip optional white space before operand. */
4194 if (is_space_char (*l))
4195 ++l;
4196 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4197 {
4198 as_bad (_("invalid character %s before operand %d"),
4199 output_invalid (*l),
4200 i.operands + 1);
4201 return NULL;
4202 }
4203 token_start = l; /* After white space. */
4204 paren_not_balanced = 0;
4205 while (paren_not_balanced || *l != ',')
4206 {
4207 if (*l == END_OF_INSN)
4208 {
4209 if (paren_not_balanced)
4210 {
4211 if (!intel_syntax)
4212 as_bad (_("unbalanced parenthesis in operand %d."),
4213 i.operands + 1);
4214 else
4215 as_bad (_("unbalanced brackets in operand %d."),
4216 i.operands + 1);
4217 return NULL;
4218 }
4219 else
4220 break; /* we are done */
4221 }
4222 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4223 {
4224 as_bad (_("invalid character %s in operand %d"),
4225 output_invalid (*l),
4226 i.operands + 1);
4227 return NULL;
4228 }
4229 if (!intel_syntax)
4230 {
4231 if (*l == '(')
4232 ++paren_not_balanced;
4233 if (*l == ')')
4234 --paren_not_balanced;
4235 }
4236 else
4237 {
4238 if (*l == '[')
4239 ++paren_not_balanced;
4240 if (*l == ']')
4241 --paren_not_balanced;
4242 }
4243 l++;
4244 }
4245 if (l != token_start)
4246 { /* Yes, we've read in another operand. */
4247 unsigned int operand_ok;
4248 this_operand = i.operands++;
4249 if (i.operands > MAX_OPERANDS)
4250 {
4251 as_bad (_("spurious operands; (%d operands/instruction max)"),
4252 MAX_OPERANDS);
4253 return NULL;
4254 }
4255 i.types[this_operand].bitfield.unspecified = 1;
4256 /* Now parse operand adding info to 'i' as we go along. */
4257 END_STRING_AND_SAVE (l);
4258
4259 if (intel_syntax)
4260 operand_ok =
4261 i386_intel_operand (token_start,
4262 intel_float_operand (mnemonic));
4263 else
4264 operand_ok = i386_att_operand (token_start);
4265
4266 RESTORE_END_STRING (l);
4267 if (!operand_ok)
4268 return NULL;
4269 }
4270 else
4271 {
4272 if (expecting_operand)
4273 {
4274 expecting_operand_after_comma:
4275 as_bad (_("expecting operand after ','; got nothing"));
4276 return NULL;
4277 }
4278 if (*l == ',')
4279 {
4280 as_bad (_("expecting operand before ','; got nothing"));
4281 return NULL;
4282 }
4283 }
4284
4285 /* Now *l must be either ',' or END_OF_INSN. */
4286 if (*l == ',')
4287 {
4288 if (*++l == END_OF_INSN)
4289 {
4290 /* Just skip it, if it's \n complain. */
4291 goto expecting_operand_after_comma;
4292 }
4293 expecting_operand = 1;
4294 }
4295 }
4296 return l;
4297 }
4298
4299 static void
4300 swap_2_operands (int xchg1, int xchg2)
4301 {
4302 union i386_op temp_op;
4303 i386_operand_type temp_type;
4304 enum bfd_reloc_code_real temp_reloc;
4305
4306 temp_type = i.types[xchg2];
4307 i.types[xchg2] = i.types[xchg1];
4308 i.types[xchg1] = temp_type;
4309 temp_op = i.op[xchg2];
4310 i.op[xchg2] = i.op[xchg1];
4311 i.op[xchg1] = temp_op;
4312 temp_reloc = i.reloc[xchg2];
4313 i.reloc[xchg2] = i.reloc[xchg1];
4314 i.reloc[xchg1] = temp_reloc;
4315
4316 if (i.mask)
4317 {
4318 if (i.mask->operand == xchg1)
4319 i.mask->operand = xchg2;
4320 else if (i.mask->operand == xchg2)
4321 i.mask->operand = xchg1;
4322 }
4323 if (i.broadcast)
4324 {
4325 if (i.broadcast->operand == xchg1)
4326 i.broadcast->operand = xchg2;
4327 else if (i.broadcast->operand == xchg2)
4328 i.broadcast->operand = xchg1;
4329 }
4330 if (i.rounding)
4331 {
4332 if (i.rounding->operand == xchg1)
4333 i.rounding->operand = xchg2;
4334 else if (i.rounding->operand == xchg2)
4335 i.rounding->operand = xchg1;
4336 }
4337 }
4338
4339 static void
4340 swap_operands (void)
4341 {
4342 switch (i.operands)
4343 {
4344 case 5:
4345 case 4:
4346 swap_2_operands (1, i.operands - 2);
4347 /* Fall through. */
4348 case 3:
4349 case 2:
4350 swap_2_operands (0, i.operands - 1);
4351 break;
4352 default:
4353 abort ();
4354 }
4355
4356 if (i.mem_operands == 2)
4357 {
4358 const seg_entry *temp_seg;
4359 temp_seg = i.seg[0];
4360 i.seg[0] = i.seg[1];
4361 i.seg[1] = temp_seg;
4362 }
4363 }
4364
4365 /* Try to ensure constant immediates are represented in the smallest
4366 opcode possible. */
4367 static void
4368 optimize_imm (void)
4369 {
4370 char guess_suffix = 0;
4371 int op;
4372
4373 if (i.suffix)
4374 guess_suffix = i.suffix;
4375 else if (i.reg_operands)
4376 {
4377 /* Figure out a suffix from the last register operand specified.
4378 We can't do this properly yet, ie. excluding InOutPortReg,
4379 but the following works for instructions with immediates.
4380 In any case, we can't set i.suffix yet. */
4381 for (op = i.operands; --op >= 0;)
4382 if (i.types[op].bitfield.reg8)
4383 {
4384 guess_suffix = BYTE_MNEM_SUFFIX;
4385 break;
4386 }
4387 else if (i.types[op].bitfield.reg16)
4388 {
4389 guess_suffix = WORD_MNEM_SUFFIX;
4390 break;
4391 }
4392 else if (i.types[op].bitfield.reg32)
4393 {
4394 guess_suffix = LONG_MNEM_SUFFIX;
4395 break;
4396 }
4397 else if (i.types[op].bitfield.reg64)
4398 {
4399 guess_suffix = QWORD_MNEM_SUFFIX;
4400 break;
4401 }
4402 }
4403 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4404 guess_suffix = WORD_MNEM_SUFFIX;
4405
4406 for (op = i.operands; --op >= 0;)
4407 if (operand_type_check (i.types[op], imm))
4408 {
4409 switch (i.op[op].imms->X_op)
4410 {
4411 case O_constant:
4412 /* If a suffix is given, this operand may be shortened. */
4413 switch (guess_suffix)
4414 {
4415 case LONG_MNEM_SUFFIX:
4416 i.types[op].bitfield.imm32 = 1;
4417 i.types[op].bitfield.imm64 = 1;
4418 break;
4419 case WORD_MNEM_SUFFIX:
4420 i.types[op].bitfield.imm16 = 1;
4421 i.types[op].bitfield.imm32 = 1;
4422 i.types[op].bitfield.imm32s = 1;
4423 i.types[op].bitfield.imm64 = 1;
4424 break;
4425 case BYTE_MNEM_SUFFIX:
4426 i.types[op].bitfield.imm8 = 1;
4427 i.types[op].bitfield.imm8s = 1;
4428 i.types[op].bitfield.imm16 = 1;
4429 i.types[op].bitfield.imm32 = 1;
4430 i.types[op].bitfield.imm32s = 1;
4431 i.types[op].bitfield.imm64 = 1;
4432 break;
4433 }
4434
4435 /* If this operand is at most 16 bits, convert it
4436 to a signed 16 bit number before trying to see
4437 whether it will fit in an even smaller size.
4438 This allows a 16-bit operand such as $0xffe0 to
4439 be recognised as within Imm8S range. */
4440 if ((i.types[op].bitfield.imm16)
4441 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4442 {
4443 i.op[op].imms->X_add_number =
4444 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4445 }
4446 #ifdef BFD64
4447 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4448 if ((i.types[op].bitfield.imm32)
4449 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4450 == 0))
4451 {
4452 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4453 ^ ((offsetT) 1 << 31))
4454 - ((offsetT) 1 << 31));
4455 }
4456 #endif
4457 i.types[op]
4458 = operand_type_or (i.types[op],
4459 smallest_imm_type (i.op[op].imms->X_add_number));
4460
4461 /* We must avoid matching of Imm32 templates when 64bit
4462 only immediate is available. */
4463 if (guess_suffix == QWORD_MNEM_SUFFIX)
4464 i.types[op].bitfield.imm32 = 0;
4465 break;
4466
4467 case O_absent:
4468 case O_register:
4469 abort ();
4470
4471 /* Symbols and expressions. */
4472 default:
4473 /* Convert symbolic operand to proper sizes for matching, but don't
4474 prevent matching a set of insns that only supports sizes other
4475 than those matching the insn suffix. */
4476 {
4477 i386_operand_type mask, allowed;
4478 const insn_template *t;
4479
4480 operand_type_set (&mask, 0);
4481 operand_type_set (&allowed, 0);
4482
4483 for (t = current_templates->start;
4484 t < current_templates->end;
4485 ++t)
4486 allowed = operand_type_or (allowed,
4487 t->operand_types[op]);
4488 switch (guess_suffix)
4489 {
4490 case QWORD_MNEM_SUFFIX:
4491 mask.bitfield.imm64 = 1;
4492 mask.bitfield.imm32s = 1;
4493 break;
4494 case LONG_MNEM_SUFFIX:
4495 mask.bitfield.imm32 = 1;
4496 break;
4497 case WORD_MNEM_SUFFIX:
4498 mask.bitfield.imm16 = 1;
4499 break;
4500 case BYTE_MNEM_SUFFIX:
4501 mask.bitfield.imm8 = 1;
4502 break;
4503 default:
4504 break;
4505 }
4506 allowed = operand_type_and (mask, allowed);
4507 if (!operand_type_all_zero (&allowed))
4508 i.types[op] = operand_type_and (i.types[op], mask);
4509 }
4510 break;
4511 }
4512 }
4513 }
4514
4515 /* Try to use the smallest displacement type too. */
4516 static void
4517 optimize_disp (void)
4518 {
4519 int op;
4520
4521 for (op = i.operands; --op >= 0;)
4522 if (operand_type_check (i.types[op], disp))
4523 {
4524 if (i.op[op].disps->X_op == O_constant)
4525 {
4526 offsetT op_disp = i.op[op].disps->X_add_number;
4527
4528 if (i.types[op].bitfield.disp16
4529 && (op_disp & ~(offsetT) 0xffff) == 0)
4530 {
4531 /* If this operand is at most 16 bits, convert
4532 to a signed 16 bit number and don't use 64bit
4533 displacement. */
4534 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4535 i.types[op].bitfield.disp64 = 0;
4536 }
4537 #ifdef BFD64
4538 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4539 if (i.types[op].bitfield.disp32
4540 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4541 {
4542 /* If this operand is at most 32 bits, convert
4543 to a signed 32 bit number and don't use 64bit
4544 displacement. */
4545 op_disp &= (((offsetT) 2 << 31) - 1);
4546 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4547 i.types[op].bitfield.disp64 = 0;
4548 }
4549 #endif
4550 if (!op_disp && i.types[op].bitfield.baseindex)
4551 {
4552 i.types[op].bitfield.disp8 = 0;
4553 i.types[op].bitfield.disp16 = 0;
4554 i.types[op].bitfield.disp32 = 0;
4555 i.types[op].bitfield.disp32s = 0;
4556 i.types[op].bitfield.disp64 = 0;
4557 i.op[op].disps = 0;
4558 i.disp_operands--;
4559 }
4560 else if (flag_code == CODE_64BIT)
4561 {
4562 if (fits_in_signed_long (op_disp))
4563 {
4564 i.types[op].bitfield.disp64 = 0;
4565 i.types[op].bitfield.disp32s = 1;
4566 }
4567 if (i.prefix[ADDR_PREFIX]
4568 && fits_in_unsigned_long (op_disp))
4569 i.types[op].bitfield.disp32 = 1;
4570 }
4571 if ((i.types[op].bitfield.disp32
4572 || i.types[op].bitfield.disp32s
4573 || i.types[op].bitfield.disp16)
4574 && fits_in_signed_byte (op_disp))
4575 i.types[op].bitfield.disp8 = 1;
4576 }
4577 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4578 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4579 {
4580 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4581 i.op[op].disps, 0, i.reloc[op]);
4582 i.types[op].bitfield.disp8 = 0;
4583 i.types[op].bitfield.disp16 = 0;
4584 i.types[op].bitfield.disp32 = 0;
4585 i.types[op].bitfield.disp32s = 0;
4586 i.types[op].bitfield.disp64 = 0;
4587 }
4588 else
4589 /* We only support 64bit displacement on constants. */
4590 i.types[op].bitfield.disp64 = 0;
4591 }
4592 }
4593
4594 /* Check if operands are valid for the instruction. */
4595
4596 static int
4597 check_VecOperands (const insn_template *t)
4598 {
4599 unsigned int op;
4600
4601 /* Without VSIB byte, we can't have a vector register for index. */
4602 if (!t->opcode_modifier.vecsib
4603 && i.index_reg
4604 && (i.index_reg->reg_type.bitfield.regxmm
4605 || i.index_reg->reg_type.bitfield.regymm
4606 || i.index_reg->reg_type.bitfield.regzmm))
4607 {
4608 i.error = unsupported_vector_index_register;
4609 return 1;
4610 }
4611
4612 /* Check if default mask is allowed. */
4613 if (t->opcode_modifier.nodefmask
4614 && (!i.mask || i.mask->mask->reg_num == 0))
4615 {
4616 i.error = no_default_mask;
4617 return 1;
4618 }
4619
4620 /* For VSIB byte, we need a vector register for index, and all vector
4621 registers must be distinct. */
4622 if (t->opcode_modifier.vecsib)
4623 {
4624 if (!i.index_reg
4625 || !((t->opcode_modifier.vecsib == VecSIB128
4626 && i.index_reg->reg_type.bitfield.regxmm)
4627 || (t->opcode_modifier.vecsib == VecSIB256
4628 && i.index_reg->reg_type.bitfield.regymm)
4629 || (t->opcode_modifier.vecsib == VecSIB512
4630 && i.index_reg->reg_type.bitfield.regzmm)))
4631 {
4632 i.error = invalid_vsib_address;
4633 return 1;
4634 }
4635
4636 gas_assert (i.reg_operands == 2 || i.mask);
4637 if (i.reg_operands == 2 && !i.mask)
4638 {
4639 gas_assert (i.types[0].bitfield.regxmm
4640 || i.types[0].bitfield.regymm);
4641 gas_assert (i.types[2].bitfield.regxmm
4642 || i.types[2].bitfield.regymm);
4643 if (operand_check == check_none)
4644 return 0;
4645 if (register_number (i.op[0].regs)
4646 != register_number (i.index_reg)
4647 && register_number (i.op[2].regs)
4648 != register_number (i.index_reg)
4649 && register_number (i.op[0].regs)
4650 != register_number (i.op[2].regs))
4651 return 0;
4652 if (operand_check == check_error)
4653 {
4654 i.error = invalid_vector_register_set;
4655 return 1;
4656 }
4657 as_warn (_("mask, index, and destination registers should be distinct"));
4658 }
4659 else if (i.reg_operands == 1 && i.mask)
4660 {
4661 if ((i.types[1].bitfield.regxmm
4662 || i.types[1].bitfield.regymm
4663 || i.types[1].bitfield.regzmm)
4664 && (register_number (i.op[1].regs)
4665 == register_number (i.index_reg)))
4666 {
4667 if (operand_check == check_error)
4668 {
4669 i.error = invalid_vector_register_set;
4670 return 1;
4671 }
4672 if (operand_check != check_none)
4673 as_warn (_("index and destination registers should be distinct"));
4674 }
4675 }
4676 }
4677
4678 /* Check if broadcast is supported by the instruction and is applied
4679 to the memory operand. */
4680 if (i.broadcast)
4681 {
4682 int broadcasted_opnd_size;
4683
4684 /* Check if specified broadcast is supported in this instruction,
4685 and it's applied to memory operand of DWORD or QWORD type,
4686 depending on VecESize. */
4687 if (i.broadcast->type != t->opcode_modifier.broadcast
4688 || !i.types[i.broadcast->operand].bitfield.mem
4689 || (t->opcode_modifier.vecesize == 0
4690 && !i.types[i.broadcast->operand].bitfield.dword
4691 && !i.types[i.broadcast->operand].bitfield.unspecified)
4692 || (t->opcode_modifier.vecesize == 1
4693 && !i.types[i.broadcast->operand].bitfield.qword
4694 && !i.types[i.broadcast->operand].bitfield.unspecified))
4695 goto bad_broadcast;
4696
4697 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4698 if (i.broadcast->type == BROADCAST_1TO16)
4699 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4700 else if (i.broadcast->type == BROADCAST_1TO8)
4701 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4702 else if (i.broadcast->type == BROADCAST_1TO4)
4703 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4704 else if (i.broadcast->type == BROADCAST_1TO2)
4705 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4706 else
4707 goto bad_broadcast;
4708
4709 if ((broadcasted_opnd_size == 256
4710 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4711 || (broadcasted_opnd_size == 512
4712 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4713 {
4714 bad_broadcast:
4715 i.error = unsupported_broadcast;
4716 return 1;
4717 }
4718 }
4719 /* If broadcast is supported in this instruction, we need to check if
4720 operand of one-element size isn't specified without broadcast. */
4721 else if (t->opcode_modifier.broadcast && i.mem_operands)
4722 {
4723 /* Find memory operand. */
4724 for (op = 0; op < i.operands; op++)
4725 if (operand_type_check (i.types[op], anymem))
4726 break;
4727 gas_assert (op < i.operands);
4728 /* Check size of the memory operand. */
4729 if ((t->opcode_modifier.vecesize == 0
4730 && i.types[op].bitfield.dword)
4731 || (t->opcode_modifier.vecesize == 1
4732 && i.types[op].bitfield.qword))
4733 {
4734 i.error = broadcast_needed;
4735 return 1;
4736 }
4737 }
4738
4739 /* Check if requested masking is supported. */
4740 if (i.mask
4741 && (!t->opcode_modifier.masking
4742 || (i.mask->zeroing
4743 && t->opcode_modifier.masking == MERGING_MASKING)))
4744 {
4745 i.error = unsupported_masking;
4746 return 1;
4747 }
4748
4749 /* Check if masking is applied to dest operand. */
4750 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4751 {
4752 i.error = mask_not_on_destination;
4753 return 1;
4754 }
4755
4756 /* Check RC/SAE. */
4757 if (i.rounding)
4758 {
4759 if ((i.rounding->type != saeonly
4760 && !t->opcode_modifier.staticrounding)
4761 || (i.rounding->type == saeonly
4762 && (t->opcode_modifier.staticrounding
4763 || !t->opcode_modifier.sae)))
4764 {
4765 i.error = unsupported_rc_sae;
4766 return 1;
4767 }
4768 /* If the instruction has several immediate operands and one of
4769 them is rounding, the rounding operand should be the last
4770 immediate operand. */
4771 if (i.imm_operands > 1
4772 && i.rounding->operand != (int) (i.imm_operands - 1))
4773 {
4774 i.error = rc_sae_operand_not_last_imm;
4775 return 1;
4776 }
4777 }
4778
4779 /* Check vector Disp8 operand. */
4780 if (t->opcode_modifier.disp8memshift)
4781 {
4782 if (i.broadcast)
4783 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4784 else
4785 i.memshift = t->opcode_modifier.disp8memshift;
4786
4787 for (op = 0; op < i.operands; op++)
4788 if (operand_type_check (i.types[op], disp)
4789 && i.op[op].disps->X_op == O_constant)
4790 {
4791 offsetT value = i.op[op].disps->X_add_number;
4792 int vec_disp8_ok
4793 = (i.disp_encoding != disp_encoding_32bit
4794 && fits_in_vec_disp8 (value));
4795 if (t->operand_types [op].bitfield.vec_disp8)
4796 {
4797 if (vec_disp8_ok)
4798 i.types[op].bitfield.vec_disp8 = 1;
4799 else
4800 {
4801 /* Vector insn can only have Vec_Disp8/Disp32 in
4802 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4803 mode. */
4804 i.types[op].bitfield.disp8 = 0;
4805 if (flag_code != CODE_16BIT)
4806 i.types[op].bitfield.disp16 = 0;
4807 }
4808 }
4809 else if (flag_code != CODE_16BIT)
4810 {
4811 /* One form of this instruction supports vector Disp8.
4812 Try vector Disp8 if we need to use Disp32. */
4813 if (vec_disp8_ok && !fits_in_signed_byte (value))
4814 {
4815 i.error = try_vector_disp8;
4816 return 1;
4817 }
4818 }
4819 }
4820 }
4821 else
4822 i.memshift = -1;
4823
4824 return 0;
4825 }
4826
4827 /* Check if operands are valid for the instruction. Update VEX
4828 operand types. */
4829
4830 static int
4831 VEX_check_operands (const insn_template *t)
4832 {
4833 if (i.vec_encoding == vex_encoding_evex)
4834 {
4835 /* This instruction must be encoded with EVEX prefix. */
4836 if (!t->opcode_modifier.evex)
4837 {
4838 i.error = unsupported;
4839 return 1;
4840 }
4841 return 0;
4842 }
4843
4844 if (!t->opcode_modifier.vex)
4845 {
4846 /* This instruction template doesn't have VEX prefix. */
4847 if (i.vec_encoding != vex_encoding_default)
4848 {
4849 i.error = unsupported;
4850 return 1;
4851 }
4852 return 0;
4853 }
4854
4855 /* Only check VEX_Imm4, which must be the first operand. */
4856 if (t->operand_types[0].bitfield.vec_imm4)
4857 {
4858 if (i.op[0].imms->X_op != O_constant
4859 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4860 {
4861 i.error = bad_imm4;
4862 return 1;
4863 }
4864
4865 /* Turn off Imm8 so that update_imm won't complain. */
4866 i.types[0] = vec_imm4;
4867 }
4868
4869 return 0;
4870 }
4871
4872 static const insn_template *
4873 match_template (char mnem_suffix)
4874 {
4875 /* Points to template once we've found it. */
4876 const insn_template *t;
4877 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4878 i386_operand_type overlap4;
4879 unsigned int found_reverse_match;
4880 i386_opcode_modifier suffix_check, mnemsuf_check;
4881 i386_operand_type operand_types [MAX_OPERANDS];
4882 int addr_prefix_disp;
4883 unsigned int j;
4884 unsigned int found_cpu_match;
4885 unsigned int check_register;
4886 enum i386_error specific_error = 0;
4887
4888 #if MAX_OPERANDS != 5
4889 # error "MAX_OPERANDS must be 5."
4890 #endif
4891
4892 found_reverse_match = 0;
4893 addr_prefix_disp = -1;
4894
4895 memset (&suffix_check, 0, sizeof (suffix_check));
4896 if (i.suffix == BYTE_MNEM_SUFFIX)
4897 suffix_check.no_bsuf = 1;
4898 else if (i.suffix == WORD_MNEM_SUFFIX)
4899 suffix_check.no_wsuf = 1;
4900 else if (i.suffix == SHORT_MNEM_SUFFIX)
4901 suffix_check.no_ssuf = 1;
4902 else if (i.suffix == LONG_MNEM_SUFFIX)
4903 suffix_check.no_lsuf = 1;
4904 else if (i.suffix == QWORD_MNEM_SUFFIX)
4905 suffix_check.no_qsuf = 1;
4906 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4907 suffix_check.no_ldsuf = 1;
4908
4909 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4910 if (intel_syntax)
4911 {
4912 switch (mnem_suffix)
4913 {
4914 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4915 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4916 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4917 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4918 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4919 }
4920 }
4921
4922 /* Must have right number of operands. */
4923 i.error = number_of_operands_mismatch;
4924
4925 for (t = current_templates->start; t < current_templates->end; t++)
4926 {
4927 addr_prefix_disp = -1;
4928
4929 if (i.operands != t->operands)
4930 continue;
4931
4932 /* Check processor support. */
4933 i.error = unsupported;
4934 found_cpu_match = (cpu_flags_match (t)
4935 == CPU_FLAGS_PERFECT_MATCH);
4936 if (!found_cpu_match)
4937 continue;
4938
4939 /* Check old gcc support. */
4940 i.error = old_gcc_only;
4941 if (!old_gcc && t->opcode_modifier.oldgcc)
4942 continue;
4943
4944 /* Check AT&T mnemonic. */
4945 i.error = unsupported_with_intel_mnemonic;
4946 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4947 continue;
4948
4949 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4950 i.error = unsupported_syntax;
4951 if ((intel_syntax && t->opcode_modifier.attsyntax)
4952 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4953 || (intel64 && t->opcode_modifier.amd64)
4954 || (!intel64 && t->opcode_modifier.intel64))
4955 continue;
4956
4957 /* Check the suffix, except for some instructions in intel mode. */
4958 i.error = invalid_instruction_suffix;
4959 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4960 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4961 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4962 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4963 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4964 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4965 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4966 continue;
4967 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4968 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4969 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4970 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4971 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4972 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4973 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4974 continue;
4975
4976 if (!operand_size_match (t))
4977 continue;
4978
4979 for (j = 0; j < MAX_OPERANDS; j++)
4980 operand_types[j] = t->operand_types[j];
4981
4982 /* In general, don't allow 64-bit operands in 32-bit mode. */
4983 if (i.suffix == QWORD_MNEM_SUFFIX
4984 && flag_code != CODE_64BIT
4985 && (intel_syntax
4986 ? (!t->opcode_modifier.ignoresize
4987 && !intel_float_operand (t->name))
4988 : intel_float_operand (t->name) != 2)
4989 && ((!operand_types[0].bitfield.regmmx
4990 && !operand_types[0].bitfield.regxmm
4991 && !operand_types[0].bitfield.regymm
4992 && !operand_types[0].bitfield.regzmm)
4993 || (!operand_types[t->operands > 1].bitfield.regmmx
4994 && operand_types[t->operands > 1].bitfield.regxmm
4995 && operand_types[t->operands > 1].bitfield.regymm
4996 && operand_types[t->operands > 1].bitfield.regzmm))
4997 && (t->base_opcode != 0x0fc7
4998 || t->extension_opcode != 1 /* cmpxchg8b */))
4999 continue;
5000
5001 /* In general, don't allow 32-bit operands on pre-386. */
5002 else if (i.suffix == LONG_MNEM_SUFFIX
5003 && !cpu_arch_flags.bitfield.cpui386
5004 && (intel_syntax
5005 ? (!t->opcode_modifier.ignoresize
5006 && !intel_float_operand (t->name))
5007 : intel_float_operand (t->name) != 2)
5008 && ((!operand_types[0].bitfield.regmmx
5009 && !operand_types[0].bitfield.regxmm)
5010 || (!operand_types[t->operands > 1].bitfield.regmmx
5011 && operand_types[t->operands > 1].bitfield.regxmm)))
5012 continue;
5013
5014 /* Do not verify operands when there are none. */
5015 else
5016 {
5017 if (!t->operands)
5018 /* We've found a match; break out of loop. */
5019 break;
5020 }
5021
5022 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5023 into Disp32/Disp16/Disp32 operand. */
5024 if (i.prefix[ADDR_PREFIX] != 0)
5025 {
5026 /* There should be only one Disp operand. */
5027 switch (flag_code)
5028 {
5029 case CODE_16BIT:
5030 for (j = 0; j < MAX_OPERANDS; j++)
5031 {
5032 if (operand_types[j].bitfield.disp16)
5033 {
5034 addr_prefix_disp = j;
5035 operand_types[j].bitfield.disp32 = 1;
5036 operand_types[j].bitfield.disp16 = 0;
5037 break;
5038 }
5039 }
5040 break;
5041 case CODE_32BIT:
5042 for (j = 0; j < MAX_OPERANDS; j++)
5043 {
5044 if (operand_types[j].bitfield.disp32)
5045 {
5046 addr_prefix_disp = j;
5047 operand_types[j].bitfield.disp32 = 0;
5048 operand_types[j].bitfield.disp16 = 1;
5049 break;
5050 }
5051 }
5052 break;
5053 case CODE_64BIT:
5054 for (j = 0; j < MAX_OPERANDS; j++)
5055 {
5056 if (operand_types[j].bitfield.disp64)
5057 {
5058 addr_prefix_disp = j;
5059 operand_types[j].bitfield.disp64 = 0;
5060 operand_types[j].bitfield.disp32 = 1;
5061 break;
5062 }
5063 }
5064 break;
5065 }
5066 }
5067
5068 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5069 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5070 continue;
5071
5072 /* We check register size if needed. */
5073 check_register = t->opcode_modifier.checkregsize;
5074 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5075 switch (t->operands)
5076 {
5077 case 1:
5078 if (!operand_type_match (overlap0, i.types[0]))
5079 continue;
5080 break;
5081 case 2:
5082 /* xchg %eax, %eax is a special case. It is an alias for nop
5083 only in 32bit mode and we can use opcode 0x90. In 64bit
5084 mode, we can't use 0x90 for xchg %eax, %eax since it should
5085 zero-extend %eax to %rax. */
5086 if (flag_code == CODE_64BIT
5087 && t->base_opcode == 0x90
5088 && operand_type_equal (&i.types [0], &acc32)
5089 && operand_type_equal (&i.types [1], &acc32))
5090 continue;
5091 /* If we want store form, we reverse direction of operands. */
5092 if (i.dir_encoding == dir_encoding_store
5093 && t->opcode_modifier.d)
5094 goto check_reverse;
5095 /* Fall through. */
5096
5097 case 3:
5098 /* If we want store form, we skip the current load. */
5099 if (i.dir_encoding == dir_encoding_store
5100 && i.mem_operands == 0
5101 && t->opcode_modifier.load)
5102 continue;
5103 /* Fall through. */
5104 case 4:
5105 case 5:
5106 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5107 if (!operand_type_match (overlap0, i.types[0])
5108 || !operand_type_match (overlap1, i.types[1])
5109 || (check_register
5110 && !operand_type_register_match (overlap0, i.types[0],
5111 operand_types[0],
5112 overlap1, i.types[1],
5113 operand_types[1])))
5114 {
5115 /* Check if other direction is valid ... */
5116 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
5117 continue;
5118
5119 check_reverse:
5120 /* Try reversing direction of operands. */
5121 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5122 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5123 if (!operand_type_match (overlap0, i.types[0])
5124 || !operand_type_match (overlap1, i.types[1])
5125 || (check_register
5126 && !operand_type_register_match (overlap0,
5127 i.types[0],
5128 operand_types[1],
5129 overlap1,
5130 i.types[1],
5131 operand_types[0])))
5132 {
5133 /* Does not match either direction. */
5134 continue;
5135 }
5136 /* found_reverse_match holds which of D or FloatDR
5137 we've found. */
5138 if (t->opcode_modifier.d)
5139 found_reverse_match = Opcode_D;
5140 else if (t->opcode_modifier.floatd)
5141 found_reverse_match = Opcode_FloatD;
5142 else
5143 found_reverse_match = 0;
5144 if (t->opcode_modifier.floatr)
5145 found_reverse_match |= Opcode_FloatR;
5146 }
5147 else
5148 {
5149 /* Found a forward 2 operand match here. */
5150 switch (t->operands)
5151 {
5152 case 5:
5153 overlap4 = operand_type_and (i.types[4],
5154 operand_types[4]);
5155 /* Fall through. */
5156 case 4:
5157 overlap3 = operand_type_and (i.types[3],
5158 operand_types[3]);
5159 /* Fall through. */
5160 case 3:
5161 overlap2 = operand_type_and (i.types[2],
5162 operand_types[2]);
5163 break;
5164 }
5165
5166 switch (t->operands)
5167 {
5168 case 5:
5169 if (!operand_type_match (overlap4, i.types[4])
5170 || !operand_type_register_match (overlap3,
5171 i.types[3],
5172 operand_types[3],
5173 overlap4,
5174 i.types[4],
5175 operand_types[4]))
5176 continue;
5177 /* Fall through. */
5178 case 4:
5179 if (!operand_type_match (overlap3, i.types[3])
5180 || (check_register
5181 && !operand_type_register_match (overlap2,
5182 i.types[2],
5183 operand_types[2],
5184 overlap3,
5185 i.types[3],
5186 operand_types[3])))
5187 continue;
5188 /* Fall through. */
5189 case 3:
5190 /* Here we make use of the fact that there are no
5191 reverse match 3 operand instructions, and all 3
5192 operand instructions only need to be checked for
5193 register consistency between operands 2 and 3. */
5194 if (!operand_type_match (overlap2, i.types[2])
5195 || (check_register
5196 && !operand_type_register_match (overlap1,
5197 i.types[1],
5198 operand_types[1],
5199 overlap2,
5200 i.types[2],
5201 operand_types[2])))
5202 continue;
5203 break;
5204 }
5205 }
5206 /* Found either forward/reverse 2, 3 or 4 operand match here:
5207 slip through to break. */
5208 }
5209 if (!found_cpu_match)
5210 {
5211 found_reverse_match = 0;
5212 continue;
5213 }
5214
5215 /* Check if vector and VEX operands are valid. */
5216 if (check_VecOperands (t) || VEX_check_operands (t))
5217 {
5218 specific_error = i.error;
5219 continue;
5220 }
5221
5222 /* We've found a match; break out of loop. */
5223 break;
5224 }
5225
5226 if (t == current_templates->end)
5227 {
5228 /* We found no match. */
5229 const char *err_msg;
5230 switch (specific_error ? specific_error : i.error)
5231 {
5232 default:
5233 abort ();
5234 case operand_size_mismatch:
5235 err_msg = _("operand size mismatch");
5236 break;
5237 case operand_type_mismatch:
5238 err_msg = _("operand type mismatch");
5239 break;
5240 case register_type_mismatch:
5241 err_msg = _("register type mismatch");
5242 break;
5243 case number_of_operands_mismatch:
5244 err_msg = _("number of operands mismatch");
5245 break;
5246 case invalid_instruction_suffix:
5247 err_msg = _("invalid instruction suffix");
5248 break;
5249 case bad_imm4:
5250 err_msg = _("constant doesn't fit in 4 bits");
5251 break;
5252 case old_gcc_only:
5253 err_msg = _("only supported with old gcc");
5254 break;
5255 case unsupported_with_intel_mnemonic:
5256 err_msg = _("unsupported with Intel mnemonic");
5257 break;
5258 case unsupported_syntax:
5259 err_msg = _("unsupported syntax");
5260 break;
5261 case unsupported:
5262 as_bad (_("unsupported instruction `%s'"),
5263 current_templates->start->name);
5264 return NULL;
5265 case invalid_vsib_address:
5266 err_msg = _("invalid VSIB address");
5267 break;
5268 case invalid_vector_register_set:
5269 err_msg = _("mask, index, and destination registers must be distinct");
5270 break;
5271 case unsupported_vector_index_register:
5272 err_msg = _("unsupported vector index register");
5273 break;
5274 case unsupported_broadcast:
5275 err_msg = _("unsupported broadcast");
5276 break;
5277 case broadcast_not_on_src_operand:
5278 err_msg = _("broadcast not on source memory operand");
5279 break;
5280 case broadcast_needed:
5281 err_msg = _("broadcast is needed for operand of such type");
5282 break;
5283 case unsupported_masking:
5284 err_msg = _("unsupported masking");
5285 break;
5286 case mask_not_on_destination:
5287 err_msg = _("mask not on destination operand");
5288 break;
5289 case no_default_mask:
5290 err_msg = _("default mask isn't allowed");
5291 break;
5292 case unsupported_rc_sae:
5293 err_msg = _("unsupported static rounding/sae");
5294 break;
5295 case rc_sae_operand_not_last_imm:
5296 if (intel_syntax)
5297 err_msg = _("RC/SAE operand must precede immediate operands");
5298 else
5299 err_msg = _("RC/SAE operand must follow immediate operands");
5300 break;
5301 case invalid_register_operand:
5302 err_msg = _("invalid register operand");
5303 break;
5304 }
5305 as_bad (_("%s for `%s'"), err_msg,
5306 current_templates->start->name);
5307 return NULL;
5308 }
5309
5310 if (!quiet_warnings)
5311 {
5312 if (!intel_syntax
5313 && (i.types[0].bitfield.jumpabsolute
5314 != operand_types[0].bitfield.jumpabsolute))
5315 {
5316 as_warn (_("indirect %s without `*'"), t->name);
5317 }
5318
5319 if (t->opcode_modifier.isprefix
5320 && t->opcode_modifier.ignoresize)
5321 {
5322 /* Warn them that a data or address size prefix doesn't
5323 affect assembly of the next line of code. */
5324 as_warn (_("stand-alone `%s' prefix"), t->name);
5325 }
5326 }
5327
5328 /* Copy the template we found. */
5329 i.tm = *t;
5330
5331 if (addr_prefix_disp != -1)
5332 i.tm.operand_types[addr_prefix_disp]
5333 = operand_types[addr_prefix_disp];
5334
5335 if (found_reverse_match)
5336 {
5337 /* If we found a reverse match we must alter the opcode
5338 direction bit. found_reverse_match holds bits to change
5339 (different for int & float insns). */
5340
5341 i.tm.base_opcode ^= found_reverse_match;
5342
5343 i.tm.operand_types[0] = operand_types[1];
5344 i.tm.operand_types[1] = operand_types[0];
5345 }
5346
5347 return t;
5348 }
5349
5350 static int
5351 check_string (void)
5352 {
5353 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5354 if (i.tm.operand_types[mem_op].bitfield.esseg)
5355 {
5356 if (i.seg[0] != NULL && i.seg[0] != &es)
5357 {
5358 as_bad (_("`%s' operand %d must use `%ses' segment"),
5359 i.tm.name,
5360 mem_op + 1,
5361 register_prefix);
5362 return 0;
5363 }
5364 /* There's only ever one segment override allowed per instruction.
5365 This instruction possibly has a legal segment override on the
5366 second operand, so copy the segment to where non-string
5367 instructions store it, allowing common code. */
5368 i.seg[0] = i.seg[1];
5369 }
5370 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5371 {
5372 if (i.seg[1] != NULL && i.seg[1] != &es)
5373 {
5374 as_bad (_("`%s' operand %d must use `%ses' segment"),
5375 i.tm.name,
5376 mem_op + 2,
5377 register_prefix);
5378 return 0;
5379 }
5380 }
5381 return 1;
5382 }
5383
5384 static int
5385 process_suffix (void)
5386 {
5387 /* If matched instruction specifies an explicit instruction mnemonic
5388 suffix, use it. */
5389 if (i.tm.opcode_modifier.size16)
5390 i.suffix = WORD_MNEM_SUFFIX;
5391 else if (i.tm.opcode_modifier.size32)
5392 i.suffix = LONG_MNEM_SUFFIX;
5393 else if (i.tm.opcode_modifier.size64)
5394 i.suffix = QWORD_MNEM_SUFFIX;
5395 else if (i.reg_operands)
5396 {
5397 /* If there's no instruction mnemonic suffix we try to invent one
5398 based on register operands. */
5399 if (!i.suffix)
5400 {
5401 /* We take i.suffix from the last register operand specified,
5402 Destination register type is more significant than source
5403 register type. crc32 in SSE4.2 prefers source register
5404 type. */
5405 if (i.tm.base_opcode == 0xf20f38f1)
5406 {
5407 if (i.types[0].bitfield.reg16)
5408 i.suffix = WORD_MNEM_SUFFIX;
5409 else if (i.types[0].bitfield.reg32)
5410 i.suffix = LONG_MNEM_SUFFIX;
5411 else if (i.types[0].bitfield.reg64)
5412 i.suffix = QWORD_MNEM_SUFFIX;
5413 }
5414 else if (i.tm.base_opcode == 0xf20f38f0)
5415 {
5416 if (i.types[0].bitfield.reg8)
5417 i.suffix = BYTE_MNEM_SUFFIX;
5418 }
5419
5420 if (!i.suffix)
5421 {
5422 int op;
5423
5424 if (i.tm.base_opcode == 0xf20f38f1
5425 || i.tm.base_opcode == 0xf20f38f0)
5426 {
5427 /* We have to know the operand size for crc32. */
5428 as_bad (_("ambiguous memory operand size for `%s`"),
5429 i.tm.name);
5430 return 0;
5431 }
5432
5433 for (op = i.operands; --op >= 0;)
5434 if (!i.tm.operand_types[op].bitfield.inoutportreg
5435 && !i.tm.operand_types[op].bitfield.shiftcount)
5436 {
5437 if (i.types[op].bitfield.reg8)
5438 {
5439 i.suffix = BYTE_MNEM_SUFFIX;
5440 break;
5441 }
5442 else if (i.types[op].bitfield.reg16)
5443 {
5444 i.suffix = WORD_MNEM_SUFFIX;
5445 break;
5446 }
5447 else if (i.types[op].bitfield.reg32)
5448 {
5449 i.suffix = LONG_MNEM_SUFFIX;
5450 break;
5451 }
5452 else if (i.types[op].bitfield.reg64)
5453 {
5454 i.suffix = QWORD_MNEM_SUFFIX;
5455 break;
5456 }
5457 }
5458 }
5459 }
5460 else if (i.suffix == BYTE_MNEM_SUFFIX)
5461 {
5462 if (intel_syntax
5463 && i.tm.opcode_modifier.ignoresize
5464 && i.tm.opcode_modifier.no_bsuf)
5465 i.suffix = 0;
5466 else if (!check_byte_reg ())
5467 return 0;
5468 }
5469 else if (i.suffix == LONG_MNEM_SUFFIX)
5470 {
5471 if (intel_syntax
5472 && i.tm.opcode_modifier.ignoresize
5473 && i.tm.opcode_modifier.no_lsuf)
5474 i.suffix = 0;
5475 else if (!check_long_reg ())
5476 return 0;
5477 }
5478 else if (i.suffix == QWORD_MNEM_SUFFIX)
5479 {
5480 if (intel_syntax
5481 && i.tm.opcode_modifier.ignoresize
5482 && i.tm.opcode_modifier.no_qsuf)
5483 i.suffix = 0;
5484 else if (!check_qword_reg ())
5485 return 0;
5486 }
5487 else if (i.suffix == WORD_MNEM_SUFFIX)
5488 {
5489 if (intel_syntax
5490 && i.tm.opcode_modifier.ignoresize
5491 && i.tm.opcode_modifier.no_wsuf)
5492 i.suffix = 0;
5493 else if (!check_word_reg ())
5494 return 0;
5495 }
5496 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5497 || i.suffix == YMMWORD_MNEM_SUFFIX
5498 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5499 {
5500 /* Skip if the instruction has x/y/z suffix. match_template
5501 should check if it is a valid suffix. */
5502 }
5503 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5504 /* Do nothing if the instruction is going to ignore the prefix. */
5505 ;
5506 else
5507 abort ();
5508 }
5509 else if (i.tm.opcode_modifier.defaultsize
5510 && !i.suffix
5511 /* exclude fldenv/frstor/fsave/fstenv */
5512 && i.tm.opcode_modifier.no_ssuf)
5513 {
5514 i.suffix = stackop_size;
5515 }
5516 else if (intel_syntax
5517 && !i.suffix
5518 && (i.tm.operand_types[0].bitfield.jumpabsolute
5519 || i.tm.opcode_modifier.jumpbyte
5520 || i.tm.opcode_modifier.jumpintersegment
5521 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5522 && i.tm.extension_opcode <= 3)))
5523 {
5524 switch (flag_code)
5525 {
5526 case CODE_64BIT:
5527 if (!i.tm.opcode_modifier.no_qsuf)
5528 {
5529 i.suffix = QWORD_MNEM_SUFFIX;
5530 break;
5531 }
5532 /* Fall through. */
5533 case CODE_32BIT:
5534 if (!i.tm.opcode_modifier.no_lsuf)
5535 i.suffix = LONG_MNEM_SUFFIX;
5536 break;
5537 case CODE_16BIT:
5538 if (!i.tm.opcode_modifier.no_wsuf)
5539 i.suffix = WORD_MNEM_SUFFIX;
5540 break;
5541 }
5542 }
5543
5544 if (!i.suffix)
5545 {
5546 if (!intel_syntax)
5547 {
5548 if (i.tm.opcode_modifier.w)
5549 {
5550 as_bad (_("no instruction mnemonic suffix given and "
5551 "no register operands; can't size instruction"));
5552 return 0;
5553 }
5554 }
5555 else
5556 {
5557 unsigned int suffixes;
5558
5559 suffixes = !i.tm.opcode_modifier.no_bsuf;
5560 if (!i.tm.opcode_modifier.no_wsuf)
5561 suffixes |= 1 << 1;
5562 if (!i.tm.opcode_modifier.no_lsuf)
5563 suffixes |= 1 << 2;
5564 if (!i.tm.opcode_modifier.no_ldsuf)
5565 suffixes |= 1 << 3;
5566 if (!i.tm.opcode_modifier.no_ssuf)
5567 suffixes |= 1 << 4;
5568 if (!i.tm.opcode_modifier.no_qsuf)
5569 suffixes |= 1 << 5;
5570
5571 /* There are more than suffix matches. */
5572 if (i.tm.opcode_modifier.w
5573 || ((suffixes & (suffixes - 1))
5574 && !i.tm.opcode_modifier.defaultsize
5575 && !i.tm.opcode_modifier.ignoresize))
5576 {
5577 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5578 return 0;
5579 }
5580 }
5581 }
5582
5583 /* Change the opcode based on the operand size given by i.suffix;
5584 We don't need to change things for byte insns. */
5585
5586 if (i.suffix
5587 && i.suffix != BYTE_MNEM_SUFFIX
5588 && i.suffix != XMMWORD_MNEM_SUFFIX
5589 && i.suffix != YMMWORD_MNEM_SUFFIX
5590 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5591 {
5592 /* It's not a byte, select word/dword operation. */
5593 if (i.tm.opcode_modifier.w)
5594 {
5595 if (i.tm.opcode_modifier.shortform)
5596 i.tm.base_opcode |= 8;
5597 else
5598 i.tm.base_opcode |= 1;
5599 }
5600
5601 /* Now select between word & dword operations via the operand
5602 size prefix, except for instructions that will ignore this
5603 prefix anyway. */
5604 if (i.tm.opcode_modifier.addrprefixop0)
5605 {
5606 /* The address size override prefix changes the size of the
5607 first operand. */
5608 if ((flag_code == CODE_32BIT
5609 && i.op->regs[0].reg_type.bitfield.reg16)
5610 || (flag_code != CODE_32BIT
5611 && i.op->regs[0].reg_type.bitfield.reg32))
5612 if (!add_prefix (ADDR_PREFIX_OPCODE))
5613 return 0;
5614 }
5615 else if (i.suffix != QWORD_MNEM_SUFFIX
5616 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5617 && !i.tm.opcode_modifier.ignoresize
5618 && !i.tm.opcode_modifier.floatmf
5619 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5620 || (flag_code == CODE_64BIT
5621 && i.tm.opcode_modifier.jumpbyte)))
5622 {
5623 unsigned int prefix = DATA_PREFIX_OPCODE;
5624
5625 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5626 prefix = ADDR_PREFIX_OPCODE;
5627
5628 if (!add_prefix (prefix))
5629 return 0;
5630 }
5631
5632 /* Set mode64 for an operand. */
5633 if (i.suffix == QWORD_MNEM_SUFFIX
5634 && flag_code == CODE_64BIT
5635 && !i.tm.opcode_modifier.norex64)
5636 {
5637 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5638 need rex64. cmpxchg8b is also a special case. */
5639 if (! (i.operands == 2
5640 && i.tm.base_opcode == 0x90
5641 && i.tm.extension_opcode == None
5642 && operand_type_equal (&i.types [0], &acc64)
5643 && operand_type_equal (&i.types [1], &acc64))
5644 && ! (i.operands == 1
5645 && i.tm.base_opcode == 0xfc7
5646 && i.tm.extension_opcode == 1
5647 && !operand_type_check (i.types [0], reg)
5648 && operand_type_check (i.types [0], anymem)))
5649 i.rex |= REX_W;
5650 }
5651
5652 /* Size floating point instruction. */
5653 if (i.suffix == LONG_MNEM_SUFFIX)
5654 if (i.tm.opcode_modifier.floatmf)
5655 i.tm.base_opcode ^= 4;
5656 }
5657
5658 return 1;
5659 }
5660
5661 static int
5662 check_byte_reg (void)
5663 {
5664 int op;
5665
5666 for (op = i.operands; --op >= 0;)
5667 {
5668 /* If this is an eight bit register, it's OK. If it's the 16 or
5669 32 bit version of an eight bit register, we will just use the
5670 low portion, and that's OK too. */
5671 if (i.types[op].bitfield.reg8)
5672 continue;
5673
5674 /* I/O port address operands are OK too. */
5675 if (i.tm.operand_types[op].bitfield.inoutportreg)
5676 continue;
5677
5678 /* crc32 doesn't generate this warning. */
5679 if (i.tm.base_opcode == 0xf20f38f0)
5680 continue;
5681
5682 if ((i.types[op].bitfield.reg16
5683 || i.types[op].bitfield.reg32
5684 || i.types[op].bitfield.reg64)
5685 && i.op[op].regs->reg_num < 4
5686 /* Prohibit these changes in 64bit mode, since the lowering
5687 would be more complicated. */
5688 && flag_code != CODE_64BIT)
5689 {
5690 #if REGISTER_WARNINGS
5691 if (!quiet_warnings)
5692 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5693 register_prefix,
5694 (i.op[op].regs + (i.types[op].bitfield.reg16
5695 ? REGNAM_AL - REGNAM_AX
5696 : REGNAM_AL - REGNAM_EAX))->reg_name,
5697 register_prefix,
5698 i.op[op].regs->reg_name,
5699 i.suffix);
5700 #endif
5701 continue;
5702 }
5703 /* Any other register is bad. */
5704 if (i.types[op].bitfield.reg16
5705 || i.types[op].bitfield.reg32
5706 || i.types[op].bitfield.reg64
5707 || i.types[op].bitfield.regmmx
5708 || i.types[op].bitfield.regxmm
5709 || i.types[op].bitfield.regymm
5710 || i.types[op].bitfield.regzmm
5711 || i.types[op].bitfield.sreg2
5712 || i.types[op].bitfield.sreg3
5713 || i.types[op].bitfield.control
5714 || i.types[op].bitfield.debug
5715 || i.types[op].bitfield.test
5716 || i.types[op].bitfield.floatreg
5717 || i.types[op].bitfield.floatacc)
5718 {
5719 as_bad (_("`%s%s' not allowed with `%s%c'"),
5720 register_prefix,
5721 i.op[op].regs->reg_name,
5722 i.tm.name,
5723 i.suffix);
5724 return 0;
5725 }
5726 }
5727 return 1;
5728 }
5729
5730 static int
5731 check_long_reg (void)
5732 {
5733 int op;
5734
5735 for (op = i.operands; --op >= 0;)
5736 /* Reject eight bit registers, except where the template requires
5737 them. (eg. movzb) */
5738 if (i.types[op].bitfield.reg8
5739 && (i.tm.operand_types[op].bitfield.reg16
5740 || i.tm.operand_types[op].bitfield.reg32
5741 || i.tm.operand_types[op].bitfield.acc))
5742 {
5743 as_bad (_("`%s%s' not allowed with `%s%c'"),
5744 register_prefix,
5745 i.op[op].regs->reg_name,
5746 i.tm.name,
5747 i.suffix);
5748 return 0;
5749 }
5750 /* Warn if the e prefix on a general reg is missing. */
5751 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5752 && i.types[op].bitfield.reg16
5753 && (i.tm.operand_types[op].bitfield.reg32
5754 || i.tm.operand_types[op].bitfield.acc))
5755 {
5756 /* Prohibit these changes in the 64bit mode, since the
5757 lowering is more complicated. */
5758 if (flag_code == CODE_64BIT)
5759 {
5760 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5761 register_prefix, i.op[op].regs->reg_name,
5762 i.suffix);
5763 return 0;
5764 }
5765 #if REGISTER_WARNINGS
5766 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5767 register_prefix,
5768 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5769 register_prefix, i.op[op].regs->reg_name, i.suffix);
5770 #endif
5771 }
5772 /* Warn if the r prefix on a general reg is present. */
5773 else if (i.types[op].bitfield.reg64
5774 && (i.tm.operand_types[op].bitfield.reg32
5775 || i.tm.operand_types[op].bitfield.acc))
5776 {
5777 if (intel_syntax
5778 && i.tm.opcode_modifier.toqword
5779 && !i.types[0].bitfield.regxmm)
5780 {
5781 /* Convert to QWORD. We want REX byte. */
5782 i.suffix = QWORD_MNEM_SUFFIX;
5783 }
5784 else
5785 {
5786 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5787 register_prefix, i.op[op].regs->reg_name,
5788 i.suffix);
5789 return 0;
5790 }
5791 }
5792 return 1;
5793 }
5794
5795 static int
5796 check_qword_reg (void)
5797 {
5798 int op;
5799
5800 for (op = i.operands; --op >= 0; )
5801 /* Reject eight bit registers, except where the template requires
5802 them. (eg. movzb) */
5803 if (i.types[op].bitfield.reg8
5804 && (i.tm.operand_types[op].bitfield.reg16
5805 || i.tm.operand_types[op].bitfield.reg32
5806 || i.tm.operand_types[op].bitfield.acc))
5807 {
5808 as_bad (_("`%s%s' not allowed with `%s%c'"),
5809 register_prefix,
5810 i.op[op].regs->reg_name,
5811 i.tm.name,
5812 i.suffix);
5813 return 0;
5814 }
5815 /* Warn if the r prefix on a general reg is missing. */
5816 else if ((i.types[op].bitfield.reg16
5817 || i.types[op].bitfield.reg32)
5818 && (i.tm.operand_types[op].bitfield.reg64
5819 || i.tm.operand_types[op].bitfield.acc))
5820 {
5821 /* Prohibit these changes in the 64bit mode, since the
5822 lowering is more complicated. */
5823 if (intel_syntax
5824 && i.tm.opcode_modifier.todword
5825 && !i.types[0].bitfield.regxmm)
5826 {
5827 /* Convert to DWORD. We don't want REX byte. */
5828 i.suffix = LONG_MNEM_SUFFIX;
5829 }
5830 else
5831 {
5832 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5833 register_prefix, i.op[op].regs->reg_name,
5834 i.suffix);
5835 return 0;
5836 }
5837 }
5838 return 1;
5839 }
5840
5841 static int
5842 check_word_reg (void)
5843 {
5844 int op;
5845 for (op = i.operands; --op >= 0;)
5846 /* Reject eight bit registers, except where the template requires
5847 them. (eg. movzb) */
5848 if (i.types[op].bitfield.reg8
5849 && (i.tm.operand_types[op].bitfield.reg16
5850 || i.tm.operand_types[op].bitfield.reg32
5851 || i.tm.operand_types[op].bitfield.acc))
5852 {
5853 as_bad (_("`%s%s' not allowed with `%s%c'"),
5854 register_prefix,
5855 i.op[op].regs->reg_name,
5856 i.tm.name,
5857 i.suffix);
5858 return 0;
5859 }
5860 /* Warn if the e or r prefix on a general reg is present. */
5861 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5862 && (i.types[op].bitfield.reg32
5863 || i.types[op].bitfield.reg64)
5864 && (i.tm.operand_types[op].bitfield.reg16
5865 || i.tm.operand_types[op].bitfield.acc))
5866 {
5867 /* Prohibit these changes in the 64bit mode, since the
5868 lowering is more complicated. */
5869 if (flag_code == CODE_64BIT)
5870 {
5871 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5872 register_prefix, i.op[op].regs->reg_name,
5873 i.suffix);
5874 return 0;
5875 }
5876 #if REGISTER_WARNINGS
5877 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5878 register_prefix,
5879 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5880 register_prefix, i.op[op].regs->reg_name, i.suffix);
5881 #endif
5882 }
5883 return 1;
5884 }
5885
5886 static int
5887 update_imm (unsigned int j)
5888 {
5889 i386_operand_type overlap = i.types[j];
5890 if ((overlap.bitfield.imm8
5891 || overlap.bitfield.imm8s
5892 || overlap.bitfield.imm16
5893 || overlap.bitfield.imm32
5894 || overlap.bitfield.imm32s
5895 || overlap.bitfield.imm64)
5896 && !operand_type_equal (&overlap, &imm8)
5897 && !operand_type_equal (&overlap, &imm8s)
5898 && !operand_type_equal (&overlap, &imm16)
5899 && !operand_type_equal (&overlap, &imm32)
5900 && !operand_type_equal (&overlap, &imm32s)
5901 && !operand_type_equal (&overlap, &imm64))
5902 {
5903 if (i.suffix)
5904 {
5905 i386_operand_type temp;
5906
5907 operand_type_set (&temp, 0);
5908 if (i.suffix == BYTE_MNEM_SUFFIX)
5909 {
5910 temp.bitfield.imm8 = overlap.bitfield.imm8;
5911 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5912 }
5913 else if (i.suffix == WORD_MNEM_SUFFIX)
5914 temp.bitfield.imm16 = overlap.bitfield.imm16;
5915 else if (i.suffix == QWORD_MNEM_SUFFIX)
5916 {
5917 temp.bitfield.imm64 = overlap.bitfield.imm64;
5918 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5919 }
5920 else
5921 temp.bitfield.imm32 = overlap.bitfield.imm32;
5922 overlap = temp;
5923 }
5924 else if (operand_type_equal (&overlap, &imm16_32_32s)
5925 || operand_type_equal (&overlap, &imm16_32)
5926 || operand_type_equal (&overlap, &imm16_32s))
5927 {
5928 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5929 overlap = imm16;
5930 else
5931 overlap = imm32s;
5932 }
5933 if (!operand_type_equal (&overlap, &imm8)
5934 && !operand_type_equal (&overlap, &imm8s)
5935 && !operand_type_equal (&overlap, &imm16)
5936 && !operand_type_equal (&overlap, &imm32)
5937 && !operand_type_equal (&overlap, &imm32s)
5938 && !operand_type_equal (&overlap, &imm64))
5939 {
5940 as_bad (_("no instruction mnemonic suffix given; "
5941 "can't determine immediate size"));
5942 return 0;
5943 }
5944 }
5945 i.types[j] = overlap;
5946
5947 return 1;
5948 }
5949
5950 static int
5951 finalize_imm (void)
5952 {
5953 unsigned int j, n;
5954
5955 /* Update the first 2 immediate operands. */
5956 n = i.operands > 2 ? 2 : i.operands;
5957 if (n)
5958 {
5959 for (j = 0; j < n; j++)
5960 if (update_imm (j) == 0)
5961 return 0;
5962
5963 /* The 3rd operand can't be immediate operand. */
5964 gas_assert (operand_type_check (i.types[2], imm) == 0);
5965 }
5966
5967 return 1;
5968 }
5969
5970 static int
5971 bad_implicit_operand (int xmm)
5972 {
5973 const char *ireg = xmm ? "xmm0" : "ymm0";
5974
5975 if (intel_syntax)
5976 as_bad (_("the last operand of `%s' must be `%s%s'"),
5977 i.tm.name, register_prefix, ireg);
5978 else
5979 as_bad (_("the first operand of `%s' must be `%s%s'"),
5980 i.tm.name, register_prefix, ireg);
5981 return 0;
5982 }
5983
5984 static int
5985 process_operands (void)
5986 {
5987 /* Default segment register this instruction will use for memory
5988 accesses. 0 means unknown. This is only for optimizing out
5989 unnecessary segment overrides. */
5990 const seg_entry *default_seg = 0;
5991
5992 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5993 {
5994 unsigned int dupl = i.operands;
5995 unsigned int dest = dupl - 1;
5996 unsigned int j;
5997
5998 /* The destination must be an xmm register. */
5999 gas_assert (i.reg_operands
6000 && MAX_OPERANDS > dupl
6001 && operand_type_equal (&i.types[dest], &regxmm));
6002
6003 if (i.tm.opcode_modifier.firstxmm0)
6004 {
6005 /* The first operand is implicit and must be xmm0. */
6006 gas_assert (operand_type_equal (&i.types[0], &regxmm));
6007 if (register_number (i.op[0].regs) != 0)
6008 return bad_implicit_operand (1);
6009
6010 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6011 {
6012 /* Keep xmm0 for instructions with VEX prefix and 3
6013 sources. */
6014 goto duplicate;
6015 }
6016 else
6017 {
6018 /* We remove the first xmm0 and keep the number of
6019 operands unchanged, which in fact duplicates the
6020 destination. */
6021 for (j = 1; j < i.operands; j++)
6022 {
6023 i.op[j - 1] = i.op[j];
6024 i.types[j - 1] = i.types[j];
6025 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6026 }
6027 }
6028 }
6029 else if (i.tm.opcode_modifier.implicit1stxmm0)
6030 {
6031 gas_assert ((MAX_OPERANDS - 1) > dupl
6032 && (i.tm.opcode_modifier.vexsources
6033 == VEX3SOURCES));
6034
6035 /* Add the implicit xmm0 for instructions with VEX prefix
6036 and 3 sources. */
6037 for (j = i.operands; j > 0; j--)
6038 {
6039 i.op[j] = i.op[j - 1];
6040 i.types[j] = i.types[j - 1];
6041 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6042 }
6043 i.op[0].regs
6044 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6045 i.types[0] = regxmm;
6046 i.tm.operand_types[0] = regxmm;
6047
6048 i.operands += 2;
6049 i.reg_operands += 2;
6050 i.tm.operands += 2;
6051
6052 dupl++;
6053 dest++;
6054 i.op[dupl] = i.op[dest];
6055 i.types[dupl] = i.types[dest];
6056 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6057 }
6058 else
6059 {
6060 duplicate:
6061 i.operands++;
6062 i.reg_operands++;
6063 i.tm.operands++;
6064
6065 i.op[dupl] = i.op[dest];
6066 i.types[dupl] = i.types[dest];
6067 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6068 }
6069
6070 if (i.tm.opcode_modifier.immext)
6071 process_immext ();
6072 }
6073 else if (i.tm.opcode_modifier.firstxmm0)
6074 {
6075 unsigned int j;
6076
6077 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
6078 gas_assert (i.reg_operands
6079 && (operand_type_equal (&i.types[0], &regxmm)
6080 || operand_type_equal (&i.types[0], &regymm)
6081 || operand_type_equal (&i.types[0], &regzmm)));
6082 if (register_number (i.op[0].regs) != 0)
6083 return bad_implicit_operand (i.types[0].bitfield.regxmm);
6084
6085 for (j = 1; j < i.operands; j++)
6086 {
6087 i.op[j - 1] = i.op[j];
6088 i.types[j - 1] = i.types[j];
6089
6090 /* We need to adjust fields in i.tm since they are used by
6091 build_modrm_byte. */
6092 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6093 }
6094
6095 i.operands--;
6096 i.reg_operands--;
6097 i.tm.operands--;
6098 }
6099 else if (i.tm.opcode_modifier.implicitquadgroup)
6100 {
6101 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6102 gas_assert (i.operands >= 2
6103 && (operand_type_equal (&i.types[1], &regxmm)
6104 || operand_type_equal (&i.types[1], &regymm)
6105 || operand_type_equal (&i.types[1], &regzmm)));
6106 unsigned int regnum = register_number (i.op[1].regs);
6107 unsigned int first_reg_in_group = regnum & ~3;
6108 unsigned int last_reg_in_group = first_reg_in_group + 3;
6109 if (regnum != first_reg_in_group) {
6110 as_warn (_("the second source register `%s%s' implicitly denotes"
6111 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6112 register_prefix, i.op[1].regs->reg_name,
6113 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6114 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6115 i.tm.name);
6116 }
6117 }
6118 else if (i.tm.opcode_modifier.regkludge)
6119 {
6120 /* The imul $imm, %reg instruction is converted into
6121 imul $imm, %reg, %reg, and the clr %reg instruction
6122 is converted into xor %reg, %reg. */
6123
6124 unsigned int first_reg_op;
6125
6126 if (operand_type_check (i.types[0], reg))
6127 first_reg_op = 0;
6128 else
6129 first_reg_op = 1;
6130 /* Pretend we saw the extra register operand. */
6131 gas_assert (i.reg_operands == 1
6132 && i.op[first_reg_op + 1].regs == 0);
6133 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6134 i.types[first_reg_op + 1] = i.types[first_reg_op];
6135 i.operands++;
6136 i.reg_operands++;
6137 }
6138
6139 if (i.tm.opcode_modifier.shortform)
6140 {
6141 if (i.types[0].bitfield.sreg2
6142 || i.types[0].bitfield.sreg3)
6143 {
6144 if (i.tm.base_opcode == POP_SEG_SHORT
6145 && i.op[0].regs->reg_num == 1)
6146 {
6147 as_bad (_("you can't `pop %scs'"), register_prefix);
6148 return 0;
6149 }
6150 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6151 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6152 i.rex |= REX_B;
6153 }
6154 else
6155 {
6156 /* The register or float register operand is in operand
6157 0 or 1. */
6158 unsigned int op;
6159
6160 if (i.types[0].bitfield.floatreg
6161 || operand_type_check (i.types[0], reg))
6162 op = 0;
6163 else
6164 op = 1;
6165 /* Register goes in low 3 bits of opcode. */
6166 i.tm.base_opcode |= i.op[op].regs->reg_num;
6167 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6168 i.rex |= REX_B;
6169 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6170 {
6171 /* Warn about some common errors, but press on regardless.
6172 The first case can be generated by gcc (<= 2.8.1). */
6173 if (i.operands == 2)
6174 {
6175 /* Reversed arguments on faddp, fsubp, etc. */
6176 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6177 register_prefix, i.op[!intel_syntax].regs->reg_name,
6178 register_prefix, i.op[intel_syntax].regs->reg_name);
6179 }
6180 else
6181 {
6182 /* Extraneous `l' suffix on fp insn. */
6183 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6184 register_prefix, i.op[0].regs->reg_name);
6185 }
6186 }
6187 }
6188 }
6189 else if (i.tm.opcode_modifier.modrm)
6190 {
6191 /* The opcode is completed (modulo i.tm.extension_opcode which
6192 must be put into the modrm byte). Now, we make the modrm and
6193 index base bytes based on all the info we've collected. */
6194
6195 default_seg = build_modrm_byte ();
6196 }
6197 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6198 {
6199 default_seg = &ds;
6200 }
6201 else if (i.tm.opcode_modifier.isstring)
6202 {
6203 /* For the string instructions that allow a segment override
6204 on one of their operands, the default segment is ds. */
6205 default_seg = &ds;
6206 }
6207
6208 if (i.tm.base_opcode == 0x8d /* lea */
6209 && i.seg[0]
6210 && !quiet_warnings)
6211 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6212
6213 /* If a segment was explicitly specified, and the specified segment
6214 is not the default, use an opcode prefix to select it. If we
6215 never figured out what the default segment is, then default_seg
6216 will be zero at this point, and the specified segment prefix will
6217 always be used. */
6218 if ((i.seg[0]) && (i.seg[0] != default_seg))
6219 {
6220 if (!add_prefix (i.seg[0]->seg_prefix))
6221 return 0;
6222 }
6223 return 1;
6224 }
6225
6226 static const seg_entry *
6227 build_modrm_byte (void)
6228 {
6229 const seg_entry *default_seg = 0;
6230 unsigned int source, dest;
6231 int vex_3_sources;
6232
6233 /* The first operand of instructions with VEX prefix and 3 sources
6234 must be VEX_Imm4. */
6235 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6236 if (vex_3_sources)
6237 {
6238 unsigned int nds, reg_slot;
6239 expressionS *exp;
6240
6241 if (i.tm.opcode_modifier.veximmext
6242 && i.tm.opcode_modifier.immext)
6243 {
6244 dest = i.operands - 2;
6245 gas_assert (dest == 3);
6246 }
6247 else
6248 dest = i.operands - 1;
6249 nds = dest - 1;
6250
6251 /* There are 2 kinds of instructions:
6252 1. 5 operands: 4 register operands or 3 register operands
6253 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6254 VexW0 or VexW1. The destination must be either XMM, YMM or
6255 ZMM register.
6256 2. 4 operands: 4 register operands or 3 register operands
6257 plus 1 memory operand, VexXDS, and VexImmExt */
6258 gas_assert ((i.reg_operands == 4
6259 || (i.reg_operands == 3 && i.mem_operands == 1))
6260 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6261 && (i.tm.opcode_modifier.veximmext
6262 || (i.imm_operands == 1
6263 && i.types[0].bitfield.vec_imm4
6264 && (i.tm.opcode_modifier.vexw == VEXW0
6265 || i.tm.opcode_modifier.vexw == VEXW1)
6266 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
6267 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6268 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
6269
6270 if (i.imm_operands == 0)
6271 {
6272 /* When there is no immediate operand, generate an 8bit
6273 immediate operand to encode the first operand. */
6274 exp = &im_expressions[i.imm_operands++];
6275 i.op[i.operands].imms = exp;
6276 i.types[i.operands] = imm8;
6277 i.operands++;
6278 /* If VexW1 is set, the first operand is the source and
6279 the second operand is encoded in the immediate operand. */
6280 if (i.tm.opcode_modifier.vexw == VEXW1)
6281 {
6282 source = 0;
6283 reg_slot = 1;
6284 }
6285 else
6286 {
6287 source = 1;
6288 reg_slot = 0;
6289 }
6290
6291 /* FMA swaps REG and NDS. */
6292 if (i.tm.cpu_flags.bitfield.cpufma)
6293 {
6294 unsigned int tmp;
6295 tmp = reg_slot;
6296 reg_slot = nds;
6297 nds = tmp;
6298 }
6299
6300 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6301 &regxmm)
6302 || operand_type_equal (&i.tm.operand_types[reg_slot],
6303 &regymm)
6304 || operand_type_equal (&i.tm.operand_types[reg_slot],
6305 &regzmm));
6306 exp->X_op = O_constant;
6307 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6308 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6309 }
6310 else
6311 {
6312 unsigned int imm_slot;
6313
6314 if (i.tm.opcode_modifier.vexw == VEXW0)
6315 {
6316 /* If VexW0 is set, the third operand is the source and
6317 the second operand is encoded in the immediate
6318 operand. */
6319 source = 2;
6320 reg_slot = 1;
6321 }
6322 else
6323 {
6324 /* VexW1 is set, the second operand is the source and
6325 the third operand is encoded in the immediate
6326 operand. */
6327 source = 1;
6328 reg_slot = 2;
6329 }
6330
6331 if (i.tm.opcode_modifier.immext)
6332 {
6333 /* When ImmExt is set, the immediate byte is the last
6334 operand. */
6335 imm_slot = i.operands - 1;
6336 source--;
6337 reg_slot--;
6338 }
6339 else
6340 {
6341 imm_slot = 0;
6342
6343 /* Turn on Imm8 so that output_imm will generate it. */
6344 i.types[imm_slot].bitfield.imm8 = 1;
6345 }
6346
6347 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6348 &regxmm)
6349 || operand_type_equal (&i.tm.operand_types[reg_slot],
6350 &regymm)
6351 || operand_type_equal (&i.tm.operand_types[reg_slot],
6352 &regzmm));
6353 i.op[imm_slot].imms->X_add_number
6354 |= register_number (i.op[reg_slot].regs) << 4;
6355 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6356 }
6357
6358 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6359 || operand_type_equal (&i.tm.operand_types[nds],
6360 &regymm)
6361 || operand_type_equal (&i.tm.operand_types[nds],
6362 &regzmm));
6363 i.vex.register_specifier = i.op[nds].regs;
6364 }
6365 else
6366 source = dest = 0;
6367
6368 /* i.reg_operands MUST be the number of real register operands;
6369 implicit registers do not count. If there are 3 register
6370 operands, it must be a instruction with VexNDS. For a
6371 instruction with VexNDD, the destination register is encoded
6372 in VEX prefix. If there are 4 register operands, it must be
6373 a instruction with VEX prefix and 3 sources. */
6374 if (i.mem_operands == 0
6375 && ((i.reg_operands == 2
6376 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6377 || (i.reg_operands == 3
6378 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6379 || (i.reg_operands == 4 && vex_3_sources)))
6380 {
6381 switch (i.operands)
6382 {
6383 case 2:
6384 source = 0;
6385 break;
6386 case 3:
6387 /* When there are 3 operands, one of them may be immediate,
6388 which may be the first or the last operand. Otherwise,
6389 the first operand must be shift count register (cl) or it
6390 is an instruction with VexNDS. */
6391 gas_assert (i.imm_operands == 1
6392 || (i.imm_operands == 0
6393 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6394 || i.types[0].bitfield.shiftcount)));
6395 if (operand_type_check (i.types[0], imm)
6396 || i.types[0].bitfield.shiftcount)
6397 source = 1;
6398 else
6399 source = 0;
6400 break;
6401 case 4:
6402 /* When there are 4 operands, the first two must be 8bit
6403 immediate operands. The source operand will be the 3rd
6404 one.
6405
6406 For instructions with VexNDS, if the first operand
6407 an imm8, the source operand is the 2nd one. If the last
6408 operand is imm8, the source operand is the first one. */
6409 gas_assert ((i.imm_operands == 2
6410 && i.types[0].bitfield.imm8
6411 && i.types[1].bitfield.imm8)
6412 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6413 && i.imm_operands == 1
6414 && (i.types[0].bitfield.imm8
6415 || i.types[i.operands - 1].bitfield.imm8
6416 || i.rounding)));
6417 if (i.imm_operands == 2)
6418 source = 2;
6419 else
6420 {
6421 if (i.types[0].bitfield.imm8)
6422 source = 1;
6423 else
6424 source = 0;
6425 }
6426 break;
6427 case 5:
6428 if (i.tm.opcode_modifier.evex)
6429 {
6430 /* For EVEX instructions, when there are 5 operands, the
6431 first one must be immediate operand. If the second one
6432 is immediate operand, the source operand is the 3th
6433 one. If the last one is immediate operand, the source
6434 operand is the 2nd one. */
6435 gas_assert (i.imm_operands == 2
6436 && i.tm.opcode_modifier.sae
6437 && operand_type_check (i.types[0], imm));
6438 if (operand_type_check (i.types[1], imm))
6439 source = 2;
6440 else if (operand_type_check (i.types[4], imm))
6441 source = 1;
6442 else
6443 abort ();
6444 }
6445 break;
6446 default:
6447 abort ();
6448 }
6449
6450 if (!vex_3_sources)
6451 {
6452 dest = source + 1;
6453
6454 /* RC/SAE operand could be between DEST and SRC. That happens
6455 when one operand is GPR and the other one is XMM/YMM/ZMM
6456 register. */
6457 if (i.rounding && i.rounding->operand == (int) dest)
6458 dest++;
6459
6460 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6461 {
6462 /* For instructions with VexNDS, the register-only source
6463 operand must be 32/64bit integer, XMM, YMM or ZMM
6464 register. It is encoded in VEX prefix. We need to
6465 clear RegMem bit before calling operand_type_equal. */
6466
6467 i386_operand_type op;
6468 unsigned int vvvv;
6469
6470 /* Check register-only source operand when two source
6471 operands are swapped. */
6472 if (!i.tm.operand_types[source].bitfield.baseindex
6473 && i.tm.operand_types[dest].bitfield.baseindex)
6474 {
6475 vvvv = source;
6476 source = dest;
6477 }
6478 else
6479 vvvv = dest;
6480
6481 op = i.tm.operand_types[vvvv];
6482 op.bitfield.regmem = 0;
6483 if ((dest + 1) >= i.operands
6484 || (!op.bitfield.reg32
6485 && op.bitfield.reg64
6486 && !operand_type_equal (&op, &regxmm)
6487 && !operand_type_equal (&op, &regymm)
6488 && !operand_type_equal (&op, &regzmm)
6489 && !operand_type_equal (&op, &regmask)))
6490 abort ();
6491 i.vex.register_specifier = i.op[vvvv].regs;
6492 dest++;
6493 }
6494 }
6495
6496 i.rm.mode = 3;
6497 /* One of the register operands will be encoded in the i.tm.reg
6498 field, the other in the combined i.tm.mode and i.tm.regmem
6499 fields. If no form of this instruction supports a memory
6500 destination operand, then we assume the source operand may
6501 sometimes be a memory operand and so we need to store the
6502 destination in the i.rm.reg field. */
6503 if (!i.tm.operand_types[dest].bitfield.regmem
6504 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6505 {
6506 i.rm.reg = i.op[dest].regs->reg_num;
6507 i.rm.regmem = i.op[source].regs->reg_num;
6508 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6509 i.rex |= REX_R;
6510 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6511 i.vrex |= REX_R;
6512 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6513 i.rex |= REX_B;
6514 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6515 i.vrex |= REX_B;
6516 }
6517 else
6518 {
6519 i.rm.reg = i.op[source].regs->reg_num;
6520 i.rm.regmem = i.op[dest].regs->reg_num;
6521 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6522 i.rex |= REX_B;
6523 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6524 i.vrex |= REX_B;
6525 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6526 i.rex |= REX_R;
6527 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6528 i.vrex |= REX_R;
6529 }
6530 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6531 {
6532 if (!i.types[0].bitfield.control
6533 && !i.types[1].bitfield.control)
6534 abort ();
6535 i.rex &= ~(REX_R | REX_B);
6536 add_prefix (LOCK_PREFIX_OPCODE);
6537 }
6538 }
6539 else
6540 { /* If it's not 2 reg operands... */
6541 unsigned int mem;
6542
6543 if (i.mem_operands)
6544 {
6545 unsigned int fake_zero_displacement = 0;
6546 unsigned int op;
6547
6548 for (op = 0; op < i.operands; op++)
6549 if (operand_type_check (i.types[op], anymem))
6550 break;
6551 gas_assert (op < i.operands);
6552
6553 if (i.tm.opcode_modifier.vecsib)
6554 {
6555 if (i.index_reg->reg_num == RegEiz
6556 || i.index_reg->reg_num == RegRiz)
6557 abort ();
6558
6559 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6560 if (!i.base_reg)
6561 {
6562 i.sib.base = NO_BASE_REGISTER;
6563 i.sib.scale = i.log2_scale_factor;
6564 /* No Vec_Disp8 if there is no base. */
6565 i.types[op].bitfield.vec_disp8 = 0;
6566 i.types[op].bitfield.disp8 = 0;
6567 i.types[op].bitfield.disp16 = 0;
6568 i.types[op].bitfield.disp64 = 0;
6569 if (flag_code != CODE_64BIT)
6570 {
6571 /* Must be 32 bit */
6572 i.types[op].bitfield.disp32 = 1;
6573 i.types[op].bitfield.disp32s = 0;
6574 }
6575 else
6576 {
6577 i.types[op].bitfield.disp32 = 0;
6578 i.types[op].bitfield.disp32s = 1;
6579 }
6580 }
6581 i.sib.index = i.index_reg->reg_num;
6582 if ((i.index_reg->reg_flags & RegRex) != 0)
6583 i.rex |= REX_X;
6584 if ((i.index_reg->reg_flags & RegVRex) != 0)
6585 i.vrex |= REX_X;
6586 }
6587
6588 default_seg = &ds;
6589
6590 if (i.base_reg == 0)
6591 {
6592 i.rm.mode = 0;
6593 if (!i.disp_operands)
6594 {
6595 fake_zero_displacement = 1;
6596 /* Instructions with VSIB byte need 32bit displacement
6597 if there is no base register. */
6598 if (i.tm.opcode_modifier.vecsib)
6599 i.types[op].bitfield.disp32 = 1;
6600 }
6601 if (i.index_reg == 0)
6602 {
6603 gas_assert (!i.tm.opcode_modifier.vecsib);
6604 /* Operand is just <disp> */
6605 if (flag_code == CODE_64BIT)
6606 {
6607 /* 64bit mode overwrites the 32bit absolute
6608 addressing by RIP relative addressing and
6609 absolute addressing is encoded by one of the
6610 redundant SIB forms. */
6611 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6612 i.sib.base = NO_BASE_REGISTER;
6613 i.sib.index = NO_INDEX_REGISTER;
6614 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6615 ? disp32s : disp32);
6616 }
6617 else if ((flag_code == CODE_16BIT)
6618 ^ (i.prefix[ADDR_PREFIX] != 0))
6619 {
6620 i.rm.regmem = NO_BASE_REGISTER_16;
6621 i.types[op] = disp16;
6622 }
6623 else
6624 {
6625 i.rm.regmem = NO_BASE_REGISTER;
6626 i.types[op] = disp32;
6627 }
6628 }
6629 else if (!i.tm.opcode_modifier.vecsib)
6630 {
6631 /* !i.base_reg && i.index_reg */
6632 if (i.index_reg->reg_num == RegEiz
6633 || i.index_reg->reg_num == RegRiz)
6634 i.sib.index = NO_INDEX_REGISTER;
6635 else
6636 i.sib.index = i.index_reg->reg_num;
6637 i.sib.base = NO_BASE_REGISTER;
6638 i.sib.scale = i.log2_scale_factor;
6639 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6640 /* No Vec_Disp8 if there is no base. */
6641 i.types[op].bitfield.vec_disp8 = 0;
6642 i.types[op].bitfield.disp8 = 0;
6643 i.types[op].bitfield.disp16 = 0;
6644 i.types[op].bitfield.disp64 = 0;
6645 if (flag_code != CODE_64BIT)
6646 {
6647 /* Must be 32 bit */
6648 i.types[op].bitfield.disp32 = 1;
6649 i.types[op].bitfield.disp32s = 0;
6650 }
6651 else
6652 {
6653 i.types[op].bitfield.disp32 = 0;
6654 i.types[op].bitfield.disp32s = 1;
6655 }
6656 if ((i.index_reg->reg_flags & RegRex) != 0)
6657 i.rex |= REX_X;
6658 }
6659 }
6660 /* RIP addressing for 64bit mode. */
6661 else if (i.base_reg->reg_num == RegRip ||
6662 i.base_reg->reg_num == RegEip)
6663 {
6664 gas_assert (!i.tm.opcode_modifier.vecsib);
6665 i.rm.regmem = NO_BASE_REGISTER;
6666 i.types[op].bitfield.disp8 = 0;
6667 i.types[op].bitfield.disp16 = 0;
6668 i.types[op].bitfield.disp32 = 0;
6669 i.types[op].bitfield.disp32s = 1;
6670 i.types[op].bitfield.disp64 = 0;
6671 i.types[op].bitfield.vec_disp8 = 0;
6672 i.flags[op] |= Operand_PCrel;
6673 if (! i.disp_operands)
6674 fake_zero_displacement = 1;
6675 }
6676 else if (i.base_reg->reg_type.bitfield.reg16)
6677 {
6678 gas_assert (!i.tm.opcode_modifier.vecsib);
6679 switch (i.base_reg->reg_num)
6680 {
6681 case 3: /* (%bx) */
6682 if (i.index_reg == 0)
6683 i.rm.regmem = 7;
6684 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6685 i.rm.regmem = i.index_reg->reg_num - 6;
6686 break;
6687 case 5: /* (%bp) */
6688 default_seg = &ss;
6689 if (i.index_reg == 0)
6690 {
6691 i.rm.regmem = 6;
6692 if (operand_type_check (i.types[op], disp) == 0)
6693 {
6694 /* fake (%bp) into 0(%bp) */
6695 if (i.tm.operand_types[op].bitfield.vec_disp8)
6696 i.types[op].bitfield.vec_disp8 = 1;
6697 else
6698 i.types[op].bitfield.disp8 = 1;
6699 fake_zero_displacement = 1;
6700 }
6701 }
6702 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6703 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6704 break;
6705 default: /* (%si) -> 4 or (%di) -> 5 */
6706 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6707 }
6708 i.rm.mode = mode_from_disp_size (i.types[op]);
6709 }
6710 else /* i.base_reg and 32/64 bit mode */
6711 {
6712 if (flag_code == CODE_64BIT
6713 && operand_type_check (i.types[op], disp))
6714 {
6715 i386_operand_type temp;
6716 operand_type_set (&temp, 0);
6717 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6718 temp.bitfield.vec_disp8
6719 = i.types[op].bitfield.vec_disp8;
6720 i.types[op] = temp;
6721 if (i.prefix[ADDR_PREFIX] == 0)
6722 i.types[op].bitfield.disp32s = 1;
6723 else
6724 i.types[op].bitfield.disp32 = 1;
6725 }
6726
6727 if (!i.tm.opcode_modifier.vecsib)
6728 i.rm.regmem = i.base_reg->reg_num;
6729 if ((i.base_reg->reg_flags & RegRex) != 0)
6730 i.rex |= REX_B;
6731 i.sib.base = i.base_reg->reg_num;
6732 /* x86-64 ignores REX prefix bit here to avoid decoder
6733 complications. */
6734 if (!(i.base_reg->reg_flags & RegRex)
6735 && (i.base_reg->reg_num == EBP_REG_NUM
6736 || i.base_reg->reg_num == ESP_REG_NUM))
6737 default_seg = &ss;
6738 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6739 {
6740 fake_zero_displacement = 1;
6741 if (i.tm.operand_types [op].bitfield.vec_disp8)
6742 i.types[op].bitfield.vec_disp8 = 1;
6743 else
6744 i.types[op].bitfield.disp8 = 1;
6745 }
6746 i.sib.scale = i.log2_scale_factor;
6747 if (i.index_reg == 0)
6748 {
6749 gas_assert (!i.tm.opcode_modifier.vecsib);
6750 /* <disp>(%esp) becomes two byte modrm with no index
6751 register. We've already stored the code for esp
6752 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6753 Any base register besides %esp will not use the
6754 extra modrm byte. */
6755 i.sib.index = NO_INDEX_REGISTER;
6756 }
6757 else if (!i.tm.opcode_modifier.vecsib)
6758 {
6759 if (i.index_reg->reg_num == RegEiz
6760 || i.index_reg->reg_num == RegRiz)
6761 i.sib.index = NO_INDEX_REGISTER;
6762 else
6763 i.sib.index = i.index_reg->reg_num;
6764 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6765 if ((i.index_reg->reg_flags & RegRex) != 0)
6766 i.rex |= REX_X;
6767 }
6768
6769 if (i.disp_operands
6770 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6771 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6772 i.rm.mode = 0;
6773 else
6774 {
6775 if (!fake_zero_displacement
6776 && !i.disp_operands
6777 && i.disp_encoding)
6778 {
6779 fake_zero_displacement = 1;
6780 if (i.disp_encoding == disp_encoding_8bit)
6781 i.types[op].bitfield.disp8 = 1;
6782 else
6783 i.types[op].bitfield.disp32 = 1;
6784 }
6785 i.rm.mode = mode_from_disp_size (i.types[op]);
6786 }
6787 }
6788
6789 if (fake_zero_displacement)
6790 {
6791 /* Fakes a zero displacement assuming that i.types[op]
6792 holds the correct displacement size. */
6793 expressionS *exp;
6794
6795 gas_assert (i.op[op].disps == 0);
6796 exp = &disp_expressions[i.disp_operands++];
6797 i.op[op].disps = exp;
6798 exp->X_op = O_constant;
6799 exp->X_add_number = 0;
6800 exp->X_add_symbol = (symbolS *) 0;
6801 exp->X_op_symbol = (symbolS *) 0;
6802 }
6803
6804 mem = op;
6805 }
6806 else
6807 mem = ~0;
6808
6809 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6810 {
6811 if (operand_type_check (i.types[0], imm))
6812 i.vex.register_specifier = NULL;
6813 else
6814 {
6815 /* VEX.vvvv encodes one of the sources when the first
6816 operand is not an immediate. */
6817 if (i.tm.opcode_modifier.vexw == VEXW0)
6818 i.vex.register_specifier = i.op[0].regs;
6819 else
6820 i.vex.register_specifier = i.op[1].regs;
6821 }
6822
6823 /* Destination is a XMM register encoded in the ModRM.reg
6824 and VEX.R bit. */
6825 i.rm.reg = i.op[2].regs->reg_num;
6826 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6827 i.rex |= REX_R;
6828
6829 /* ModRM.rm and VEX.B encodes the other source. */
6830 if (!i.mem_operands)
6831 {
6832 i.rm.mode = 3;
6833
6834 if (i.tm.opcode_modifier.vexw == VEXW0)
6835 i.rm.regmem = i.op[1].regs->reg_num;
6836 else
6837 i.rm.regmem = i.op[0].regs->reg_num;
6838
6839 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6840 i.rex |= REX_B;
6841 }
6842 }
6843 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6844 {
6845 i.vex.register_specifier = i.op[2].regs;
6846 if (!i.mem_operands)
6847 {
6848 i.rm.mode = 3;
6849 i.rm.regmem = i.op[1].regs->reg_num;
6850 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6851 i.rex |= REX_B;
6852 }
6853 }
6854 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6855 (if any) based on i.tm.extension_opcode. Again, we must be
6856 careful to make sure that segment/control/debug/test/MMX
6857 registers are coded into the i.rm.reg field. */
6858 else if (i.reg_operands)
6859 {
6860 unsigned int op;
6861 unsigned int vex_reg = ~0;
6862
6863 for (op = 0; op < i.operands; op++)
6864 if (i.types[op].bitfield.reg8
6865 || i.types[op].bitfield.reg16
6866 || i.types[op].bitfield.reg32
6867 || i.types[op].bitfield.reg64
6868 || i.types[op].bitfield.regmmx
6869 || i.types[op].bitfield.regxmm
6870 || i.types[op].bitfield.regymm
6871 || i.types[op].bitfield.regbnd
6872 || i.types[op].bitfield.regzmm
6873 || i.types[op].bitfield.regmask
6874 || i.types[op].bitfield.sreg2
6875 || i.types[op].bitfield.sreg3
6876 || i.types[op].bitfield.control
6877 || i.types[op].bitfield.debug
6878 || i.types[op].bitfield.test)
6879 break;
6880
6881 if (vex_3_sources)
6882 op = dest;
6883 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6884 {
6885 /* For instructions with VexNDS, the register-only
6886 source operand is encoded in VEX prefix. */
6887 gas_assert (mem != (unsigned int) ~0);
6888
6889 if (op > mem)
6890 {
6891 vex_reg = op++;
6892 gas_assert (op < i.operands);
6893 }
6894 else
6895 {
6896 /* Check register-only source operand when two source
6897 operands are swapped. */
6898 if (!i.tm.operand_types[op].bitfield.baseindex
6899 && i.tm.operand_types[op + 1].bitfield.baseindex)
6900 {
6901 vex_reg = op;
6902 op += 2;
6903 gas_assert (mem == (vex_reg + 1)
6904 && op < i.operands);
6905 }
6906 else
6907 {
6908 vex_reg = op + 1;
6909 gas_assert (vex_reg < i.operands);
6910 }
6911 }
6912 }
6913 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6914 {
6915 /* For instructions with VexNDD, the register destination
6916 is encoded in VEX prefix. */
6917 if (i.mem_operands == 0)
6918 {
6919 /* There is no memory operand. */
6920 gas_assert ((op + 2) == i.operands);
6921 vex_reg = op + 1;
6922 }
6923 else
6924 {
6925 /* There are only 2 operands. */
6926 gas_assert (op < 2 && i.operands == 2);
6927 vex_reg = 1;
6928 }
6929 }
6930 else
6931 gas_assert (op < i.operands);
6932
6933 if (vex_reg != (unsigned int) ~0)
6934 {
6935 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6936
6937 if (type->bitfield.reg32 != 1
6938 && type->bitfield.reg64 != 1
6939 && !operand_type_equal (type, &regxmm)
6940 && !operand_type_equal (type, &regymm)
6941 && !operand_type_equal (type, &regzmm)
6942 && !operand_type_equal (type, &regmask))
6943 abort ();
6944
6945 i.vex.register_specifier = i.op[vex_reg].regs;
6946 }
6947
6948 /* Don't set OP operand twice. */
6949 if (vex_reg != op)
6950 {
6951 /* If there is an extension opcode to put here, the
6952 register number must be put into the regmem field. */
6953 if (i.tm.extension_opcode != None)
6954 {
6955 i.rm.regmem = i.op[op].regs->reg_num;
6956 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6957 i.rex |= REX_B;
6958 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6959 i.vrex |= REX_B;
6960 }
6961 else
6962 {
6963 i.rm.reg = i.op[op].regs->reg_num;
6964 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6965 i.rex |= REX_R;
6966 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6967 i.vrex |= REX_R;
6968 }
6969 }
6970
6971 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6972 must set it to 3 to indicate this is a register operand
6973 in the regmem field. */
6974 if (!i.mem_operands)
6975 i.rm.mode = 3;
6976 }
6977
6978 /* Fill in i.rm.reg field with extension opcode (if any). */
6979 if (i.tm.extension_opcode != None)
6980 i.rm.reg = i.tm.extension_opcode;
6981 }
6982 return default_seg;
6983 }
6984
6985 static void
6986 output_branch (void)
6987 {
6988 char *p;
6989 int size;
6990 int code16;
6991 int prefix;
6992 relax_substateT subtype;
6993 symbolS *sym;
6994 offsetT off;
6995
6996 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6997 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6998
6999 prefix = 0;
7000 if (i.prefix[DATA_PREFIX] != 0)
7001 {
7002 prefix = 1;
7003 i.prefixes -= 1;
7004 code16 ^= CODE16;
7005 }
7006 /* Pentium4 branch hints. */
7007 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7008 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7009 {
7010 prefix++;
7011 i.prefixes--;
7012 }
7013 if (i.prefix[REX_PREFIX] != 0)
7014 {
7015 prefix++;
7016 i.prefixes--;
7017 }
7018
7019 /* BND prefixed jump. */
7020 if (i.prefix[BND_PREFIX] != 0)
7021 {
7022 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7023 i.prefixes -= 1;
7024 }
7025
7026 if (i.prefixes != 0 && !intel_syntax)
7027 as_warn (_("skipping prefixes on this instruction"));
7028
7029 /* It's always a symbol; End frag & setup for relax.
7030 Make sure there is enough room in this frag for the largest
7031 instruction we may generate in md_convert_frag. This is 2
7032 bytes for the opcode and room for the prefix and largest
7033 displacement. */
7034 frag_grow (prefix + 2 + 4);
7035 /* Prefix and 1 opcode byte go in fr_fix. */
7036 p = frag_more (prefix + 1);
7037 if (i.prefix[DATA_PREFIX] != 0)
7038 *p++ = DATA_PREFIX_OPCODE;
7039 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7040 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7041 *p++ = i.prefix[SEG_PREFIX];
7042 if (i.prefix[REX_PREFIX] != 0)
7043 *p++ = i.prefix[REX_PREFIX];
7044 *p = i.tm.base_opcode;
7045
7046 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7047 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7048 else if (cpu_arch_flags.bitfield.cpui386)
7049 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7050 else
7051 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7052 subtype |= code16;
7053
7054 sym = i.op[0].disps->X_add_symbol;
7055 off = i.op[0].disps->X_add_number;
7056
7057 if (i.op[0].disps->X_op != O_constant
7058 && i.op[0].disps->X_op != O_symbol)
7059 {
7060 /* Handle complex expressions. */
7061 sym = make_expr_symbol (i.op[0].disps);
7062 off = 0;
7063 }
7064
7065 /* 1 possible extra opcode + 4 byte displacement go in var part.
7066 Pass reloc in fr_var. */
7067 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7068 }
7069
7070 static void
7071 output_jump (void)
7072 {
7073 char *p;
7074 int size;
7075 fixS *fixP;
7076
7077 if (i.tm.opcode_modifier.jumpbyte)
7078 {
7079 /* This is a loop or jecxz type instruction. */
7080 size = 1;
7081 if (i.prefix[ADDR_PREFIX] != 0)
7082 {
7083 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7084 i.prefixes -= 1;
7085 }
7086 /* Pentium4 branch hints. */
7087 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7088 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7089 {
7090 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7091 i.prefixes--;
7092 }
7093 }
7094 else
7095 {
7096 int code16;
7097
7098 code16 = 0;
7099 if (flag_code == CODE_16BIT)
7100 code16 = CODE16;
7101
7102 if (i.prefix[DATA_PREFIX] != 0)
7103 {
7104 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7105 i.prefixes -= 1;
7106 code16 ^= CODE16;
7107 }
7108
7109 size = 4;
7110 if (code16)
7111 size = 2;
7112 }
7113
7114 if (i.prefix[REX_PREFIX] != 0)
7115 {
7116 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7117 i.prefixes -= 1;
7118 }
7119
7120 /* BND prefixed jump. */
7121 if (i.prefix[BND_PREFIX] != 0)
7122 {
7123 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7124 i.prefixes -= 1;
7125 }
7126
7127 if (i.prefixes != 0 && !intel_syntax)
7128 as_warn (_("skipping prefixes on this instruction"));
7129
7130 p = frag_more (i.tm.opcode_length + size);
7131 switch (i.tm.opcode_length)
7132 {
7133 case 2:
7134 *p++ = i.tm.base_opcode >> 8;
7135 /* Fall through. */
7136 case 1:
7137 *p++ = i.tm.base_opcode;
7138 break;
7139 default:
7140 abort ();
7141 }
7142
7143 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7144 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
7145
7146 /* All jumps handled here are signed, but don't use a signed limit
7147 check for 32 and 16 bit jumps as we want to allow wrap around at
7148 4G and 64k respectively. */
7149 if (size == 1)
7150 fixP->fx_signed = 1;
7151 }
7152
7153 static void
7154 output_interseg_jump (void)
7155 {
7156 char *p;
7157 int size;
7158 int prefix;
7159 int code16;
7160
7161 code16 = 0;
7162 if (flag_code == CODE_16BIT)
7163 code16 = CODE16;
7164
7165 prefix = 0;
7166 if (i.prefix[DATA_PREFIX] != 0)
7167 {
7168 prefix = 1;
7169 i.prefixes -= 1;
7170 code16 ^= CODE16;
7171 }
7172 if (i.prefix[REX_PREFIX] != 0)
7173 {
7174 prefix++;
7175 i.prefixes -= 1;
7176 }
7177
7178 size = 4;
7179 if (code16)
7180 size = 2;
7181
7182 if (i.prefixes != 0 && !intel_syntax)
7183 as_warn (_("skipping prefixes on this instruction"));
7184
7185 /* 1 opcode; 2 segment; offset */
7186 p = frag_more (prefix + 1 + 2 + size);
7187
7188 if (i.prefix[DATA_PREFIX] != 0)
7189 *p++ = DATA_PREFIX_OPCODE;
7190
7191 if (i.prefix[REX_PREFIX] != 0)
7192 *p++ = i.prefix[REX_PREFIX];
7193
7194 *p++ = i.tm.base_opcode;
7195 if (i.op[1].imms->X_op == O_constant)
7196 {
7197 offsetT n = i.op[1].imms->X_add_number;
7198
7199 if (size == 2
7200 && !fits_in_unsigned_word (n)
7201 && !fits_in_signed_word (n))
7202 {
7203 as_bad (_("16-bit jump out of range"));
7204 return;
7205 }
7206 md_number_to_chars (p, n, size);
7207 }
7208 else
7209 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7210 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7211 if (i.op[0].imms->X_op != O_constant)
7212 as_bad (_("can't handle non absolute segment in `%s'"),
7213 i.tm.name);
7214 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7215 }
7216
7217 static void
7218 output_insn (void)
7219 {
7220 fragS *insn_start_frag;
7221 offsetT insn_start_off;
7222
7223 /* Tie dwarf2 debug info to the address at the start of the insn.
7224 We can't do this after the insn has been output as the current
7225 frag may have been closed off. eg. by frag_var. */
7226 dwarf2_emit_insn (0);
7227
7228 insn_start_frag = frag_now;
7229 insn_start_off = frag_now_fix ();
7230
7231 /* Output jumps. */
7232 if (i.tm.opcode_modifier.jump)
7233 output_branch ();
7234 else if (i.tm.opcode_modifier.jumpbyte
7235 || i.tm.opcode_modifier.jumpdword)
7236 output_jump ();
7237 else if (i.tm.opcode_modifier.jumpintersegment)
7238 output_interseg_jump ();
7239 else
7240 {
7241 /* Output normal instructions here. */
7242 char *p;
7243 unsigned char *q;
7244 unsigned int j;
7245 unsigned int prefix;
7246
7247 if (avoid_fence
7248 && i.tm.base_opcode == 0xfae
7249 && i.operands == 1
7250 && i.imm_operands == 1
7251 && (i.op[0].imms->X_add_number == 0xe8
7252 || i.op[0].imms->X_add_number == 0xf0
7253 || i.op[0].imms->X_add_number == 0xf8))
7254 {
7255 /* Encode lfence, mfence, and sfence as
7256 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7257 offsetT val = 0x240483f0ULL;
7258 p = frag_more (5);
7259 md_number_to_chars (p, val, 5);
7260 return;
7261 }
7262
7263 /* Some processors fail on LOCK prefix. This options makes
7264 assembler ignore LOCK prefix and serves as a workaround. */
7265 if (omit_lock_prefix)
7266 {
7267 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7268 return;
7269 i.prefix[LOCK_PREFIX] = 0;
7270 }
7271
7272 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7273 don't need the explicit prefix. */
7274 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7275 {
7276 switch (i.tm.opcode_length)
7277 {
7278 case 3:
7279 if (i.tm.base_opcode & 0xff000000)
7280 {
7281 prefix = (i.tm.base_opcode >> 24) & 0xff;
7282 goto check_prefix;
7283 }
7284 break;
7285 case 2:
7286 if ((i.tm.base_opcode & 0xff0000) != 0)
7287 {
7288 prefix = (i.tm.base_opcode >> 16) & 0xff;
7289 if (i.tm.cpu_flags.bitfield.cpupadlock)
7290 {
7291 check_prefix:
7292 if (prefix != REPE_PREFIX_OPCODE
7293 || (i.prefix[REP_PREFIX]
7294 != REPE_PREFIX_OPCODE))
7295 add_prefix (prefix);
7296 }
7297 else
7298 add_prefix (prefix);
7299 }
7300 break;
7301 case 1:
7302 break;
7303 default:
7304 abort ();
7305 }
7306
7307 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7308 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7309 R_X86_64_GOTTPOFF relocation so that linker can safely
7310 perform IE->LE optimization. */
7311 if (x86_elf_abi == X86_64_X32_ABI
7312 && i.operands == 2
7313 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7314 && i.prefix[REX_PREFIX] == 0)
7315 add_prefix (REX_OPCODE);
7316 #endif
7317
7318 /* The prefix bytes. */
7319 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7320 if (*q)
7321 FRAG_APPEND_1_CHAR (*q);
7322 }
7323 else
7324 {
7325 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7326 if (*q)
7327 switch (j)
7328 {
7329 case REX_PREFIX:
7330 /* REX byte is encoded in VEX prefix. */
7331 break;
7332 case SEG_PREFIX:
7333 case ADDR_PREFIX:
7334 FRAG_APPEND_1_CHAR (*q);
7335 break;
7336 default:
7337 /* There should be no other prefixes for instructions
7338 with VEX prefix. */
7339 abort ();
7340 }
7341
7342 /* For EVEX instructions i.vrex should become 0 after
7343 build_evex_prefix. For VEX instructions upper 16 registers
7344 aren't available, so VREX should be 0. */
7345 if (i.vrex)
7346 abort ();
7347 /* Now the VEX prefix. */
7348 p = frag_more (i.vex.length);
7349 for (j = 0; j < i.vex.length; j++)
7350 p[j] = i.vex.bytes[j];
7351 }
7352
7353 /* Now the opcode; be careful about word order here! */
7354 if (i.tm.opcode_length == 1)
7355 {
7356 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7357 }
7358 else
7359 {
7360 switch (i.tm.opcode_length)
7361 {
7362 case 4:
7363 p = frag_more (4);
7364 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7365 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7366 break;
7367 case 3:
7368 p = frag_more (3);
7369 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7370 break;
7371 case 2:
7372 p = frag_more (2);
7373 break;
7374 default:
7375 abort ();
7376 break;
7377 }
7378
7379 /* Put out high byte first: can't use md_number_to_chars! */
7380 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7381 *p = i.tm.base_opcode & 0xff;
7382 }
7383
7384 /* Now the modrm byte and sib byte (if present). */
7385 if (i.tm.opcode_modifier.modrm)
7386 {
7387 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7388 | i.rm.reg << 3
7389 | i.rm.mode << 6));
7390 /* If i.rm.regmem == ESP (4)
7391 && i.rm.mode != (Register mode)
7392 && not 16 bit
7393 ==> need second modrm byte. */
7394 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7395 && i.rm.mode != 3
7396 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
7397 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7398 | i.sib.index << 3
7399 | i.sib.scale << 6));
7400 }
7401
7402 if (i.disp_operands)
7403 output_disp (insn_start_frag, insn_start_off);
7404
7405 if (i.imm_operands)
7406 output_imm (insn_start_frag, insn_start_off);
7407 }
7408
7409 #ifdef DEBUG386
7410 if (flag_debug)
7411 {
7412 pi ("" /*line*/, &i);
7413 }
7414 #endif /* DEBUG386 */
7415 }
7416
7417 /* Return the size of the displacement operand N. */
7418
7419 static int
7420 disp_size (unsigned int n)
7421 {
7422 int size = 4;
7423
7424 /* Vec_Disp8 has to be 8bit. */
7425 if (i.types[n].bitfield.vec_disp8)
7426 size = 1;
7427 else if (i.types[n].bitfield.disp64)
7428 size = 8;
7429 else if (i.types[n].bitfield.disp8)
7430 size = 1;
7431 else if (i.types[n].bitfield.disp16)
7432 size = 2;
7433 return size;
7434 }
7435
7436 /* Return the size of the immediate operand N. */
7437
7438 static int
7439 imm_size (unsigned int n)
7440 {
7441 int size = 4;
7442 if (i.types[n].bitfield.imm64)
7443 size = 8;
7444 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7445 size = 1;
7446 else if (i.types[n].bitfield.imm16)
7447 size = 2;
7448 return size;
7449 }
7450
7451 static void
7452 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7453 {
7454 char *p;
7455 unsigned int n;
7456
7457 for (n = 0; n < i.operands; n++)
7458 {
7459 if (i.types[n].bitfield.vec_disp8
7460 || operand_type_check (i.types[n], disp))
7461 {
7462 if (i.op[n].disps->X_op == O_constant)
7463 {
7464 int size = disp_size (n);
7465 offsetT val = i.op[n].disps->X_add_number;
7466
7467 if (i.types[n].bitfield.vec_disp8)
7468 val >>= i.memshift;
7469 val = offset_in_range (val, size);
7470 p = frag_more (size);
7471 md_number_to_chars (p, val, size);
7472 }
7473 else
7474 {
7475 enum bfd_reloc_code_real reloc_type;
7476 int size = disp_size (n);
7477 int sign = i.types[n].bitfield.disp32s;
7478 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7479 fixS *fixP;
7480
7481 /* We can't have 8 bit displacement here. */
7482 gas_assert (!i.types[n].bitfield.disp8);
7483
7484 /* The PC relative address is computed relative
7485 to the instruction boundary, so in case immediate
7486 fields follows, we need to adjust the value. */
7487 if (pcrel && i.imm_operands)
7488 {
7489 unsigned int n1;
7490 int sz = 0;
7491
7492 for (n1 = 0; n1 < i.operands; n1++)
7493 if (operand_type_check (i.types[n1], imm))
7494 {
7495 /* Only one immediate is allowed for PC
7496 relative address. */
7497 gas_assert (sz == 0);
7498 sz = imm_size (n1);
7499 i.op[n].disps->X_add_number -= sz;
7500 }
7501 /* We should find the immediate. */
7502 gas_assert (sz != 0);
7503 }
7504
7505 p = frag_more (size);
7506 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7507 if (GOT_symbol
7508 && GOT_symbol == i.op[n].disps->X_add_symbol
7509 && (((reloc_type == BFD_RELOC_32
7510 || reloc_type == BFD_RELOC_X86_64_32S
7511 || (reloc_type == BFD_RELOC_64
7512 && object_64bit))
7513 && (i.op[n].disps->X_op == O_symbol
7514 || (i.op[n].disps->X_op == O_add
7515 && ((symbol_get_value_expression
7516 (i.op[n].disps->X_op_symbol)->X_op)
7517 == O_subtract))))
7518 || reloc_type == BFD_RELOC_32_PCREL))
7519 {
7520 offsetT add;
7521
7522 if (insn_start_frag == frag_now)
7523 add = (p - frag_now->fr_literal) - insn_start_off;
7524 else
7525 {
7526 fragS *fr;
7527
7528 add = insn_start_frag->fr_fix - insn_start_off;
7529 for (fr = insn_start_frag->fr_next;
7530 fr && fr != frag_now; fr = fr->fr_next)
7531 add += fr->fr_fix;
7532 add += p - frag_now->fr_literal;
7533 }
7534
7535 if (!object_64bit)
7536 {
7537 reloc_type = BFD_RELOC_386_GOTPC;
7538 i.op[n].imms->X_add_number += add;
7539 }
7540 else if (reloc_type == BFD_RELOC_64)
7541 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7542 else
7543 /* Don't do the adjustment for x86-64, as there
7544 the pcrel addressing is relative to the _next_
7545 insn, and that is taken care of in other code. */
7546 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7547 }
7548 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7549 size, i.op[n].disps, pcrel,
7550 reloc_type);
7551 /* Check for "call/jmp *mem", "mov mem, %reg",
7552 "test %reg, mem" and "binop mem, %reg" where binop
7553 is one of adc, add, and, cmp, or, sbb, sub, xor
7554 instructions. Always generate R_386_GOT32X for
7555 "sym*GOT" operand in 32-bit mode. */
7556 if ((generate_relax_relocations
7557 || (!object_64bit
7558 && i.rm.mode == 0
7559 && i.rm.regmem == 5))
7560 && (i.rm.mode == 2
7561 || (i.rm.mode == 0 && i.rm.regmem == 5))
7562 && ((i.operands == 1
7563 && i.tm.base_opcode == 0xff
7564 && (i.rm.reg == 2 || i.rm.reg == 4))
7565 || (i.operands == 2
7566 && (i.tm.base_opcode == 0x8b
7567 || i.tm.base_opcode == 0x85
7568 || (i.tm.base_opcode & 0xc7) == 0x03))))
7569 {
7570 if (object_64bit)
7571 {
7572 fixP->fx_tcbit = i.rex != 0;
7573 if (i.base_reg
7574 && (i.base_reg->reg_num == RegRip
7575 || i.base_reg->reg_num == RegEip))
7576 fixP->fx_tcbit2 = 1;
7577 }
7578 else
7579 fixP->fx_tcbit2 = 1;
7580 }
7581 }
7582 }
7583 }
7584 }
7585
7586 static void
7587 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7588 {
7589 char *p;
7590 unsigned int n;
7591
7592 for (n = 0; n < i.operands; n++)
7593 {
7594 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7595 if (i.rounding && (int) n == i.rounding->operand)
7596 continue;
7597
7598 if (operand_type_check (i.types[n], imm))
7599 {
7600 if (i.op[n].imms->X_op == O_constant)
7601 {
7602 int size = imm_size (n);
7603 offsetT val;
7604
7605 val = offset_in_range (i.op[n].imms->X_add_number,
7606 size);
7607 p = frag_more (size);
7608 md_number_to_chars (p, val, size);
7609 }
7610 else
7611 {
7612 /* Not absolute_section.
7613 Need a 32-bit fixup (don't support 8bit
7614 non-absolute imms). Try to support other
7615 sizes ... */
7616 enum bfd_reloc_code_real reloc_type;
7617 int size = imm_size (n);
7618 int sign;
7619
7620 if (i.types[n].bitfield.imm32s
7621 && (i.suffix == QWORD_MNEM_SUFFIX
7622 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7623 sign = 1;
7624 else
7625 sign = 0;
7626
7627 p = frag_more (size);
7628 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7629
7630 /* This is tough to explain. We end up with this one if we
7631 * have operands that look like
7632 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7633 * obtain the absolute address of the GOT, and it is strongly
7634 * preferable from a performance point of view to avoid using
7635 * a runtime relocation for this. The actual sequence of
7636 * instructions often look something like:
7637 *
7638 * call .L66
7639 * .L66:
7640 * popl %ebx
7641 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7642 *
7643 * The call and pop essentially return the absolute address
7644 * of the label .L66 and store it in %ebx. The linker itself
7645 * will ultimately change the first operand of the addl so
7646 * that %ebx points to the GOT, but to keep things simple, the
7647 * .o file must have this operand set so that it generates not
7648 * the absolute address of .L66, but the absolute address of
7649 * itself. This allows the linker itself simply treat a GOTPC
7650 * relocation as asking for a pcrel offset to the GOT to be
7651 * added in, and the addend of the relocation is stored in the
7652 * operand field for the instruction itself.
7653 *
7654 * Our job here is to fix the operand so that it would add
7655 * the correct offset so that %ebx would point to itself. The
7656 * thing that is tricky is that .-.L66 will point to the
7657 * beginning of the instruction, so we need to further modify
7658 * the operand so that it will point to itself. There are
7659 * other cases where you have something like:
7660 *
7661 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7662 *
7663 * and here no correction would be required. Internally in
7664 * the assembler we treat operands of this form as not being
7665 * pcrel since the '.' is explicitly mentioned, and I wonder
7666 * whether it would simplify matters to do it this way. Who
7667 * knows. In earlier versions of the PIC patches, the
7668 * pcrel_adjust field was used to store the correction, but
7669 * since the expression is not pcrel, I felt it would be
7670 * confusing to do it this way. */
7671
7672 if ((reloc_type == BFD_RELOC_32
7673 || reloc_type == BFD_RELOC_X86_64_32S
7674 || reloc_type == BFD_RELOC_64)
7675 && GOT_symbol
7676 && GOT_symbol == i.op[n].imms->X_add_symbol
7677 && (i.op[n].imms->X_op == O_symbol
7678 || (i.op[n].imms->X_op == O_add
7679 && ((symbol_get_value_expression
7680 (i.op[n].imms->X_op_symbol)->X_op)
7681 == O_subtract))))
7682 {
7683 offsetT add;
7684
7685 if (insn_start_frag == frag_now)
7686 add = (p - frag_now->fr_literal) - insn_start_off;
7687 else
7688 {
7689 fragS *fr;
7690
7691 add = insn_start_frag->fr_fix - insn_start_off;
7692 for (fr = insn_start_frag->fr_next;
7693 fr && fr != frag_now; fr = fr->fr_next)
7694 add += fr->fr_fix;
7695 add += p - frag_now->fr_literal;
7696 }
7697
7698 if (!object_64bit)
7699 reloc_type = BFD_RELOC_386_GOTPC;
7700 else if (size == 4)
7701 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7702 else if (size == 8)
7703 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7704 i.op[n].imms->X_add_number += add;
7705 }
7706 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7707 i.op[n].imms, 0, reloc_type);
7708 }
7709 }
7710 }
7711 }
7712 \f
7713 /* x86_cons_fix_new is called via the expression parsing code when a
7714 reloc is needed. We use this hook to get the correct .got reloc. */
7715 static int cons_sign = -1;
7716
7717 void
7718 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7719 expressionS *exp, bfd_reloc_code_real_type r)
7720 {
7721 r = reloc (len, 0, cons_sign, r);
7722
7723 #ifdef TE_PE
7724 if (exp->X_op == O_secrel)
7725 {
7726 exp->X_op = O_symbol;
7727 r = BFD_RELOC_32_SECREL;
7728 }
7729 #endif
7730
7731 fix_new_exp (frag, off, len, exp, 0, r);
7732 }
7733
7734 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7735 purpose of the `.dc.a' internal pseudo-op. */
7736
7737 int
7738 x86_address_bytes (void)
7739 {
7740 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7741 return 4;
7742 return stdoutput->arch_info->bits_per_address / 8;
7743 }
7744
7745 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7746 || defined (LEX_AT)
7747 # define lex_got(reloc, adjust, types) NULL
7748 #else
7749 /* Parse operands of the form
7750 <symbol>@GOTOFF+<nnn>
7751 and similar .plt or .got references.
7752
7753 If we find one, set up the correct relocation in RELOC and copy the
7754 input string, minus the `@GOTOFF' into a malloc'd buffer for
7755 parsing by the calling routine. Return this buffer, and if ADJUST
7756 is non-null set it to the length of the string we removed from the
7757 input line. Otherwise return NULL. */
7758 static char *
7759 lex_got (enum bfd_reloc_code_real *rel,
7760 int *adjust,
7761 i386_operand_type *types)
7762 {
7763 /* Some of the relocations depend on the size of what field is to
7764 be relocated. But in our callers i386_immediate and i386_displacement
7765 we don't yet know the operand size (this will be set by insn
7766 matching). Hence we record the word32 relocation here,
7767 and adjust the reloc according to the real size in reloc(). */
7768 static const struct {
7769 const char *str;
7770 int len;
7771 const enum bfd_reloc_code_real rel[2];
7772 const i386_operand_type types64;
7773 } gotrel[] = {
7774 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7775 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7776 BFD_RELOC_SIZE32 },
7777 OPERAND_TYPE_IMM32_64 },
7778 #endif
7779 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7780 BFD_RELOC_X86_64_PLTOFF64 },
7781 OPERAND_TYPE_IMM64 },
7782 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7783 BFD_RELOC_X86_64_PLT32 },
7784 OPERAND_TYPE_IMM32_32S_DISP32 },
7785 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7786 BFD_RELOC_X86_64_GOTPLT64 },
7787 OPERAND_TYPE_IMM64_DISP64 },
7788 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7789 BFD_RELOC_X86_64_GOTOFF64 },
7790 OPERAND_TYPE_IMM64_DISP64 },
7791 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7792 BFD_RELOC_X86_64_GOTPCREL },
7793 OPERAND_TYPE_IMM32_32S_DISP32 },
7794 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7795 BFD_RELOC_X86_64_TLSGD },
7796 OPERAND_TYPE_IMM32_32S_DISP32 },
7797 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7798 _dummy_first_bfd_reloc_code_real },
7799 OPERAND_TYPE_NONE },
7800 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7801 BFD_RELOC_X86_64_TLSLD },
7802 OPERAND_TYPE_IMM32_32S_DISP32 },
7803 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7804 BFD_RELOC_X86_64_GOTTPOFF },
7805 OPERAND_TYPE_IMM32_32S_DISP32 },
7806 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7807 BFD_RELOC_X86_64_TPOFF32 },
7808 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7809 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7810 _dummy_first_bfd_reloc_code_real },
7811 OPERAND_TYPE_NONE },
7812 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7813 BFD_RELOC_X86_64_DTPOFF32 },
7814 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7815 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7816 _dummy_first_bfd_reloc_code_real },
7817 OPERAND_TYPE_NONE },
7818 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7819 _dummy_first_bfd_reloc_code_real },
7820 OPERAND_TYPE_NONE },
7821 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7822 BFD_RELOC_X86_64_GOT32 },
7823 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7824 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7825 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7826 OPERAND_TYPE_IMM32_32S_DISP32 },
7827 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7828 BFD_RELOC_X86_64_TLSDESC_CALL },
7829 OPERAND_TYPE_IMM32_32S_DISP32 },
7830 };
7831 char *cp;
7832 unsigned int j;
7833
7834 #if defined (OBJ_MAYBE_ELF)
7835 if (!IS_ELF)
7836 return NULL;
7837 #endif
7838
7839 for (cp = input_line_pointer; *cp != '@'; cp++)
7840 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7841 return NULL;
7842
7843 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7844 {
7845 int len = gotrel[j].len;
7846 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7847 {
7848 if (gotrel[j].rel[object_64bit] != 0)
7849 {
7850 int first, second;
7851 char *tmpbuf, *past_reloc;
7852
7853 *rel = gotrel[j].rel[object_64bit];
7854
7855 if (types)
7856 {
7857 if (flag_code != CODE_64BIT)
7858 {
7859 types->bitfield.imm32 = 1;
7860 types->bitfield.disp32 = 1;
7861 }
7862 else
7863 *types = gotrel[j].types64;
7864 }
7865
7866 if (j != 0 && GOT_symbol == NULL)
7867 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7868
7869 /* The length of the first part of our input line. */
7870 first = cp - input_line_pointer;
7871
7872 /* The second part goes from after the reloc token until
7873 (and including) an end_of_line char or comma. */
7874 past_reloc = cp + 1 + len;
7875 cp = past_reloc;
7876 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7877 ++cp;
7878 second = cp + 1 - past_reloc;
7879
7880 /* Allocate and copy string. The trailing NUL shouldn't
7881 be necessary, but be safe. */
7882 tmpbuf = XNEWVEC (char, first + second + 2);
7883 memcpy (tmpbuf, input_line_pointer, first);
7884 if (second != 0 && *past_reloc != ' ')
7885 /* Replace the relocation token with ' ', so that
7886 errors like foo@GOTOFF1 will be detected. */
7887 tmpbuf[first++] = ' ';
7888 else
7889 /* Increment length by 1 if the relocation token is
7890 removed. */
7891 len++;
7892 if (adjust)
7893 *adjust = len;
7894 memcpy (tmpbuf + first, past_reloc, second);
7895 tmpbuf[first + second] = '\0';
7896 return tmpbuf;
7897 }
7898
7899 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7900 gotrel[j].str, 1 << (5 + object_64bit));
7901 return NULL;
7902 }
7903 }
7904
7905 /* Might be a symbol version string. Don't as_bad here. */
7906 return NULL;
7907 }
7908 #endif
7909
7910 #ifdef TE_PE
7911 #ifdef lex_got
7912 #undef lex_got
7913 #endif
7914 /* Parse operands of the form
7915 <symbol>@SECREL32+<nnn>
7916
7917 If we find one, set up the correct relocation in RELOC and copy the
7918 input string, minus the `@SECREL32' into a malloc'd buffer for
7919 parsing by the calling routine. Return this buffer, and if ADJUST
7920 is non-null set it to the length of the string we removed from the
7921 input line. Otherwise return NULL.
7922
7923 This function is copied from the ELF version above adjusted for PE targets. */
7924
7925 static char *
7926 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7927 int *adjust ATTRIBUTE_UNUSED,
7928 i386_operand_type *types)
7929 {
7930 static const struct
7931 {
7932 const char *str;
7933 int len;
7934 const enum bfd_reloc_code_real rel[2];
7935 const i386_operand_type types64;
7936 }
7937 gotrel[] =
7938 {
7939 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7940 BFD_RELOC_32_SECREL },
7941 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7942 };
7943
7944 char *cp;
7945 unsigned j;
7946
7947 for (cp = input_line_pointer; *cp != '@'; cp++)
7948 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7949 return NULL;
7950
7951 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7952 {
7953 int len = gotrel[j].len;
7954
7955 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7956 {
7957 if (gotrel[j].rel[object_64bit] != 0)
7958 {
7959 int first, second;
7960 char *tmpbuf, *past_reloc;
7961
7962 *rel = gotrel[j].rel[object_64bit];
7963 if (adjust)
7964 *adjust = len;
7965
7966 if (types)
7967 {
7968 if (flag_code != CODE_64BIT)
7969 {
7970 types->bitfield.imm32 = 1;
7971 types->bitfield.disp32 = 1;
7972 }
7973 else
7974 *types = gotrel[j].types64;
7975 }
7976
7977 /* The length of the first part of our input line. */
7978 first = cp - input_line_pointer;
7979
7980 /* The second part goes from after the reloc token until
7981 (and including) an end_of_line char or comma. */
7982 past_reloc = cp + 1 + len;
7983 cp = past_reloc;
7984 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7985 ++cp;
7986 second = cp + 1 - past_reloc;
7987
7988 /* Allocate and copy string. The trailing NUL shouldn't
7989 be necessary, but be safe. */
7990 tmpbuf = XNEWVEC (char, first + second + 2);
7991 memcpy (tmpbuf, input_line_pointer, first);
7992 if (second != 0 && *past_reloc != ' ')
7993 /* Replace the relocation token with ' ', so that
7994 errors like foo@SECLREL321 will be detected. */
7995 tmpbuf[first++] = ' ';
7996 memcpy (tmpbuf + first, past_reloc, second);
7997 tmpbuf[first + second] = '\0';
7998 return tmpbuf;
7999 }
8000
8001 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8002 gotrel[j].str, 1 << (5 + object_64bit));
8003 return NULL;
8004 }
8005 }
8006
8007 /* Might be a symbol version string. Don't as_bad here. */
8008 return NULL;
8009 }
8010
8011 #endif /* TE_PE */
8012
8013 bfd_reloc_code_real_type
8014 x86_cons (expressionS *exp, int size)
8015 {
8016 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8017
8018 intel_syntax = -intel_syntax;
8019
8020 exp->X_md = 0;
8021 if (size == 4 || (object_64bit && size == 8))
8022 {
8023 /* Handle @GOTOFF and the like in an expression. */
8024 char *save;
8025 char *gotfree_input_line;
8026 int adjust = 0;
8027
8028 save = input_line_pointer;
8029 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8030 if (gotfree_input_line)
8031 input_line_pointer = gotfree_input_line;
8032
8033 expression (exp);
8034
8035 if (gotfree_input_line)
8036 {
8037 /* expression () has merrily parsed up to the end of line,
8038 or a comma - in the wrong buffer. Transfer how far
8039 input_line_pointer has moved to the right buffer. */
8040 input_line_pointer = (save
8041 + (input_line_pointer - gotfree_input_line)
8042 + adjust);
8043 free (gotfree_input_line);
8044 if (exp->X_op == O_constant
8045 || exp->X_op == O_absent
8046 || exp->X_op == O_illegal
8047 || exp->X_op == O_register
8048 || exp->X_op == O_big)
8049 {
8050 char c = *input_line_pointer;
8051 *input_line_pointer = 0;
8052 as_bad (_("missing or invalid expression `%s'"), save);
8053 *input_line_pointer = c;
8054 }
8055 }
8056 }
8057 else
8058 expression (exp);
8059
8060 intel_syntax = -intel_syntax;
8061
8062 if (intel_syntax)
8063 i386_intel_simplify (exp);
8064
8065 return got_reloc;
8066 }
8067
8068 static void
8069 signed_cons (int size)
8070 {
8071 if (flag_code == CODE_64BIT)
8072 cons_sign = 1;
8073 cons (size);
8074 cons_sign = -1;
8075 }
8076
8077 #ifdef TE_PE
8078 static void
8079 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8080 {
8081 expressionS exp;
8082
8083 do
8084 {
8085 expression (&exp);
8086 if (exp.X_op == O_symbol)
8087 exp.X_op = O_secrel;
8088
8089 emit_expr (&exp, 4);
8090 }
8091 while (*input_line_pointer++ == ',');
8092
8093 input_line_pointer--;
8094 demand_empty_rest_of_line ();
8095 }
8096 #endif
8097
8098 /* Handle Vector operations. */
8099
8100 static char *
8101 check_VecOperations (char *op_string, char *op_end)
8102 {
8103 const reg_entry *mask;
8104 const char *saved;
8105 char *end_op;
8106
8107 while (*op_string
8108 && (op_end == NULL || op_string < op_end))
8109 {
8110 saved = op_string;
8111 if (*op_string == '{')
8112 {
8113 op_string++;
8114
8115 /* Check broadcasts. */
8116 if (strncmp (op_string, "1to", 3) == 0)
8117 {
8118 int bcst_type;
8119
8120 if (i.broadcast)
8121 goto duplicated_vec_op;
8122
8123 op_string += 3;
8124 if (*op_string == '8')
8125 bcst_type = BROADCAST_1TO8;
8126 else if (*op_string == '4')
8127 bcst_type = BROADCAST_1TO4;
8128 else if (*op_string == '2')
8129 bcst_type = BROADCAST_1TO2;
8130 else if (*op_string == '1'
8131 && *(op_string+1) == '6')
8132 {
8133 bcst_type = BROADCAST_1TO16;
8134 op_string++;
8135 }
8136 else
8137 {
8138 as_bad (_("Unsupported broadcast: `%s'"), saved);
8139 return NULL;
8140 }
8141 op_string++;
8142
8143 broadcast_op.type = bcst_type;
8144 broadcast_op.operand = this_operand;
8145 i.broadcast = &broadcast_op;
8146 }
8147 /* Check masking operation. */
8148 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8149 {
8150 /* k0 can't be used for write mask. */
8151 if (mask->reg_num == 0)
8152 {
8153 as_bad (_("`%s' can't be used for write mask"),
8154 op_string);
8155 return NULL;
8156 }
8157
8158 if (!i.mask)
8159 {
8160 mask_op.mask = mask;
8161 mask_op.zeroing = 0;
8162 mask_op.operand = this_operand;
8163 i.mask = &mask_op;
8164 }
8165 else
8166 {
8167 if (i.mask->mask)
8168 goto duplicated_vec_op;
8169
8170 i.mask->mask = mask;
8171
8172 /* Only "{z}" is allowed here. No need to check
8173 zeroing mask explicitly. */
8174 if (i.mask->operand != this_operand)
8175 {
8176 as_bad (_("invalid write mask `%s'"), saved);
8177 return NULL;
8178 }
8179 }
8180
8181 op_string = end_op;
8182 }
8183 /* Check zeroing-flag for masking operation. */
8184 else if (*op_string == 'z')
8185 {
8186 if (!i.mask)
8187 {
8188 mask_op.mask = NULL;
8189 mask_op.zeroing = 1;
8190 mask_op.operand = this_operand;
8191 i.mask = &mask_op;
8192 }
8193 else
8194 {
8195 if (i.mask->zeroing)
8196 {
8197 duplicated_vec_op:
8198 as_bad (_("duplicated `%s'"), saved);
8199 return NULL;
8200 }
8201
8202 i.mask->zeroing = 1;
8203
8204 /* Only "{%k}" is allowed here. No need to check mask
8205 register explicitly. */
8206 if (i.mask->operand != this_operand)
8207 {
8208 as_bad (_("invalid zeroing-masking `%s'"),
8209 saved);
8210 return NULL;
8211 }
8212 }
8213
8214 op_string++;
8215 }
8216 else
8217 goto unknown_vec_op;
8218
8219 if (*op_string != '}')
8220 {
8221 as_bad (_("missing `}' in `%s'"), saved);
8222 return NULL;
8223 }
8224 op_string++;
8225 continue;
8226 }
8227 unknown_vec_op:
8228 /* We don't know this one. */
8229 as_bad (_("unknown vector operation: `%s'"), saved);
8230 return NULL;
8231 }
8232
8233 return op_string;
8234 }
8235
8236 static int
8237 i386_immediate (char *imm_start)
8238 {
8239 char *save_input_line_pointer;
8240 char *gotfree_input_line;
8241 segT exp_seg = 0;
8242 expressionS *exp;
8243 i386_operand_type types;
8244
8245 operand_type_set (&types, ~0);
8246
8247 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8248 {
8249 as_bad (_("at most %d immediate operands are allowed"),
8250 MAX_IMMEDIATE_OPERANDS);
8251 return 0;
8252 }
8253
8254 exp = &im_expressions[i.imm_operands++];
8255 i.op[this_operand].imms = exp;
8256
8257 if (is_space_char (*imm_start))
8258 ++imm_start;
8259
8260 save_input_line_pointer = input_line_pointer;
8261 input_line_pointer = imm_start;
8262
8263 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8264 if (gotfree_input_line)
8265 input_line_pointer = gotfree_input_line;
8266
8267 exp_seg = expression (exp);
8268
8269 SKIP_WHITESPACE ();
8270
8271 /* Handle vector operations. */
8272 if (*input_line_pointer == '{')
8273 {
8274 input_line_pointer = check_VecOperations (input_line_pointer,
8275 NULL);
8276 if (input_line_pointer == NULL)
8277 return 0;
8278 }
8279
8280 if (*input_line_pointer)
8281 as_bad (_("junk `%s' after expression"), input_line_pointer);
8282
8283 input_line_pointer = save_input_line_pointer;
8284 if (gotfree_input_line)
8285 {
8286 free (gotfree_input_line);
8287
8288 if (exp->X_op == O_constant || exp->X_op == O_register)
8289 exp->X_op = O_illegal;
8290 }
8291
8292 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8293 }
8294
8295 static int
8296 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8297 i386_operand_type types, const char *imm_start)
8298 {
8299 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8300 {
8301 if (imm_start)
8302 as_bad (_("missing or invalid immediate expression `%s'"),
8303 imm_start);
8304 return 0;
8305 }
8306 else if (exp->X_op == O_constant)
8307 {
8308 /* Size it properly later. */
8309 i.types[this_operand].bitfield.imm64 = 1;
8310 /* If not 64bit, sign extend val. */
8311 if (flag_code != CODE_64BIT
8312 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8313 exp->X_add_number
8314 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8315 }
8316 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8317 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8318 && exp_seg != absolute_section
8319 && exp_seg != text_section
8320 && exp_seg != data_section
8321 && exp_seg != bss_section
8322 && exp_seg != undefined_section
8323 && !bfd_is_com_section (exp_seg))
8324 {
8325 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8326 return 0;
8327 }
8328 #endif
8329 else if (!intel_syntax && exp_seg == reg_section)
8330 {
8331 if (imm_start)
8332 as_bad (_("illegal immediate register operand %s"), imm_start);
8333 return 0;
8334 }
8335 else
8336 {
8337 /* This is an address. The size of the address will be
8338 determined later, depending on destination register,
8339 suffix, or the default for the section. */
8340 i.types[this_operand].bitfield.imm8 = 1;
8341 i.types[this_operand].bitfield.imm16 = 1;
8342 i.types[this_operand].bitfield.imm32 = 1;
8343 i.types[this_operand].bitfield.imm32s = 1;
8344 i.types[this_operand].bitfield.imm64 = 1;
8345 i.types[this_operand] = operand_type_and (i.types[this_operand],
8346 types);
8347 }
8348
8349 return 1;
8350 }
8351
8352 static char *
8353 i386_scale (char *scale)
8354 {
8355 offsetT val;
8356 char *save = input_line_pointer;
8357
8358 input_line_pointer = scale;
8359 val = get_absolute_expression ();
8360
8361 switch (val)
8362 {
8363 case 1:
8364 i.log2_scale_factor = 0;
8365 break;
8366 case 2:
8367 i.log2_scale_factor = 1;
8368 break;
8369 case 4:
8370 i.log2_scale_factor = 2;
8371 break;
8372 case 8:
8373 i.log2_scale_factor = 3;
8374 break;
8375 default:
8376 {
8377 char sep = *input_line_pointer;
8378
8379 *input_line_pointer = '\0';
8380 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8381 scale);
8382 *input_line_pointer = sep;
8383 input_line_pointer = save;
8384 return NULL;
8385 }
8386 }
8387 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8388 {
8389 as_warn (_("scale factor of %d without an index register"),
8390 1 << i.log2_scale_factor);
8391 i.log2_scale_factor = 0;
8392 }
8393 scale = input_line_pointer;
8394 input_line_pointer = save;
8395 return scale;
8396 }
8397
8398 static int
8399 i386_displacement (char *disp_start, char *disp_end)
8400 {
8401 expressionS *exp;
8402 segT exp_seg = 0;
8403 char *save_input_line_pointer;
8404 char *gotfree_input_line;
8405 int override;
8406 i386_operand_type bigdisp, types = anydisp;
8407 int ret;
8408
8409 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8410 {
8411 as_bad (_("at most %d displacement operands are allowed"),
8412 MAX_MEMORY_OPERANDS);
8413 return 0;
8414 }
8415
8416 operand_type_set (&bigdisp, 0);
8417 if ((i.types[this_operand].bitfield.jumpabsolute)
8418 || (!current_templates->start->opcode_modifier.jump
8419 && !current_templates->start->opcode_modifier.jumpdword))
8420 {
8421 bigdisp.bitfield.disp32 = 1;
8422 override = (i.prefix[ADDR_PREFIX] != 0);
8423 if (flag_code == CODE_64BIT)
8424 {
8425 if (!override)
8426 {
8427 bigdisp.bitfield.disp32s = 1;
8428 bigdisp.bitfield.disp64 = 1;
8429 }
8430 }
8431 else if ((flag_code == CODE_16BIT) ^ override)
8432 {
8433 bigdisp.bitfield.disp32 = 0;
8434 bigdisp.bitfield.disp16 = 1;
8435 }
8436 }
8437 else
8438 {
8439 /* For PC-relative branches, the width of the displacement
8440 is dependent upon data size, not address size. */
8441 override = (i.prefix[DATA_PREFIX] != 0);
8442 if (flag_code == CODE_64BIT)
8443 {
8444 if (override || i.suffix == WORD_MNEM_SUFFIX)
8445 bigdisp.bitfield.disp16 = 1;
8446 else
8447 {
8448 bigdisp.bitfield.disp32 = 1;
8449 bigdisp.bitfield.disp32s = 1;
8450 }
8451 }
8452 else
8453 {
8454 if (!override)
8455 override = (i.suffix == (flag_code != CODE_16BIT
8456 ? WORD_MNEM_SUFFIX
8457 : LONG_MNEM_SUFFIX));
8458 bigdisp.bitfield.disp32 = 1;
8459 if ((flag_code == CODE_16BIT) ^ override)
8460 {
8461 bigdisp.bitfield.disp32 = 0;
8462 bigdisp.bitfield.disp16 = 1;
8463 }
8464 }
8465 }
8466 i.types[this_operand] = operand_type_or (i.types[this_operand],
8467 bigdisp);
8468
8469 exp = &disp_expressions[i.disp_operands];
8470 i.op[this_operand].disps = exp;
8471 i.disp_operands++;
8472 save_input_line_pointer = input_line_pointer;
8473 input_line_pointer = disp_start;
8474 END_STRING_AND_SAVE (disp_end);
8475
8476 #ifndef GCC_ASM_O_HACK
8477 #define GCC_ASM_O_HACK 0
8478 #endif
8479 #if GCC_ASM_O_HACK
8480 END_STRING_AND_SAVE (disp_end + 1);
8481 if (i.types[this_operand].bitfield.baseIndex
8482 && displacement_string_end[-1] == '+')
8483 {
8484 /* This hack is to avoid a warning when using the "o"
8485 constraint within gcc asm statements.
8486 For instance:
8487
8488 #define _set_tssldt_desc(n,addr,limit,type) \
8489 __asm__ __volatile__ ( \
8490 "movw %w2,%0\n\t" \
8491 "movw %w1,2+%0\n\t" \
8492 "rorl $16,%1\n\t" \
8493 "movb %b1,4+%0\n\t" \
8494 "movb %4,5+%0\n\t" \
8495 "movb $0,6+%0\n\t" \
8496 "movb %h1,7+%0\n\t" \
8497 "rorl $16,%1" \
8498 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8499
8500 This works great except that the output assembler ends
8501 up looking a bit weird if it turns out that there is
8502 no offset. You end up producing code that looks like:
8503
8504 #APP
8505 movw $235,(%eax)
8506 movw %dx,2+(%eax)
8507 rorl $16,%edx
8508 movb %dl,4+(%eax)
8509 movb $137,5+(%eax)
8510 movb $0,6+(%eax)
8511 movb %dh,7+(%eax)
8512 rorl $16,%edx
8513 #NO_APP
8514
8515 So here we provide the missing zero. */
8516
8517 *displacement_string_end = '0';
8518 }
8519 #endif
8520 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8521 if (gotfree_input_line)
8522 input_line_pointer = gotfree_input_line;
8523
8524 exp_seg = expression (exp);
8525
8526 SKIP_WHITESPACE ();
8527 if (*input_line_pointer)
8528 as_bad (_("junk `%s' after expression"), input_line_pointer);
8529 #if GCC_ASM_O_HACK
8530 RESTORE_END_STRING (disp_end + 1);
8531 #endif
8532 input_line_pointer = save_input_line_pointer;
8533 if (gotfree_input_line)
8534 {
8535 free (gotfree_input_line);
8536
8537 if (exp->X_op == O_constant || exp->X_op == O_register)
8538 exp->X_op = O_illegal;
8539 }
8540
8541 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8542
8543 RESTORE_END_STRING (disp_end);
8544
8545 return ret;
8546 }
8547
8548 static int
8549 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8550 i386_operand_type types, const char *disp_start)
8551 {
8552 i386_operand_type bigdisp;
8553 int ret = 1;
8554
8555 /* We do this to make sure that the section symbol is in
8556 the symbol table. We will ultimately change the relocation
8557 to be relative to the beginning of the section. */
8558 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8559 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8560 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8561 {
8562 if (exp->X_op != O_symbol)
8563 goto inv_disp;
8564
8565 if (S_IS_LOCAL (exp->X_add_symbol)
8566 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8567 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8568 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8569 exp->X_op = O_subtract;
8570 exp->X_op_symbol = GOT_symbol;
8571 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8572 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8573 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8574 i.reloc[this_operand] = BFD_RELOC_64;
8575 else
8576 i.reloc[this_operand] = BFD_RELOC_32;
8577 }
8578
8579 else if (exp->X_op == O_absent
8580 || exp->X_op == O_illegal
8581 || exp->X_op == O_big)
8582 {
8583 inv_disp:
8584 as_bad (_("missing or invalid displacement expression `%s'"),
8585 disp_start);
8586 ret = 0;
8587 }
8588
8589 else if (flag_code == CODE_64BIT
8590 && !i.prefix[ADDR_PREFIX]
8591 && exp->X_op == O_constant)
8592 {
8593 /* Since displacement is signed extended to 64bit, don't allow
8594 disp32 and turn off disp32s if they are out of range. */
8595 i.types[this_operand].bitfield.disp32 = 0;
8596 if (!fits_in_signed_long (exp->X_add_number))
8597 {
8598 i.types[this_operand].bitfield.disp32s = 0;
8599 if (i.types[this_operand].bitfield.baseindex)
8600 {
8601 as_bad (_("0x%lx out range of signed 32bit displacement"),
8602 (long) exp->X_add_number);
8603 ret = 0;
8604 }
8605 }
8606 }
8607
8608 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8609 else if (exp->X_op != O_constant
8610 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8611 && exp_seg != absolute_section
8612 && exp_seg != text_section
8613 && exp_seg != data_section
8614 && exp_seg != bss_section
8615 && exp_seg != undefined_section
8616 && !bfd_is_com_section (exp_seg))
8617 {
8618 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8619 ret = 0;
8620 }
8621 #endif
8622
8623 /* Check if this is a displacement only operand. */
8624 bigdisp = i.types[this_operand];
8625 bigdisp.bitfield.disp8 = 0;
8626 bigdisp.bitfield.disp16 = 0;
8627 bigdisp.bitfield.disp32 = 0;
8628 bigdisp.bitfield.disp32s = 0;
8629 bigdisp.bitfield.disp64 = 0;
8630 if (operand_type_all_zero (&bigdisp))
8631 i.types[this_operand] = operand_type_and (i.types[this_operand],
8632 types);
8633
8634 return ret;
8635 }
8636
8637 /* Return the active addressing mode, taking address override and
8638 registers forming the address into consideration. Update the
8639 address override prefix if necessary. */
8640
8641 static enum flag_code
8642 i386_addressing_mode (void)
8643 {
8644 enum flag_code addr_mode;
8645
8646 if (i.prefix[ADDR_PREFIX])
8647 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8648 else
8649 {
8650 addr_mode = flag_code;
8651
8652 #if INFER_ADDR_PREFIX
8653 if (i.mem_operands == 0)
8654 {
8655 /* Infer address prefix from the first memory operand. */
8656 const reg_entry *addr_reg = i.base_reg;
8657
8658 if (addr_reg == NULL)
8659 addr_reg = i.index_reg;
8660
8661 if (addr_reg)
8662 {
8663 if (addr_reg->reg_num == RegEip
8664 || addr_reg->reg_num == RegEiz
8665 || addr_reg->reg_type.bitfield.reg32)
8666 addr_mode = CODE_32BIT;
8667 else if (flag_code != CODE_64BIT
8668 && addr_reg->reg_type.bitfield.reg16)
8669 addr_mode = CODE_16BIT;
8670
8671 if (addr_mode != flag_code)
8672 {
8673 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8674 i.prefixes += 1;
8675 /* Change the size of any displacement too. At most one
8676 of Disp16 or Disp32 is set.
8677 FIXME. There doesn't seem to be any real need for
8678 separate Disp16 and Disp32 flags. The same goes for
8679 Imm16 and Imm32. Removing them would probably clean
8680 up the code quite a lot. */
8681 if (flag_code != CODE_64BIT
8682 && (i.types[this_operand].bitfield.disp16
8683 || i.types[this_operand].bitfield.disp32))
8684 i.types[this_operand]
8685 = operand_type_xor (i.types[this_operand], disp16_32);
8686 }
8687 }
8688 }
8689 #endif
8690 }
8691
8692 return addr_mode;
8693 }
8694
8695 /* Make sure the memory operand we've been dealt is valid.
8696 Return 1 on success, 0 on a failure. */
8697
8698 static int
8699 i386_index_check (const char *operand_string)
8700 {
8701 const char *kind = "base/index";
8702 enum flag_code addr_mode = i386_addressing_mode ();
8703
8704 if (current_templates->start->opcode_modifier.isstring
8705 && !current_templates->start->opcode_modifier.immext
8706 && (current_templates->end[-1].opcode_modifier.isstring
8707 || i.mem_operands))
8708 {
8709 /* Memory operands of string insns are special in that they only allow
8710 a single register (rDI, rSI, or rBX) as their memory address. */
8711 const reg_entry *expected_reg;
8712 static const char *di_si[][2] =
8713 {
8714 { "esi", "edi" },
8715 { "si", "di" },
8716 { "rsi", "rdi" }
8717 };
8718 static const char *bx[] = { "ebx", "bx", "rbx" };
8719
8720 kind = "string address";
8721
8722 if (current_templates->start->opcode_modifier.repprefixok)
8723 {
8724 i386_operand_type type = current_templates->end[-1].operand_types[0];
8725
8726 if (!type.bitfield.baseindex
8727 || ((!i.mem_operands != !intel_syntax)
8728 && current_templates->end[-1].operand_types[1]
8729 .bitfield.baseindex))
8730 type = current_templates->end[-1].operand_types[1];
8731 expected_reg = hash_find (reg_hash,
8732 di_si[addr_mode][type.bitfield.esseg]);
8733
8734 }
8735 else
8736 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8737
8738 if (i.base_reg != expected_reg
8739 || i.index_reg
8740 || operand_type_check (i.types[this_operand], disp))
8741 {
8742 /* The second memory operand must have the same size as
8743 the first one. */
8744 if (i.mem_operands
8745 && i.base_reg
8746 && !((addr_mode == CODE_64BIT
8747 && i.base_reg->reg_type.bitfield.reg64)
8748 || (addr_mode == CODE_32BIT
8749 ? i.base_reg->reg_type.bitfield.reg32
8750 : i.base_reg->reg_type.bitfield.reg16)))
8751 goto bad_address;
8752
8753 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8754 operand_string,
8755 intel_syntax ? '[' : '(',
8756 register_prefix,
8757 expected_reg->reg_name,
8758 intel_syntax ? ']' : ')');
8759 return 1;
8760 }
8761 else
8762 return 1;
8763
8764 bad_address:
8765 as_bad (_("`%s' is not a valid %s expression"),
8766 operand_string, kind);
8767 return 0;
8768 }
8769 else
8770 {
8771 if (addr_mode != CODE_16BIT)
8772 {
8773 /* 32-bit/64-bit checks. */
8774 if ((i.base_reg
8775 && (addr_mode == CODE_64BIT
8776 ? !i.base_reg->reg_type.bitfield.reg64
8777 : !i.base_reg->reg_type.bitfield.reg32)
8778 && (i.index_reg
8779 || (i.base_reg->reg_num
8780 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8781 || (i.index_reg
8782 && !i.index_reg->reg_type.bitfield.regxmm
8783 && !i.index_reg->reg_type.bitfield.regymm
8784 && !i.index_reg->reg_type.bitfield.regzmm
8785 && ((addr_mode == CODE_64BIT
8786 ? !(i.index_reg->reg_type.bitfield.reg64
8787 || i.index_reg->reg_num == RegRiz)
8788 : !(i.index_reg->reg_type.bitfield.reg32
8789 || i.index_reg->reg_num == RegEiz))
8790 || !i.index_reg->reg_type.bitfield.baseindex)))
8791 goto bad_address;
8792
8793 /* bndmk, bndldx, and bndstx have special restrictions. */
8794 if (current_templates->start->base_opcode == 0xf30f1b
8795 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8796 {
8797 /* They cannot use RIP-relative addressing. */
8798 if (i.base_reg && i.base_reg->reg_num == RegRip)
8799 {
8800 as_bad (_("`%s' cannot be used here"), operand_string);
8801 return 0;
8802 }
8803
8804 /* bndldx and bndstx ignore their scale factor. */
8805 if (current_templates->start->base_opcode != 0xf30f1b
8806 && i.log2_scale_factor)
8807 as_warn (_("register scaling is being ignored here"));
8808 }
8809 }
8810 else
8811 {
8812 /* 16-bit checks. */
8813 if ((i.base_reg
8814 && (!i.base_reg->reg_type.bitfield.reg16
8815 || !i.base_reg->reg_type.bitfield.baseindex))
8816 || (i.index_reg
8817 && (!i.index_reg->reg_type.bitfield.reg16
8818 || !i.index_reg->reg_type.bitfield.baseindex
8819 || !(i.base_reg
8820 && i.base_reg->reg_num < 6
8821 && i.index_reg->reg_num >= 6
8822 && i.log2_scale_factor == 0))))
8823 goto bad_address;
8824 }
8825 }
8826 return 1;
8827 }
8828
8829 /* Handle vector immediates. */
8830
8831 static int
8832 RC_SAE_immediate (const char *imm_start)
8833 {
8834 unsigned int match_found, j;
8835 const char *pstr = imm_start;
8836 expressionS *exp;
8837
8838 if (*pstr != '{')
8839 return 0;
8840
8841 pstr++;
8842 match_found = 0;
8843 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8844 {
8845 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8846 {
8847 if (!i.rounding)
8848 {
8849 rc_op.type = RC_NamesTable[j].type;
8850 rc_op.operand = this_operand;
8851 i.rounding = &rc_op;
8852 }
8853 else
8854 {
8855 as_bad (_("duplicated `%s'"), imm_start);
8856 return 0;
8857 }
8858 pstr += RC_NamesTable[j].len;
8859 match_found = 1;
8860 break;
8861 }
8862 }
8863 if (!match_found)
8864 return 0;
8865
8866 if (*pstr++ != '}')
8867 {
8868 as_bad (_("Missing '}': '%s'"), imm_start);
8869 return 0;
8870 }
8871 /* RC/SAE immediate string should contain nothing more. */;
8872 if (*pstr != 0)
8873 {
8874 as_bad (_("Junk after '}': '%s'"), imm_start);
8875 return 0;
8876 }
8877
8878 exp = &im_expressions[i.imm_operands++];
8879 i.op[this_operand].imms = exp;
8880
8881 exp->X_op = O_constant;
8882 exp->X_add_number = 0;
8883 exp->X_add_symbol = (symbolS *) 0;
8884 exp->X_op_symbol = (symbolS *) 0;
8885
8886 i.types[this_operand].bitfield.imm8 = 1;
8887 return 1;
8888 }
8889
8890 /* Only string instructions can have a second memory operand, so
8891 reduce current_templates to just those if it contains any. */
8892 static int
8893 maybe_adjust_templates (void)
8894 {
8895 const insn_template *t;
8896
8897 gas_assert (i.mem_operands == 1);
8898
8899 for (t = current_templates->start; t < current_templates->end; ++t)
8900 if (t->opcode_modifier.isstring)
8901 break;
8902
8903 if (t < current_templates->end)
8904 {
8905 static templates aux_templates;
8906 bfd_boolean recheck;
8907
8908 aux_templates.start = t;
8909 for (; t < current_templates->end; ++t)
8910 if (!t->opcode_modifier.isstring)
8911 break;
8912 aux_templates.end = t;
8913
8914 /* Determine whether to re-check the first memory operand. */
8915 recheck = (aux_templates.start != current_templates->start
8916 || t != current_templates->end);
8917
8918 current_templates = &aux_templates;
8919
8920 if (recheck)
8921 {
8922 i.mem_operands = 0;
8923 if (i.memop1_string != NULL
8924 && i386_index_check (i.memop1_string) == 0)
8925 return 0;
8926 i.mem_operands = 1;
8927 }
8928 }
8929
8930 return 1;
8931 }
8932
8933 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8934 on error. */
8935
8936 static int
8937 i386_att_operand (char *operand_string)
8938 {
8939 const reg_entry *r;
8940 char *end_op;
8941 char *op_string = operand_string;
8942
8943 if (is_space_char (*op_string))
8944 ++op_string;
8945
8946 /* We check for an absolute prefix (differentiating,
8947 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8948 if (*op_string == ABSOLUTE_PREFIX)
8949 {
8950 ++op_string;
8951 if (is_space_char (*op_string))
8952 ++op_string;
8953 i.types[this_operand].bitfield.jumpabsolute = 1;
8954 }
8955
8956 /* Check if operand is a register. */
8957 if ((r = parse_register (op_string, &end_op)) != NULL)
8958 {
8959 i386_operand_type temp;
8960
8961 /* Check for a segment override by searching for ':' after a
8962 segment register. */
8963 op_string = end_op;
8964 if (is_space_char (*op_string))
8965 ++op_string;
8966 if (*op_string == ':'
8967 && (r->reg_type.bitfield.sreg2
8968 || r->reg_type.bitfield.sreg3))
8969 {
8970 switch (r->reg_num)
8971 {
8972 case 0:
8973 i.seg[i.mem_operands] = &es;
8974 break;
8975 case 1:
8976 i.seg[i.mem_operands] = &cs;
8977 break;
8978 case 2:
8979 i.seg[i.mem_operands] = &ss;
8980 break;
8981 case 3:
8982 i.seg[i.mem_operands] = &ds;
8983 break;
8984 case 4:
8985 i.seg[i.mem_operands] = &fs;
8986 break;
8987 case 5:
8988 i.seg[i.mem_operands] = &gs;
8989 break;
8990 }
8991
8992 /* Skip the ':' and whitespace. */
8993 ++op_string;
8994 if (is_space_char (*op_string))
8995 ++op_string;
8996
8997 if (!is_digit_char (*op_string)
8998 && !is_identifier_char (*op_string)
8999 && *op_string != '('
9000 && *op_string != ABSOLUTE_PREFIX)
9001 {
9002 as_bad (_("bad memory operand `%s'"), op_string);
9003 return 0;
9004 }
9005 /* Handle case of %es:*foo. */
9006 if (*op_string == ABSOLUTE_PREFIX)
9007 {
9008 ++op_string;
9009 if (is_space_char (*op_string))
9010 ++op_string;
9011 i.types[this_operand].bitfield.jumpabsolute = 1;
9012 }
9013 goto do_memory_reference;
9014 }
9015
9016 /* Handle vector operations. */
9017 if (*op_string == '{')
9018 {
9019 op_string = check_VecOperations (op_string, NULL);
9020 if (op_string == NULL)
9021 return 0;
9022 }
9023
9024 if (*op_string)
9025 {
9026 as_bad (_("junk `%s' after register"), op_string);
9027 return 0;
9028 }
9029 temp = r->reg_type;
9030 temp.bitfield.baseindex = 0;
9031 i.types[this_operand] = operand_type_or (i.types[this_operand],
9032 temp);
9033 i.types[this_operand].bitfield.unspecified = 0;
9034 i.op[this_operand].regs = r;
9035 i.reg_operands++;
9036 }
9037 else if (*op_string == REGISTER_PREFIX)
9038 {
9039 as_bad (_("bad register name `%s'"), op_string);
9040 return 0;
9041 }
9042 else if (*op_string == IMMEDIATE_PREFIX)
9043 {
9044 ++op_string;
9045 if (i.types[this_operand].bitfield.jumpabsolute)
9046 {
9047 as_bad (_("immediate operand illegal with absolute jump"));
9048 return 0;
9049 }
9050 if (!i386_immediate (op_string))
9051 return 0;
9052 }
9053 else if (RC_SAE_immediate (operand_string))
9054 {
9055 /* If it is a RC or SAE immediate, do nothing. */
9056 ;
9057 }
9058 else if (is_digit_char (*op_string)
9059 || is_identifier_char (*op_string)
9060 || *op_string == '"'
9061 || *op_string == '(')
9062 {
9063 /* This is a memory reference of some sort. */
9064 char *base_string;
9065
9066 /* Start and end of displacement string expression (if found). */
9067 char *displacement_string_start;
9068 char *displacement_string_end;
9069 char *vop_start;
9070
9071 do_memory_reference:
9072 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9073 return 0;
9074 if ((i.mem_operands == 1
9075 && !current_templates->start->opcode_modifier.isstring)
9076 || i.mem_operands == 2)
9077 {
9078 as_bad (_("too many memory references for `%s'"),
9079 current_templates->start->name);
9080 return 0;
9081 }
9082
9083 /* Check for base index form. We detect the base index form by
9084 looking for an ')' at the end of the operand, searching
9085 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9086 after the '('. */
9087 base_string = op_string + strlen (op_string);
9088
9089 /* Handle vector operations. */
9090 vop_start = strchr (op_string, '{');
9091 if (vop_start && vop_start < base_string)
9092 {
9093 if (check_VecOperations (vop_start, base_string) == NULL)
9094 return 0;
9095 base_string = vop_start;
9096 }
9097
9098 --base_string;
9099 if (is_space_char (*base_string))
9100 --base_string;
9101
9102 /* If we only have a displacement, set-up for it to be parsed later. */
9103 displacement_string_start = op_string;
9104 displacement_string_end = base_string + 1;
9105
9106 if (*base_string == ')')
9107 {
9108 char *temp_string;
9109 unsigned int parens_balanced = 1;
9110 /* We've already checked that the number of left & right ()'s are
9111 equal, so this loop will not be infinite. */
9112 do
9113 {
9114 base_string--;
9115 if (*base_string == ')')
9116 parens_balanced++;
9117 if (*base_string == '(')
9118 parens_balanced--;
9119 }
9120 while (parens_balanced);
9121
9122 temp_string = base_string;
9123
9124 /* Skip past '(' and whitespace. */
9125 ++base_string;
9126 if (is_space_char (*base_string))
9127 ++base_string;
9128
9129 if (*base_string == ','
9130 || ((i.base_reg = parse_register (base_string, &end_op))
9131 != NULL))
9132 {
9133 displacement_string_end = temp_string;
9134
9135 i.types[this_operand].bitfield.baseindex = 1;
9136
9137 if (i.base_reg)
9138 {
9139 base_string = end_op;
9140 if (is_space_char (*base_string))
9141 ++base_string;
9142 }
9143
9144 /* There may be an index reg or scale factor here. */
9145 if (*base_string == ',')
9146 {
9147 ++base_string;
9148 if (is_space_char (*base_string))
9149 ++base_string;
9150
9151 if ((i.index_reg = parse_register (base_string, &end_op))
9152 != NULL)
9153 {
9154 base_string = end_op;
9155 if (is_space_char (*base_string))
9156 ++base_string;
9157 if (*base_string == ',')
9158 {
9159 ++base_string;
9160 if (is_space_char (*base_string))
9161 ++base_string;
9162 }
9163 else if (*base_string != ')')
9164 {
9165 as_bad (_("expecting `,' or `)' "
9166 "after index register in `%s'"),
9167 operand_string);
9168 return 0;
9169 }
9170 }
9171 else if (*base_string == REGISTER_PREFIX)
9172 {
9173 end_op = strchr (base_string, ',');
9174 if (end_op)
9175 *end_op = '\0';
9176 as_bad (_("bad register name `%s'"), base_string);
9177 return 0;
9178 }
9179
9180 /* Check for scale factor. */
9181 if (*base_string != ')')
9182 {
9183 char *end_scale = i386_scale (base_string);
9184
9185 if (!end_scale)
9186 return 0;
9187
9188 base_string = end_scale;
9189 if (is_space_char (*base_string))
9190 ++base_string;
9191 if (*base_string != ')')
9192 {
9193 as_bad (_("expecting `)' "
9194 "after scale factor in `%s'"),
9195 operand_string);
9196 return 0;
9197 }
9198 }
9199 else if (!i.index_reg)
9200 {
9201 as_bad (_("expecting index register or scale factor "
9202 "after `,'; got '%c'"),
9203 *base_string);
9204 return 0;
9205 }
9206 }
9207 else if (*base_string != ')')
9208 {
9209 as_bad (_("expecting `,' or `)' "
9210 "after base register in `%s'"),
9211 operand_string);
9212 return 0;
9213 }
9214 }
9215 else if (*base_string == REGISTER_PREFIX)
9216 {
9217 end_op = strchr (base_string, ',');
9218 if (end_op)
9219 *end_op = '\0';
9220 as_bad (_("bad register name `%s'"), base_string);
9221 return 0;
9222 }
9223 }
9224
9225 /* If there's an expression beginning the operand, parse it,
9226 assuming displacement_string_start and
9227 displacement_string_end are meaningful. */
9228 if (displacement_string_start != displacement_string_end)
9229 {
9230 if (!i386_displacement (displacement_string_start,
9231 displacement_string_end))
9232 return 0;
9233 }
9234
9235 /* Special case for (%dx) while doing input/output op. */
9236 if (i.base_reg
9237 && operand_type_equal (&i.base_reg->reg_type,
9238 &reg16_inoutportreg)
9239 && i.index_reg == 0
9240 && i.log2_scale_factor == 0
9241 && i.seg[i.mem_operands] == 0
9242 && !operand_type_check (i.types[this_operand], disp))
9243 {
9244 i.types[this_operand] = inoutportreg;
9245 return 1;
9246 }
9247
9248 if (i386_index_check (operand_string) == 0)
9249 return 0;
9250 i.types[this_operand].bitfield.mem = 1;
9251 if (i.mem_operands == 0)
9252 i.memop1_string = xstrdup (operand_string);
9253 i.mem_operands++;
9254 }
9255 else
9256 {
9257 /* It's not a memory operand; argh! */
9258 as_bad (_("invalid char %s beginning operand %d `%s'"),
9259 output_invalid (*op_string),
9260 this_operand + 1,
9261 op_string);
9262 return 0;
9263 }
9264 return 1; /* Normal return. */
9265 }
9266 \f
9267 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9268 that an rs_machine_dependent frag may reach. */
9269
9270 unsigned int
9271 i386_frag_max_var (fragS *frag)
9272 {
9273 /* The only relaxable frags are for jumps.
9274 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9275 gas_assert (frag->fr_type == rs_machine_dependent);
9276 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9277 }
9278
9279 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9280 static int
9281 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9282 {
9283 /* STT_GNU_IFUNC symbol must go through PLT. */
9284 if ((symbol_get_bfdsym (fr_symbol)->flags
9285 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9286 return 0;
9287
9288 if (!S_IS_EXTERNAL (fr_symbol))
9289 /* Symbol may be weak or local. */
9290 return !S_IS_WEAK (fr_symbol);
9291
9292 /* Global symbols with non-default visibility can't be preempted. */
9293 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9294 return 1;
9295
9296 if (fr_var != NO_RELOC)
9297 switch ((enum bfd_reloc_code_real) fr_var)
9298 {
9299 case BFD_RELOC_386_PLT32:
9300 case BFD_RELOC_X86_64_PLT32:
9301 /* Symbol with PLT relocation may be preempted. */
9302 return 0;
9303 default:
9304 abort ();
9305 }
9306
9307 /* Global symbols with default visibility in a shared library may be
9308 preempted by another definition. */
9309 return !shared;
9310 }
9311 #endif
9312
9313 /* md_estimate_size_before_relax()
9314
9315 Called just before relax() for rs_machine_dependent frags. The x86
9316 assembler uses these frags to handle variable size jump
9317 instructions.
9318
9319 Any symbol that is now undefined will not become defined.
9320 Return the correct fr_subtype in the frag.
9321 Return the initial "guess for variable size of frag" to caller.
9322 The guess is actually the growth beyond the fixed part. Whatever
9323 we do to grow the fixed or variable part contributes to our
9324 returned value. */
9325
9326 int
9327 md_estimate_size_before_relax (fragS *fragP, segT segment)
9328 {
9329 /* We've already got fragP->fr_subtype right; all we have to do is
9330 check for un-relaxable symbols. On an ELF system, we can't relax
9331 an externally visible symbol, because it may be overridden by a
9332 shared library. */
9333 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9334 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9335 || (IS_ELF
9336 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9337 fragP->fr_var))
9338 #endif
9339 #if defined (OBJ_COFF) && defined (TE_PE)
9340 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9341 && S_IS_WEAK (fragP->fr_symbol))
9342 #endif
9343 )
9344 {
9345 /* Symbol is undefined in this segment, or we need to keep a
9346 reloc so that weak symbols can be overridden. */
9347 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9348 enum bfd_reloc_code_real reloc_type;
9349 unsigned char *opcode;
9350 int old_fr_fix;
9351
9352 if (fragP->fr_var != NO_RELOC)
9353 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9354 else if (size == 2)
9355 reloc_type = BFD_RELOC_16_PCREL;
9356 else
9357 reloc_type = BFD_RELOC_32_PCREL;
9358
9359 old_fr_fix = fragP->fr_fix;
9360 opcode = (unsigned char *) fragP->fr_opcode;
9361
9362 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9363 {
9364 case UNCOND_JUMP:
9365 /* Make jmp (0xeb) a (d)word displacement jump. */
9366 opcode[0] = 0xe9;
9367 fragP->fr_fix += size;
9368 fix_new (fragP, old_fr_fix, size,
9369 fragP->fr_symbol,
9370 fragP->fr_offset, 1,
9371 reloc_type);
9372 break;
9373
9374 case COND_JUMP86:
9375 if (size == 2
9376 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9377 {
9378 /* Negate the condition, and branch past an
9379 unconditional jump. */
9380 opcode[0] ^= 1;
9381 opcode[1] = 3;
9382 /* Insert an unconditional jump. */
9383 opcode[2] = 0xe9;
9384 /* We added two extra opcode bytes, and have a two byte
9385 offset. */
9386 fragP->fr_fix += 2 + 2;
9387 fix_new (fragP, old_fr_fix + 2, 2,
9388 fragP->fr_symbol,
9389 fragP->fr_offset, 1,
9390 reloc_type);
9391 break;
9392 }
9393 /* Fall through. */
9394
9395 case COND_JUMP:
9396 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9397 {
9398 fixS *fixP;
9399
9400 fragP->fr_fix += 1;
9401 fixP = fix_new (fragP, old_fr_fix, 1,
9402 fragP->fr_symbol,
9403 fragP->fr_offset, 1,
9404 BFD_RELOC_8_PCREL);
9405 fixP->fx_signed = 1;
9406 break;
9407 }
9408
9409 /* This changes the byte-displacement jump 0x7N
9410 to the (d)word-displacement jump 0x0f,0x8N. */
9411 opcode[1] = opcode[0] + 0x10;
9412 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9413 /* We've added an opcode byte. */
9414 fragP->fr_fix += 1 + size;
9415 fix_new (fragP, old_fr_fix + 1, size,
9416 fragP->fr_symbol,
9417 fragP->fr_offset, 1,
9418 reloc_type);
9419 break;
9420
9421 default:
9422 BAD_CASE (fragP->fr_subtype);
9423 break;
9424 }
9425 frag_wane (fragP);
9426 return fragP->fr_fix - old_fr_fix;
9427 }
9428
9429 /* Guess size depending on current relax state. Initially the relax
9430 state will correspond to a short jump and we return 1, because
9431 the variable part of the frag (the branch offset) is one byte
9432 long. However, we can relax a section more than once and in that
9433 case we must either set fr_subtype back to the unrelaxed state,
9434 or return the value for the appropriate branch. */
9435 return md_relax_table[fragP->fr_subtype].rlx_length;
9436 }
9437
9438 /* Called after relax() is finished.
9439
9440 In: Address of frag.
9441 fr_type == rs_machine_dependent.
9442 fr_subtype is what the address relaxed to.
9443
9444 Out: Any fixSs and constants are set up.
9445 Caller will turn frag into a ".space 0". */
9446
9447 void
9448 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9449 fragS *fragP)
9450 {
9451 unsigned char *opcode;
9452 unsigned char *where_to_put_displacement = NULL;
9453 offsetT target_address;
9454 offsetT opcode_address;
9455 unsigned int extension = 0;
9456 offsetT displacement_from_opcode_start;
9457
9458 opcode = (unsigned char *) fragP->fr_opcode;
9459
9460 /* Address we want to reach in file space. */
9461 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9462
9463 /* Address opcode resides at in file space. */
9464 opcode_address = fragP->fr_address + fragP->fr_fix;
9465
9466 /* Displacement from opcode start to fill into instruction. */
9467 displacement_from_opcode_start = target_address - opcode_address;
9468
9469 if ((fragP->fr_subtype & BIG) == 0)
9470 {
9471 /* Don't have to change opcode. */
9472 extension = 1; /* 1 opcode + 1 displacement */
9473 where_to_put_displacement = &opcode[1];
9474 }
9475 else
9476 {
9477 if (no_cond_jump_promotion
9478 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9479 as_warn_where (fragP->fr_file, fragP->fr_line,
9480 _("long jump required"));
9481
9482 switch (fragP->fr_subtype)
9483 {
9484 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9485 extension = 4; /* 1 opcode + 4 displacement */
9486 opcode[0] = 0xe9;
9487 where_to_put_displacement = &opcode[1];
9488 break;
9489
9490 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9491 extension = 2; /* 1 opcode + 2 displacement */
9492 opcode[0] = 0xe9;
9493 where_to_put_displacement = &opcode[1];
9494 break;
9495
9496 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9497 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9498 extension = 5; /* 2 opcode + 4 displacement */
9499 opcode[1] = opcode[0] + 0x10;
9500 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9501 where_to_put_displacement = &opcode[2];
9502 break;
9503
9504 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9505 extension = 3; /* 2 opcode + 2 displacement */
9506 opcode[1] = opcode[0] + 0x10;
9507 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9508 where_to_put_displacement = &opcode[2];
9509 break;
9510
9511 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9512 extension = 4;
9513 opcode[0] ^= 1;
9514 opcode[1] = 3;
9515 opcode[2] = 0xe9;
9516 where_to_put_displacement = &opcode[3];
9517 break;
9518
9519 default:
9520 BAD_CASE (fragP->fr_subtype);
9521 break;
9522 }
9523 }
9524
9525 /* If size if less then four we are sure that the operand fits,
9526 but if it's 4, then it could be that the displacement is larger
9527 then -/+ 2GB. */
9528 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9529 && object_64bit
9530 && ((addressT) (displacement_from_opcode_start - extension
9531 + ((addressT) 1 << 31))
9532 > (((addressT) 2 << 31) - 1)))
9533 {
9534 as_bad_where (fragP->fr_file, fragP->fr_line,
9535 _("jump target out of range"));
9536 /* Make us emit 0. */
9537 displacement_from_opcode_start = extension;
9538 }
9539 /* Now put displacement after opcode. */
9540 md_number_to_chars ((char *) where_to_put_displacement,
9541 (valueT) (displacement_from_opcode_start - extension),
9542 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9543 fragP->fr_fix += extension;
9544 }
9545 \f
9546 /* Apply a fixup (fixP) to segment data, once it has been determined
9547 by our caller that we have all the info we need to fix it up.
9548
9549 Parameter valP is the pointer to the value of the bits.
9550
9551 On the 386, immediates, displacements, and data pointers are all in
9552 the same (little-endian) format, so we don't need to care about which
9553 we are handling. */
9554
9555 void
9556 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9557 {
9558 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9559 valueT value = *valP;
9560
9561 #if !defined (TE_Mach)
9562 if (fixP->fx_pcrel)
9563 {
9564 switch (fixP->fx_r_type)
9565 {
9566 default:
9567 break;
9568
9569 case BFD_RELOC_64:
9570 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9571 break;
9572 case BFD_RELOC_32:
9573 case BFD_RELOC_X86_64_32S:
9574 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9575 break;
9576 case BFD_RELOC_16:
9577 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9578 break;
9579 case BFD_RELOC_8:
9580 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9581 break;
9582 }
9583 }
9584
9585 if (fixP->fx_addsy != NULL
9586 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9587 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9588 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9589 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9590 && !use_rela_relocations)
9591 {
9592 /* This is a hack. There should be a better way to handle this.
9593 This covers for the fact that bfd_install_relocation will
9594 subtract the current location (for partial_inplace, PC relative
9595 relocations); see more below. */
9596 #ifndef OBJ_AOUT
9597 if (IS_ELF
9598 #ifdef TE_PE
9599 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9600 #endif
9601 )
9602 value += fixP->fx_where + fixP->fx_frag->fr_address;
9603 #endif
9604 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9605 if (IS_ELF)
9606 {
9607 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9608
9609 if ((sym_seg == seg
9610 || (symbol_section_p (fixP->fx_addsy)
9611 && sym_seg != absolute_section))
9612 && !generic_force_reloc (fixP))
9613 {
9614 /* Yes, we add the values in twice. This is because
9615 bfd_install_relocation subtracts them out again. I think
9616 bfd_install_relocation is broken, but I don't dare change
9617 it. FIXME. */
9618 value += fixP->fx_where + fixP->fx_frag->fr_address;
9619 }
9620 }
9621 #endif
9622 #if defined (OBJ_COFF) && defined (TE_PE)
9623 /* For some reason, the PE format does not store a
9624 section address offset for a PC relative symbol. */
9625 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9626 || S_IS_WEAK (fixP->fx_addsy))
9627 value += md_pcrel_from (fixP);
9628 #endif
9629 }
9630 #if defined (OBJ_COFF) && defined (TE_PE)
9631 if (fixP->fx_addsy != NULL
9632 && S_IS_WEAK (fixP->fx_addsy)
9633 /* PR 16858: Do not modify weak function references. */
9634 && ! fixP->fx_pcrel)
9635 {
9636 #if !defined (TE_PEP)
9637 /* For x86 PE weak function symbols are neither PC-relative
9638 nor do they set S_IS_FUNCTION. So the only reliable way
9639 to detect them is to check the flags of their containing
9640 section. */
9641 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9642 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9643 ;
9644 else
9645 #endif
9646 value -= S_GET_VALUE (fixP->fx_addsy);
9647 }
9648 #endif
9649
9650 /* Fix a few things - the dynamic linker expects certain values here,
9651 and we must not disappoint it. */
9652 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9653 if (IS_ELF && fixP->fx_addsy)
9654 switch (fixP->fx_r_type)
9655 {
9656 case BFD_RELOC_386_PLT32:
9657 case BFD_RELOC_X86_64_PLT32:
9658 /* Make the jump instruction point to the address of the operand. At
9659 runtime we merely add the offset to the actual PLT entry. */
9660 value = -4;
9661 break;
9662
9663 case BFD_RELOC_386_TLS_GD:
9664 case BFD_RELOC_386_TLS_LDM:
9665 case BFD_RELOC_386_TLS_IE_32:
9666 case BFD_RELOC_386_TLS_IE:
9667 case BFD_RELOC_386_TLS_GOTIE:
9668 case BFD_RELOC_386_TLS_GOTDESC:
9669 case BFD_RELOC_X86_64_TLSGD:
9670 case BFD_RELOC_X86_64_TLSLD:
9671 case BFD_RELOC_X86_64_GOTTPOFF:
9672 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9673 value = 0; /* Fully resolved at runtime. No addend. */
9674 /* Fallthrough */
9675 case BFD_RELOC_386_TLS_LE:
9676 case BFD_RELOC_386_TLS_LDO_32:
9677 case BFD_RELOC_386_TLS_LE_32:
9678 case BFD_RELOC_X86_64_DTPOFF32:
9679 case BFD_RELOC_X86_64_DTPOFF64:
9680 case BFD_RELOC_X86_64_TPOFF32:
9681 case BFD_RELOC_X86_64_TPOFF64:
9682 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9683 break;
9684
9685 case BFD_RELOC_386_TLS_DESC_CALL:
9686 case BFD_RELOC_X86_64_TLSDESC_CALL:
9687 value = 0; /* Fully resolved at runtime. No addend. */
9688 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9689 fixP->fx_done = 0;
9690 return;
9691
9692 case BFD_RELOC_VTABLE_INHERIT:
9693 case BFD_RELOC_VTABLE_ENTRY:
9694 fixP->fx_done = 0;
9695 return;
9696
9697 default:
9698 break;
9699 }
9700 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9701 *valP = value;
9702 #endif /* !defined (TE_Mach) */
9703
9704 /* Are we finished with this relocation now? */
9705 if (fixP->fx_addsy == NULL)
9706 fixP->fx_done = 1;
9707 #if defined (OBJ_COFF) && defined (TE_PE)
9708 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9709 {
9710 fixP->fx_done = 0;
9711 /* Remember value for tc_gen_reloc. */
9712 fixP->fx_addnumber = value;
9713 /* Clear out the frag for now. */
9714 value = 0;
9715 }
9716 #endif
9717 else if (use_rela_relocations)
9718 {
9719 fixP->fx_no_overflow = 1;
9720 /* Remember value for tc_gen_reloc. */
9721 fixP->fx_addnumber = value;
9722 value = 0;
9723 }
9724
9725 md_number_to_chars (p, value, fixP->fx_size);
9726 }
9727 \f
9728 const char *
9729 md_atof (int type, char *litP, int *sizeP)
9730 {
9731 /* This outputs the LITTLENUMs in REVERSE order;
9732 in accord with the bigendian 386. */
9733 return ieee_md_atof (type, litP, sizeP, FALSE);
9734 }
9735 \f
9736 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9737
9738 static char *
9739 output_invalid (int c)
9740 {
9741 if (ISPRINT (c))
9742 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9743 "'%c'", c);
9744 else
9745 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9746 "(0x%x)", (unsigned char) c);
9747 return output_invalid_buf;
9748 }
9749
9750 /* REG_STRING starts *before* REGISTER_PREFIX. */
9751
9752 static const reg_entry *
9753 parse_real_register (char *reg_string, char **end_op)
9754 {
9755 char *s = reg_string;
9756 char *p;
9757 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9758 const reg_entry *r;
9759
9760 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9761 if (*s == REGISTER_PREFIX)
9762 ++s;
9763
9764 if (is_space_char (*s))
9765 ++s;
9766
9767 p = reg_name_given;
9768 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9769 {
9770 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9771 return (const reg_entry *) NULL;
9772 s++;
9773 }
9774
9775 /* For naked regs, make sure that we are not dealing with an identifier.
9776 This prevents confusing an identifier like `eax_var' with register
9777 `eax'. */
9778 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9779 return (const reg_entry *) NULL;
9780
9781 *end_op = s;
9782
9783 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9784
9785 /* Handle floating point regs, allowing spaces in the (i) part. */
9786 if (r == i386_regtab /* %st is first entry of table */)
9787 {
9788 if (is_space_char (*s))
9789 ++s;
9790 if (*s == '(')
9791 {
9792 ++s;
9793 if (is_space_char (*s))
9794 ++s;
9795 if (*s >= '0' && *s <= '7')
9796 {
9797 int fpr = *s - '0';
9798 ++s;
9799 if (is_space_char (*s))
9800 ++s;
9801 if (*s == ')')
9802 {
9803 *end_op = s + 1;
9804 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9805 know (r);
9806 return r + fpr;
9807 }
9808 }
9809 /* We have "%st(" then garbage. */
9810 return (const reg_entry *) NULL;
9811 }
9812 }
9813
9814 if (r == NULL || allow_pseudo_reg)
9815 return r;
9816
9817 if (operand_type_all_zero (&r->reg_type))
9818 return (const reg_entry *) NULL;
9819
9820 if ((r->reg_type.bitfield.reg32
9821 || r->reg_type.bitfield.sreg3
9822 || r->reg_type.bitfield.control
9823 || r->reg_type.bitfield.debug
9824 || r->reg_type.bitfield.test)
9825 && !cpu_arch_flags.bitfield.cpui386)
9826 return (const reg_entry *) NULL;
9827
9828 if (r->reg_type.bitfield.floatreg
9829 && !cpu_arch_flags.bitfield.cpu8087
9830 && !cpu_arch_flags.bitfield.cpu287
9831 && !cpu_arch_flags.bitfield.cpu387)
9832 return (const reg_entry *) NULL;
9833
9834 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
9835 return (const reg_entry *) NULL;
9836
9837 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
9838 return (const reg_entry *) NULL;
9839
9840 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
9841 return (const reg_entry *) NULL;
9842
9843 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9844 return (const reg_entry *) NULL;
9845
9846 if (r->reg_type.bitfield.regmask
9847 && !cpu_arch_flags.bitfield.cpuregmask)
9848 return (const reg_entry *) NULL;
9849
9850 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9851 if (!allow_index_reg
9852 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9853 return (const reg_entry *) NULL;
9854
9855 /* Upper 16 vector register is only available with VREX in 64bit
9856 mode. */
9857 if ((r->reg_flags & RegVRex))
9858 {
9859 if (i.vec_encoding == vex_encoding_default)
9860 i.vec_encoding = vex_encoding_evex;
9861
9862 if (!cpu_arch_flags.bitfield.cpuvrex
9863 || i.vec_encoding != vex_encoding_evex
9864 || flag_code != CODE_64BIT)
9865 return (const reg_entry *) NULL;
9866 }
9867
9868 if (((r->reg_flags & (RegRex64 | RegRex))
9869 || r->reg_type.bitfield.reg64)
9870 && (!cpu_arch_flags.bitfield.cpulm
9871 || !operand_type_equal (&r->reg_type, &control))
9872 && flag_code != CODE_64BIT)
9873 return (const reg_entry *) NULL;
9874
9875 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9876 return (const reg_entry *) NULL;
9877
9878 return r;
9879 }
9880
9881 /* REG_STRING starts *before* REGISTER_PREFIX. */
9882
9883 static const reg_entry *
9884 parse_register (char *reg_string, char **end_op)
9885 {
9886 const reg_entry *r;
9887
9888 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9889 r = parse_real_register (reg_string, end_op);
9890 else
9891 r = NULL;
9892 if (!r)
9893 {
9894 char *save = input_line_pointer;
9895 char c;
9896 symbolS *symbolP;
9897
9898 input_line_pointer = reg_string;
9899 c = get_symbol_name (&reg_string);
9900 symbolP = symbol_find (reg_string);
9901 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9902 {
9903 const expressionS *e = symbol_get_value_expression (symbolP);
9904
9905 know (e->X_op == O_register);
9906 know (e->X_add_number >= 0
9907 && (valueT) e->X_add_number < i386_regtab_size);
9908 r = i386_regtab + e->X_add_number;
9909 if ((r->reg_flags & RegVRex))
9910 i.vec_encoding = vex_encoding_evex;
9911 *end_op = input_line_pointer;
9912 }
9913 *input_line_pointer = c;
9914 input_line_pointer = save;
9915 }
9916 return r;
9917 }
9918
9919 int
9920 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9921 {
9922 const reg_entry *r;
9923 char *end = input_line_pointer;
9924
9925 *end = *nextcharP;
9926 r = parse_register (name, &input_line_pointer);
9927 if (r && end <= input_line_pointer)
9928 {
9929 *nextcharP = *input_line_pointer;
9930 *input_line_pointer = 0;
9931 e->X_op = O_register;
9932 e->X_add_number = r - i386_regtab;
9933 return 1;
9934 }
9935 input_line_pointer = end;
9936 *end = 0;
9937 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9938 }
9939
9940 void
9941 md_operand (expressionS *e)
9942 {
9943 char *end;
9944 const reg_entry *r;
9945
9946 switch (*input_line_pointer)
9947 {
9948 case REGISTER_PREFIX:
9949 r = parse_real_register (input_line_pointer, &end);
9950 if (r)
9951 {
9952 e->X_op = O_register;
9953 e->X_add_number = r - i386_regtab;
9954 input_line_pointer = end;
9955 }
9956 break;
9957
9958 case '[':
9959 gas_assert (intel_syntax);
9960 end = input_line_pointer++;
9961 expression (e);
9962 if (*input_line_pointer == ']')
9963 {
9964 ++input_line_pointer;
9965 e->X_op_symbol = make_expr_symbol (e);
9966 e->X_add_symbol = NULL;
9967 e->X_add_number = 0;
9968 e->X_op = O_index;
9969 }
9970 else
9971 {
9972 e->X_op = O_absent;
9973 input_line_pointer = end;
9974 }
9975 break;
9976 }
9977 }
9978
9979 \f
9980 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9981 const char *md_shortopts = "kVQ:sqn";
9982 #else
9983 const char *md_shortopts = "qn";
9984 #endif
9985
9986 #define OPTION_32 (OPTION_MD_BASE + 0)
9987 #define OPTION_64 (OPTION_MD_BASE + 1)
9988 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9989 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9990 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9991 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9992 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9993 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9994 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9995 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9996 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9997 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9998 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9999 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10000 #define OPTION_X32 (OPTION_MD_BASE + 14)
10001 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10002 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10003 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10004 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10005 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10006 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10007 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10008 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10009 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10010 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10011 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10012
10013 struct option md_longopts[] =
10014 {
10015 {"32", no_argument, NULL, OPTION_32},
10016 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10017 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10018 {"64", no_argument, NULL, OPTION_64},
10019 #endif
10020 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10021 {"x32", no_argument, NULL, OPTION_X32},
10022 {"mshared", no_argument, NULL, OPTION_MSHARED},
10023 #endif
10024 {"divide", no_argument, NULL, OPTION_DIVIDE},
10025 {"march", required_argument, NULL, OPTION_MARCH},
10026 {"mtune", required_argument, NULL, OPTION_MTUNE},
10027 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10028 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10029 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10030 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10031 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10032 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10033 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10034 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10035 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10036 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10037 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10038 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10039 # if defined (TE_PE) || defined (TE_PEP)
10040 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10041 #endif
10042 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10043 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10044 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10045 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10046 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10047 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10048 {NULL, no_argument, NULL, 0}
10049 };
10050 size_t md_longopts_size = sizeof (md_longopts);
10051
10052 int
10053 md_parse_option (int c, const char *arg)
10054 {
10055 unsigned int j;
10056 char *arch, *next, *saved;
10057
10058 switch (c)
10059 {
10060 case 'n':
10061 optimize_align_code = 0;
10062 break;
10063
10064 case 'q':
10065 quiet_warnings = 1;
10066 break;
10067
10068 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10069 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10070 should be emitted or not. FIXME: Not implemented. */
10071 case 'Q':
10072 break;
10073
10074 /* -V: SVR4 argument to print version ID. */
10075 case 'V':
10076 print_version_id ();
10077 break;
10078
10079 /* -k: Ignore for FreeBSD compatibility. */
10080 case 'k':
10081 break;
10082
10083 case 's':
10084 /* -s: On i386 Solaris, this tells the native assembler to use
10085 .stab instead of .stab.excl. We always use .stab anyhow. */
10086 break;
10087
10088 case OPTION_MSHARED:
10089 shared = 1;
10090 break;
10091 #endif
10092 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10093 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10094 case OPTION_64:
10095 {
10096 const char **list, **l;
10097
10098 list = bfd_target_list ();
10099 for (l = list; *l != NULL; l++)
10100 if (CONST_STRNEQ (*l, "elf64-x86-64")
10101 || strcmp (*l, "coff-x86-64") == 0
10102 || strcmp (*l, "pe-x86-64") == 0
10103 || strcmp (*l, "pei-x86-64") == 0
10104 || strcmp (*l, "mach-o-x86-64") == 0)
10105 {
10106 default_arch = "x86_64";
10107 break;
10108 }
10109 if (*l == NULL)
10110 as_fatal (_("no compiled in support for x86_64"));
10111 free (list);
10112 }
10113 break;
10114 #endif
10115
10116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10117 case OPTION_X32:
10118 if (IS_ELF)
10119 {
10120 const char **list, **l;
10121
10122 list = bfd_target_list ();
10123 for (l = list; *l != NULL; l++)
10124 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10125 {
10126 default_arch = "x86_64:32";
10127 break;
10128 }
10129 if (*l == NULL)
10130 as_fatal (_("no compiled in support for 32bit x86_64"));
10131 free (list);
10132 }
10133 else
10134 as_fatal (_("32bit x86_64 is only supported for ELF"));
10135 break;
10136 #endif
10137
10138 case OPTION_32:
10139 default_arch = "i386";
10140 break;
10141
10142 case OPTION_DIVIDE:
10143 #ifdef SVR4_COMMENT_CHARS
10144 {
10145 char *n, *t;
10146 const char *s;
10147
10148 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10149 t = n;
10150 for (s = i386_comment_chars; *s != '\0'; s++)
10151 if (*s != '/')
10152 *t++ = *s;
10153 *t = '\0';
10154 i386_comment_chars = n;
10155 }
10156 #endif
10157 break;
10158
10159 case OPTION_MARCH:
10160 saved = xstrdup (arg);
10161 arch = saved;
10162 /* Allow -march=+nosse. */
10163 if (*arch == '+')
10164 arch++;
10165 do
10166 {
10167 if (*arch == '.')
10168 as_fatal (_("invalid -march= option: `%s'"), arg);
10169 next = strchr (arch, '+');
10170 if (next)
10171 *next++ = '\0';
10172 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10173 {
10174 if (strcmp (arch, cpu_arch [j].name) == 0)
10175 {
10176 /* Processor. */
10177 if (! cpu_arch[j].flags.bitfield.cpui386)
10178 continue;
10179
10180 cpu_arch_name = cpu_arch[j].name;
10181 cpu_sub_arch_name = NULL;
10182 cpu_arch_flags = cpu_arch[j].flags;
10183 cpu_arch_isa = cpu_arch[j].type;
10184 cpu_arch_isa_flags = cpu_arch[j].flags;
10185 if (!cpu_arch_tune_set)
10186 {
10187 cpu_arch_tune = cpu_arch_isa;
10188 cpu_arch_tune_flags = cpu_arch_isa_flags;
10189 }
10190 break;
10191 }
10192 else if (*cpu_arch [j].name == '.'
10193 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10194 {
10195 /* ISA extension. */
10196 i386_cpu_flags flags;
10197
10198 flags = cpu_flags_or (cpu_arch_flags,
10199 cpu_arch[j].flags);
10200
10201 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10202 {
10203 if (cpu_sub_arch_name)
10204 {
10205 char *name = cpu_sub_arch_name;
10206 cpu_sub_arch_name = concat (name,
10207 cpu_arch[j].name,
10208 (const char *) NULL);
10209 free (name);
10210 }
10211 else
10212 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10213 cpu_arch_flags = flags;
10214 cpu_arch_isa_flags = flags;
10215 }
10216 break;
10217 }
10218 }
10219
10220 if (j >= ARRAY_SIZE (cpu_arch))
10221 {
10222 /* Disable an ISA extension. */
10223 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10224 if (strcmp (arch, cpu_noarch [j].name) == 0)
10225 {
10226 i386_cpu_flags flags;
10227
10228 flags = cpu_flags_and_not (cpu_arch_flags,
10229 cpu_noarch[j].flags);
10230 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10231 {
10232 if (cpu_sub_arch_name)
10233 {
10234 char *name = cpu_sub_arch_name;
10235 cpu_sub_arch_name = concat (arch,
10236 (const char *) NULL);
10237 free (name);
10238 }
10239 else
10240 cpu_sub_arch_name = xstrdup (arch);
10241 cpu_arch_flags = flags;
10242 cpu_arch_isa_flags = flags;
10243 }
10244 break;
10245 }
10246
10247 if (j >= ARRAY_SIZE (cpu_noarch))
10248 j = ARRAY_SIZE (cpu_arch);
10249 }
10250
10251 if (j >= ARRAY_SIZE (cpu_arch))
10252 as_fatal (_("invalid -march= option: `%s'"), arg);
10253
10254 arch = next;
10255 }
10256 while (next != NULL);
10257 free (saved);
10258 break;
10259
10260 case OPTION_MTUNE:
10261 if (*arg == '.')
10262 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10263 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10264 {
10265 if (strcmp (arg, cpu_arch [j].name) == 0)
10266 {
10267 cpu_arch_tune_set = 1;
10268 cpu_arch_tune = cpu_arch [j].type;
10269 cpu_arch_tune_flags = cpu_arch[j].flags;
10270 break;
10271 }
10272 }
10273 if (j >= ARRAY_SIZE (cpu_arch))
10274 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10275 break;
10276
10277 case OPTION_MMNEMONIC:
10278 if (strcasecmp (arg, "att") == 0)
10279 intel_mnemonic = 0;
10280 else if (strcasecmp (arg, "intel") == 0)
10281 intel_mnemonic = 1;
10282 else
10283 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10284 break;
10285
10286 case OPTION_MSYNTAX:
10287 if (strcasecmp (arg, "att") == 0)
10288 intel_syntax = 0;
10289 else if (strcasecmp (arg, "intel") == 0)
10290 intel_syntax = 1;
10291 else
10292 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10293 break;
10294
10295 case OPTION_MINDEX_REG:
10296 allow_index_reg = 1;
10297 break;
10298
10299 case OPTION_MNAKED_REG:
10300 allow_naked_reg = 1;
10301 break;
10302
10303 case OPTION_MOLD_GCC:
10304 old_gcc = 1;
10305 break;
10306
10307 case OPTION_MSSE2AVX:
10308 sse2avx = 1;
10309 break;
10310
10311 case OPTION_MSSE_CHECK:
10312 if (strcasecmp (arg, "error") == 0)
10313 sse_check = check_error;
10314 else if (strcasecmp (arg, "warning") == 0)
10315 sse_check = check_warning;
10316 else if (strcasecmp (arg, "none") == 0)
10317 sse_check = check_none;
10318 else
10319 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10320 break;
10321
10322 case OPTION_MOPERAND_CHECK:
10323 if (strcasecmp (arg, "error") == 0)
10324 operand_check = check_error;
10325 else if (strcasecmp (arg, "warning") == 0)
10326 operand_check = check_warning;
10327 else if (strcasecmp (arg, "none") == 0)
10328 operand_check = check_none;
10329 else
10330 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10331 break;
10332
10333 case OPTION_MAVXSCALAR:
10334 if (strcasecmp (arg, "128") == 0)
10335 avxscalar = vex128;
10336 else if (strcasecmp (arg, "256") == 0)
10337 avxscalar = vex256;
10338 else
10339 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10340 break;
10341
10342 case OPTION_MADD_BND_PREFIX:
10343 add_bnd_prefix = 1;
10344 break;
10345
10346 case OPTION_MEVEXLIG:
10347 if (strcmp (arg, "128") == 0)
10348 evexlig = evexl128;
10349 else if (strcmp (arg, "256") == 0)
10350 evexlig = evexl256;
10351 else if (strcmp (arg, "512") == 0)
10352 evexlig = evexl512;
10353 else
10354 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10355 break;
10356
10357 case OPTION_MEVEXRCIG:
10358 if (strcmp (arg, "rne") == 0)
10359 evexrcig = rne;
10360 else if (strcmp (arg, "rd") == 0)
10361 evexrcig = rd;
10362 else if (strcmp (arg, "ru") == 0)
10363 evexrcig = ru;
10364 else if (strcmp (arg, "rz") == 0)
10365 evexrcig = rz;
10366 else
10367 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10368 break;
10369
10370 case OPTION_MEVEXWIG:
10371 if (strcmp (arg, "0") == 0)
10372 evexwig = evexw0;
10373 else if (strcmp (arg, "1") == 0)
10374 evexwig = evexw1;
10375 else
10376 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10377 break;
10378
10379 # if defined (TE_PE) || defined (TE_PEP)
10380 case OPTION_MBIG_OBJ:
10381 use_big_obj = 1;
10382 break;
10383 #endif
10384
10385 case OPTION_MOMIT_LOCK_PREFIX:
10386 if (strcasecmp (arg, "yes") == 0)
10387 omit_lock_prefix = 1;
10388 else if (strcasecmp (arg, "no") == 0)
10389 omit_lock_prefix = 0;
10390 else
10391 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10392 break;
10393
10394 case OPTION_MFENCE_AS_LOCK_ADD:
10395 if (strcasecmp (arg, "yes") == 0)
10396 avoid_fence = 1;
10397 else if (strcasecmp (arg, "no") == 0)
10398 avoid_fence = 0;
10399 else
10400 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10401 break;
10402
10403 case OPTION_MRELAX_RELOCATIONS:
10404 if (strcasecmp (arg, "yes") == 0)
10405 generate_relax_relocations = 1;
10406 else if (strcasecmp (arg, "no") == 0)
10407 generate_relax_relocations = 0;
10408 else
10409 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10410 break;
10411
10412 case OPTION_MAMD64:
10413 intel64 = 0;
10414 break;
10415
10416 case OPTION_MINTEL64:
10417 intel64 = 1;
10418 break;
10419
10420 default:
10421 return 0;
10422 }
10423 return 1;
10424 }
10425
10426 #define MESSAGE_TEMPLATE \
10427 " "
10428
10429 static char *
10430 output_message (FILE *stream, char *p, char *message, char *start,
10431 int *left_p, const char *name, int len)
10432 {
10433 int size = sizeof (MESSAGE_TEMPLATE);
10434 int left = *left_p;
10435
10436 /* Reserve 2 spaces for ", " or ",\0" */
10437 left -= len + 2;
10438
10439 /* Check if there is any room. */
10440 if (left >= 0)
10441 {
10442 if (p != start)
10443 {
10444 *p++ = ',';
10445 *p++ = ' ';
10446 }
10447 p = mempcpy (p, name, len);
10448 }
10449 else
10450 {
10451 /* Output the current message now and start a new one. */
10452 *p++ = ',';
10453 *p = '\0';
10454 fprintf (stream, "%s\n", message);
10455 p = start;
10456 left = size - (start - message) - len - 2;
10457
10458 gas_assert (left >= 0);
10459
10460 p = mempcpy (p, name, len);
10461 }
10462
10463 *left_p = left;
10464 return p;
10465 }
10466
10467 static void
10468 show_arch (FILE *stream, int ext, int check)
10469 {
10470 static char message[] = MESSAGE_TEMPLATE;
10471 char *start = message + 27;
10472 char *p;
10473 int size = sizeof (MESSAGE_TEMPLATE);
10474 int left;
10475 const char *name;
10476 int len;
10477 unsigned int j;
10478
10479 p = start;
10480 left = size - (start - message);
10481 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10482 {
10483 /* Should it be skipped? */
10484 if (cpu_arch [j].skip)
10485 continue;
10486
10487 name = cpu_arch [j].name;
10488 len = cpu_arch [j].len;
10489 if (*name == '.')
10490 {
10491 /* It is an extension. Skip if we aren't asked to show it. */
10492 if (ext)
10493 {
10494 name++;
10495 len--;
10496 }
10497 else
10498 continue;
10499 }
10500 else if (ext)
10501 {
10502 /* It is an processor. Skip if we show only extension. */
10503 continue;
10504 }
10505 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10506 {
10507 /* It is an impossible processor - skip. */
10508 continue;
10509 }
10510
10511 p = output_message (stream, p, message, start, &left, name, len);
10512 }
10513
10514 /* Display disabled extensions. */
10515 if (ext)
10516 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10517 {
10518 name = cpu_noarch [j].name;
10519 len = cpu_noarch [j].len;
10520 p = output_message (stream, p, message, start, &left, name,
10521 len);
10522 }
10523
10524 *p = '\0';
10525 fprintf (stream, "%s\n", message);
10526 }
10527
10528 void
10529 md_show_usage (FILE *stream)
10530 {
10531 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10532 fprintf (stream, _("\
10533 -Q ignored\n\
10534 -V print assembler version number\n\
10535 -k ignored\n"));
10536 #endif
10537 fprintf (stream, _("\
10538 -n Do not optimize code alignment\n\
10539 -q quieten some warnings\n"));
10540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10541 fprintf (stream, _("\
10542 -s ignored\n"));
10543 #endif
10544 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10545 || defined (TE_PE) || defined (TE_PEP))
10546 fprintf (stream, _("\
10547 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10548 #endif
10549 #ifdef SVR4_COMMENT_CHARS
10550 fprintf (stream, _("\
10551 --divide do not treat `/' as a comment character\n"));
10552 #else
10553 fprintf (stream, _("\
10554 --divide ignored\n"));
10555 #endif
10556 fprintf (stream, _("\
10557 -march=CPU[,+EXTENSION...]\n\
10558 generate code for CPU and EXTENSION, CPU is one of:\n"));
10559 show_arch (stream, 0, 1);
10560 fprintf (stream, _("\
10561 EXTENSION is combination of:\n"));
10562 show_arch (stream, 1, 0);
10563 fprintf (stream, _("\
10564 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10565 show_arch (stream, 0, 0);
10566 fprintf (stream, _("\
10567 -msse2avx encode SSE instructions with VEX prefix\n"));
10568 fprintf (stream, _("\
10569 -msse-check=[none|error|warning]\n\
10570 check SSE instructions\n"));
10571 fprintf (stream, _("\
10572 -moperand-check=[none|error|warning]\n\
10573 check operand combinations for validity\n"));
10574 fprintf (stream, _("\
10575 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10576 length\n"));
10577 fprintf (stream, _("\
10578 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10579 length\n"));
10580 fprintf (stream, _("\
10581 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10582 for EVEX.W bit ignored instructions\n"));
10583 fprintf (stream, _("\
10584 -mevexrcig=[rne|rd|ru|rz]\n\
10585 encode EVEX instructions with specific EVEX.RC value\n\
10586 for SAE-only ignored instructions\n"));
10587 fprintf (stream, _("\
10588 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10589 fprintf (stream, _("\
10590 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10591 fprintf (stream, _("\
10592 -mindex-reg support pseudo index registers\n"));
10593 fprintf (stream, _("\
10594 -mnaked-reg don't require `%%' prefix for registers\n"));
10595 fprintf (stream, _("\
10596 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10597 fprintf (stream, _("\
10598 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10599 fprintf (stream, _("\
10600 -mshared disable branch optimization for shared code\n"));
10601 # if defined (TE_PE) || defined (TE_PEP)
10602 fprintf (stream, _("\
10603 -mbig-obj generate big object files\n"));
10604 #endif
10605 fprintf (stream, _("\
10606 -momit-lock-prefix=[no|yes]\n\
10607 strip all lock prefixes\n"));
10608 fprintf (stream, _("\
10609 -mfence-as-lock-add=[no|yes]\n\
10610 encode lfence, mfence and sfence as\n\
10611 lock addl $0x0, (%%{re}sp)\n"));
10612 fprintf (stream, _("\
10613 -mrelax-relocations=[no|yes]\n\
10614 generate relax relocations\n"));
10615 fprintf (stream, _("\
10616 -mamd64 accept only AMD64 ISA\n"));
10617 fprintf (stream, _("\
10618 -mintel64 accept only Intel64 ISA\n"));
10619 }
10620
10621 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10622 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10623 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10624
10625 /* Pick the target format to use. */
10626
10627 const char *
10628 i386_target_format (void)
10629 {
10630 if (!strncmp (default_arch, "x86_64", 6))
10631 {
10632 update_code_flag (CODE_64BIT, 1);
10633 if (default_arch[6] == '\0')
10634 x86_elf_abi = X86_64_ABI;
10635 else
10636 x86_elf_abi = X86_64_X32_ABI;
10637 }
10638 else if (!strcmp (default_arch, "i386"))
10639 update_code_flag (CODE_32BIT, 1);
10640 else if (!strcmp (default_arch, "iamcu"))
10641 {
10642 update_code_flag (CODE_32BIT, 1);
10643 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10644 {
10645 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10646 cpu_arch_name = "iamcu";
10647 cpu_sub_arch_name = NULL;
10648 cpu_arch_flags = iamcu_flags;
10649 cpu_arch_isa = PROCESSOR_IAMCU;
10650 cpu_arch_isa_flags = iamcu_flags;
10651 if (!cpu_arch_tune_set)
10652 {
10653 cpu_arch_tune = cpu_arch_isa;
10654 cpu_arch_tune_flags = cpu_arch_isa_flags;
10655 }
10656 }
10657 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10658 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10659 cpu_arch_name);
10660 }
10661 else
10662 as_fatal (_("unknown architecture"));
10663
10664 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10665 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10666 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10667 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10668
10669 switch (OUTPUT_FLAVOR)
10670 {
10671 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10672 case bfd_target_aout_flavour:
10673 return AOUT_TARGET_FORMAT;
10674 #endif
10675 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10676 # if defined (TE_PE) || defined (TE_PEP)
10677 case bfd_target_coff_flavour:
10678 if (flag_code == CODE_64BIT)
10679 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10680 else
10681 return "pe-i386";
10682 # elif defined (TE_GO32)
10683 case bfd_target_coff_flavour:
10684 return "coff-go32";
10685 # else
10686 case bfd_target_coff_flavour:
10687 return "coff-i386";
10688 # endif
10689 #endif
10690 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10691 case bfd_target_elf_flavour:
10692 {
10693 const char *format;
10694
10695 switch (x86_elf_abi)
10696 {
10697 default:
10698 format = ELF_TARGET_FORMAT;
10699 break;
10700 case X86_64_ABI:
10701 use_rela_relocations = 1;
10702 object_64bit = 1;
10703 format = ELF_TARGET_FORMAT64;
10704 break;
10705 case X86_64_X32_ABI:
10706 use_rela_relocations = 1;
10707 object_64bit = 1;
10708 disallow_64bit_reloc = 1;
10709 format = ELF_TARGET_FORMAT32;
10710 break;
10711 }
10712 if (cpu_arch_isa == PROCESSOR_L1OM)
10713 {
10714 if (x86_elf_abi != X86_64_ABI)
10715 as_fatal (_("Intel L1OM is 64bit only"));
10716 return ELF_TARGET_L1OM_FORMAT;
10717 }
10718 else if (cpu_arch_isa == PROCESSOR_K1OM)
10719 {
10720 if (x86_elf_abi != X86_64_ABI)
10721 as_fatal (_("Intel K1OM is 64bit only"));
10722 return ELF_TARGET_K1OM_FORMAT;
10723 }
10724 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10725 {
10726 if (x86_elf_abi != I386_ABI)
10727 as_fatal (_("Intel MCU is 32bit only"));
10728 return ELF_TARGET_IAMCU_FORMAT;
10729 }
10730 else
10731 return format;
10732 }
10733 #endif
10734 #if defined (OBJ_MACH_O)
10735 case bfd_target_mach_o_flavour:
10736 if (flag_code == CODE_64BIT)
10737 {
10738 use_rela_relocations = 1;
10739 object_64bit = 1;
10740 return "mach-o-x86-64";
10741 }
10742 else
10743 return "mach-o-i386";
10744 #endif
10745 default:
10746 abort ();
10747 return NULL;
10748 }
10749 }
10750
10751 #endif /* OBJ_MAYBE_ more than one */
10752 \f
10753 symbolS *
10754 md_undefined_symbol (char *name)
10755 {
10756 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10757 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10758 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10759 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10760 {
10761 if (!GOT_symbol)
10762 {
10763 if (symbol_find (name))
10764 as_bad (_("GOT already in symbol table"));
10765 GOT_symbol = symbol_new (name, undefined_section,
10766 (valueT) 0, &zero_address_frag);
10767 };
10768 return GOT_symbol;
10769 }
10770 return 0;
10771 }
10772
10773 /* Round up a section size to the appropriate boundary. */
10774
10775 valueT
10776 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10777 {
10778 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10779 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10780 {
10781 /* For a.out, force the section size to be aligned. If we don't do
10782 this, BFD will align it for us, but it will not write out the
10783 final bytes of the section. This may be a bug in BFD, but it is
10784 easier to fix it here since that is how the other a.out targets
10785 work. */
10786 int align;
10787
10788 align = bfd_get_section_alignment (stdoutput, segment);
10789 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
10790 }
10791 #endif
10792
10793 return size;
10794 }
10795
10796 /* On the i386, PC-relative offsets are relative to the start of the
10797 next instruction. That is, the address of the offset, plus its
10798 size, since the offset is always the last part of the insn. */
10799
10800 long
10801 md_pcrel_from (fixS *fixP)
10802 {
10803 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10804 }
10805
10806 #ifndef I386COFF
10807
10808 static void
10809 s_bss (int ignore ATTRIBUTE_UNUSED)
10810 {
10811 int temp;
10812
10813 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10814 if (IS_ELF)
10815 obj_elf_section_change_hook ();
10816 #endif
10817 temp = get_absolute_expression ();
10818 subseg_set (bss_section, (subsegT) temp);
10819 demand_empty_rest_of_line ();
10820 }
10821
10822 #endif
10823
10824 void
10825 i386_validate_fix (fixS *fixp)
10826 {
10827 if (fixp->fx_subsy)
10828 {
10829 if (fixp->fx_subsy == GOT_symbol)
10830 {
10831 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10832 {
10833 if (!object_64bit)
10834 abort ();
10835 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10836 if (fixp->fx_tcbit2)
10837 fixp->fx_r_type = (fixp->fx_tcbit
10838 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10839 : BFD_RELOC_X86_64_GOTPCRELX);
10840 else
10841 #endif
10842 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10843 }
10844 else
10845 {
10846 if (!object_64bit)
10847 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10848 else
10849 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10850 }
10851 fixp->fx_subsy = 0;
10852 }
10853 }
10854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10855 else if (!object_64bit)
10856 {
10857 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10858 && fixp->fx_tcbit2)
10859 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10860 }
10861 #endif
10862 }
10863
10864 arelent *
10865 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10866 {
10867 arelent *rel;
10868 bfd_reloc_code_real_type code;
10869
10870 switch (fixp->fx_r_type)
10871 {
10872 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10873 case BFD_RELOC_SIZE32:
10874 case BFD_RELOC_SIZE64:
10875 if (S_IS_DEFINED (fixp->fx_addsy)
10876 && !S_IS_EXTERNAL (fixp->fx_addsy))
10877 {
10878 /* Resolve size relocation against local symbol to size of
10879 the symbol plus addend. */
10880 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10881 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10882 && !fits_in_unsigned_long (value))
10883 as_bad_where (fixp->fx_file, fixp->fx_line,
10884 _("symbol size computation overflow"));
10885 fixp->fx_addsy = NULL;
10886 fixp->fx_subsy = NULL;
10887 md_apply_fix (fixp, (valueT *) &value, NULL);
10888 return NULL;
10889 }
10890 #endif
10891 /* Fall through. */
10892
10893 case BFD_RELOC_X86_64_PLT32:
10894 case BFD_RELOC_X86_64_GOT32:
10895 case BFD_RELOC_X86_64_GOTPCREL:
10896 case BFD_RELOC_X86_64_GOTPCRELX:
10897 case BFD_RELOC_X86_64_REX_GOTPCRELX:
10898 case BFD_RELOC_386_PLT32:
10899 case BFD_RELOC_386_GOT32:
10900 case BFD_RELOC_386_GOT32X:
10901 case BFD_RELOC_386_GOTOFF:
10902 case BFD_RELOC_386_GOTPC:
10903 case BFD_RELOC_386_TLS_GD:
10904 case BFD_RELOC_386_TLS_LDM:
10905 case BFD_RELOC_386_TLS_LDO_32:
10906 case BFD_RELOC_386_TLS_IE_32:
10907 case BFD_RELOC_386_TLS_IE:
10908 case BFD_RELOC_386_TLS_GOTIE:
10909 case BFD_RELOC_386_TLS_LE_32:
10910 case BFD_RELOC_386_TLS_LE:
10911 case BFD_RELOC_386_TLS_GOTDESC:
10912 case BFD_RELOC_386_TLS_DESC_CALL:
10913 case BFD_RELOC_X86_64_TLSGD:
10914 case BFD_RELOC_X86_64_TLSLD:
10915 case BFD_RELOC_X86_64_DTPOFF32:
10916 case BFD_RELOC_X86_64_DTPOFF64:
10917 case BFD_RELOC_X86_64_GOTTPOFF:
10918 case BFD_RELOC_X86_64_TPOFF32:
10919 case BFD_RELOC_X86_64_TPOFF64:
10920 case BFD_RELOC_X86_64_GOTOFF64:
10921 case BFD_RELOC_X86_64_GOTPC32:
10922 case BFD_RELOC_X86_64_GOT64:
10923 case BFD_RELOC_X86_64_GOTPCREL64:
10924 case BFD_RELOC_X86_64_GOTPC64:
10925 case BFD_RELOC_X86_64_GOTPLT64:
10926 case BFD_RELOC_X86_64_PLTOFF64:
10927 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10928 case BFD_RELOC_X86_64_TLSDESC_CALL:
10929 case BFD_RELOC_RVA:
10930 case BFD_RELOC_VTABLE_ENTRY:
10931 case BFD_RELOC_VTABLE_INHERIT:
10932 #ifdef TE_PE
10933 case BFD_RELOC_32_SECREL:
10934 #endif
10935 code = fixp->fx_r_type;
10936 break;
10937 case BFD_RELOC_X86_64_32S:
10938 if (!fixp->fx_pcrel)
10939 {
10940 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10941 code = fixp->fx_r_type;
10942 break;
10943 }
10944 /* Fall through. */
10945 default:
10946 if (fixp->fx_pcrel)
10947 {
10948 switch (fixp->fx_size)
10949 {
10950 default:
10951 as_bad_where (fixp->fx_file, fixp->fx_line,
10952 _("can not do %d byte pc-relative relocation"),
10953 fixp->fx_size);
10954 code = BFD_RELOC_32_PCREL;
10955 break;
10956 case 1: code = BFD_RELOC_8_PCREL; break;
10957 case 2: code = BFD_RELOC_16_PCREL; break;
10958 case 4: code = BFD_RELOC_32_PCREL; break;
10959 #ifdef BFD64
10960 case 8: code = BFD_RELOC_64_PCREL; break;
10961 #endif
10962 }
10963 }
10964 else
10965 {
10966 switch (fixp->fx_size)
10967 {
10968 default:
10969 as_bad_where (fixp->fx_file, fixp->fx_line,
10970 _("can not do %d byte relocation"),
10971 fixp->fx_size);
10972 code = BFD_RELOC_32;
10973 break;
10974 case 1: code = BFD_RELOC_8; break;
10975 case 2: code = BFD_RELOC_16; break;
10976 case 4: code = BFD_RELOC_32; break;
10977 #ifdef BFD64
10978 case 8: code = BFD_RELOC_64; break;
10979 #endif
10980 }
10981 }
10982 break;
10983 }
10984
10985 if ((code == BFD_RELOC_32
10986 || code == BFD_RELOC_32_PCREL
10987 || code == BFD_RELOC_X86_64_32S)
10988 && GOT_symbol
10989 && fixp->fx_addsy == GOT_symbol)
10990 {
10991 if (!object_64bit)
10992 code = BFD_RELOC_386_GOTPC;
10993 else
10994 code = BFD_RELOC_X86_64_GOTPC32;
10995 }
10996 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10997 && GOT_symbol
10998 && fixp->fx_addsy == GOT_symbol)
10999 {
11000 code = BFD_RELOC_X86_64_GOTPC64;
11001 }
11002
11003 rel = XNEW (arelent);
11004 rel->sym_ptr_ptr = XNEW (asymbol *);
11005 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11006
11007 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11008
11009 if (!use_rela_relocations)
11010 {
11011 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11012 vtable entry to be used in the relocation's section offset. */
11013 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11014 rel->address = fixp->fx_offset;
11015 #if defined (OBJ_COFF) && defined (TE_PE)
11016 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11017 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11018 else
11019 #endif
11020 rel->addend = 0;
11021 }
11022 /* Use the rela in 64bit mode. */
11023 else
11024 {
11025 if (disallow_64bit_reloc)
11026 switch (code)
11027 {
11028 case BFD_RELOC_X86_64_DTPOFF64:
11029 case BFD_RELOC_X86_64_TPOFF64:
11030 case BFD_RELOC_64_PCREL:
11031 case BFD_RELOC_X86_64_GOTOFF64:
11032 case BFD_RELOC_X86_64_GOT64:
11033 case BFD_RELOC_X86_64_GOTPCREL64:
11034 case BFD_RELOC_X86_64_GOTPC64:
11035 case BFD_RELOC_X86_64_GOTPLT64:
11036 case BFD_RELOC_X86_64_PLTOFF64:
11037 as_bad_where (fixp->fx_file, fixp->fx_line,
11038 _("cannot represent relocation type %s in x32 mode"),
11039 bfd_get_reloc_code_name (code));
11040 break;
11041 default:
11042 break;
11043 }
11044
11045 if (!fixp->fx_pcrel)
11046 rel->addend = fixp->fx_offset;
11047 else
11048 switch (code)
11049 {
11050 case BFD_RELOC_X86_64_PLT32:
11051 case BFD_RELOC_X86_64_GOT32:
11052 case BFD_RELOC_X86_64_GOTPCREL:
11053 case BFD_RELOC_X86_64_GOTPCRELX:
11054 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11055 case BFD_RELOC_X86_64_TLSGD:
11056 case BFD_RELOC_X86_64_TLSLD:
11057 case BFD_RELOC_X86_64_GOTTPOFF:
11058 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11059 case BFD_RELOC_X86_64_TLSDESC_CALL:
11060 rel->addend = fixp->fx_offset - fixp->fx_size;
11061 break;
11062 default:
11063 rel->addend = (section->vma
11064 - fixp->fx_size
11065 + fixp->fx_addnumber
11066 + md_pcrel_from (fixp));
11067 break;
11068 }
11069 }
11070
11071 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11072 if (rel->howto == NULL)
11073 {
11074 as_bad_where (fixp->fx_file, fixp->fx_line,
11075 _("cannot represent relocation type %s"),
11076 bfd_get_reloc_code_name (code));
11077 /* Set howto to a garbage value so that we can keep going. */
11078 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11079 gas_assert (rel->howto != NULL);
11080 }
11081
11082 return rel;
11083 }
11084
11085 #include "tc-i386-intel.c"
11086
11087 void
11088 tc_x86_parse_to_dw2regnum (expressionS *exp)
11089 {
11090 int saved_naked_reg;
11091 char saved_register_dot;
11092
11093 saved_naked_reg = allow_naked_reg;
11094 allow_naked_reg = 1;
11095 saved_register_dot = register_chars['.'];
11096 register_chars['.'] = '.';
11097 allow_pseudo_reg = 1;
11098 expression_and_evaluate (exp);
11099 allow_pseudo_reg = 0;
11100 register_chars['.'] = saved_register_dot;
11101 allow_naked_reg = saved_naked_reg;
11102
11103 if (exp->X_op == O_register && exp->X_add_number >= 0)
11104 {
11105 if ((addressT) exp->X_add_number < i386_regtab_size)
11106 {
11107 exp->X_op = O_constant;
11108 exp->X_add_number = i386_regtab[exp->X_add_number]
11109 .dw2_regnum[flag_code >> 1];
11110 }
11111 else
11112 exp->X_op = O_illegal;
11113 }
11114 }
11115
11116 void
11117 tc_x86_frame_initial_instructions (void)
11118 {
11119 static unsigned int sp_regno[2];
11120
11121 if (!sp_regno[flag_code >> 1])
11122 {
11123 char *saved_input = input_line_pointer;
11124 char sp[][4] = {"esp", "rsp"};
11125 expressionS exp;
11126
11127 input_line_pointer = sp[flag_code >> 1];
11128 tc_x86_parse_to_dw2regnum (&exp);
11129 gas_assert (exp.X_op == O_constant);
11130 sp_regno[flag_code >> 1] = exp.X_add_number;
11131 input_line_pointer = saved_input;
11132 }
11133
11134 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11135 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11136 }
11137
11138 int
11139 x86_dwarf2_addr_size (void)
11140 {
11141 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11142 if (x86_elf_abi == X86_64_X32_ABI)
11143 return 4;
11144 #endif
11145 return bfd_arch_bits_per_address (stdoutput) / 8;
11146 }
11147
11148 int
11149 i386_elf_section_type (const char *str, size_t len)
11150 {
11151 if (flag_code == CODE_64BIT
11152 && len == sizeof ("unwind") - 1
11153 && strncmp (str, "unwind", 6) == 0)
11154 return SHT_X86_64_UNWIND;
11155
11156 return -1;
11157 }
11158
11159 #ifdef TE_SOLARIS
11160 void
11161 i386_solaris_fix_up_eh_frame (segT sec)
11162 {
11163 if (flag_code == CODE_64BIT)
11164 elf_section_type (sec) = SHT_X86_64_UNWIND;
11165 }
11166 #endif
11167
11168 #ifdef TE_PE
11169 void
11170 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11171 {
11172 expressionS exp;
11173
11174 exp.X_op = O_secrel;
11175 exp.X_add_symbol = symbol;
11176 exp.X_add_number = 0;
11177 emit_expr (&exp, size);
11178 }
11179 #endif
11180
11181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11182 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11183
11184 bfd_vma
11185 x86_64_section_letter (int letter, const char **ptr_msg)
11186 {
11187 if (flag_code == CODE_64BIT)
11188 {
11189 if (letter == 'l')
11190 return SHF_X86_64_LARGE;
11191
11192 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11193 }
11194 else
11195 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11196 return -1;
11197 }
11198
11199 bfd_vma
11200 x86_64_section_word (char *str, size_t len)
11201 {
11202 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11203 return SHF_X86_64_LARGE;
11204
11205 return -1;
11206 }
11207
11208 static void
11209 handle_large_common (int small ATTRIBUTE_UNUSED)
11210 {
11211 if (flag_code != CODE_64BIT)
11212 {
11213 s_comm_internal (0, elf_common_parse);
11214 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11215 }
11216 else
11217 {
11218 static segT lbss_section;
11219 asection *saved_com_section_ptr = elf_com_section_ptr;
11220 asection *saved_bss_section = bss_section;
11221
11222 if (lbss_section == NULL)
11223 {
11224 flagword applicable;
11225 segT seg = now_seg;
11226 subsegT subseg = now_subseg;
11227
11228 /* The .lbss section is for local .largecomm symbols. */
11229 lbss_section = subseg_new (".lbss", 0);
11230 applicable = bfd_applicable_section_flags (stdoutput);
11231 bfd_set_section_flags (stdoutput, lbss_section,
11232 applicable & SEC_ALLOC);
11233 seg_info (lbss_section)->bss = 1;
11234
11235 subseg_set (seg, subseg);
11236 }
11237
11238 elf_com_section_ptr = &_bfd_elf_large_com_section;
11239 bss_section = lbss_section;
11240
11241 s_comm_internal (0, elf_common_parse);
11242
11243 elf_com_section_ptr = saved_com_section_ptr;
11244 bss_section = saved_bss_section;
11245 }
11246 }
11247 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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