gas/config/tc-xtensa.c

   1 /* tc-xtensa.c -- Assemble Xtensa instructions.
   2    Copyright (C) 2003-2023 Free Software Foundation, Inc.
   3
   4    This file is part of GAS, the GNU Assembler.
   5
   6    GAS is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    GAS is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to
  18    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 #include "as.h"
  22 #include <limits.h>
  23 #include "sb.h"
  24 #include "safe-ctype.h"
  25 #include "tc-xtensa.h"
  26 #include "subsegs.h"
  27 #include "xtensa-relax.h"
  28 #include "dwarf2dbg.h"
  29 #include "xtensa-istack.h"
  30 #include "xtensa-dynconfig.h"
  31 #include "elf/xtensa.h"
  32
  33 #ifndef uint32
  34 #define uint32 unsigned int
  35 #endif
  36 #ifndef int32
  37 #define int32 signed int
  38 #endif
  39
  40 /* Notes:
  41
  42    Naming conventions (used somewhat inconsistently):
  43       The xtensa_ functions are exported
  44       The xg_ functions are internal
  45
  46    We also have a couple of different extensibility mechanisms.
  47    1) The idiom replacement:
  48       This is used when a line is first parsed to
  49       replace an instruction pattern with another instruction
  50       It is currently limited to replacements of instructions
  51       with constant operands.
  52    2) The xtensa-relax.c mechanism that has stronger instruction
  53       replacement patterns.  When an instruction's immediate field
  54       does not fit the next instruction sequence is attempted.
  55       In addition, "narrow" opcodes are supported this way.  */
  56
  57
  58 /* Define characters with special meanings to GAS.  */
  59 const char comment_chars[] = "#";
  60 const char line_comment_chars[] = "#";
  61 const char line_separator_chars[] = ";";
  62 const char EXP_CHARS[] = "eE";
  63 const char FLT_CHARS[] = "rRsSfFdDxXpP";
  64
  65
  66 /* Flags to indicate whether the hardware supports the density and
  67    absolute literals options.  */
  68
  69 bool density_supported;
  70 bool absolute_literals_supported;
  71
  72 static unsigned microarch_earliest;
  73
  74 static vliw_insn cur_vinsn;
  75
  76 unsigned xtensa_num_pipe_stages;
  77 unsigned xtensa_fetch_width;
  78
  79 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
  80
  81 /* Some functions are only valid in the front end.  This variable
  82    allows us to assert that we haven't crossed over into the
  83    back end.  */
  84 static bool past_xtensa_md_finish = false;
  85
  86 /* Flags for properties of the last instruction in a segment.  */
  87 #define FLAG_IS_A0_WRITER       0x1
  88 #define FLAG_IS_BAD_LOOPEND     0x2
  89
  90
  91 /* We define a special segment names ".literal" to place literals
  92    into.  The .fini and .init sections are special because they
  93    contain code that is moved together by the linker.  We give them
  94    their own special .fini.literal and .init.literal sections.  */
  95
  96 #define LITERAL_SECTION_NAME            xtensa_section_rename (".literal")
  97 #define LIT4_SECTION_NAME               xtensa_section_rename (".lit4")
  98 #define INIT_SECTION_NAME               xtensa_section_rename (".init")
  99 #define FINI_SECTION_NAME               xtensa_section_rename (".fini")
 100
 101
 102 /* This type is used for the directive_stack to keep track of the
 103    state of the literal collection pools.  If lit_prefix is set, it is
 104    used to determine the literal section names; otherwise, the literal
 105    sections are determined based on the current text section.  The
 106    lit_seg and lit4_seg fields cache these literal sections, with the
 107    current_text_seg field used a tag to indicate whether the cached
 108    values are valid.  */
 109
 110 typedef struct lit_state_struct
 111 {
 112   char *lit_prefix;
 113   segT current_text_seg;
 114   segT lit_seg;
 115   segT lit4_seg;
 116 } lit_state;
 117
 118 static lit_state default_lit_sections;
 119
 120
 121 /* We keep a list of literal segments.  The seg_list type is the node
 122    for this list.  The literal_head pointer is the head of the list,
 123    with the literal_head_h dummy node at the start.  */
 124
 125 typedef struct seg_list_struct
 126 {
 127   struct seg_list_struct *next;
 128   segT seg;
 129 } seg_list;
 130
 131 static seg_list literal_head_h;
 132 static seg_list *literal_head = &literal_head_h;
 133
 134
 135 /* Lists of symbols.  We keep a list of symbols that label the current
 136    instruction, so that we can adjust the symbols when inserting alignment
 137    for various instructions.  We also keep a list of all the symbols on
 138    literals, so that we can fix up those symbols when the literals are
 139    later moved into the text sections.  */
 140
 141 typedef struct sym_list_struct
 142 {
 143   struct sym_list_struct *next;
 144   symbolS *sym;
 145 } sym_list;
 146
 147 static sym_list *insn_labels = NULL;
 148 static sym_list *free_insn_labels = NULL;
 149 static sym_list *saved_insn_labels = NULL;
 150
 151 static sym_list *literal_syms;
 152
 153
 154 /* Flags to determine whether to prefer const16 or l32r
 155    if both options are available.  */
 156 int prefer_const16 = 0;
 157 int prefer_l32r = 0;
 158
 159 /* Global flag to indicate when we are emitting literals.  */
 160 int generating_literals = 0;
 161
 162 /* The following PROPERTY table definitions are copied from
 163    <elf/xtensa.h> and must be kept in sync with the code there.  */
 164
 165 /* Flags in the property tables to specify whether blocks of memory
 166    are literals, instructions, data, or unreachable.  For
 167    instructions, blocks that begin loop targets and branch targets are
 168    designated.  Blocks that do not allow density, instruction
 169    reordering or transformation are also specified.  Finally, for
 170    branch targets, branch target alignment priority is included.
 171    Alignment of the next block is specified in the current block
 172    and the size of the current block does not include any fill required
 173    to align to the next block.  */
 174
 175 #define XTENSA_PROP_LITERAL             0x00000001
 176 #define XTENSA_PROP_INSN                0x00000002
 177 #define XTENSA_PROP_DATA                0x00000004
 178 #define XTENSA_PROP_UNREACHABLE         0x00000008
 179 /* Instruction only properties at beginning of code.  */
 180 #define XTENSA_PROP_INSN_LOOP_TARGET    0x00000010
 181 #define XTENSA_PROP_INSN_BRANCH_TARGET  0x00000020
 182 /* Instruction only properties about code.  */
 183 #define XTENSA_PROP_INSN_NO_DENSITY     0x00000040
 184 #define XTENSA_PROP_INSN_NO_REORDER     0x00000080
 185 /* Historically, NO_TRANSFORM was a property of instructions,
 186    but it should apply to literals under certain circumstances.  */
 187 #define XTENSA_PROP_NO_TRANSFORM        0x00000100
 188
 189 /*  Branch target alignment information.  This transmits information
 190     to the linker optimization about the priority of aligning a
 191     particular block for branch target alignment: None, low priority,
 192     high priority, or required.  These only need to be checked in
 193     instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
 194     Common usage is
 195
 196     switch (GET_XTENSA_PROP_BT_ALIGN (flags))
 197     case XTENSA_PROP_BT_ALIGN_NONE:
 198     case XTENSA_PROP_BT_ALIGN_LOW:
 199     case XTENSA_PROP_BT_ALIGN_HIGH:
 200     case XTENSA_PROP_BT_ALIGN_REQUIRE:
 201 */
 202 #define XTENSA_PROP_BT_ALIGN_MASK       0x00000600
 203
 204 /* No branch target alignment.  */
 205 #define XTENSA_PROP_BT_ALIGN_NONE       0x0
 206 /* Low priority branch target alignment.  */
 207 #define XTENSA_PROP_BT_ALIGN_LOW        0x1
 208 /* High priority branch target alignment.  */
 209 #define XTENSA_PROP_BT_ALIGN_HIGH       0x2
 210 /* Required branch target alignment.  */
 211 #define XTENSA_PROP_BT_ALIGN_REQUIRE    0x3
 212
 213 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
 214   (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
 215     (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
 216
 217
 218 /* Alignment is specified in the block BEFORE the one that needs
 219    alignment.  Up to 5 bits.  Use GET_XTENSA_PROP_ALIGNMENT(flags) to
 220    get the required alignment specified as a power of 2.  Use
 221    SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
 222    alignment.  Be careful of side effects since the SET will evaluate
 223    flags twice.  Also, note that the SIZE of a block in the property
 224    table does not include the alignment size, so the alignment fill
 225    must be calculated to determine if two blocks are contiguous.
 226    TEXT_ALIGN is not currently implemented but is a placeholder for a
 227    possible future implementation.  */
 228
 229 #define XTENSA_PROP_ALIGN               0x00000800
 230
 231 #define XTENSA_PROP_ALIGNMENT_MASK      0x0001f000
 232
 233 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
 234   (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
 235     (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
 236
 237 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
 238
 239
 240 /* Structure for saving instruction and alignment per-fragment data
 241    that will be written to the object file.  This structure is
 242    equivalent to the actual data that will be written out to the file
 243    but is easier to use.   We provide a conversion to file flags
 244    in frag_flags_to_number.  */
 245
 246 typedef struct frag_flags_struct frag_flags;
 247
 248 struct frag_flags_struct
 249 {
 250   /* is_literal should only be used after xtensa_move_literals.
 251      If you need to check if you are generating a literal fragment,
 252      then use the generating_literals global.  */
 253
 254   unsigned is_literal : 1;
 255   unsigned is_insn : 1;
 256   unsigned is_data : 1;
 257   unsigned is_unreachable : 1;
 258
 259   /* is_specific_opcode implies no_transform.  */
 260   unsigned is_no_transform : 1;
 261
 262   struct
 263   {
 264     unsigned is_loop_target : 1;
 265     unsigned is_branch_target : 1; /* Branch targets have a priority.  */
 266     unsigned bt_align_priority : 2;
 267
 268     unsigned is_no_density : 1;
 269     /* no_longcalls flag does not need to be placed in the object file.  */
 270
 271     unsigned is_no_reorder : 1;
 272
 273     /* Uses absolute literal addressing for l32r.  */
 274     unsigned is_abslit : 1;
 275   } insn;
 276   unsigned is_align : 1;
 277   unsigned alignment : 5;
 278 };
 279
 280
 281 /* Structure for saving information about a block of property data
 282    for frags that have the same flags.  */
 283 struct xtensa_block_info_struct
 284 {
 285   segT sec;
 286   bfd_vma offset;
 287   size_t size;
 288   frag_flags flags;
 289   struct xtensa_block_info_struct *next;
 290 };
 291
 292
 293 /* Structure for saving the current state before emitting literals.  */
 294 typedef struct emit_state_struct
 295 {
 296   const char *name;
 297   segT now_seg;
 298   subsegT now_subseg;
 299   int generating_literals;
 300 } emit_state;
 301
 302
 303 /* Opcode placement information */
 304
 305 typedef unsigned long long bitfield;
 306 #define bit_is_set(bit, bf)     ((bf) & (0x01ll << (bit)))
 307 #define set_bit(bit, bf)        ((bf) |= (0x01ll << (bit)))
 308 #define clear_bit(bit, bf)      ((bf) &= ~(0x01ll << (bit)))
 309
 310 #define MAX_FORMATS 32
 311
 312 typedef struct op_placement_info_struct
 313 {
 314   int num_formats;
 315   /* A number describing how restrictive the issue is for this
 316      opcode.  For example, an opcode that fits lots of different
 317      formats has a high freedom, as does an opcode that fits
 318      only one format but many slots in that format.  The most
 319      restrictive is the opcode that fits only one slot in one
 320      format.  */
 321   int issuef;
 322   xtensa_format narrowest;
 323   char narrowest_size;
 324   char narrowest_slot;
 325
 326   /* formats is a bitfield with the Nth bit set
 327      if the opcode fits in the Nth xtensa_format.  */
 328   bitfield formats;
 329
 330   /* slots[N]'s Mth bit is set if the op fits in the
 331      Mth slot of the Nth xtensa_format.  */
 332   bitfield slots[MAX_FORMATS];
 333
 334   /* A count of the number of slots in a given format
 335      an op can fit (i.e., the bitcount of the slot field above).  */
 336   char slots_in_format[MAX_FORMATS];
 337
 338 } op_placement_info, *op_placement_info_table;
 339
 340 op_placement_info_table op_placement_table;
 341
 342
 343 /* Extra expression types.  */
 344
 345 #define O_pltrel        O_md1   /* like O_symbol but use a PLT reloc */
 346 #define O_hi16          O_md2   /* use high 16 bits of symbolic value */
 347 #define O_lo16          O_md3   /* use low 16 bits of symbolic value */
 348 #define O_pcrel         O_md4   /* value is a PC-relative offset */
 349 #define O_tlsfunc       O_md5   /* TLS_FUNC/TLSDESC_FN relocation */
 350 #define O_tlsarg        O_md6   /* TLS_ARG/TLSDESC_ARG relocation */
 351 #define O_tlscall       O_md7   /* TLS_CALL relocation */
 352 #define O_tpoff         O_md8   /* TPOFF relocation */
 353 #define O_dtpoff        O_md9   /* DTPOFF relocation */
 354
 355 struct suffix_reloc_map
 356 {
 357   const char *suffix;
 358   int length;
 359   bfd_reloc_code_real_type reloc;
 360   operatorT operator;
 361 };
 362
 363 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
 364
 365 static struct suffix_reloc_map suffix_relocs[] =
 366 {
 367   SUFFIX_MAP ("l",      BFD_RELOC_LO16,                 O_lo16),
 368   SUFFIX_MAP ("h",      BFD_RELOC_HI16,                 O_hi16),
 369   SUFFIX_MAP ("plt",    BFD_RELOC_XTENSA_PLT,           O_pltrel),
 370   SUFFIX_MAP ("pcrel",  BFD_RELOC_32_PCREL,             O_pcrel),
 371   SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC,     O_tlsfunc),
 372   SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG,       O_tlsarg),
 373   SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL,     O_tlscall),
 374   SUFFIX_MAP ("tpoff",  BFD_RELOC_XTENSA_TLS_TPOFF,     O_tpoff),
 375   SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF,    O_dtpoff),
 376 };
 377
 378
 379 /* Directives.  */
 380
 381 typedef enum
 382 {
 383   directive_none = 0,
 384   directive_literal,
 385   directive_density,
 386   directive_transform,
 387   directive_freeregs,
 388   directive_longcalls,
 389   directive_literal_prefix,
 390   directive_schedule,
 391   directive_absolute_literals,
 392   directive_last_directive
 393 } directiveE;
 394
 395 typedef struct
 396 {
 397   const char *name;
 398   bool can_be_negated;
 399 } directive_infoS;
 400
 401 const directive_infoS directive_info[] =
 402 {
 403   { "none",             false },
 404   { "literal",          false },
 405   { "density",          true },
 406   { "transform",        true },
 407   { "freeregs",         false },
 408   { "longcalls",        true },
 409   { "literal_prefix",   false },
 410   { "schedule",         true },
 411   { "absolute-literals", true }
 412 };
 413
 414 bool directive_state[] =
 415 {
 416   false,                        /* none */
 417   false,                        /* literal */
 418   false,                        /* density */
 419   true,                         /* transform */
 420   false,                        /* freeregs */
 421   false,                        /* longcalls */
 422   false,                        /* literal_prefix */
 423   false,                        /* schedule */
 424   false                         /* absolute_literals */
 425 };
 426
 427 /* A circular list of all potential and actual literal pool locations
 428    in a segment.  */
 429 struct litpool_frag
 430 {
 431   struct litpool_frag *next;
 432   struct litpool_frag *prev;
 433   fragS *fragP;
 434   addressT addr;
 435   short priority; /* 1, 2, or 3 -- 1 is highest  */
 436   short original_priority;
 437   int literal_count;
 438 };
 439
 440 /* Map a segment to its litpool_frag list.  */
 441 struct litpool_seg
 442 {
 443   struct litpool_seg *next;
 444   asection *seg;
 445   struct litpool_frag frag_list;
 446   int frag_count; /* since last litpool location  */
 447 };
 448
 449 static struct litpool_seg litpool_seg_list;
 450
 451 /* Limit maximal size of auto litpool by half of the j range.  */
 452 #define MAX_AUTO_POOL_LITERALS 16384
 453
 454 /* Limit maximal size of explicit literal pool by l32r range.  */
 455 #define MAX_EXPLICIT_POOL_LITERALS 65536
 456
 457 #define MAX_POOL_LITERALS \
 458   (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS)
 459
 460 /* Directive functions.  */
 461
 462 static void xtensa_begin_directive (int);
 463 static void xtensa_end_directive (int);
 464 static void xtensa_literal_prefix (void);
 465 static void xtensa_literal_position (int);
 466 static void xtensa_literal_pseudo (int);
 467 static void xtensa_frequency_pseudo (int);
 468 static void xtensa_elf_cons (int);
 469 static void xtensa_leb128 (int);
 470
 471 /* Parsing and Idiom Translation.  */
 472
 473 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
 474
 475 /* Various Other Internal Functions.  */
 476
 477 extern bool xg_is_single_relaxable_insn (TInsn *, TInsn *, bool);
 478 static bool xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
 479 static void xtensa_mark_literal_pool_location (void);
 480 static addressT get_expanded_loop_offset (xtensa_opcode);
 481 static fragS *get_literal_pool_location (segT);
 482 static void set_literal_pool_location (segT, fragS *);
 483 static void xtensa_set_frag_assembly_state (fragS *);
 484 static void finish_vinsn (vliw_insn *);
 485 static bool emit_single_op (TInsn *);
 486 static int total_frag_text_expansion (fragS *);
 487 static bool use_trampolines = true;
 488 static void xtensa_check_frag_count (void);
 489 static void xtensa_create_trampoline_frag (bool);
 490 static void xtensa_maybe_create_trampoline_frag (void);
 491 struct trampoline_frag;
 492 static int init_trampoline_frag (fragS *);
 493 static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset);
 494 static void xtensa_maybe_create_literal_pool_frag (bool, bool);
 495 static bool auto_litpools = false;
 496 static int auto_litpool_limit = 0;
 497 static bool xtensa_is_init_fini (segT seg);
 498
 499 /* Alignment Functions.  */
 500
 501 static int get_text_align_power (unsigned);
 502 static int get_text_align_max_fill_size (int, bool, bool);
 503 static int branch_align_power (segT);
 504
 505 /* Helpers for xtensa_relax_frag().  */
 506
 507 static long relax_frag_add_nop (fragS *);
 508
 509 /* Accessors for additional per-subsegment information.  */
 510
 511 static unsigned get_last_insn_flags (segT, subsegT);
 512 static void set_last_insn_flags (segT, subsegT, unsigned, bool);
 513 static float get_subseg_total_freq (segT, subsegT);
 514 static float get_subseg_target_freq (segT, subsegT);
 515 static void set_subseg_freq (segT, subsegT, float, float);
 516
 517 /* Segment list functions.  */
 518
 519 static void xtensa_move_literals (void);
 520 static void xtensa_reorder_segments (void);
 521 static void xtensa_switch_to_literal_fragment (emit_state *);
 522 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
 523 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
 524 static void xtensa_restore_emit_state (emit_state *);
 525 static segT cache_literal_section (bool);
 526
 527 /* op_placement_info functions.  */
 528
 529 static void init_op_placement_info_table (void);
 530 extern bool opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
 531 static int xg_get_single_size (xtensa_opcode);
 532 static xtensa_format xg_get_single_format (xtensa_opcode);
 533 static int xg_get_single_slot (xtensa_opcode);
 534
 535 /* TInsn and IStack functions.  */
 536
 537 static bool tinsn_has_symbolic_operands (const TInsn *);
 538 static bool tinsn_has_invalid_symbolic_operands (const TInsn *);
 539 static bool tinsn_has_complex_operands (const TInsn *);
 540 static bool tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
 541 static bool tinsn_check_arguments (const TInsn *);
 542 static void tinsn_from_chars (TInsn *, char *, int);
 543 static void tinsn_immed_from_frag (TInsn *, fragS *, int);
 544 static int get_num_stack_text_bytes (IStack *);
 545 static int get_num_stack_literal_bytes (IStack *);
 546 static bool tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf);
 547
 548 /* vliw_insn functions.  */
 549
 550 static void xg_init_vinsn (vliw_insn *);
 551 static void xg_copy_vinsn (vliw_insn *, vliw_insn *);
 552 static void xg_clear_vinsn (vliw_insn *);
 553 static bool vinsn_has_specific_opcodes (vliw_insn *);
 554 static void xg_free_vinsn (vliw_insn *);
 555 static bool vinsn_to_insnbuf
 556   (vliw_insn *, char *, fragS *, bool);
 557 static void vinsn_from_chars (vliw_insn *, char *);
 558
 559 /* Expression Utilities.  */
 560
 561 bool expr_is_const (const expressionS *);
 562 offsetT get_expr_const (const expressionS *);
 563 void set_expr_const (expressionS *, offsetT);
 564 bool expr_is_register (const expressionS *);
 565 offsetT get_expr_register (const expressionS *);
 566 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
 567 bool expr_is_equal (expressionS *, expressionS *);
 568 static void copy_expr (expressionS *, const expressionS *);
 569
 570 /* Section renaming.  */
 571
 572 static void build_section_rename (const char *);
 573
 574
 575 /* ISA imported from bfd.  */
 576 extern xtensa_isa xtensa_default_isa;
 577
 578 extern int target_big_endian;
 579
 580 static xtensa_opcode xtensa_addi_opcode;
 581 static xtensa_opcode xtensa_addmi_opcode;
 582 static xtensa_opcode xtensa_call0_opcode;
 583 static xtensa_opcode xtensa_call4_opcode;
 584 static xtensa_opcode xtensa_call8_opcode;
 585 static xtensa_opcode xtensa_call12_opcode;
 586 static xtensa_opcode xtensa_callx0_opcode;
 587 static xtensa_opcode xtensa_callx4_opcode;
 588 static xtensa_opcode xtensa_callx8_opcode;
 589 static xtensa_opcode xtensa_callx12_opcode;
 590 static xtensa_opcode xtensa_const16_opcode;
 591 static xtensa_opcode xtensa_entry_opcode;
 592 static xtensa_opcode xtensa_extui_opcode;
 593 static xtensa_opcode xtensa_movi_opcode;
 594 static xtensa_opcode xtensa_movi_n_opcode;
 595 static xtensa_opcode xtensa_isync_opcode;
 596 static xtensa_opcode xtensa_j_opcode;
 597 static xtensa_opcode xtensa_jx_opcode;
 598 static xtensa_opcode xtensa_l32r_opcode;
 599 static xtensa_opcode xtensa_loop_opcode;
 600 static xtensa_opcode xtensa_loopnez_opcode;
 601 static xtensa_opcode xtensa_loopgtz_opcode;
 602 static xtensa_opcode xtensa_nop_opcode;
 603 static xtensa_opcode xtensa_nop_n_opcode;
 604 static xtensa_opcode xtensa_or_opcode;
 605 static xtensa_opcode xtensa_ret_opcode;
 606 static xtensa_opcode xtensa_ret_n_opcode;
 607 static xtensa_opcode xtensa_retw_opcode;
 608 static xtensa_opcode xtensa_retw_n_opcode;
 609 static xtensa_opcode xtensa_rsr_lcount_opcode;
 610 static xtensa_opcode xtensa_waiti_opcode;
 611 static int config_max_slots = 0;
 612
 613 \f
 614 /* Command-line Options.  */
 615
 616 bool use_literal_section = true;
 617 enum flix_level produce_flix = FLIX_ALL;
 618 static bool align_targets = true;
 619 static bool warn_unaligned_branch_targets = false;
 620 static bool has_a0_b_retw = false;
 621 static bool workaround_a0_b_retw = false;
 622 static bool workaround_b_j_loop_end = false;
 623 static bool workaround_short_loop = false;
 624 static bool maybe_has_short_loop = false;
 625 static bool workaround_close_loop_end = false;
 626 static bool maybe_has_close_loop_end = false;
 627 static bool enforce_three_byte_loop_align = false;
 628 static bool opt_linkrelax = true;
 629
 630 /* When workaround_short_loops is TRUE, all loops with early exits must
 631    have at least 3 instructions.  workaround_all_short_loops is a modifier
 632    to the workaround_short_loop flag.  In addition to the
 633    workaround_short_loop actions, all straightline loopgtz and loopnez
 634    must have at least 3 instructions.  */
 635
 636 static bool workaround_all_short_loops = false;
 637
 638 /* Generate individual property section for every section.
 639    This option is defined in BDF library.  */
 640 extern bool elf32xtensa_separate_props;
 641
 642 /* Xtensa ABI.
 643    This option is defined in BDF library.  */
 644 extern int elf32xtensa_abi;
 645
 646 static void
 647 xtensa_setup_hw_workarounds (int earliest, int latest)
 648 {
 649   if (earliest > latest)
 650     as_fatal (_("illegal range of target hardware versions"));
 651
 652   /* Enable all workarounds for pre-T1050.0 hardware.  */
 653   if (earliest < 105000 || latest < 105000)
 654     {
 655       workaround_a0_b_retw |= true;
 656       workaround_b_j_loop_end |= true;
 657       workaround_short_loop |= true;
 658       workaround_close_loop_end |= true;
 659       workaround_all_short_loops |= true;
 660       enforce_three_byte_loop_align = true;
 661     }
 662 }
 663
 664
 665 enum
 666 {
 667   option_density = OPTION_MD_BASE,
 668   option_no_density,
 669
 670   option_flix,
 671   option_no_generate_flix,
 672   option_no_flix,
 673
 674   option_relax,
 675   option_no_relax,
 676
 677   option_link_relax,
 678   option_no_link_relax,
 679
 680   option_generics,
 681   option_no_generics,
 682
 683   option_transform,
 684   option_no_transform,
 685
 686   option_text_section_literals,
 687   option_no_text_section_literals,
 688
 689   option_absolute_literals,
 690   option_no_absolute_literals,
 691
 692   option_align_targets,
 693   option_no_align_targets,
 694
 695   option_warn_unaligned_targets,
 696
 697   option_longcalls,
 698   option_no_longcalls,
 699
 700   option_workaround_a0_b_retw,
 701   option_no_workaround_a0_b_retw,
 702
 703   option_workaround_b_j_loop_end,
 704   option_no_workaround_b_j_loop_end,
 705
 706   option_workaround_short_loop,
 707   option_no_workaround_short_loop,
 708
 709   option_workaround_all_short_loops,
 710   option_no_workaround_all_short_loops,
 711
 712   option_workaround_close_loop_end,
 713   option_no_workaround_close_loop_end,
 714
 715   option_no_workarounds,
 716
 717   option_rename_section_name,
 718
 719   option_prefer_l32r,
 720   option_prefer_const16,
 721
 722   option_target_hardware,
 723
 724   option_trampolines,
 725   option_no_trampolines,
 726
 727   option_auto_litpools,
 728   option_no_auto_litpools,
 729   option_auto_litpool_limit,
 730
 731   option_separate_props,
 732   option_no_separate_props,
 733
 734   option_abi_windowed,
 735   option_abi_call0,
 736 };
 737
 738 const char *md_shortopts = "";
 739
 740 struct option md_longopts[] =
 741 {
 742   { "density", no_argument, NULL, option_density },
 743   { "no-density", no_argument, NULL, option_no_density },
 744
 745   { "flix", no_argument, NULL, option_flix },
 746   { "no-generate-flix", no_argument, NULL, option_no_generate_flix },
 747   { "no-allow-flix", no_argument, NULL, option_no_flix },
 748
 749   /* Both "relax" and "generics" are deprecated and treated as equivalent
 750      to the "transform" option.  */
 751   { "relax", no_argument, NULL, option_relax },
 752   { "no-relax", no_argument, NULL, option_no_relax },
 753   { "generics", no_argument, NULL, option_generics },
 754   { "no-generics", no_argument, NULL, option_no_generics },
 755
 756   { "transform", no_argument, NULL, option_transform },
 757   { "no-transform", no_argument, NULL, option_no_transform },
 758   { "text-section-literals", no_argument, NULL, option_text_section_literals },
 759   { "no-text-section-literals", no_argument, NULL,
 760     option_no_text_section_literals },
 761   { "absolute-literals", no_argument, NULL, option_absolute_literals },
 762   { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
 763   /* This option was changed from -align-target to -target-align
 764      because it conflicted with the "-al" option.  */
 765   { "target-align", no_argument, NULL, option_align_targets },
 766   { "no-target-align", no_argument, NULL, option_no_align_targets },
 767   { "warn-unaligned-targets", no_argument, NULL,
 768     option_warn_unaligned_targets },
 769   { "longcalls", no_argument, NULL, option_longcalls },
 770   { "no-longcalls", no_argument, NULL, option_no_longcalls },
 771
 772   { "no-workaround-a0-b-retw", no_argument, NULL,
 773     option_no_workaround_a0_b_retw },
 774   { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
 775
 776   { "no-workaround-b-j-loop-end", no_argument, NULL,
 777     option_no_workaround_b_j_loop_end },
 778   { "workaround-b-j-loop-end", no_argument, NULL,
 779     option_workaround_b_j_loop_end },
 780
 781   { "no-workaround-short-loops", no_argument, NULL,
 782     option_no_workaround_short_loop },
 783   { "workaround-short-loops", no_argument, NULL,
 784     option_workaround_short_loop },
 785
 786   { "no-workaround-all-short-loops", no_argument, NULL,
 787     option_no_workaround_all_short_loops },
 788   { "workaround-all-short-loop", no_argument, NULL,
 789     option_workaround_all_short_loops },
 790
 791   { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
 792   { "prefer-const16", no_argument, NULL, option_prefer_const16 },
 793
 794   { "no-workarounds", no_argument, NULL, option_no_workarounds },
 795
 796   { "no-workaround-close-loop-end", no_argument, NULL,
 797     option_no_workaround_close_loop_end },
 798   { "workaround-close-loop-end", no_argument, NULL,
 799     option_workaround_close_loop_end },
 800
 801   { "rename-section", required_argument, NULL, option_rename_section_name },
 802
 803   { "link-relax", no_argument, NULL, option_link_relax },
 804   { "no-link-relax", no_argument, NULL, option_no_link_relax },
 805
 806   { "target-hardware", required_argument, NULL, option_target_hardware },
 807
 808   { "trampolines", no_argument, NULL, option_trampolines },
 809   { "no-trampolines", no_argument, NULL, option_no_trampolines },
 810
 811   { "auto-litpools", no_argument, NULL, option_auto_litpools },
 812   { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools },
 813   { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit },
 814
 815   { "separate-prop-tables", no_argument, NULL, option_separate_props },
 816
 817   { "abi-windowed", no_argument, NULL, option_abi_windowed },
 818   { "abi-call0", no_argument, NULL, option_abi_call0 },
 819
 820   { NULL, no_argument, NULL, 0 }
 821 };
 822
 823 size_t md_longopts_size = sizeof md_longopts;
 824
 825
 826 int
 827 md_parse_option (int c, const char *arg)
 828 {
 829   switch (c)
 830     {
 831     case option_density:
 832       as_warn (_("--density option is ignored"));
 833       return 1;
 834     case option_no_density:
 835       as_warn (_("--no-density option is ignored"));
 836       return 1;
 837     case option_link_relax:
 838       opt_linkrelax = true;
 839       return 1;
 840     case option_no_link_relax:
 841       opt_linkrelax = false;
 842       return 1;
 843     case option_flix:
 844       produce_flix = FLIX_ALL;
 845       return 1;
 846     case option_no_generate_flix:
 847       produce_flix = FLIX_NO_GENERATE;
 848       return 1;
 849     case option_no_flix:
 850       produce_flix = FLIX_NONE;
 851       return 1;
 852     case option_generics:
 853       as_warn (_("--generics is deprecated; use --transform instead"));
 854       return md_parse_option (option_transform, arg);
 855     case option_no_generics:
 856       as_warn (_("--no-generics is deprecated; use --no-transform instead"));
 857       return md_parse_option (option_no_transform, arg);
 858     case option_relax:
 859       as_warn (_("--relax is deprecated; use --transform instead"));
 860       return md_parse_option (option_transform, arg);
 861     case option_no_relax:
 862       as_warn (_("--no-relax is deprecated; use --no-transform instead"));
 863       return md_parse_option (option_no_transform, arg);
 864     case option_longcalls:
 865       directive_state[directive_longcalls] = true;
 866       return 1;
 867     case option_no_longcalls:
 868       directive_state[directive_longcalls] = false;
 869       return 1;
 870     case option_text_section_literals:
 871       use_literal_section = false;
 872       return 1;
 873     case option_no_text_section_literals:
 874       use_literal_section = true;
 875       return 1;
 876     case option_absolute_literals:
 877       if (!absolute_literals_supported)
 878         {
 879           as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
 880           return 0;
 881         }
 882       directive_state[directive_absolute_literals] = true;
 883       return 1;
 884     case option_no_absolute_literals:
 885       directive_state[directive_absolute_literals] = false;
 886       return 1;
 887
 888     case option_workaround_a0_b_retw:
 889       workaround_a0_b_retw = true;
 890       return 1;
 891     case option_no_workaround_a0_b_retw:
 892       workaround_a0_b_retw = false;
 893       return 1;
 894     case option_workaround_b_j_loop_end:
 895       workaround_b_j_loop_end = true;
 896       return 1;
 897     case option_no_workaround_b_j_loop_end:
 898       workaround_b_j_loop_end = false;
 899       return 1;
 900
 901     case option_workaround_short_loop:
 902       workaround_short_loop = true;
 903       return 1;
 904     case option_no_workaround_short_loop:
 905       workaround_short_loop = false;
 906       return 1;
 907
 908     case option_workaround_all_short_loops:
 909       workaround_all_short_loops = true;
 910       return 1;
 911     case option_no_workaround_all_short_loops:
 912       workaround_all_short_loops = false;
 913       return 1;
 914
 915     case option_workaround_close_loop_end:
 916       workaround_close_loop_end = true;
 917       return 1;
 918     case option_no_workaround_close_loop_end:
 919       workaround_close_loop_end = false;
 920       return 1;
 921
 922     case option_no_workarounds:
 923       workaround_a0_b_retw = false;
 924       workaround_b_j_loop_end = false;
 925       workaround_short_loop = false;
 926       workaround_all_short_loops = false;
 927       workaround_close_loop_end = false;
 928       return 1;
 929
 930     case option_align_targets:
 931       align_targets = true;
 932       return 1;
 933     case option_no_align_targets:
 934       align_targets = false;
 935       return 1;
 936
 937     case option_warn_unaligned_targets:
 938       warn_unaligned_branch_targets = true;
 939       return 1;
 940
 941     case option_rename_section_name:
 942       build_section_rename (arg);
 943       return 1;
 944
 945     case 'Q':
 946       /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
 947          should be emitted or not.  FIXME: Not implemented.  */
 948       return 1;
 949
 950     case option_prefer_l32r:
 951       if (prefer_const16)
 952         as_fatal (_("prefer-l32r conflicts with prefer-const16"));
 953       prefer_l32r = 1;
 954       return 1;
 955
 956     case option_prefer_const16:
 957       if (prefer_l32r)
 958         as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
 959       prefer_const16 = 1;
 960       return 1;
 961
 962     case option_target_hardware:
 963       {
 964         int earliest, latest = 0;
 965         char *end;
 966         if (*arg == 0 || *arg == '-')
 967           as_fatal (_("invalid target hardware version"));
 968
 969         earliest = strtol (arg, &end, 0);
 970
 971         if (*end == 0)
 972           latest = earliest;
 973         else if (*end == '-')
 974           {
 975             if (*++end == 0)
 976               as_fatal (_("invalid target hardware version"));
 977             latest = strtol (end, &end, 0);
 978           }
 979         if (*end != 0)
 980           as_fatal (_("invalid target hardware version"));
 981
 982         xtensa_setup_hw_workarounds (earliest, latest);
 983         return 1;
 984       }
 985
 986     case option_transform:
 987       /* This option has no affect other than to use the defaults,
 988          which are already set.  */
 989       return 1;
 990
 991     case option_no_transform:
 992       /* This option turns off all transformations of any kind.
 993          However, because we want to preserve the state of other
 994          directives, we only change its own field.  Thus, before
 995          you perform any transformation, always check if transform
 996          is available.  If you use the functions we provide for this
 997          purpose, you will be ok.  */
 998       directive_state[directive_transform] = false;
 999       return 1;
1000
1001     case option_trampolines:
1002       use_trampolines = true;
1003       return 1;
1004
1005     case option_no_trampolines:
1006       use_trampolines = false;
1007       return 1;
1008
1009     case option_auto_litpools:
1010       auto_litpools = true;
1011       use_literal_section = false;
1012       if (auto_litpool_limit <= 0)
1013         auto_litpool_limit = MAX_AUTO_POOL_LITERALS / 2;
1014       return 1;
1015
1016     case option_no_auto_litpools:
1017       auto_litpools = false;
1018       auto_litpool_limit = -1;
1019       return 1;
1020
1021     case option_auto_litpool_limit:
1022       {
1023         int value = 0;
1024         char *end;
1025         if (auto_litpool_limit < 0)
1026           as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1027         if (*arg == 0 || *arg == '-')
1028           as_fatal (_("invalid auto-litpool-limit argument"));
1029         value = strtol (arg, &end, 10);
1030         if (*end != 0)
1031           as_fatal (_("invalid auto-litpool-limit argument"));
1032         if (value < 100 || value > 10000)
1033           as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1034         auto_litpool_limit = value;
1035         auto_litpools = true;
1036         use_literal_section = false;
1037         return 1;
1038       }
1039
1040     case option_separate_props:
1041       elf32xtensa_separate_props = true;
1042       return 1;
1043
1044     case option_no_separate_props:
1045       elf32xtensa_separate_props = false;
1046       return 1;
1047
1048     case option_abi_windowed:
1049       elf32xtensa_abi = XTHAL_ABI_WINDOWED;
1050       return 1;
1051
1052     case option_abi_call0:
1053       elf32xtensa_abi = XTHAL_ABI_CALL0;
1054       return 1;
1055
1056     default:
1057       return 0;
1058     }
1059 }
1060
1061
1062 void
1063 md_show_usage (FILE *stream)
1064 {
1065   fputs ("\n\
1066 Xtensa options:\n\
1067   --[no-]text-section-literals\n\
1068                           [Do not] put literals in the text section\n\
1069   --[no-]absolute-literals\n\
1070                           [Do not] default to use non-PC-relative literals\n\
1071   --[no-]target-align     [Do not] try to align branch targets\n\
1072   --[no-]longcalls        [Do not] emit 32-bit call sequences\n\
1073   --[no-]transform        [Do not] transform instructions\n\
1074   --flix                  both allow hand-written and generate flix bundles\n\
1075   --no-generate-flix      allow hand-written but do not generate\n\
1076                           flix bundles\n\
1077   --no-allow-flix         neither allow hand-written nor generate\n\
1078                           flix bundles\n\
1079   --rename-section old=new Rename section 'old' to 'new'\n\
1080   --[no-]trampolines      [Do not] generate trampolines (jumps to jumps)\n\
1081                           when jumps do not reach their targets\n\
1082   --[no-]auto-litpools    [Do not] automatically create literal pools\n\
1083   --auto-litpool-limit=<value>\n\
1084                           (range 100-10000) Maximum number of blocks of\n\
1085                           instructions to emit between literal pool\n\
1086                           locations; implies --auto-litpools flag\n\
1087   --[no-]separate-prop-tables\n\
1088                           [Do not] place Xtensa property records into\n\
1089                           individual property sections for each section.\n\
1090                           Default is to generate single property section.\n", stream);
1091 }
1092
1093 \f
1094 /* Functions related to the list of current label symbols.  */
1095
1096 static void
1097 xtensa_add_insn_label (symbolS *sym)
1098 {
1099   sym_list *l;
1100
1101   if (!free_insn_labels)
1102     l = XNEW (sym_list);
1103   else
1104     {
1105       l = free_insn_labels;
1106       free_insn_labels = l->next;
1107     }
1108
1109   l->sym = sym;
1110   l->next = insn_labels;
1111   insn_labels = l;
1112 }
1113
1114
1115 static void
1116 xtensa_clear_insn_labels (void)
1117 {
1118   sym_list **pl;
1119
1120   for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1121     ;
1122   *pl = insn_labels;
1123   insn_labels = NULL;
1124 }
1125
1126
1127 static void
1128 xtensa_move_labels (fragS *new_frag, valueT new_offset)
1129 {
1130   sym_list *lit;
1131
1132   for (lit = insn_labels; lit; lit = lit->next)
1133     {
1134       symbolS *lit_sym = lit->sym;
1135       S_SET_VALUE (lit_sym, new_offset);
1136       symbol_set_frag (lit_sym, new_frag);
1137     }
1138 }
1139
1140 \f
1141 /* Directive data and functions.  */
1142
1143 typedef struct state_stackS_struct
1144 {
1145   directiveE directive;
1146   bool negated;
1147   bool old_state;
1148   const char *file;
1149   unsigned int line;
1150   const void *datum;
1151   struct state_stackS_struct *prev;
1152 } state_stackS;
1153
1154 state_stackS *directive_state_stack;
1155
1156 const pseudo_typeS md_pseudo_table[] =
1157 {
1158   { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
1159   { "literal_position", xtensa_literal_position, 0 },
1160   { "frame", s_ignore, 0 },     /* Formerly used for STABS debugging.  */
1161   { "long", xtensa_elf_cons, 4 },
1162   { "word", xtensa_elf_cons, 4 },
1163   { "4byte", xtensa_elf_cons, 4 },
1164   { "short", xtensa_elf_cons, 2 },
1165   { "2byte", xtensa_elf_cons, 2 },
1166   { "sleb128", xtensa_leb128, 1},
1167   { "uleb128", xtensa_leb128, 0},
1168   { "begin", xtensa_begin_directive, 0 },
1169   { "end", xtensa_end_directive, 0 },
1170   { "literal", xtensa_literal_pseudo, 0 },
1171   { "frequency", xtensa_frequency_pseudo, 0 },
1172   { NULL, 0, 0 },
1173 };
1174
1175
1176 static bool
1177 use_transform (void)
1178 {
1179   /* After md_finish, you should be checking frag by frag, rather
1180      than state directives.  */
1181   gas_assert (!past_xtensa_md_finish);
1182   return directive_state[directive_transform];
1183 }
1184
1185
1186 static bool
1187 do_align_targets (void)
1188 {
1189   /* Do not use this function after md_finish; just look at align_targets
1190      instead.  There is no target-align directive, so alignment is either
1191      enabled for all frags or not done at all.  */
1192   gas_assert (!past_xtensa_md_finish);
1193   return align_targets && use_transform ();
1194 }
1195
1196
1197 static void
1198 directive_push (directiveE directive, bool negated, const void *datum)
1199 {
1200   const char *file;
1201   unsigned int line;
1202   state_stackS *stack = XNEW (state_stackS);
1203
1204   file = as_where (&line);
1205
1206   stack->directive = directive;
1207   stack->negated = negated;
1208   stack->old_state = directive_state[directive];
1209   stack->file = file;
1210   stack->line = line;
1211   stack->datum = datum;
1212   stack->prev = directive_state_stack;
1213   directive_state_stack = stack;
1214
1215   directive_state[directive] = !negated;
1216 }
1217
1218
1219 static void
1220 directive_pop (directiveE *directive,
1221                bool *negated,
1222                const char **file,
1223                unsigned int *line,
1224                const void **datum)
1225 {
1226   state_stackS *top = directive_state_stack;
1227
1228   if (!directive_state_stack)
1229     {
1230       as_bad (_("unmatched .end directive"));
1231       *directive = directive_none;
1232       return;
1233     }
1234
1235   directive_state[directive_state_stack->directive] = top->old_state;
1236   *directive = top->directive;
1237   *negated = top->negated;
1238   *file = top->file;
1239   *line = top->line;
1240   *datum = top->datum;
1241   directive_state_stack = top->prev;
1242   free (top);
1243 }
1244
1245
1246 static void
1247 directive_balance (void)
1248 {
1249   while (directive_state_stack)
1250     {
1251       directiveE directive;
1252       bool negated;
1253       const char *file;
1254       unsigned int line;
1255       const void *datum;
1256
1257       directive_pop (&directive, &negated, &file, &line, &datum);
1258       as_warn_where ((char *) file, line,
1259                      _(".begin directive with no matching .end directive"));
1260     }
1261 }
1262
1263
1264 static bool
1265 inside_directive (directiveE dir)
1266 {
1267   state_stackS *top = directive_state_stack;
1268
1269   while (top && top->directive != dir)
1270     top = top->prev;
1271
1272   return (top != NULL);
1273 }
1274
1275
1276 static void
1277 get_directive (directiveE *directive, bool *negated)
1278 {
1279   int len;
1280   unsigned i;
1281   const char *directive_string;
1282
1283   if (!startswith (input_line_pointer, "no-"))
1284     *negated = false;
1285   else
1286     {
1287       *negated = true;
1288       input_line_pointer += 3;
1289     }
1290
1291   len = strspn (input_line_pointer,
1292                 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1293
1294   /* This code is a hack to make .begin [no-][generics|relax] exactly
1295      equivalent to .begin [no-]transform.  We should remove it when
1296      we stop accepting those options.  */
1297
1298   if (startswith (input_line_pointer, "generics"))
1299     {
1300       as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1301       directive_string = "transform";
1302     }
1303   else if (startswith (input_line_pointer, "relax"))
1304     {
1305       as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1306       directive_string = "transform";
1307     }
1308   else
1309     directive_string = input_line_pointer;
1310
1311   for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
1312     {
1313       if (strncmp (directive_string, directive_info[i].name, len) == 0)
1314         {
1315           input_line_pointer += len;
1316           *directive = (directiveE) i;
1317           if (*negated && !directive_info[i].can_be_negated)
1318             as_bad (_("directive %s cannot be negated"),
1319                     directive_info[i].name);
1320           return;
1321         }
1322     }
1323
1324   as_bad (_("unknown directive"));
1325   *directive = (directiveE) XTENSA_UNDEFINED;
1326 }
1327
1328
1329 static void
1330 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
1331 {
1332   directiveE directive;
1333   bool negated;
1334   emit_state *state;
1335   lit_state *ls;
1336
1337   get_directive (&directive, &negated);
1338   if (directive == (directiveE) XTENSA_UNDEFINED)
1339     {
1340       discard_rest_of_line ();
1341       return;
1342     }
1343
1344   if (cur_vinsn.inside_bundle)
1345     as_bad (_("directives are not valid inside bundles"));
1346
1347   switch (directive)
1348     {
1349     case directive_literal:
1350       if (!inside_directive (directive_literal))
1351         {
1352           /* Previous labels go with whatever follows this directive, not with
1353              the literal, so save them now.  */
1354           saved_insn_labels = insn_labels;
1355           insn_labels = NULL;
1356         }
1357       as_warn (_(".begin literal is deprecated; use .literal instead"));
1358       state = XNEW (emit_state);
1359       xtensa_switch_to_literal_fragment (state);
1360       directive_push (directive_literal, negated, state);
1361       break;
1362
1363     case directive_literal_prefix:
1364       /* Have to flush pending output because a movi relaxed to an l32r
1365          might produce a literal.  */
1366       md_flush_pending_output ();
1367       /* Check to see if the current fragment is a literal
1368          fragment.  If it is, then this operation is not allowed.  */
1369       if (generating_literals)
1370         {
1371           as_bad (_("cannot set literal_prefix inside literal fragment"));
1372           return;
1373         }
1374
1375       /* Allocate the literal state for this section and push
1376          onto the directive stack.  */
1377       ls = XNEW (lit_state);
1378       gas_assert (ls);
1379
1380       *ls = default_lit_sections;
1381       directive_push (directive_literal_prefix, negated, ls);
1382
1383       /* Process the new prefix.  */
1384       xtensa_literal_prefix ();
1385       break;
1386
1387     case directive_freeregs:
1388       /* This information is currently unused, but we'll accept the statement
1389          and just discard the rest of the line.  This won't check the syntax,
1390          but it will accept every correct freeregs directive.  */
1391       input_line_pointer += strcspn (input_line_pointer, "\n");
1392       directive_push (directive_freeregs, negated, 0);
1393       break;
1394
1395     case directive_schedule:
1396       md_flush_pending_output ();
1397       frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
1398                 frag_now->fr_symbol, frag_now->fr_offset, NULL);
1399       directive_push (directive_schedule, negated, 0);
1400       xtensa_set_frag_assembly_state (frag_now);
1401       break;
1402
1403     case directive_density:
1404       as_warn (_(".begin [no-]density is ignored"));
1405       break;
1406
1407     case directive_absolute_literals:
1408       md_flush_pending_output ();
1409       if (!absolute_literals_supported && !negated)
1410         {
1411           as_warn (_("Xtensa absolute literals option not supported; ignored"));
1412           break;
1413         }
1414       xtensa_set_frag_assembly_state (frag_now);
1415       directive_push (directive, negated, 0);
1416       break;
1417
1418     default:
1419       md_flush_pending_output ();
1420       xtensa_set_frag_assembly_state (frag_now);
1421       directive_push (directive, negated, 0);
1422       break;
1423     }
1424
1425   demand_empty_rest_of_line ();
1426 }
1427
1428
1429 static void
1430 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
1431 {
1432   directiveE begin_directive, end_directive;
1433   bool begin_negated, end_negated;
1434   const char *file;
1435   unsigned int line;
1436   emit_state *state;
1437   emit_state **state_ptr;
1438   lit_state *s;
1439
1440   if (cur_vinsn.inside_bundle)
1441     as_bad (_("directives are not valid inside bundles"));
1442
1443   get_directive (&end_directive, &end_negated);
1444
1445   md_flush_pending_output ();
1446
1447   switch ((int) end_directive)
1448     {
1449     case XTENSA_UNDEFINED:
1450       discard_rest_of_line ();
1451       return;
1452
1453     case (int) directive_density:
1454       as_warn (_(".end [no-]density is ignored"));
1455       demand_empty_rest_of_line ();
1456       break;
1457
1458     case (int) directive_absolute_literals:
1459       if (!absolute_literals_supported && !end_negated)
1460         {
1461           as_warn (_("Xtensa absolute literals option not supported; ignored"));
1462           demand_empty_rest_of_line ();
1463           return;
1464         }
1465       break;
1466
1467     default:
1468       break;
1469     }
1470
1471   state_ptr = &state; /* use state_ptr to avoid type-punning warning */
1472   directive_pop (&begin_directive, &begin_negated, &file, &line,
1473                  (const void **) state_ptr);
1474
1475   if (begin_directive != directive_none)
1476     {
1477       if (begin_directive != end_directive || begin_negated != end_negated)
1478         {
1479           as_bad (_("does not match begin %s%s at %s:%d"),
1480                   begin_negated ? "no-" : "",
1481                   directive_info[begin_directive].name, file, line);
1482         }
1483       else
1484         {
1485           switch (end_directive)
1486             {
1487             case directive_literal:
1488               frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
1489               xtensa_restore_emit_state (state);
1490               xtensa_set_frag_assembly_state (frag_now);
1491               free (state);
1492               if (!inside_directive (directive_literal))
1493                 {
1494                   /* Restore the list of current labels.  */
1495                   xtensa_clear_insn_labels ();
1496                   insn_labels = saved_insn_labels;
1497                 }
1498               break;
1499
1500             case directive_literal_prefix:
1501               /* Restore the default collection sections from saved state.  */
1502               s = (lit_state *) state;
1503               gas_assert (s);
1504               default_lit_sections = *s;
1505
1506               /* Free the state storage.  */
1507               free (s->lit_prefix);
1508               free (s);
1509               break;
1510
1511             case directive_schedule:
1512             case directive_freeregs:
1513               break;
1514
1515             default:
1516               xtensa_set_frag_assembly_state (frag_now);
1517               break;
1518             }
1519         }
1520     }
1521
1522   demand_empty_rest_of_line ();
1523 }
1524
1525
1526 /* Place an aligned literal fragment at the current location.  */
1527
1528 static void
1529 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
1530 {
1531   md_flush_pending_output ();
1532
1533   if (inside_directive (directive_literal))
1534     as_warn (_(".literal_position inside literal directive; ignoring"));
1535   xtensa_mark_literal_pool_location ();
1536
1537   demand_empty_rest_of_line ();
1538   xtensa_clear_insn_labels ();
1539 }
1540
1541
1542 /* Support .literal label, expr, ...  */
1543
1544 static void
1545 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
1546 {
1547   emit_state state;
1548   char *p, *base_name;
1549   char c;
1550
1551   if (inside_directive (directive_literal))
1552     {
1553       as_bad (_(".literal not allowed inside .begin literal region"));
1554       ignore_rest_of_line ();
1555       return;
1556     }
1557
1558   md_flush_pending_output ();
1559
1560   /* Previous labels go with whatever follows this directive, not with
1561      the literal, so save them now.  */
1562   saved_insn_labels = insn_labels;
1563   insn_labels = NULL;
1564
1565   base_name = input_line_pointer;
1566
1567   xtensa_switch_to_literal_fragment (&state);
1568
1569   /* All literals are aligned to four-byte boundaries.  */
1570   frag_align (2, 0, 0);
1571   record_alignment (now_seg, 2);
1572
1573   c = get_symbol_name (&base_name);
1574   /* Just after name is now '\0'.  */
1575   p = input_line_pointer;
1576   *p = c;
1577   SKIP_WHITESPACE_AFTER_NAME ();
1578
1579   if (*input_line_pointer != ',' && *input_line_pointer != ':')
1580     {
1581       as_bad (_("expected comma or colon after symbol name; "
1582                 "rest of line ignored"));
1583       ignore_rest_of_line ();
1584       xtensa_restore_emit_state (&state);
1585       return;
1586     }
1587
1588   *p = 0;
1589   colon (base_name);
1590   *p = c;
1591
1592   input_line_pointer++;         /* skip ',' or ':' */
1593
1594   xtensa_elf_cons (4);
1595
1596   xtensa_restore_emit_state (&state);
1597
1598   /* Restore the list of current labels.  */
1599   xtensa_clear_insn_labels ();
1600   insn_labels = saved_insn_labels;
1601 }
1602
1603
1604 static void
1605 xtensa_literal_prefix (void)
1606 {
1607   char *name;
1608   int len;
1609
1610   /* Parse the new prefix from the input_line_pointer.  */
1611   SKIP_WHITESPACE ();
1612   len = strspn (input_line_pointer,
1613                 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1614                 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1615
1616   /* Get a null-terminated copy of the name.  */
1617   name = xmemdup0 (input_line_pointer, len);
1618
1619   /* Skip the name in the input line.  */
1620   input_line_pointer += len;
1621
1622   default_lit_sections.lit_prefix = name;
1623
1624   /* Clear cached literal sections, since the prefix has changed.  */
1625   default_lit_sections.lit_seg = NULL;
1626   default_lit_sections.lit4_seg = NULL;
1627 }
1628
1629
1630 /* Support ".frequency branch_target_frequency fall_through_frequency".  */
1631
1632 static void
1633 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
1634 {
1635   float fall_through_f, target_f;
1636
1637   fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
1638   if (fall_through_f < 0)
1639     {
1640       as_bad (_("fall through frequency must be greater than 0"));
1641       ignore_rest_of_line ();
1642       return;
1643     }
1644
1645   target_f = (float) strtod (input_line_pointer, &input_line_pointer);
1646   if (target_f < 0)
1647     {
1648       as_bad (_("branch target frequency must be greater than 0"));
1649       ignore_rest_of_line ();
1650       return;
1651     }
1652
1653   set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
1654
1655   demand_empty_rest_of_line ();
1656 }
1657
1658
1659 /* Like normal .long/.short/.word, except support @plt, etc.
1660    Clobbers input_line_pointer, checks end-of-line.  */
1661
1662 static void
1663 xtensa_elf_cons (int nbytes)
1664 {
1665   expressionS exp;
1666   bfd_reloc_code_real_type reloc;
1667
1668   md_flush_pending_output ();
1669
1670   if (cur_vinsn.inside_bundle)
1671     as_bad (_("directives are not valid inside bundles"));
1672
1673   if (is_it_end_of_statement ())
1674     {
1675       demand_empty_rest_of_line ();
1676       return;
1677     }
1678
1679   do
1680     {
1681       expression (&exp);
1682       if (exp.X_op == O_symbol
1683           && *input_line_pointer == '@'
1684           && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
1685               != BFD_RELOC_NONE))
1686         {
1687           reloc_howto_type *reloc_howto =
1688             bfd_reloc_type_lookup (stdoutput, reloc);
1689
1690           if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
1691             as_bad (_("unsupported relocation"));
1692           else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
1693                     && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
1694                    || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
1695                        && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
1696             as_bad (_("opcode-specific %s relocation used outside "
1697                       "an instruction"), reloc_howto->name);
1698           else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
1699             as_bad (ngettext ("%s relocations do not fit in %d byte",
1700                               "%s relocations do not fit in %d bytes",
1701                               nbytes),
1702                     reloc_howto->name, nbytes);
1703           else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC
1704                    || reloc == BFD_RELOC_XTENSA_TLS_ARG
1705                    || reloc == BFD_RELOC_XTENSA_TLS_CALL)
1706             as_bad (_("invalid use of %s relocation"), reloc_howto->name);
1707           else
1708             {
1709               char *p = frag_more ((int) nbytes);
1710               xtensa_set_frag_assembly_state (frag_now);
1711               fix_new_exp (frag_now, p - frag_now->fr_literal,
1712                            nbytes, &exp, reloc_howto->pc_relative, reloc);
1713             }
1714         }
1715       else
1716         {
1717           xtensa_set_frag_assembly_state (frag_now);
1718           emit_expr (&exp, (unsigned int) nbytes);
1719         }
1720     }
1721   while (*input_line_pointer++ == ',');
1722
1723   input_line_pointer--;         /* Put terminator back into stream.  */
1724   demand_empty_rest_of_line ();
1725 }
1726
1727 static bool is_leb128_expr;
1728
1729 static void
1730 xtensa_leb128 (int sign)
1731 {
1732   is_leb128_expr = true;
1733   s_leb128 (sign);
1734   is_leb128_expr = false;
1735 }
1736
1737 \f
1738 /* Parsing and Idiom Translation.  */
1739
1740 /* Parse @plt, etc. and return the desired relocation.  */
1741 static bfd_reloc_code_real_type
1742 xtensa_elf_suffix (char **str_p, expressionS *exp_p)
1743 {
1744   char ident[20];
1745   char *str = *str_p;
1746   char *str2;
1747   int ch;
1748   int len;
1749   unsigned int i;
1750
1751   if (*str++ != '@')
1752     return BFD_RELOC_NONE;
1753
1754   for (ch = *str, str2 = ident;
1755        (str2 < ident + sizeof (ident) - 1
1756         && (ISALNUM (ch) || ch == '@'));
1757        ch = *++str)
1758     {
1759       *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
1760     }
1761
1762   *str2 = '\0';
1763   len = str2 - ident;
1764
1765   ch = ident[0];
1766   for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1767     if (ch == suffix_relocs[i].suffix[0]
1768         && len == suffix_relocs[i].length
1769         && memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0)
1770       {
1771         /* Now check for "identifier@suffix+constant".  */
1772         if (*str == '-' || *str == '+')
1773           {
1774             char *orig_line = input_line_pointer;
1775             expressionS new_exp;
1776
1777             input_line_pointer = str;
1778             expression (&new_exp);
1779             if (new_exp.X_op == O_constant)
1780               {
1781                 exp_p->X_add_number += new_exp.X_add_number;
1782                 str = input_line_pointer;
1783               }
1784
1785             if (&input_line_pointer != str_p)
1786               input_line_pointer = orig_line;
1787           }
1788
1789         *str_p = str;
1790         return suffix_relocs[i].reloc;
1791       }
1792
1793   return BFD_RELOC_UNUSED;
1794 }
1795
1796
1797 /* Find the matching operator type.  */
1798 static operatorT
1799 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc)
1800 {
1801   operatorT operator = O_illegal;
1802   unsigned int i;
1803
1804   for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1805     {
1806       if (suffix_relocs[i].reloc == reloc)
1807         {
1808           operator = suffix_relocs[i].operator;
1809           break;
1810         }
1811     }
1812   gas_assert (operator != O_illegal);
1813   return operator;
1814 }
1815
1816
1817 /* Find the matching reloc type.  */
1818 static bfd_reloc_code_real_type
1819 map_operator_to_reloc (unsigned char operator, bool is_literal)
1820 {
1821   unsigned int i;
1822   bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
1823
1824   for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++)
1825     {
1826       if (suffix_relocs[i].operator == operator)
1827         {
1828           reloc = suffix_relocs[i].reloc;
1829           break;
1830         }
1831     }
1832
1833   if (is_literal)
1834     {
1835       if (reloc == BFD_RELOC_XTENSA_TLS_FUNC)
1836         return BFD_RELOC_XTENSA_TLSDESC_FN;
1837       else if (reloc == BFD_RELOC_XTENSA_TLS_ARG)
1838         return BFD_RELOC_XTENSA_TLSDESC_ARG;
1839     }
1840
1841   if (reloc == BFD_RELOC_UNUSED)
1842     return BFD_RELOC_32;
1843
1844   return reloc;
1845 }
1846
1847
1848 static const char *
1849 expression_end (const char *name)
1850 {
1851   while (1)
1852     {
1853       switch (*name)
1854         {
1855         case '}':
1856         case ';':
1857         case '\0':
1858         case ',':
1859         case ':':
1860           return name;
1861         case ' ':
1862         case '\t':
1863           ++name;
1864           continue;
1865         default:
1866           return 0;
1867         }
1868     }
1869 }
1870
1871
1872 #define ERROR_REG_NUM ((unsigned) -1)
1873
1874 static unsigned
1875 tc_get_register (const char *prefix)
1876 {
1877   unsigned reg;
1878   const char *next_expr;
1879   const char *old_line_pointer;
1880
1881   SKIP_WHITESPACE ();
1882   old_line_pointer = input_line_pointer;
1883
1884   if (*input_line_pointer == '$')
1885     ++input_line_pointer;
1886
1887   /* Accept "sp" as a synonym for "a1".  */
1888   if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p'
1889       && expression_end (input_line_pointer + 2))
1890     {
1891       input_line_pointer += 2;
1892       return 1;  /* AR[1] */
1893     }
1894
1895   while (*input_line_pointer++ == *prefix++)
1896     ;
1897   --input_line_pointer;
1898   --prefix;
1899
1900   if (*prefix)
1901     {
1902       as_bad (_("bad register name: %s"), old_line_pointer);
1903       return ERROR_REG_NUM;
1904     }
1905
1906   if (!ISDIGIT ((unsigned char) *input_line_pointer))
1907     {
1908       as_bad (_("bad register number: %s"), input_line_pointer);
1909       return ERROR_REG_NUM;
1910     }
1911
1912   reg = 0;
1913
1914   while (ISDIGIT ((int) *input_line_pointer))
1915     reg = reg * 10 + *input_line_pointer++ - '0';
1916
1917   if (!(next_expr = expression_end (input_line_pointer)))
1918     {
1919       as_bad (_("bad register name: %s"), old_line_pointer);
1920       return ERROR_REG_NUM;
1921     }
1922
1923   input_line_pointer = (char *) next_expr;
1924
1925   return reg;
1926 }
1927
1928
1929 static void
1930 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
1931 {
1932   xtensa_isa isa = xtensa_default_isa;
1933
1934   /* Check if this is an immediate operand.  */
1935   if (xtensa_operand_is_register (isa, opc, opnd) == 0)
1936     {
1937       bfd_reloc_code_real_type reloc;
1938       segT t = expression (tok);
1939
1940       if (t == absolute_section
1941           && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
1942         {
1943           gas_assert (tok->X_op == O_constant);
1944           tok->X_op = O_symbol;
1945           tok->X_add_symbol = &abs_symbol;
1946         }
1947
1948       if ((tok->X_op == O_constant || tok->X_op == O_symbol)
1949           && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
1950               != BFD_RELOC_NONE))
1951         {
1952           switch (reloc)
1953             {
1954             case BFD_RELOC_LO16:
1955               if (tok->X_op == O_constant)
1956                 {
1957                   tok->X_add_number &= 0xffff;
1958                   return;
1959                 }
1960               break;
1961             case BFD_RELOC_HI16:
1962               if (tok->X_op == O_constant)
1963                 {
1964                   tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
1965                   return;
1966                 }
1967               break;
1968             case BFD_RELOC_UNUSED:
1969               as_bad (_("unsupported relocation"));
1970               return;
1971             case BFD_RELOC_32_PCREL:
1972               as_bad (_("pcrel relocation not allowed in an instruction"));
1973               return;
1974             default:
1975               break;
1976             }
1977           tok->X_op = map_suffix_reloc_to_operator (reloc);
1978         }
1979     }
1980   else
1981     {
1982       xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
1983       unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
1984
1985       if (reg != ERROR_REG_NUM) /* Already errored */
1986         {
1987           uint32 buf = reg;
1988           if (xtensa_operand_encode (isa, opc, opnd, &buf))
1989             as_bad (_("register number out of range"));
1990         }
1991
1992       tok->X_op = O_register;
1993       tok->X_add_symbol = 0;
1994       tok->X_add_number = reg;
1995     }
1996 }
1997
1998
1999 /* Split up the arguments for an opcode or pseudo-op.  */
2000
2001 static int
2002 tokenize_arguments (char **args, char *str)
2003 {
2004   char *old_input_line_pointer;
2005   bool saw_comma = false;
2006   bool saw_arg = false;
2007   bool saw_colon = false;
2008   int num_args = 0;
2009   char *arg_end, *arg;
2010   int arg_len;
2011
2012   /* Save and restore input_line_pointer around this function.  */
2013   old_input_line_pointer = input_line_pointer;
2014   input_line_pointer = str;
2015
2016   while (*input_line_pointer)
2017     {
2018       SKIP_WHITESPACE ();
2019       switch (*input_line_pointer)
2020         {
2021         case '\0':
2022         case '}':
2023           goto fini;
2024
2025         case ':':
2026           input_line_pointer++;
2027           if (saw_comma || saw_colon || !saw_arg)
2028             goto err;
2029           saw_colon = true;
2030           break;
2031
2032         case ',':
2033           input_line_pointer++;
2034           if (saw_comma || saw_colon || !saw_arg)
2035             goto err;
2036           saw_comma = true;
2037           break;
2038
2039         default:
2040           if (!saw_comma && !saw_colon && saw_arg)
2041             goto err;
2042
2043           arg_end = input_line_pointer + 1;
2044           while (!expression_end (arg_end))
2045             arg_end += 1;
2046
2047           arg_len = arg_end - input_line_pointer;
2048           arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1);
2049           args[num_args] = arg;
2050
2051           if (saw_colon)
2052             *arg++ = ':';
2053           strncpy (arg, input_line_pointer, arg_len);
2054           arg[arg_len] = '\0';
2055
2056           input_line_pointer = arg_end;
2057           num_args += 1;
2058           saw_comma = false;
2059           saw_colon = false;
2060           saw_arg = true;
2061           break;
2062         }
2063     }
2064
2065  fini:
2066   if (saw_comma || saw_colon)
2067     goto err;
2068   input_line_pointer = old_input_line_pointer;
2069   return num_args;
2070
2071  err:
2072   if (saw_comma)
2073     as_bad (_("extra comma"));
2074   else if (saw_colon)
2075     as_bad (_("extra colon"));
2076   else if (!saw_arg)
2077     as_bad (_("missing argument"));
2078   else
2079     as_bad (_("missing comma or colon"));
2080   input_line_pointer = old_input_line_pointer;
2081   return -1;
2082 }
2083
2084
2085 /* Parse the arguments to an opcode.  Return TRUE on error.  */
2086
2087 static bool
2088 parse_arguments (TInsn *insn, int num_args, char **arg_strings)
2089 {
2090   expressionS *tok, *last_tok;
2091   xtensa_opcode opcode = insn->opcode;
2092   bool had_error = true;
2093   xtensa_isa isa = xtensa_default_isa;
2094   int n, num_regs = 0;
2095   int opcode_operand_count;
2096   int opnd_cnt, last_opnd_cnt;
2097   unsigned int next_reg = 0;
2098   char *old_input_line_pointer;
2099
2100   if (insn->insn_type == ITYPE_LITERAL)
2101     opcode_operand_count = 1;
2102   else
2103     opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
2104
2105   tok = insn->tok;
2106   memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
2107
2108   /* Save and restore input_line_pointer around this function.  */
2109   old_input_line_pointer = input_line_pointer;
2110
2111   last_tok = 0;
2112   last_opnd_cnt = -1;
2113   opnd_cnt = 0;
2114
2115   /* Skip invisible operands.  */
2116   while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
2117     {
2118       opnd_cnt += 1;
2119       tok++;
2120     }
2121
2122   for (n = 0; n < num_args; n++)
2123     {
2124       input_line_pointer = arg_strings[n];
2125       if (*input_line_pointer == ':')
2126         {
2127           xtensa_regfile opnd_rf;
2128           input_line_pointer++;
2129           if (num_regs == 0)
2130             goto err;
2131           gas_assert (opnd_cnt > 0);
2132           num_regs--;
2133           opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
2134           if (next_reg
2135               != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
2136             as_warn (_("incorrect register number, ignoring"));
2137           next_reg++;
2138         }
2139       else
2140         {
2141           if (opnd_cnt >= opcode_operand_count)
2142             {
2143               as_warn (_("too many arguments"));
2144               goto err;
2145             }
2146           gas_assert (opnd_cnt < MAX_INSN_ARGS);
2147
2148           expression_maybe_register (opcode, opnd_cnt, tok);
2149           next_reg = tok->X_add_number + 1;
2150
2151           if (tok->X_op == O_illegal || tok->X_op == O_absent)
2152             goto err;
2153           if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
2154             {
2155               num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
2156               /* minus 1 because we are seeing one right now */
2157             }
2158           else
2159             num_regs = 0;
2160
2161           last_tok = tok;
2162           last_opnd_cnt = opnd_cnt;
2163           demand_empty_rest_of_line ();
2164
2165           do
2166             {
2167               opnd_cnt += 1;
2168               tok++;
2169             }
2170           while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
2171         }
2172     }
2173
2174   if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
2175     goto err;
2176
2177   insn->ntok = tok - insn->tok;
2178   had_error = false;
2179
2180  err:
2181   input_line_pointer = old_input_line_pointer;
2182   return had_error;
2183 }
2184
2185
2186 static int
2187 get_invisible_operands (TInsn *insn)
2188 {
2189   xtensa_isa isa = xtensa_default_isa;
2190   static xtensa_insnbuf slotbuf = NULL;
2191   xtensa_format fmt;
2192   xtensa_opcode opc = insn->opcode;
2193   int slot, opnd, fmt_found;
2194   unsigned val;
2195
2196   if (!slotbuf)
2197     slotbuf = xtensa_insnbuf_alloc (isa);
2198
2199   /* Find format/slot where this can be encoded.  */
2200   fmt_found = 0;
2201   slot = 0;
2202   for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
2203     {
2204       for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
2205         {
2206           if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
2207             {
2208               fmt_found = 1;
2209               break;
2210             }
2211         }
2212       if (fmt_found) break;
2213     }
2214
2215   if (!fmt_found)
2216     {
2217       as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
2218       return -1;
2219     }
2220
2221   /* First encode all the visible operands
2222      (to deal with shared field operands).  */
2223   for (opnd = 0; opnd < insn->ntok; opnd++)
2224     {
2225       if (xtensa_operand_is_visible (isa, opc, opnd) == 1
2226           && (insn->tok[opnd].X_op == O_register
2227               || insn->tok[opnd].X_op == O_constant))
2228         {
2229           val = insn->tok[opnd].X_add_number;
2230           xtensa_operand_encode (isa, opc, opnd, &val);
2231           xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
2232         }
2233     }
2234
2235   /* Then pull out the values for the invisible ones.  */
2236   for (opnd = 0; opnd < insn->ntok; opnd++)
2237     {
2238       if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
2239         {
2240           xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
2241           xtensa_operand_decode (isa, opc, opnd, &val);
2242           insn->tok[opnd].X_add_number = val;
2243           if (xtensa_operand_is_register (isa, opc, opnd) == 1)
2244             insn->tok[opnd].X_op = O_register;
2245           else
2246             insn->tok[opnd].X_op = O_constant;
2247         }
2248     }
2249
2250   return 0;
2251 }
2252
2253
2254 static void
2255 xg_reverse_shift_count (char **cnt_argp)
2256 {
2257   char *cnt_arg, *new_arg;
2258   cnt_arg = *cnt_argp;
2259
2260   /* replace the argument with "31-(argument)" */
2261   new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL);
2262
2263   free (cnt_arg);
2264   *cnt_argp = new_arg;
2265 }
2266
2267
2268 /* If "arg" is a constant expression, return non-zero with the value
2269    in *valp.  */
2270
2271 static int
2272 xg_arg_is_constant (char *arg, offsetT *valp)
2273 {
2274   expressionS exp;
2275   char *save_ptr = input_line_pointer;
2276
2277   input_line_pointer = arg;
2278   expression (&exp);
2279   input_line_pointer = save_ptr;
2280
2281   if (exp.X_op == O_constant)
2282     {
2283       *valp = exp.X_add_number;
2284       return 1;
2285     }
2286
2287   return 0;
2288 }
2289
2290
2291 static void
2292 xg_replace_opname (char **popname, const char *newop)
2293 {
2294   free (*popname);
2295   *popname = xstrdup (newop);
2296 }
2297
2298
2299 static int
2300 xg_check_num_args (int *pnum_args,
2301                    int expected_num,
2302                    char *opname,
2303                    char **arg_strings)
2304 {
2305   int num_args = *pnum_args;
2306
2307   if (num_args < expected_num)
2308     {
2309       as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2310               num_args, opname, expected_num);
2311       return -1;
2312     }
2313
2314   if (num_args > expected_num)
2315     {
2316       as_warn (_("too many operands (%d) for '%s'; expected %d"),
2317                num_args, opname, expected_num);
2318       while (num_args-- > expected_num)
2319         {
2320           free (arg_strings[num_args]);
2321           arg_strings[num_args] = 0;
2322         }
2323       *pnum_args = expected_num;
2324       return -1;
2325     }
2326
2327   return 0;
2328 }
2329
2330
2331 /* If the register is not specified as part of the opcode,
2332    then get it from the operand and move it to the opcode.  */
2333
2334 static int
2335 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
2336 {
2337   xtensa_isa isa = xtensa_default_isa;
2338   xtensa_sysreg sr;
2339   char *opname, *new_opname;
2340   const char *sr_name;
2341   int is_user, is_write;
2342
2343   opname = *popname;
2344   if (*opname == '_')
2345     opname += 1;
2346   is_user = (opname[1] == 'u');
2347   is_write = (opname[0] == 'w');
2348
2349   /* Opname == [rw]ur or [rwx]sr... */
2350
2351   if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2352     return -1;
2353
2354   /* Check if the argument is a symbolic register name.  */
2355   sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
2356   /* Handle WSR to "INTSET" as a special case.  */
2357   if (sr == XTENSA_UNDEFINED && is_write && !is_user
2358       && !strcasecmp (arg_strings[1], "intset"))
2359     sr = xtensa_sysreg_lookup_name (isa, "interrupt");
2360   if (sr == XTENSA_UNDEFINED
2361       || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
2362     {
2363       /* Maybe it's a register number.... */
2364       offsetT val;
2365       if (!xg_arg_is_constant (arg_strings[1], &val))
2366         {
2367           as_bad (_("invalid register '%s' for '%s' instruction"),
2368                   arg_strings[1], opname);
2369           return -1;
2370         }
2371       sr = xtensa_sysreg_lookup (isa, val, is_user);
2372       if (sr == XTENSA_UNDEFINED)
2373         {
2374           as_bad (_("invalid register number (%ld) for '%s' instruction"),
2375                   (long) val, opname);
2376           return -1;
2377         }
2378     }
2379
2380   /* Remove the last argument, which is now part of the opcode.  */
2381   free (arg_strings[1]);
2382   arg_strings[1] = 0;
2383   *pnum_args = 1;
2384
2385   /* Translate the opcode.  */
2386   sr_name = xtensa_sysreg_name (isa, sr);
2387   /* Another special case for "WSR.INTSET"....  */
2388   if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
2389     sr_name = "intset";
2390   new_opname = concat (*popname, ".", sr_name, (char *) NULL);
2391   free (*popname);
2392   *popname = new_opname;
2393
2394   return 0;
2395 }
2396
2397
2398 static int
2399 xtensa_translate_old_userreg_ops (char **popname)
2400 {
2401   xtensa_isa isa = xtensa_default_isa;
2402   xtensa_sysreg sr;
2403   char *opname, *new_opname;
2404   const char *sr_name;
2405   bool has_underbar = false;
2406
2407   opname = *popname;
2408   if (opname[0] == '_')
2409     {
2410       has_underbar = true;
2411       opname += 1;
2412     }
2413
2414   sr = xtensa_sysreg_lookup_name (isa, opname + 1);
2415   if (sr != XTENSA_UNDEFINED)
2416     {
2417       /* The new default name ("nnn") is different from the old default
2418          name ("URnnn").  The old default is handled below, and we don't
2419          want to recognize [RW]nnn, so do nothing if the name is the (new)
2420          default.  */
2421       static char namebuf[10];
2422       sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
2423       if (strcmp (namebuf, opname + 1) == 0)
2424         return 0;
2425     }
2426   else
2427     {
2428       offsetT val;
2429       char *end;
2430
2431       /* Only continue if the reg name is "URnnn".  */
2432       if (opname[1] != 'u' || opname[2] != 'r')
2433         return 0;
2434       val = strtoul (opname + 3, &end, 10);
2435       if (*end != '\0')
2436         return 0;
2437
2438       sr = xtensa_sysreg_lookup (isa, val, 1);
2439       if (sr == XTENSA_UNDEFINED)
2440         {
2441           as_bad (_("invalid register number (%ld) for '%s'"),
2442                   (long) val, opname);
2443           return -1;
2444         }
2445     }
2446
2447   /* Translate the opcode.  */
2448   sr_name = xtensa_sysreg_name (isa, sr);
2449   new_opname = XNEWVEC (char, strlen (sr_name) + 6);
2450   sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
2451            opname[0], sr_name);
2452   free (*popname);
2453   *popname = new_opname;
2454
2455   return 0;
2456 }
2457
2458
2459 static int
2460 xtensa_translate_zero_immed (const char *old_op,
2461                              const char *new_op,
2462                              char **popname,
2463                              int *pnum_args,
2464                              char **arg_strings)
2465 {
2466   char *opname;
2467   offsetT val;
2468
2469   opname = *popname;
2470   gas_assert (opname[0] != '_');
2471
2472   if (strcmp (opname, old_op) != 0)
2473     return 0;
2474
2475   if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2476     return -1;
2477   if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
2478     {
2479       xg_replace_opname (popname, new_op);
2480       free (arg_strings[1]);
2481       arg_strings[1] = arg_strings[2];
2482       arg_strings[2] = 0;
2483       *pnum_args = 2;
2484     }
2485
2486   return 0;
2487 }
2488
2489
2490 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2491    Returns non-zero if an error was found.  */
2492
2493 static int
2494 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
2495 {
2496   char *opname = *popname;
2497   bool has_underbar = false;
2498
2499   if (*opname == '_')
2500     {
2501       has_underbar = true;
2502       opname += 1;
2503     }
2504
2505   if (strcmp (opname, "mov") == 0)
2506     {
2507       if (use_transform () && !has_underbar && density_supported)
2508         xg_replace_opname (popname, "mov.n");
2509       else
2510         {
2511           if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
2512             return -1;
2513           xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2514           arg_strings[2] = xstrdup (arg_strings[1]);
2515           *pnum_args = 3;
2516         }
2517       return 0;
2518     }
2519
2520   /* Without an operand, this is given a default immediate operand of 0.  */
2521   if ((strcmp (opname, "simcall") == 0 && microarch_earliest >= 280000))
2522     {
2523       if (*pnum_args == 0)
2524         {
2525           arg_strings[0] = (char *) xmalloc (2);
2526           strcpy (arg_strings[0], "0");
2527           *pnum_args = 1;
2528         }
2529       return 0;
2530     }
2531
2532   if (strcmp (opname, "bbsi.l") == 0)
2533     {
2534       if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2535         return -1;
2536       xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi"));
2537       if (target_big_endian)
2538         xg_reverse_shift_count (&arg_strings[1]);
2539       return 0;
2540     }
2541
2542   if (strcmp (opname, "bbci.l") == 0)
2543     {
2544       if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
2545         return -1;
2546       xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci"));
2547       if (target_big_endian)
2548         xg_reverse_shift_count (&arg_strings[1]);
2549       return 0;
2550     }
2551
2552   /* Don't do anything special with NOPs inside FLIX instructions.  They
2553      are handled elsewhere.  Real NOP instructions are always available
2554      in configurations with FLIX, so this should never be an issue but
2555      check for it anyway.  */
2556   if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED
2557       && strcmp (opname, "nop") == 0)
2558     {
2559       if (use_transform () && !has_underbar && density_supported)
2560         xg_replace_opname (popname, "nop.n");
2561       else
2562         {
2563           if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
2564             return -1;
2565           xg_replace_opname (popname, (has_underbar ? "_or" : "or"));
2566           arg_strings[0] = xstrdup ("a1");
2567           arg_strings[1] = xstrdup ("a1");
2568           arg_strings[2] = xstrdup ("a1");
2569           *pnum_args = 3;
2570         }
2571       return 0;
2572     }
2573
2574   /* Recognize [RW]UR and [RWX]SR.  */
2575   if ((((opname[0] == 'r' || opname[0] == 'w')
2576         && (opname[1] == 'u' || opname[1] == 's'))
2577        || (opname[0] == 'x' && opname[1] == 's'))
2578       && opname[2] == 'r'
2579       && opname[3] == '\0')
2580     return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
2581
2582   /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2583      [RW]<name> if <name> is the non-default name of a user register.  */
2584   if ((opname[0] == 'r' || opname[0] == 'w')
2585       && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
2586     return xtensa_translate_old_userreg_ops (popname);
2587
2588   /* Relax branches that don't allow comparisons against an immediate value
2589      of zero to the corresponding branches with implicit zero immediates.  */
2590   if (!has_underbar && use_transform ())
2591     {
2592       if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
2593                                        pnum_args, arg_strings))
2594         return -1;
2595
2596       if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
2597                                        pnum_args, arg_strings))
2598         return -1;
2599
2600       if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
2601                                        pnum_args, arg_strings))
2602         return -1;
2603
2604       if (xtensa_translate_zero_immed ("blti", "bltz", popname,
2605                                        pnum_args, arg_strings))
2606         return -1;
2607     }
2608
2609   return 0;
2610 }
2611
2612 \f
2613 /* Functions for dealing with the Xtensa ISA.  */
2614
2615 /* Currently the assembler only allows us to use a single target per
2616    fragment.  Because of this, only one operand for a given
2617    instruction may be symbolic.  If there is a PC-relative operand,
2618    the last one is chosen.  Otherwise, the result is the number of the
2619    last immediate operand, and if there are none of those, we fail and
2620    return -1.  */
2621
2622 static int
2623 get_relaxable_immed (xtensa_opcode opcode)
2624 {
2625   int last_immed = -1;
2626   int noperands, opi;
2627
2628   if (opcode == XTENSA_UNDEFINED)
2629     return -1;
2630
2631   noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
2632   for (opi = noperands - 1; opi >= 0; opi--)
2633     {
2634       if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
2635         continue;
2636       if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
2637         return opi;
2638       if (last_immed == -1
2639           && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
2640         last_immed = opi;
2641     }
2642   return last_immed;
2643 }
2644
2645
2646 static xtensa_opcode
2647 get_opcode_from_buf (const char *buf, int slot)
2648 {
2649   static xtensa_insnbuf insnbuf = NULL;
2650   static xtensa_insnbuf slotbuf = NULL;
2651   xtensa_isa isa = xtensa_default_isa;
2652   xtensa_format fmt;
2653
2654   if (!insnbuf)
2655     {
2656       insnbuf = xtensa_insnbuf_alloc (isa);
2657       slotbuf = xtensa_insnbuf_alloc (isa);
2658     }
2659
2660   xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0);
2661   fmt = xtensa_format_decode (isa, insnbuf);
2662   if (fmt == XTENSA_UNDEFINED)
2663     return XTENSA_UNDEFINED;
2664
2665   if (slot >= xtensa_format_num_slots (isa, fmt))
2666     return XTENSA_UNDEFINED;
2667
2668   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
2669   return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
2670 }
2671
2672
2673 #ifdef TENSILICA_DEBUG
2674
2675 /* For debugging, print out the mapping of opcode numbers to opcodes.  */
2676
2677 static void
2678 xtensa_print_insn_table (void)
2679 {
2680   int num_opcodes, num_operands;
2681   xtensa_opcode opcode;
2682   xtensa_isa isa = xtensa_default_isa;
2683
2684   num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
2685   for (opcode = 0; opcode < num_opcodes; opcode++)
2686     {
2687       int opn;
2688       fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
2689       num_operands = xtensa_opcode_num_operands (isa, opcode);
2690       for (opn = 0; opn < num_operands; opn++)
2691         {
2692           if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
2693             continue;
2694           if (xtensa_operand_is_register (isa, opcode, opn) == 1)
2695             {
2696               xtensa_regfile opnd_rf =
2697                 xtensa_operand_regfile (isa, opcode, opn);
2698               fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
2699             }
2700           else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
2701             fputs ("[lLr] ", stderr);
2702           else
2703             fputs ("i ", stderr);
2704         }
2705       fprintf (stderr, "\n");
2706     }
2707 }
2708
2709
2710 static void
2711 print_vliw_insn (xtensa_insnbuf vbuf)
2712 {
2713   xtensa_isa isa = xtensa_default_isa;
2714   xtensa_format f = xtensa_format_decode (isa, vbuf);
2715   xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
2716   int op;
2717
2718   fprintf (stderr, "format = %d\n", f);
2719
2720   for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
2721     {
2722       xtensa_opcode opcode;
2723       const char *opname;
2724       int operands;
2725
2726       xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
2727       opcode = xtensa_opcode_decode (isa, f, op, sbuf);
2728       opname = xtensa_opcode_name (isa, opcode);
2729
2730       fprintf (stderr, "op in slot %i is %s;\n", op, opname);
2731       fprintf (stderr, "   operands = ");
2732       for (operands = 0;
2733            operands < xtensa_opcode_num_operands (isa, opcode);
2734            operands++)
2735         {
2736           unsigned int val;
2737           if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
2738             continue;
2739           xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
2740           xtensa_operand_decode (isa, opcode, operands, &val);
2741           fprintf (stderr, "%d ", val);
2742         }
2743       fprintf (stderr, "\n");
2744     }
2745   xtensa_insnbuf_free (isa, sbuf);
2746 }
2747
2748 #endif /* TENSILICA_DEBUG */
2749
2750
2751 static bool
2752 is_direct_call_opcode (xtensa_opcode opcode)
2753 {
2754   xtensa_isa isa = xtensa_default_isa;
2755   int n, num_operands;
2756
2757   if (xtensa_opcode_is_call (isa, opcode) != 1)
2758     return false;
2759
2760   num_operands = xtensa_opcode_num_operands (isa, opcode);
2761   for (n = 0; n < num_operands; n++)
2762     {
2763       if (xtensa_operand_is_register (isa, opcode, n) == 0
2764           && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
2765         return true;
2766     }
2767   return false;
2768 }
2769
2770
2771 /* Convert from BFD relocation type code to slot and operand number.
2772    Returns non-zero on failure.  */
2773
2774 static int
2775 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bool *is_alt)
2776 {
2777   if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
2778       && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
2779     {
2780       *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
2781       *is_alt = false;
2782     }
2783   else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
2784       && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
2785     {
2786       *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
2787       *is_alt = true;
2788     }
2789   else
2790     return -1;
2791
2792   return 0;
2793 }
2794
2795
2796 /* Convert from slot number to BFD relocation type code for the
2797    standard PC-relative relocations.  Return BFD_RELOC_NONE on
2798    failure.  */
2799
2800 static bfd_reloc_code_real_type
2801 encode_reloc (int slot)
2802 {
2803   if (slot < 0 || slot > 14)
2804     return BFD_RELOC_NONE;
2805
2806   return BFD_RELOC_XTENSA_SLOT0_OP + slot;
2807 }
2808
2809
2810 /* Convert from slot numbers to BFD relocation type code for the
2811    "alternate" relocations.  Return BFD_RELOC_NONE on failure.  */
2812
2813 static bfd_reloc_code_real_type
2814 encode_alt_reloc (int slot)
2815 {
2816   if (slot < 0 || slot > 14)
2817     return BFD_RELOC_NONE;
2818
2819   return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
2820 }
2821
2822
2823 static void
2824 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
2825                             xtensa_format fmt,
2826                             int slot,
2827                             xtensa_opcode opcode,
2828                             int operand,
2829                             uint32 value,
2830                             const char *file,
2831                             unsigned int line)
2832 {
2833   uint32 valbuf = value;
2834
2835   if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
2836     {
2837       if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
2838           == 1)
2839         as_bad_where ((char *) file, line,
2840                       _("operand %d of '%s' has out of range value '%u'"),
2841                       operand + 1,
2842                       xtensa_opcode_name (xtensa_default_isa, opcode),
2843                       value);
2844       else
2845         as_bad_where ((char *) file, line,
2846                       _("operand %d of '%s' has invalid value '%u'"),
2847                       operand + 1,
2848                       xtensa_opcode_name (xtensa_default_isa, opcode),
2849                       value);
2850       return;
2851     }
2852
2853   xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
2854                             slotbuf, valbuf);
2855 }
2856
2857
2858 static uint32
2859 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
2860                             xtensa_format fmt,
2861                             int slot,
2862                             xtensa_opcode opcode,
2863                             int opnum)
2864 {
2865   uint32 val = 0;
2866   (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
2867                                    fmt, slot, slotbuf, &val);
2868   (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
2869   return val;
2870 }
2871
2872 \f
2873 /* Checks for rules from xtensa-relax tables.  */
2874
2875 /* The routine xg_instruction_matches_option_term must return TRUE
2876    when a given option term is true.  The meaning of all of the option
2877    terms is given interpretation by this function.  */
2878
2879 static bool
2880 xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option)
2881 {
2882   if (strcmp (option->option_name, "realnop") == 0
2883       || startswith (option->option_name, "IsaUse"))
2884     {
2885       /* These conditions were evaluated statically when building the
2886          relaxation table.  There's no need to reevaluate them now.  */
2887       return true;
2888     }
2889   else if (strcmp (option->option_name, "FREEREG") == 0)
2890     return insn->extra_arg.X_op == O_register;
2891   else
2892     {
2893       as_fatal (_("internal error: unknown option name '%s'"),
2894                 option->option_name);
2895     }
2896 }
2897
2898
2899 static bool
2900 xg_instruction_matches_or_options (TInsn *insn,
2901                                    const ReqOrOptionList *or_option)
2902 {
2903   const ReqOrOption *option;
2904   /* Must match each of the AND terms.  */
2905   for (option = or_option; option != NULL; option = option->next)
2906     {
2907       if (xg_instruction_matches_option_term (insn, option))
2908         return true;
2909     }
2910   return false;
2911 }
2912
2913
2914 static bool
2915 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
2916 {
2917   const ReqOption *req_options;
2918   /* Must match each of the AND terms.  */
2919   for (req_options = options;
2920        req_options != NULL;
2921        req_options = req_options->next)
2922     {
2923       /* Must match one of the OR clauses.  */
2924       if (!xg_instruction_matches_or_options (insn,
2925                                               req_options->or_option_terms))
2926         return false;
2927     }
2928   return true;
2929 }
2930
2931
2932 /* Return the transition rule that matches or NULL if none matches.  */
2933
2934 static bool
2935 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
2936 {
2937   PreconditionList *condition_l;
2938
2939   if (rule->opcode != insn->opcode)
2940     return false;
2941
2942   for (condition_l = rule->conditions;
2943        condition_l != NULL;
2944        condition_l = condition_l->next)
2945     {
2946       expressionS *exp1;
2947       expressionS *exp2;
2948       Precondition *cond = condition_l->precond;
2949
2950       switch (cond->typ)
2951         {
2952         case OP_CONSTANT:
2953           /* The expression must be the constant.  */
2954           gas_assert (cond->op_num < insn->ntok);
2955           exp1 = &insn->tok[cond->op_num];
2956           if (expr_is_const (exp1))
2957             {
2958               switch (cond->cmp)
2959                 {
2960                 case OP_EQUAL:
2961                   if (get_expr_const (exp1) != cond->op_data)
2962                     return false;
2963                   break;
2964                 case OP_NOTEQUAL:
2965                   if (get_expr_const (exp1) == cond->op_data)
2966                     return false;
2967                   break;
2968                 default:
2969                   return false;
2970                 }
2971             }
2972           else if (expr_is_register (exp1))
2973             {
2974               switch (cond->cmp)
2975                 {
2976                 case OP_EQUAL:
2977                   if (get_expr_register (exp1) != cond->op_data)
2978                     return false;
2979                   break;
2980                 case OP_NOTEQUAL:
2981                   if (get_expr_register (exp1) == cond->op_data)
2982                     return false;
2983                   break;
2984                 default:
2985                   return false;
2986                 }
2987             }
2988           else
2989             return false;
2990           break;
2991
2992         case OP_OPERAND:
2993           gas_assert (cond->op_num < insn->ntok);
2994           gas_assert (cond->op_data < insn->ntok);
2995           exp1 = &insn->tok[cond->op_num];
2996           exp2 = &insn->tok[cond->op_data];
2997
2998           switch (cond->cmp)
2999             {
3000             case OP_EQUAL:
3001               if (!expr_is_equal (exp1, exp2))
3002                 return false;
3003               break;
3004             case OP_NOTEQUAL:
3005               if (expr_is_equal (exp1, exp2))
3006                 return false;
3007               break;
3008             }
3009           break;
3010
3011         case OP_LITERAL:
3012         case OP_LABEL:
3013         default:
3014           return false;
3015         }
3016     }
3017   if (!xg_instruction_matches_options (insn, rule->options))
3018     return false;
3019
3020   return true;
3021 }
3022
3023
3024 static int
3025 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
3026 {
3027   bool a_greater = false;
3028   bool b_greater = false;
3029
3030   ReqOptionList *l_a = a->options;
3031   ReqOptionList *l_b = b->options;
3032
3033   /* We only care if they both are the same except for
3034      a const16 vs. an l32r.  */
3035
3036   while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
3037     {
3038       ReqOrOptionList *l_or_a = l_a->or_option_terms;
3039       ReqOrOptionList *l_or_b = l_b->or_option_terms;
3040       while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
3041         {
3042           if (l_or_a->is_true != l_or_b->is_true)
3043             return 0;
3044           if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
3045             {
3046               /* This is the case we care about.  */
3047               if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
3048                   && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
3049                 {
3050                   if (prefer_const16)
3051                     a_greater = true;
3052                   else
3053                     b_greater = true;
3054                 }
3055               else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
3056                        && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
3057                 {
3058                   if (prefer_const16)
3059                     b_greater = true;
3060                   else
3061                     a_greater = true;
3062                 }
3063               else
3064                 return 0;
3065             }
3066           l_or_a = l_or_a->next;
3067           l_or_b = l_or_b->next;
3068         }
3069       if (l_or_a || l_or_b)
3070         return 0;
3071
3072       l_a = l_a->next;
3073       l_b = l_b->next;
3074     }
3075   if (l_a || l_b)
3076     return 0;
3077
3078   /* Incomparable if the substitution was used differently in two cases.  */
3079   if (a_greater && b_greater)
3080     return 0;
3081
3082   if (b_greater)
3083     return 1;
3084   if (a_greater)
3085     return -1;
3086
3087   return 0;
3088 }
3089
3090
3091 static TransitionRule *
3092 xg_instruction_match (TInsn *insn)
3093 {
3094   TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
3095   TransitionList *l;
3096   gas_assert (insn->opcode < table->num_opcodes);
3097
3098   /* Walk through all of the possible transitions.  */
3099   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3100     {
3101       TransitionRule *rule = l->rule;
3102       if (xg_instruction_matches_rule (insn, rule))
3103         return rule;
3104     }
3105   return NULL;
3106 }
3107
3108 \f
3109 /* Various Other Internal Functions.  */
3110
3111 static bool
3112 is_unique_insn_expansion (TransitionRule *r)
3113 {
3114   if (!r->to_instr || r->to_instr->next != NULL)
3115     return false;
3116   if (r->to_instr->typ != INSTR_INSTR)
3117     return false;
3118   return true;
3119 }
3120
3121
3122 /* Check if there is exactly one relaxation for INSN that converts it to
3123    another instruction of equal or larger size.  If so, and if TARG is
3124    non-null, go ahead and generate the relaxed instruction into TARG.  If
3125    NARROW_ONLY is true, then only consider relaxations that widen a narrow
3126    instruction, i.e., ignore relaxations that convert to an instruction of
3127    equal size.  In some contexts where this function is used, only
3128    a single widening is allowed and the NARROW_ONLY argument is used to
3129    exclude cases like ADDI being "widened" to an ADDMI, which may
3130    later be relaxed to an ADDMI/ADDI pair.  */
3131
3132 bool
3133 xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bool narrow_only)
3134 {
3135   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3136   TransitionList *l;
3137   TransitionRule *match = 0;
3138
3139   gas_assert (insn->insn_type == ITYPE_INSN);
3140   gas_assert (insn->opcode < table->num_opcodes);
3141
3142   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3143     {
3144       TransitionRule *rule = l->rule;
3145
3146       if (xg_instruction_matches_rule (insn, rule)
3147           && is_unique_insn_expansion (rule)
3148           && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0)
3149               <= xg_get_single_size (rule->to_instr->opcode)))
3150         {
3151           if (match)
3152             return false;
3153           match = rule;
3154         }
3155     }
3156   if (!match)
3157     return false;
3158
3159   if (targ)
3160     xg_build_to_insn (targ, insn, match->to_instr);
3161   return true;
3162 }
3163
3164
3165 /* Return the maximum number of bytes this opcode can expand to.  */
3166
3167 static int
3168 xg_get_max_insn_widen_size (xtensa_opcode opcode)
3169 {
3170   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3171   TransitionList *l;
3172   int max_size = xg_get_single_size (opcode);
3173
3174   gas_assert (opcode < table->num_opcodes);
3175
3176   for (l = table->table[opcode]; l != NULL; l = l->next)
3177     {
3178       TransitionRule *rule = l->rule;
3179       BuildInstr *build_list;
3180       int this_size = 0;
3181
3182       if (!rule)
3183         continue;
3184       build_list = rule->to_instr;
3185       if (is_unique_insn_expansion (rule))
3186         {
3187           gas_assert (build_list->typ == INSTR_INSTR);
3188           this_size = xg_get_max_insn_widen_size (build_list->opcode);
3189         }
3190       else
3191         for (; build_list != NULL; build_list = build_list->next)
3192           {
3193             switch (build_list->typ)
3194               {
3195               case INSTR_INSTR:
3196                 this_size += xg_get_single_size (build_list->opcode);
3197                 break;
3198               case INSTR_LITERAL_DEF:
3199               case INSTR_LABEL_DEF:
3200               default:
3201                 break;
3202               }
3203           }
3204       if (this_size > max_size)
3205         max_size = this_size;
3206     }
3207   return max_size;
3208 }
3209
3210
3211 /* Return the maximum number of literal bytes this opcode can generate.  */
3212
3213 static int
3214 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
3215 {
3216   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3217   TransitionList *l;
3218   int max_size = 0;
3219
3220   gas_assert (opcode < table->num_opcodes);
3221
3222   for (l = table->table[opcode]; l != NULL; l = l->next)
3223     {
3224       TransitionRule *rule = l->rule;
3225       BuildInstr *build_list;
3226       int this_size = 0;
3227
3228       if (!rule)
3229         continue;
3230       build_list = rule->to_instr;
3231       if (is_unique_insn_expansion (rule))
3232         {
3233           gas_assert (build_list->typ == INSTR_INSTR);
3234           this_size = xg_get_max_insn_widen_literal_size (build_list->opcode);
3235         }
3236       else
3237         for (; build_list != NULL; build_list = build_list->next)
3238           {
3239             switch (build_list->typ)
3240               {
3241               case INSTR_LITERAL_DEF:
3242                 /* Hard-coded 4-byte literal.  */
3243                 this_size += 4;
3244                 break;
3245               case INSTR_INSTR:
3246               case INSTR_LABEL_DEF:
3247               default:
3248                 break;
3249               }
3250           }
3251       if (this_size > max_size)
3252         max_size = this_size;
3253     }
3254   return max_size;
3255 }
3256
3257
3258 static bool
3259 xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
3260 {
3261   int steps_taken = 0;
3262   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3263   TransitionList *l;
3264
3265   gas_assert (insn->insn_type == ITYPE_INSN);
3266   gas_assert (insn->opcode < table->num_opcodes);
3267
3268   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3269     {
3270       TransitionRule *rule = l->rule;
3271
3272       if (xg_instruction_matches_rule (insn, rule))
3273         {
3274           if (steps_taken == lateral_steps)
3275             return true;
3276           steps_taken++;
3277         }
3278     }
3279   return false;
3280 }
3281
3282
3283 static symbolS *
3284 get_special_literal_symbol (void)
3285 {
3286   static symbolS *sym = NULL;
3287
3288   if (sym == NULL)
3289     sym = symbol_find_or_make ("SPECIAL_LITERAL0\001");
3290   return sym;
3291 }
3292
3293
3294 static symbolS *
3295 get_special_label_symbol (void)
3296 {
3297   static symbolS *sym = NULL;
3298
3299   if (sym == NULL)
3300     sym = symbol_find_or_make ("SPECIAL_LABEL0\001");
3301   return sym;
3302 }
3303
3304
3305 static bool
3306 xg_valid_literal_expression (const expressionS *exp)
3307 {
3308   switch (exp->X_op)
3309     {
3310     case O_constant:
3311     case O_symbol:
3312     case O_big:
3313     case O_uminus:
3314     case O_subtract:
3315     case O_pltrel:
3316     case O_pcrel:
3317     case O_tlsfunc:
3318     case O_tlsarg:
3319     case O_tpoff:
3320     case O_dtpoff:
3321       return true;
3322     default:
3323       return false;
3324     }
3325 }
3326
3327
3328 /* This will check to see if the value can be converted into the
3329    operand type.  It will return TRUE if it does not fit.  */
3330
3331 static bool
3332 xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
3333 {
3334   uint32 valbuf = value;
3335   if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
3336     return true;
3337   return false;
3338 }
3339
3340
3341 /* Assumes: All immeds are constants.  Check that all constants fit
3342    into their immeds; return FALSE if not.  */
3343
3344 static bool
3345 xg_immeds_fit (const TInsn *insn)
3346 {
3347   xtensa_isa isa = xtensa_default_isa;
3348   int i;
3349
3350   int n = insn->ntok;
3351   gas_assert (insn->insn_type == ITYPE_INSN);
3352   for (i = 0; i < n; ++i)
3353     {
3354       const expressionS *exp = &insn->tok[i];
3355
3356       if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3357         continue;
3358
3359       switch (exp->X_op)
3360         {
3361         case O_register:
3362         case O_constant:
3363           if (xg_check_operand (exp->X_add_number, insn->opcode, i))
3364             return false;
3365           break;
3366
3367         default:
3368           /* The symbol should have a fixup associated with it.  */
3369           gas_assert (false);
3370           break;
3371         }
3372     }
3373   return true;
3374 }
3375
3376
3377 /* This should only be called after we have an initial
3378    estimate of the addresses.  */
3379
3380 static bool
3381 xg_symbolic_immeds_fit (const TInsn *insn,
3382                         segT pc_seg,
3383                         fragS *pc_frag,
3384                         offsetT pc_offset,
3385                         long stretch)
3386 {
3387   xtensa_isa isa = xtensa_default_isa;
3388   symbolS *symbolP;
3389   fragS *sym_frag;
3390   offsetT target, pc;
3391   uint32 new_offset;
3392   int i;
3393   int n = insn->ntok;
3394
3395   gas_assert (insn->insn_type == ITYPE_INSN);
3396
3397   for (i = 0; i < n; ++i)
3398     {
3399       const expressionS *exp = &insn->tok[i];
3400
3401       if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
3402         continue;
3403
3404       switch (exp->X_op)
3405         {
3406         case O_register:
3407         case O_constant:
3408           if (xg_check_operand (exp->X_add_number, insn->opcode, i))
3409             return false;
3410           break;
3411
3412         case O_lo16:
3413         case O_hi16:
3414           /* Check for the worst case.  */
3415           if (xg_check_operand (0xffff, insn->opcode, i))
3416             return false;
3417           break;
3418
3419         case O_symbol:
3420           /* We only allow symbols for PC-relative references.
3421              If pc_frag == 0, then we don't have frag locations yet.  */
3422           if (pc_frag == 0
3423               || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0)
3424             return false;
3425
3426           /* If it is a weak symbol or a symbol in a different section,
3427              it cannot be known to fit at assembly time.  */
3428           if (S_IS_WEAK (exp->X_add_symbol)
3429               || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg)
3430             {
3431               /* For a direct call with --no-longcalls, be optimistic and
3432                  assume it will be in range.  If the symbol is weak and
3433                  undefined, it may remain undefined at link-time, in which
3434                  case it will have a zero value and almost certainly be out
3435                  of range for a direct call; thus, relax for undefined weak
3436                  symbols even if longcalls is not enabled.  */
3437               if (is_direct_call_opcode (insn->opcode)
3438                   && ! pc_frag->tc_frag_data.use_longcalls
3439                   && (! S_IS_WEAK (exp->X_add_symbol)
3440                       || S_IS_DEFINED (exp->X_add_symbol)))
3441                 return true;
3442
3443               return false;
3444             }
3445
3446           symbolP = exp->X_add_symbol;
3447           sym_frag = symbol_get_frag (symbolP);
3448           target = S_GET_VALUE (symbolP) + exp->X_add_number;
3449           pc = pc_frag->fr_address + pc_offset;
3450
3451           /* If frag has yet to be reached on this pass, assume it
3452              will move by STRETCH just as we did.  If this is not so,
3453              it will be because some frag between grows, and that will
3454              force another pass.  Beware zero-length frags.  There
3455              should be a faster way to do this.  */
3456
3457           if (stretch != 0
3458               && sym_frag->relax_marker != pc_frag->relax_marker
3459               && S_GET_SEGMENT (symbolP) == pc_seg)
3460             {
3461               target += stretch;
3462             }
3463
3464           new_offset = target;
3465           xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
3466           if (xg_check_operand (new_offset, insn->opcode, i))
3467             return false;
3468           break;
3469
3470         default:
3471           /* The symbol should have a fixup associated with it.  */
3472           return false;
3473         }
3474     }
3475
3476   return true;
3477 }
3478
3479
3480 /* Return TRUE on success.  */
3481
3482 static bool
3483 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
3484 {
3485   BuildOp *op;
3486   symbolS *sym;
3487
3488   tinsn_init (targ);
3489   targ->debug_line = insn->debug_line;
3490   targ->loc_directive_seen = insn->loc_directive_seen;
3491   switch (bi->typ)
3492     {
3493     case INSTR_INSTR:
3494       op = bi->ops;
3495       targ->opcode = bi->opcode;
3496       targ->insn_type = ITYPE_INSN;
3497       targ->is_specific_opcode = false;
3498
3499       for (; op != NULL; op = op->next)
3500         {
3501           int op_num = op->op_num;
3502           int op_data = op->op_data;
3503
3504           gas_assert (op->op_num < MAX_INSN_ARGS);
3505
3506           if (targ->ntok <= op_num)
3507             targ->ntok = op_num + 1;
3508
3509           switch (op->typ)
3510             {
3511             case OP_CONSTANT:
3512               set_expr_const (&targ->tok[op_num], op_data);
3513               break;
3514             case OP_OPERAND:
3515               gas_assert (op_data < insn->ntok);
3516               copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3517               break;
3518             case OP_FREEREG:
3519               if (insn->extra_arg.X_op != O_register)
3520                 return false;
3521               copy_expr (&targ->tok[op_num], &insn->extra_arg);
3522               break;
3523             case OP_LITERAL:
3524               sym = get_special_literal_symbol ();
3525               set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3526               if (insn->tok[op_data].X_op == O_tlsfunc
3527                   || insn->tok[op_data].X_op == O_tlsarg)
3528                 copy_expr (&targ->extra_arg, &insn->tok[op_data]);
3529               break;
3530             case OP_LABEL:
3531               sym = get_special_label_symbol ();
3532               set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
3533               break;
3534             case OP_OPERAND_HI16U:
3535             case OP_OPERAND_LOW16U:
3536               gas_assert (op_data < insn->ntok);
3537               if (expr_is_const (&insn->tok[op_data]))
3538                 {
3539                   long val;
3540                   copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3541                   val = xg_apply_userdef_op_fn (op->typ,
3542                                                 targ->tok[op_num].
3543                                                 X_add_number);
3544                   targ->tok[op_num].X_add_number = val;
3545                 }
3546               else
3547                 {
3548                   /* For const16 we can create relocations for these.  */
3549                   if (targ->opcode == XTENSA_UNDEFINED
3550                       || (targ->opcode != xtensa_const16_opcode))
3551                     return false;
3552                   gas_assert (op_data < insn->ntok);
3553                   /* Need to build a O_lo16 or O_hi16.  */
3554                   copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3555                   if (targ->tok[op_num].X_op == O_symbol)
3556                     {
3557                       if (op->typ == OP_OPERAND_HI16U)
3558                         targ->tok[op_num].X_op = O_hi16;
3559                       else if (op->typ == OP_OPERAND_LOW16U)
3560                         targ->tok[op_num].X_op = O_lo16;
3561                       else
3562                         return false;
3563                     }
3564                 }
3565               break;
3566             default:
3567               /* currently handles:
3568                  OP_OPERAND_LOW8
3569                  OP_OPERAND_HI24S
3570                  OP_OPERAND_F32MINUS */
3571               if (xg_has_userdef_op_fn (op->typ))
3572                 {
3573                   gas_assert (op_data < insn->ntok);
3574                   if (expr_is_const (&insn->tok[op_data]))
3575                     {
3576                       long val;
3577                       copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3578                       val = xg_apply_userdef_op_fn (op->typ,
3579                                                     targ->tok[op_num].
3580                                                     X_add_number);
3581                       targ->tok[op_num].X_add_number = val;
3582                     }
3583                   else
3584                     return false; /* We cannot use a relocation for this.  */
3585                   break;
3586                 }
3587               gas_assert (0);
3588               break;
3589             }
3590         }
3591       break;
3592
3593     case INSTR_LITERAL_DEF:
3594       op = bi->ops;
3595       targ->opcode = XTENSA_UNDEFINED;
3596       targ->insn_type = ITYPE_LITERAL;
3597       targ->is_specific_opcode = false;
3598       for (; op != NULL; op = op->next)
3599         {
3600           int op_num = op->op_num;
3601           int op_data = op->op_data;
3602           gas_assert (op->op_num < MAX_INSN_ARGS);
3603
3604           if (targ->ntok <= op_num)
3605             targ->ntok = op_num + 1;
3606
3607           switch (op->typ)
3608             {
3609             case OP_OPERAND:
3610               gas_assert (op_data < insn->ntok);
3611               /* We can only pass resolvable literals through.  */
3612               if (!xg_valid_literal_expression (&insn->tok[op_data]))
3613                 return false;
3614               copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
3615               break;
3616             case OP_LITERAL:
3617             case OP_CONSTANT:
3618             case OP_LABEL:
3619             default:
3620               gas_assert (0);
3621               break;
3622             }
3623         }
3624       break;
3625
3626     case INSTR_LABEL_DEF:
3627       op = bi->ops;
3628       targ->opcode = XTENSA_UNDEFINED;
3629       targ->insn_type = ITYPE_LABEL;
3630       targ->is_specific_opcode = false;
3631       /* Literal with no ops is a label?  */
3632       gas_assert (op == NULL);
3633       break;
3634
3635     default:
3636       gas_assert (0);
3637     }
3638
3639   return true;
3640 }
3641
3642
3643 /* Return TRUE on success.  */
3644
3645 static bool
3646 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
3647 {
3648   for (; bi != NULL; bi = bi->next)
3649     {
3650       TInsn *next_insn = istack_push_space (istack);
3651
3652       if (!xg_build_to_insn (next_insn, insn, bi))
3653         return false;
3654     }
3655   return true;
3656 }
3657
3658
3659 /* Return TRUE on valid expansion.  */
3660
3661 static bool
3662 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
3663 {
3664   int stack_size = istack->ninsn;
3665   int steps_taken = 0;
3666   TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
3667   TransitionList *l;
3668
3669   gas_assert (insn->insn_type == ITYPE_INSN);
3670   gas_assert (insn->opcode < table->num_opcodes);
3671
3672   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
3673     {
3674       TransitionRule *rule = l->rule;
3675
3676       if (xg_instruction_matches_rule (insn, rule))
3677         {
3678           if (lateral_steps == steps_taken)
3679             {
3680               int i;
3681
3682               /* This is it.  Expand the rule to the stack.  */
3683               if (!xg_build_to_stack (istack, insn, rule->to_instr))
3684                 return false;
3685
3686               /* Check to see if it fits.  */
3687               for (i = stack_size; i < istack->ninsn; i++)
3688                 {
3689                   TInsn *tinsn = &istack->insn[i];
3690
3691                   if (tinsn->insn_type == ITYPE_INSN
3692                       && !tinsn_has_symbolic_operands (tinsn)
3693                       && !xg_immeds_fit (tinsn))
3694                     {
3695                       istack->ninsn = stack_size;
3696                       return false;
3697                     }
3698                 }
3699               return true;
3700             }
3701           steps_taken++;
3702         }
3703     }
3704   return false;
3705 }
3706
3707 \f
3708 /* Relax the assembly instruction at least "min_steps".
3709    Return the number of steps taken.
3710
3711    For relaxation to correctly terminate, every relaxation chain must
3712    terminate in one of two ways:
3713
3714    1.  If the chain from one instruction to the next consists entirely of
3715        single instructions, then the chain *must* handle all possible
3716        immediates without failing.  It must not ever fail because an
3717        immediate is out of range.  The MOVI.N -> MOVI -> L32R relaxation
3718        chain is one example.  L32R loads 32 bits, and there cannot be an
3719        immediate larger than 32 bits, so it satisfies this condition.
3720        Single instruction relaxation chains are as defined by
3721        xg_is_single_relaxable_instruction.
3722
3723    2.  Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3724        BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3725
3726    Strictly speaking, in most cases you can violate condition 1 and be OK
3727    -- in particular when the last two instructions have the same single
3728    size.  But nevertheless, you should guarantee the above two conditions.
3729
3730    We could fix this so that single-instruction expansions correctly
3731    terminate when they can't handle the range, but the error messages are
3732    worse, and it actually turns out that in every case but one (18-bit wide
3733    branches), you need a multi-instruction expansion to get the full range
3734    anyway.  And because 18-bit branches are handled identically to 15-bit
3735    branches, there isn't any point in changing it.  */
3736
3737 static int
3738 xg_assembly_relax (IStack *istack,
3739                    TInsn *insn,
3740                    segT pc_seg,
3741                    fragS *pc_frag,      /* if pc_frag == 0, not pc-relative */
3742                    offsetT pc_offset,   /* offset in fragment */
3743                    int min_steps,       /* minimum conversion steps */
3744                    long stretch)        /* number of bytes stretched so far */
3745 {
3746   int steps_taken = 0;
3747
3748   /* Some of its immeds don't fit.  Try to build a relaxed version.
3749      This may go through a couple of stages of single instruction
3750      transformations before we get there.  */
3751
3752   TInsn single_target;
3753   TInsn current_insn;
3754   int lateral_steps = 0;
3755   int istack_size = istack->ninsn;
3756
3757   if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
3758       && steps_taken >= min_steps)
3759     {
3760       istack_push (istack, insn);
3761       return steps_taken;
3762     }
3763   current_insn = *insn;
3764
3765   /* Walk through all of the single instruction expansions.  */
3766   while (xg_is_single_relaxable_insn (&current_insn, &single_target, false))
3767     {
3768       steps_taken++;
3769       if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
3770                                   stretch))
3771         {
3772           if (steps_taken >= min_steps)
3773             {
3774               istack_push (istack, &single_target);
3775               return steps_taken;
3776             }
3777         }
3778       current_insn = single_target;
3779     }
3780
3781   /* Now check for a multi-instruction expansion.  */
3782   while (xg_is_relaxable_insn (&current_insn, lateral_steps))
3783     {
3784       if (xg_symbolic_immeds_fit (&current_insn, pc_seg, pc_frag, pc_offset,
3785                                   stretch))
3786         {
3787           if (steps_taken >= min_steps)
3788             {
3789               istack_push (istack, &current_insn);
3790               return steps_taken;
3791             }
3792         }
3793       steps_taken++;
3794       if (xg_expand_to_stack (istack, &current_insn, lateral_steps))
3795         {
3796           if (steps_taken >= min_steps)
3797             return steps_taken;
3798         }
3799       lateral_steps++;
3800       istack->ninsn = istack_size;
3801     }
3802
3803   /* It's not going to work -- use the original.  */
3804   istack_push (istack, insn);
3805   return steps_taken;
3806 }
3807
3808
3809 static void
3810 xg_finish_frag (char *last_insn,
3811                 enum xtensa_relax_statesE frag_state,
3812                 enum xtensa_relax_statesE slot0_state,
3813                 int max_growth,
3814                 bool is_insn)
3815 {
3816   /* Finish off this fragment so that it has at LEAST the desired
3817      max_growth.  If it doesn't fit in this fragment, close this one
3818      and start a new one.  In either case, return a pointer to the
3819      beginning of the growth area.  */
3820
3821   fragS *old_frag;
3822
3823   frag_grow (max_growth);
3824   old_frag = frag_now;
3825
3826   frag_now->fr_opcode = last_insn;
3827   if (is_insn)
3828     frag_now->tc_frag_data.is_insn = true;
3829
3830   frag_var (rs_machine_dependent, max_growth, max_growth,
3831             frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
3832
3833   old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
3834   xtensa_set_frag_assembly_state (frag_now);
3835
3836   /* Just to make sure that we did not split it up.  */
3837   gas_assert (old_frag->fr_next == frag_now);
3838 }
3839
3840
3841 /* Return TRUE if the target frag is one of the next non-empty frags.  */
3842
3843 static bool
3844 is_next_frag_target (const fragS *fragP, const fragS *target)
3845 {
3846   if (fragP == NULL)
3847     return false;
3848
3849   for (; fragP; fragP = fragP->fr_next)
3850     {
3851       if (fragP == target)
3852         return true;
3853       if (fragP->fr_fix != 0)
3854         return false;
3855       if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
3856         return false;
3857       if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
3858           && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
3859         return false;
3860       if (fragP->fr_type == rs_space)
3861         return false;
3862     }
3863   return false;
3864 }
3865
3866
3867 static bool
3868 is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
3869 {
3870   xtensa_isa isa = xtensa_default_isa;
3871   int i;
3872   int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3873   int target_op = -1;
3874   symbolS *sym;
3875   fragS *target_frag;
3876
3877   if (xtensa_opcode_is_branch (isa, insn->opcode) != 1
3878       && xtensa_opcode_is_jump (isa, insn->opcode) != 1)
3879     return false;
3880
3881   for (i = 0; i < num_ops; i++)
3882     {
3883       if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
3884         {
3885           target_op = i;
3886           break;
3887         }
3888     }
3889   if (target_op == -1)
3890     return false;
3891
3892   if (insn->ntok <= target_op)
3893     return false;
3894
3895   if (insn->tok[target_op].X_op != O_symbol)
3896     return false;
3897
3898   sym = insn->tok[target_op].X_add_symbol;
3899   if (sym == NULL)
3900     return false;
3901
3902   if (insn->tok[target_op].X_add_number != 0)
3903     return false;
3904
3905   target_frag = symbol_get_frag (sym);
3906   if (target_frag == NULL)
3907     return false;
3908
3909   if (is_next_frag_target (fragP->fr_next, target_frag)
3910       && S_GET_VALUE (sym) == target_frag->fr_address)
3911     return true;
3912
3913   return false;
3914 }
3915
3916
3917 static void
3918 xg_add_branch_and_loop_targets (TInsn *insn)
3919 {
3920   xtensa_isa isa = xtensa_default_isa;
3921   int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
3922
3923   if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3924     {
3925       int i = 1;
3926       if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3927           && insn->tok[i].X_op == O_symbol)
3928         symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = true;
3929       return;
3930     }
3931
3932   if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
3933       || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
3934     {
3935       int i;
3936
3937       for (i = 0; i < insn->ntok && i < num_ops; i++)
3938         {
3939           if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
3940               && insn->tok[i].X_op == O_symbol)
3941             {
3942               symbolS *sym = insn->tok[i].X_add_symbol;
3943               symbol_get_tc (sym)->is_branch_target = true;
3944               if (S_IS_DEFINED (sym))
3945                 symbol_get_frag (sym)->tc_frag_data.is_branch_target = true;
3946             }
3947         }
3948     }
3949 }
3950
3951
3952 /* Return FALSE if no error.  */
3953
3954 static bool
3955 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
3956 {
3957   int num_ops = 0;
3958   BuildOp *b_op;
3959
3960   switch (instr_spec->typ)
3961     {
3962     case INSTR_INSTR:
3963       new_insn->insn_type = ITYPE_INSN;
3964       new_insn->opcode = instr_spec->opcode;
3965       break;
3966     case INSTR_LITERAL_DEF:
3967       new_insn->insn_type = ITYPE_LITERAL;
3968       new_insn->opcode = XTENSA_UNDEFINED;
3969       break;
3970     case INSTR_LABEL_DEF:
3971       abort ();
3972     }
3973   new_insn->is_specific_opcode = false;
3974   new_insn->debug_line = old_insn->debug_line;
3975   new_insn->loc_directive_seen = old_insn->loc_directive_seen;
3976
3977   for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next)
3978     {
3979       expressionS *exp;
3980       const expressionS *src_exp;
3981
3982       num_ops++;
3983       switch (b_op->typ)
3984         {
3985         case OP_CONSTANT:
3986           /* The expression must be the constant.  */
3987           gas_assert (b_op->op_num < MAX_INSN_ARGS);
3988           exp = &new_insn->tok[b_op->op_num];
3989           set_expr_const (exp, b_op->op_data);
3990           break;
3991
3992         case OP_OPERAND:
3993           gas_assert (b_op->op_num < MAX_INSN_ARGS);
3994           gas_assert (b_op->op_data < (unsigned) old_insn->ntok);
3995           src_exp = &old_insn->tok[b_op->op_data];
3996           exp = &new_insn->tok[b_op->op_num];
3997           copy_expr (exp, src_exp);
3998           break;
3999
4000         case OP_LITERAL:
4001         case OP_LABEL:
4002           as_bad (_("can't handle generation of literal/labels yet"));
4003           gas_assert (0);
4004
4005         default:
4006           as_bad (_("can't handle undefined OP TYPE"));
4007           gas_assert (0);
4008         }
4009     }
4010
4011   new_insn->ntok = num_ops;
4012   return false;
4013 }
4014
4015
4016 /* Return TRUE if it was simplified.  */
4017
4018 static bool
4019 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
4020 {
4021   TransitionRule *rule;
4022   BuildInstr *insn_spec;
4023
4024   if (old_insn->is_specific_opcode || !density_supported)
4025     return false;
4026
4027   rule = xg_instruction_match (old_insn);
4028   if (rule == NULL)
4029     return false;
4030
4031   insn_spec = rule->to_instr;
4032   /* There should only be one.  */
4033   gas_assert (insn_spec != NULL);
4034   gas_assert (insn_spec->next == NULL);
4035   if (insn_spec->next != NULL)
4036     return false;
4037
4038   xg_build_token_insn (insn_spec, old_insn, new_insn);
4039
4040   return true;
4041 }
4042
4043
4044 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4045    l32i.n. (2) Check the number of operands.  (3) Place the instruction
4046    tokens into the stack or relax it and place multiple
4047    instructions/literals onto the stack.  Return FALSE if no error.  */
4048
4049 static bool
4050 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
4051 {
4052   int noperands;
4053   TInsn new_insn;
4054   bool do_expand;
4055
4056   tinsn_init (&new_insn);
4057
4058   /* Narrow it if we can.  xg_simplify_insn now does all the
4059      appropriate checking (e.g., for the density option).  */
4060   if (xg_simplify_insn (orig_insn, &new_insn))
4061     orig_insn = &new_insn;
4062
4063   noperands = xtensa_opcode_num_operands (xtensa_default_isa,
4064                                           orig_insn->opcode);
4065   if (orig_insn->ntok < noperands)
4066     {
4067       as_bad (ngettext ("found %d operand for '%s':  Expected %d",
4068                         "found %d operands for '%s':  Expected %d",
4069                         orig_insn->ntok),
4070               orig_insn->ntok,
4071               xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4072               noperands);
4073       return true;
4074     }
4075   if (orig_insn->ntok > noperands)
4076     as_warn (ngettext ("found %d operand for '%s':  Expected %d",
4077                        "found %d operands for '%s':  Expected %d",
4078                        orig_insn->ntok),
4079              orig_insn->ntok,
4080              xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
4081              noperands);
4082
4083   /* If there are not enough operands, we will assert above.  If there
4084      are too many, just cut out the extras here.  */
4085   orig_insn->ntok = noperands;
4086
4087   if (tinsn_has_invalid_symbolic_operands (orig_insn))
4088     return true;
4089
4090   /* Special case for extui opcode which has constraints not handled
4091      by the ordinary operand encoding checks.  The number of operands
4092      and related syntax issues have already been checked.  */
4093   if (orig_insn->opcode == xtensa_extui_opcode)
4094     {
4095       int shiftimm = orig_insn->tok[2].X_add_number;
4096       int maskimm = orig_insn->tok[3].X_add_number;
4097       if (shiftimm + maskimm > 32)
4098         {
4099           as_bad (_("immediate operands sum to greater than 32"));
4100           return true;
4101         }
4102     }
4103
4104   /* If the instruction will definitely need to be relaxed, it is better
4105      to expand it now for better scheduling.  Decide whether to expand
4106      now....  */
4107   do_expand = (!orig_insn->is_specific_opcode && use_transform ());
4108
4109   /* Calls should be expanded to longcalls only in the backend relaxation
4110      so that the assembly scheduler will keep the L32R/CALLX instructions
4111      adjacent.  */
4112   if (is_direct_call_opcode (orig_insn->opcode))
4113     do_expand = false;
4114
4115   if (tinsn_has_symbolic_operands (orig_insn))
4116     {
4117       /* The values of symbolic operands are not known yet, so only expand
4118          now if an operand is "complex" (e.g., difference of symbols) and
4119          will have to be stored as a literal regardless of the value.  */
4120       if (!tinsn_has_complex_operands (orig_insn))
4121         do_expand = false;
4122     }
4123   else if (xg_immeds_fit (orig_insn))
4124     do_expand = false;
4125
4126   if (do_expand)
4127     xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
4128   else
4129     istack_push (istack, orig_insn);
4130
4131   return false;
4132 }
4133
4134
4135 /* Return TRUE if the section flags are marked linkonce
4136    or the name is .gnu.linkonce.*.  */
4137
4138 static int linkonce_len = sizeof (".gnu.linkonce.") - 1;
4139
4140 static bool
4141 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
4142 {
4143   flagword flags, link_once_flags;
4144
4145   flags = bfd_section_flags (sec);
4146   link_once_flags = (flags & SEC_LINK_ONCE);
4147
4148   /* Flags might not be set yet.  */
4149   if (!link_once_flags
4150       && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0)
4151     link_once_flags = SEC_LINK_ONCE;
4152
4153   return (link_once_flags != 0);
4154 }
4155
4156
4157 static void
4158 xtensa_add_literal_sym (symbolS *sym)
4159 {
4160   sym_list *l;
4161
4162   l = XNEW (sym_list);
4163   l->sym = sym;
4164   l->next = literal_syms;
4165   literal_syms = l;
4166 }
4167
4168
4169 static symbolS *
4170 xtensa_create_literal_symbol (segT sec, fragS *frag)
4171 {
4172   static int lit_num = 0;
4173   static char name[256];
4174   symbolS *symbolP;
4175
4176   sprintf (name, ".L_lit_sym%d", lit_num);
4177
4178   /* Create a local symbol.  If it is in a linkonce section, we have to
4179      be careful to make sure that if it is used in a relocation that the
4180      symbol will be in the output file.  */
4181   if (get_is_linkonce_section (stdoutput, sec))
4182     {
4183       symbolP = symbol_new (name, sec, frag, 0);
4184       S_CLEAR_EXTERNAL (symbolP);
4185       /* symbolP->local = 1; */
4186     }
4187   else
4188     symbolP = symbol_new (name, sec, frag, 0);
4189
4190   xtensa_add_literal_sym (symbolP);
4191
4192   lit_num++;
4193   return symbolP;
4194 }
4195
4196
4197 /* Currently all literals that are generated here are 32-bit L32R targets.  */
4198
4199 static symbolS *
4200 xg_assemble_literal (/* const */ TInsn *insn)
4201 {
4202   emit_state state;
4203   symbolS *lit_sym = NULL;
4204   bfd_reloc_code_real_type reloc;
4205   bool pcrel = false;
4206   char *p;
4207
4208   /* size = 4 for L32R.  It could easily be larger when we move to
4209      larger constants.  Add a parameter later.  */
4210   offsetT litsize = 4;
4211   offsetT litalign = 2;         /* 2^2 = 4 */
4212   expressionS saved_loc;
4213   expressionS * emit_val;
4214
4215   set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
4216
4217   gas_assert (insn->insn_type == ITYPE_LITERAL);
4218   gas_assert (insn->ntok == 1); /* must be only one token here */
4219
4220   xtensa_switch_to_literal_fragment (&state);
4221
4222   emit_val = &insn->tok[0];
4223   if (emit_val->X_op == O_big)
4224     {
4225       int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
4226       if (size > litsize)
4227         {
4228           /* This happens when someone writes a "movi a2, big_number".  */
4229           as_bad_where (frag_now->fr_file, frag_now->fr_line,
4230                         _("invalid immediate"));
4231           xtensa_restore_emit_state (&state);
4232           return NULL;
4233         }
4234     }
4235
4236   /* Force a 4-byte align here.  Note that this opens a new frag, so all
4237      literals done with this function have a frag to themselves.  That's
4238      important for the way text section literals work.  */
4239   frag_align (litalign, 0, 0);
4240   record_alignment (now_seg, litalign);
4241
4242   switch (emit_val->X_op)
4243     {
4244     case O_pcrel:
4245       pcrel = true;
4246       /* fall through */
4247     case O_pltrel:
4248     case O_tlsfunc:
4249     case O_tlsarg:
4250     case O_tpoff:
4251     case O_dtpoff:
4252       p = frag_more (litsize);
4253       xtensa_set_frag_assembly_state (frag_now);
4254       reloc = map_operator_to_reloc (emit_val->X_op, true);
4255       if (emit_val->X_add_symbol)
4256         emit_val->X_op = O_symbol;
4257       else
4258         emit_val->X_op = O_constant;
4259       fix_new_exp (frag_now, p - frag_now->fr_literal,
4260                    litsize, emit_val, pcrel, reloc);
4261       break;
4262
4263     default:
4264       emit_expr (emit_val, litsize);
4265       break;
4266     }
4267
4268   gas_assert (frag_now->tc_frag_data.literal_frag == NULL);
4269   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4270   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4271   lit_sym = frag_now->fr_symbol;
4272
4273   /* Go back.  */
4274   xtensa_restore_emit_state (&state);
4275   return lit_sym;
4276 }
4277
4278
4279 static void
4280 xg_assemble_literal_space (/* const */ int size, int slot)
4281 {
4282   emit_state state;
4283   /* We might have to do something about this alignment.  It only
4284      takes effect if something is placed here.  */
4285   offsetT litalign = 2;         /* 2^2 = 4 */
4286   fragS *lit_saved_frag;
4287
4288   gas_assert (size % 4 == 0);
4289
4290   xtensa_switch_to_literal_fragment (&state);
4291
4292   /* Force a 4-byte align here.  */
4293   frag_align (litalign, 0, 0);
4294   record_alignment (now_seg, litalign);
4295
4296   frag_grow (size);
4297
4298   lit_saved_frag = frag_now;
4299   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
4300   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
4301   xg_finish_frag (0, RELAX_LITERAL, 0, size, false);
4302
4303   /* Go back.  */
4304   xtensa_restore_emit_state (&state);
4305   frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
4306 }
4307
4308
4309 /* Put in a fixup record based on the opcode.
4310    Return TRUE on success.  */
4311
4312 static bool
4313 xg_add_opcode_fix (TInsn *tinsn,
4314                    int opnum,
4315                    xtensa_format fmt,
4316                    int slot,
4317                    expressionS *exp,
4318                    fragS *fragP,
4319                    offsetT offset)
4320 {
4321   xtensa_opcode opcode = tinsn->opcode;
4322   bfd_reloc_code_real_type reloc;
4323   reloc_howto_type *howto;
4324   int fmt_length;
4325   fixS *the_fix;
4326
4327   reloc = BFD_RELOC_NONE;
4328
4329   /* First try the special cases for "alternate" relocs.  */
4330   if (opcode == xtensa_l32r_opcode)
4331     {
4332       if (fragP->tc_frag_data.use_absolute_literals)
4333         reloc = encode_alt_reloc (slot);
4334     }
4335   else if (opcode == xtensa_const16_opcode)
4336     {
4337       if (exp->X_op == O_lo16)
4338         {
4339           reloc = encode_reloc (slot);
4340           exp->X_op = O_symbol;
4341         }
4342       else if (exp->X_op == O_hi16)
4343         {
4344           reloc = encode_alt_reloc (slot);
4345           exp->X_op = O_symbol;
4346         }
4347     }
4348
4349   if (opnum != get_relaxable_immed (opcode))
4350     {
4351       as_bad (_("invalid relocation for operand %i of '%s'"),
4352               opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4353       return false;
4354     }
4355
4356   /* Handle erroneous "@h" and "@l" expressions here before they propagate
4357      into the symbol table where the generic portions of the assembler
4358      won't know what to do with them.  */
4359   if (exp->X_op == O_lo16 || exp->X_op == O_hi16)
4360     {
4361       as_bad (_("invalid expression for operand %i of '%s'"),
4362               opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
4363       return false;
4364     }
4365
4366   /* Next try the generic relocs.  */
4367   if (reloc == BFD_RELOC_NONE)
4368     reloc = encode_reloc (slot);
4369   if (reloc == BFD_RELOC_NONE)
4370     {
4371       as_bad (_("invalid relocation in instruction slot %i"), slot);
4372       return false;
4373     }
4374
4375   howto = bfd_reloc_type_lookup (stdoutput, reloc);
4376   if (!howto)
4377     {
4378       as_bad (_("undefined symbol for opcode \"%s\""),
4379               xtensa_opcode_name (xtensa_default_isa, opcode));
4380       return false;
4381     }
4382
4383   fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
4384   the_fix = fix_new_exp (fragP, offset, fmt_length, exp,
4385                          howto->pc_relative, reloc);
4386   the_fix->fx_no_overflow = 1;
4387   the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol;
4388   the_fix->tc_fix_data.X_add_number = exp->X_add_number;
4389   the_fix->tc_fix_data.slot = slot;
4390
4391   return true;
4392 }
4393
4394
4395 static bool
4396 xg_emit_insn_to_buf (TInsn *tinsn,
4397                      char *buf,
4398                      fragS *fragP,
4399                      offsetT offset,
4400                      bool build_fix)
4401 {
4402   static xtensa_insnbuf insnbuf = NULL;
4403   bool has_symbolic_immed = false;
4404   bool ok = true;
4405
4406   if (!insnbuf)
4407     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4408
4409   has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
4410   if (has_symbolic_immed && build_fix)
4411     {
4412       /* Add a fixup.  */
4413       xtensa_format fmt = xg_get_single_format (tinsn->opcode);
4414       int slot = xg_get_single_slot (tinsn->opcode);
4415       int opnum = get_relaxable_immed (tinsn->opcode);
4416       expressionS *exp = &tinsn->tok[opnum];
4417
4418       if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset))
4419         ok = false;
4420     }
4421   fragP->tc_frag_data.is_insn = true;
4422   xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4423                            (unsigned char *) buf, 0);
4424   return ok;
4425 }
4426
4427
4428 static void
4429 xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
4430 {
4431   symbolS *sym = get_special_literal_symbol ();
4432   int i;
4433   if (lit_sym == 0)
4434     return;
4435   gas_assert (insn->insn_type == ITYPE_INSN);
4436   for (i = 0; i < insn->ntok; i++)
4437     if (insn->tok[i].X_add_symbol == sym)
4438       insn->tok[i].X_add_symbol = lit_sym;
4439
4440 }
4441
4442
4443 static void
4444 xg_resolve_labels (TInsn *insn, symbolS *label_sym)
4445 {
4446   symbolS *sym = get_special_label_symbol ();
4447   int i;
4448   for (i = 0; i < insn->ntok; i++)
4449     if (insn->tok[i].X_add_symbol == sym)
4450       insn->tok[i].X_add_symbol = label_sym;
4451
4452 }
4453
4454
4455 /* Return TRUE if the instruction can write to the specified
4456    integer register.  */
4457
4458 static bool
4459 is_register_writer (const TInsn *insn, const char *regset, int regnum)
4460 {
4461   int i;
4462   int num_ops;
4463   xtensa_isa isa = xtensa_default_isa;
4464
4465   num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
4466
4467   for (i = 0; i < num_ops; i++)
4468     {
4469       char inout;
4470       inout = xtensa_operand_inout (isa, insn->opcode, i);
4471       if ((inout == 'o' || inout == 'm')
4472           && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
4473         {
4474           xtensa_regfile opnd_rf =
4475             xtensa_operand_regfile (isa, insn->opcode, i);
4476           if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
4477             {
4478               if ((insn->tok[i].X_op == O_register)
4479                   && (insn->tok[i].X_add_number == regnum))
4480                 return true;
4481             }
4482         }
4483     }
4484   return false;
4485 }
4486
4487
4488 static bool
4489 is_bad_loopend_opcode (const TInsn *tinsn)
4490 {
4491   xtensa_opcode opcode = tinsn->opcode;
4492
4493   if (opcode == XTENSA_UNDEFINED)
4494     return false;
4495
4496   if (opcode == xtensa_call0_opcode
4497       || opcode == xtensa_callx0_opcode
4498       || opcode == xtensa_call4_opcode
4499       || opcode == xtensa_callx4_opcode
4500       || opcode == xtensa_call8_opcode
4501       || opcode == xtensa_callx8_opcode
4502       || opcode == xtensa_call12_opcode
4503       || opcode == xtensa_callx12_opcode
4504       || opcode == xtensa_isync_opcode
4505       || opcode == xtensa_ret_opcode
4506       || opcode == xtensa_ret_n_opcode
4507       || opcode == xtensa_retw_opcode
4508       || opcode == xtensa_retw_n_opcode
4509       || opcode == xtensa_waiti_opcode
4510       || opcode == xtensa_rsr_lcount_opcode)
4511     return true;
4512
4513   return false;
4514 }
4515
4516
4517 /* Labels that begin with ".Ln" or ".LM"  are unaligned.
4518    This allows the debugger to add unaligned labels.
4519    Also, the assembler generates stabs labels that need
4520    not be aligned:  FAKE_LABEL_NAME . {"F", "L", "endfunc"}.  */
4521
4522 static bool
4523 is_unaligned_label (symbolS *sym)
4524 {
4525   const char *name = S_GET_NAME (sym);
4526   static size_t fake_size = 0;
4527
4528   if (name
4529       && name[0] == '.'
4530       && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M'))
4531     return true;
4532
4533   /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4534   if (fake_size == 0)
4535     fake_size = strlen (FAKE_LABEL_NAME);
4536
4537   if (name
4538       && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
4539       && (name[fake_size] == 'F'
4540           || name[fake_size] == 'L'
4541           || (name[fake_size] == 'e'
4542               && startswith (name + fake_size, "endfunc"))))
4543     return true;
4544
4545   return false;
4546 }
4547
4548
4549 static fragS *
4550 next_non_empty_frag (const fragS *fragP)
4551 {
4552   fragS *next_fragP = fragP->fr_next;
4553
4554   /* Sometimes an empty will end up here due storage allocation issues.
4555      So we have to skip until we find something legit.  */
4556   while (next_fragP && next_fragP->fr_fix == 0)
4557     next_fragP = next_fragP->fr_next;
4558
4559   if (next_fragP == NULL || next_fragP->fr_fix == 0)
4560     return NULL;
4561
4562   return next_fragP;
4563 }
4564
4565
4566 static bool
4567 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
4568 {
4569   xtensa_opcode out_opcode;
4570   const fragS *next_fragP = next_non_empty_frag (fragP);
4571
4572   if (next_fragP == NULL)
4573     return false;
4574
4575   out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
4576   if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
4577     {
4578       *opcode = out_opcode;
4579       return true;
4580     }
4581   return false;
4582 }
4583
4584
4585 static int
4586 frag_format_size (const fragS *fragP)
4587 {
4588   static xtensa_insnbuf insnbuf = NULL;
4589   xtensa_isa isa = xtensa_default_isa;
4590   xtensa_format fmt;
4591   int fmt_size;
4592
4593   if (!insnbuf)
4594     insnbuf = xtensa_insnbuf_alloc (isa);
4595
4596   if (fragP == NULL)
4597     return XTENSA_UNDEFINED;
4598
4599   xtensa_insnbuf_from_chars (isa, insnbuf,
4600                              (unsigned char *) fragP->fr_literal, 0);
4601
4602   fmt = xtensa_format_decode (isa, insnbuf);
4603   if (fmt == XTENSA_UNDEFINED)
4604     return XTENSA_UNDEFINED;
4605   fmt_size = xtensa_format_length (isa, fmt);
4606
4607   /* If the next format won't be changing due to relaxation, just
4608      return the length of the first format.  */
4609   if (fragP->fr_opcode != fragP->fr_literal)
4610     return fmt_size;
4611
4612   /* If during relaxation we have to pull an instruction out of a
4613      multi-slot instruction, we will return the more conservative
4614      number.  This works because alignment on bigger instructions
4615      is more restrictive than alignment on smaller instructions.
4616      This is more conservative than we would like, but it happens
4617      infrequently.  */
4618
4619   if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
4620     return fmt_size;
4621
4622   /* If we aren't doing one of our own relaxations or it isn't
4623      slot-based, then the insn size won't change.  */
4624   if (fragP->fr_type != rs_machine_dependent)
4625     return fmt_size;
4626   if (fragP->fr_subtype != RELAX_SLOTS)
4627     return fmt_size;
4628
4629   /* If an instruction is about to grow, return the longer size.  */
4630   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
4631       || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2
4632       || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3)
4633     {
4634       /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4635          instruction in the relaxed version is of length 3.  (The case
4636          where we have to pull the instruction out of a FLIX bundle
4637          is handled conservatively above.)  However, frags with opcodes
4638          that are expanding to wide branches end up having formats that
4639          are not determinable by the RELAX_IMMED_STEPX enumeration, and
4640          we can't tell directly what format the relaxer picked.  This
4641          is a wart in the design of the relaxer that should someday be
4642          fixed, but would require major changes, or at least should
4643          be accompanied by major changes to make use of that data.
4644
4645          In any event, we can tell that we are expanding from a single-slot
4646          format to a wider one with the logic below.  */
4647
4648       int i;
4649       int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0];
4650
4651       for (i = 0; i < xtensa_isa_num_formats (isa); i++)
4652         {
4653           if (relaxed_size == xtensa_format_length (isa, i))
4654             return relaxed_size;
4655         }
4656
4657       return 3;
4658     }
4659
4660   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
4661     return 2 + fragP->tc_frag_data.text_expansion[0];
4662
4663   return fmt_size;
4664 }
4665
4666
4667 static int
4668 next_frag_format_size (const fragS *fragP)
4669 {
4670   const fragS *next_fragP = next_non_empty_frag (fragP);
4671   return frag_format_size (next_fragP);
4672 }
4673
4674
4675 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4676    required two-byte instructions to be treated as three-byte instructions
4677    for loop instruction alignment.  This restriction was removed beginning
4678    with Xtensa LX.  Now the only requirement on loop instruction alignment
4679    is that the first instruction of the loop must appear at an address that
4680    does not cross a fetch boundary.  */
4681
4682 static int
4683 get_loop_align_size (int insn_size)
4684 {
4685   if (insn_size == XTENSA_UNDEFINED)
4686     return xtensa_fetch_width;
4687
4688   if (enforce_three_byte_loop_align && insn_size == 2)
4689     return 3;
4690
4691   return insn_size;
4692 }
4693
4694
4695 /* If the next legit fragment is an end-of-loop marker,
4696    switch its state so it will instantiate a NOP.  */
4697
4698 static void
4699 update_next_frag_state (fragS *fragP)
4700 {
4701   fragS *next_fragP = fragP->fr_next;
4702   fragS *new_target = NULL;
4703
4704   if (align_targets)
4705     {
4706       /* We are guaranteed there will be one of these...   */
4707       while (!(next_fragP->fr_type == rs_machine_dependent
4708                && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4709                    || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
4710         next_fragP = next_fragP->fr_next;
4711
4712       gas_assert (next_fragP->fr_type == rs_machine_dependent
4713               && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
4714                   || next_fragP->fr_subtype == RELAX_UNREACHABLE));
4715
4716       /* ...and one of these.  */
4717       new_target = next_fragP->fr_next;
4718       while (!(new_target->fr_type == rs_machine_dependent
4719                && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4720                    || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
4721         new_target = new_target->fr_next;
4722
4723       gas_assert (new_target->fr_type == rs_machine_dependent
4724               && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
4725                   || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
4726     }
4727
4728   while (next_fragP && next_fragP->fr_fix == 0)
4729     {
4730       if (next_fragP->fr_type == rs_machine_dependent
4731           && next_fragP->fr_subtype == RELAX_LOOP_END)
4732         {
4733           next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
4734           return;
4735         }
4736
4737       next_fragP = next_fragP->fr_next;
4738     }
4739 }
4740
4741
4742 static bool
4743 next_frag_is_branch_target (const fragS *fragP)
4744 {
4745   /* Sometimes an empty will end up here due to storage allocation issues,
4746      so we have to skip until we find something legit.  */
4747   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4748     {
4749       if (fragP->tc_frag_data.is_branch_target)
4750         return true;
4751       if (fragP->fr_fix != 0)
4752         break;
4753     }
4754   return false;
4755 }
4756
4757
4758 static bool
4759 next_frag_is_loop_target (const fragS *fragP)
4760 {
4761   /* Sometimes an empty will end up here due storage allocation issues.
4762      So we have to skip until we find something legit. */
4763   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
4764     {
4765       if (fragP->tc_frag_data.is_loop_target)
4766         return true;
4767       if (fragP->fr_fix != 0)
4768         break;
4769     }
4770   return false;
4771 }
4772
4773
4774 /* As specified in the relaxation table, when a loop instruction is
4775    relaxed, there are 24 bytes between the loop instruction itself and
4776    the first instruction in the loop.  */
4777
4778 #define RELAXED_LOOP_INSN_BYTES 24
4779
4780 static addressT
4781 next_frag_pre_opcode_bytes (const fragS *fragp)
4782 {
4783   const fragS *next_fragp = fragp->fr_next;
4784   xtensa_opcode next_opcode;
4785
4786   if (!next_frag_opcode_is_loop (fragp, &next_opcode))
4787     return 0;
4788
4789   /* Sometimes an empty will end up here due to storage allocation issues,
4790      so we have to skip until we find something legit.  */
4791   while (next_fragp->fr_fix == 0)
4792     next_fragp = next_fragp->fr_next;
4793
4794   if (next_fragp->fr_type != rs_machine_dependent)
4795     return 0;
4796
4797   /* There is some implicit knowledge encoded in here.
4798      The LOOP instructions that are NOT RELAX_IMMED have
4799      been relaxed.  Note that we can assume that the LOOP
4800      instruction is in slot 0 because loops aren't bundleable.  */
4801   if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
4802       return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES;
4803
4804   return 0;
4805 }
4806
4807
4808 /* Mark a location where we can later insert literal frags.  Update
4809    the section's literal_pool_loc, so subsequent literals can be
4810    placed nearest to their use.  */
4811
4812 static void
4813 xtensa_mark_literal_pool_location (void)
4814 {
4815   /* Any labels pointing to the current location need
4816      to be adjusted to after the literal pool.  */
4817   fragS *pool_location;
4818
4819   if (use_literal_section)
4820     return;
4821
4822   /* We stash info in these frags so we can later move the literal's
4823      fixes into this frchain's fix list.  */
4824   pool_location = frag_now;
4825   frag_now->tc_frag_data.lit_frchain = frchain_now;
4826   frag_now->tc_frag_data.literal_frag = frag_now;
4827   /* Just record this frag.  */
4828   xtensa_maybe_create_literal_pool_frag (false, false);
4829   frag_variant (rs_machine_dependent, 0, 0,
4830                 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
4831   xtensa_set_frag_assembly_state (frag_now);
4832   frag_now->tc_frag_data.lit_seg = now_seg;
4833   frag_variant (rs_machine_dependent, 0, 0,
4834                 RELAX_LITERAL_POOL_END, NULL, 0, NULL);
4835   xtensa_set_frag_assembly_state (frag_now);
4836
4837   set_literal_pool_location (now_seg, pool_location);
4838 }
4839
4840
4841 /* Build a nop of the correct size into tinsn.  */
4842
4843 static void
4844 build_nop (TInsn *tinsn, int size)
4845 {
4846   tinsn_init (tinsn);
4847   switch (size)
4848     {
4849     case 2:
4850       tinsn->opcode = xtensa_nop_n_opcode;
4851       tinsn->ntok = 0;
4852       if (tinsn->opcode == XTENSA_UNDEFINED)
4853         as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4854       break;
4855
4856     case 3:
4857       if (xtensa_nop_opcode == XTENSA_UNDEFINED)
4858         {
4859           tinsn->opcode = xtensa_or_opcode;
4860           set_expr_const (&tinsn->tok[0], 1);
4861           set_expr_const (&tinsn->tok[1], 1);
4862           set_expr_const (&tinsn->tok[2], 1);
4863           tinsn->ntok = 3;
4864         }
4865       else
4866         tinsn->opcode = xtensa_nop_opcode;
4867
4868       gas_assert (tinsn->opcode != XTENSA_UNDEFINED);
4869     }
4870 }
4871
4872
4873 /* Assemble a NOP of the requested size in the buffer.  User must have
4874    allocated "buf" with at least "size" bytes.  */
4875
4876 static void
4877 assemble_nop (int size, char *buf)
4878 {
4879   static xtensa_insnbuf insnbuf = NULL;
4880   TInsn tinsn;
4881
4882   build_nop (&tinsn, size);
4883
4884   if (!insnbuf)
4885     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
4886
4887   tinsn_to_insnbuf (&tinsn, insnbuf);
4888   xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
4889                            (unsigned char *) buf, 0);
4890 }
4891
4892
4893 /* Return the number of bytes for the offset of the expanded loop
4894    instruction.  This should be incorporated into the relaxation
4895    specification but is hard-coded here.  This is used to auto-align
4896    the loop instruction.  It is invalid to call this function if the
4897    configuration does not have loops or if the opcode is not a loop
4898    opcode.  */
4899
4900 static addressT
4901 get_expanded_loop_offset (xtensa_opcode opcode)
4902 {
4903   /* This is the OFFSET of the loop instruction in the expanded loop.
4904      This MUST correspond directly to the specification of the loop
4905      expansion.  It will be validated on fragment conversion.  */
4906   gas_assert (opcode != XTENSA_UNDEFINED);
4907   if (opcode == xtensa_loop_opcode)
4908     return 0;
4909   if (opcode == xtensa_loopnez_opcode)
4910     return 3;
4911   if (opcode == xtensa_loopgtz_opcode)
4912     return 6;
4913   as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4914   return 0;
4915 }
4916
4917
4918 static fragS *
4919 get_literal_pool_location (segT seg)
4920 {
4921   if (auto_litpools)
4922     {
4923       struct litpool_seg *lps = litpool_seg_list.next;
4924       struct litpool_frag *lpf;
4925       for ( ; lps && lps->seg->id != seg->id; lps = lps->next)
4926         ;
4927       if (lps)
4928         {
4929           for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4930             { /* Skip "candidates" for now.  */
4931               if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN &&
4932                   lpf->priority == 1)
4933                 return lpf->fragP;
4934             }
4935           /* Must convert a lower-priority pool.  */
4936           for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4937             {
4938               if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN)
4939                 return lpf->fragP;
4940             }
4941           /* Still no match -- try for a low priority pool.  */
4942           for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev)
4943             {
4944               if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
4945                 return lpf->fragP;
4946             }
4947         }
4948     }
4949   return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
4950 }
4951
4952
4953 static void
4954 set_literal_pool_location (segT seg, fragS *literal_pool_loc)
4955 {
4956   seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
4957 }
4958
4959
4960 /* Set frag assembly state should be called when a new frag is
4961    opened and after a frag has been closed.  */
4962
4963 static void
4964 xtensa_set_frag_assembly_state (fragS *fragP)
4965 {
4966   if (!density_supported)
4967     fragP->tc_frag_data.is_no_density = true;
4968
4969   /* This function is called from subsegs_finish, which is called
4970      after xtensa_md_finish, so we can't use "use_transform" or
4971      "use_schedule" here.  */
4972   if (!directive_state[directive_transform])
4973     fragP->tc_frag_data.is_no_transform = true;
4974   if (directive_state[directive_longcalls])
4975     fragP->tc_frag_data.use_longcalls = true;
4976   fragP->tc_frag_data.use_absolute_literals =
4977     directive_state[directive_absolute_literals];
4978   fragP->tc_frag_data.is_assembly_state_set = true;
4979 }
4980
4981
4982 static bool
4983 relaxable_section (asection *sec)
4984 {
4985   return ((sec->flags & SEC_DEBUGGING) == 0
4986           && strcmp (sec->name, ".eh_frame") != 0);
4987 }
4988
4989
4990 static void
4991 xtensa_mark_frags_for_org (void)
4992 {
4993   segT *seclist;
4994
4995   /* Walk over each fragment of all of the current segments.  If we find
4996      a .org frag in any of the segments, mark all frags prior to it as
4997      "no transform", which will prevent linker optimizations from messing
4998      up the .org distance.  This should be done after
4999      xtensa_find_unmarked_state_frags, because we don't want to worry here
5000      about that function trashing the data we save here.  */
5001
5002   for (seclist = &stdoutput->sections;
5003        seclist && *seclist;
5004        seclist = &(*seclist)->next)
5005     {
5006       segT sec = *seclist;
5007       segment_info_type *seginfo;
5008       fragS *fragP;
5009       flagword flags;
5010       flags = bfd_section_flags (sec);
5011       if (flags & SEC_DEBUGGING)
5012         continue;
5013       if (!(flags & SEC_ALLOC))
5014         continue;
5015
5016       seginfo = seg_info (sec);
5017       if (seginfo && seginfo->frchainP)
5018         {
5019           fragS *last_fragP = seginfo->frchainP->frch_root;
5020           for (fragP = seginfo->frchainP->frch_root; fragP;
5021                fragP = fragP->fr_next)
5022             {
5023               /* cvt_frag_to_fill has changed the fr_type of org frags to
5024                  rs_fill, so use the value as cached in rs_subtype here.  */
5025               if (fragP->fr_subtype == RELAX_ORG)
5026                 {
5027                   while (last_fragP != fragP->fr_next)
5028                     {
5029                       last_fragP->tc_frag_data.is_no_transform = true;
5030                       last_fragP = last_fragP->fr_next;
5031                     }
5032                 }
5033             }
5034         }
5035     }
5036 }
5037
5038
5039 static void
5040 xtensa_find_unmarked_state_frags (void)
5041 {
5042   segT *seclist;
5043
5044   /* Walk over each fragment of all of the current segments.  For each
5045      unmarked fragment, mark it with the same info as the previous
5046      fragment.  */
5047   for (seclist = &stdoutput->sections;
5048        seclist && *seclist;
5049        seclist = &(*seclist)->next)
5050     {
5051       segT sec = *seclist;
5052       segment_info_type *seginfo;
5053       fragS *fragP;
5054       flagword flags;
5055       flags = bfd_section_flags (sec);
5056       if (flags & SEC_DEBUGGING)
5057         continue;
5058       if (!(flags & SEC_ALLOC))
5059         continue;
5060
5061       seginfo = seg_info (sec);
5062       if (seginfo && seginfo->frchainP)
5063         {
5064           fragS *last_fragP = 0;
5065           for (fragP = seginfo->frchainP->frch_root; fragP;
5066                fragP = fragP->fr_next)
5067             {
5068               if (fragP->fr_fix != 0
5069                   && !fragP->tc_frag_data.is_assembly_state_set)
5070                 {
5071                   if (last_fragP == 0)
5072                     {
5073                       as_warn_where (fragP->fr_file, fragP->fr_line,
5074                                      _("assembly state not set for first frag in section %s"),
5075                                      sec->name);
5076                     }
5077                   else
5078                     {
5079                       fragP->tc_frag_data.is_assembly_state_set = true;
5080                       fragP->tc_frag_data.is_no_density =
5081                         last_fragP->tc_frag_data.is_no_density;
5082                       fragP->tc_frag_data.is_no_transform =
5083                         last_fragP->tc_frag_data.is_no_transform;
5084                       fragP->tc_frag_data.use_longcalls =
5085                         last_fragP->tc_frag_data.use_longcalls;
5086                       fragP->tc_frag_data.use_absolute_literals =
5087                         last_fragP->tc_frag_data.use_absolute_literals;
5088                     }
5089                 }
5090               if (fragP->tc_frag_data.is_assembly_state_set)
5091                 last_fragP = fragP;
5092             }
5093         }
5094     }
5095 }
5096
5097
5098 static void
5099 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
5100                                       asection *sec,
5101                                       void *unused ATTRIBUTE_UNUSED)
5102 {
5103   flagword flags = bfd_section_flags (sec);
5104   segment_info_type *seginfo = seg_info (sec);
5105   fragS *frag = seginfo->frchainP->frch_root;
5106
5107   if (flags & SEC_CODE)
5108     {
5109       xtensa_isa isa = xtensa_default_isa;
5110       xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5111       while (frag != NULL)
5112         {
5113           if (frag->tc_frag_data.is_branch_target)
5114             {
5115               int op_size;
5116               addressT branch_align, frag_addr;
5117               xtensa_format fmt;
5118
5119               xtensa_insnbuf_from_chars
5120                 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
5121               fmt = xtensa_format_decode (isa, insnbuf);
5122               op_size = xtensa_format_length (isa, fmt);
5123               branch_align = 1 << branch_align_power (sec);
5124               frag_addr = frag->fr_address % branch_align;
5125               if (frag_addr + op_size > branch_align)
5126                 as_warn_where (frag->fr_file, frag->fr_line,
5127                                _("unaligned branch target: %d bytes at 0x%lx"),
5128                                op_size, (long) frag->fr_address);
5129             }
5130           frag = frag->fr_next;
5131         }
5132       xtensa_insnbuf_free (isa, insnbuf);
5133     }
5134 }
5135
5136
5137 static void
5138 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
5139                              asection *sec,
5140                              void *unused ATTRIBUTE_UNUSED)
5141 {
5142   flagword flags = bfd_section_flags (sec);
5143   segment_info_type *seginfo = seg_info (sec);
5144   fragS *frag = seginfo->frchainP->frch_root;
5145   xtensa_isa isa = xtensa_default_isa;
5146
5147   if (flags & SEC_CODE)
5148     {
5149       xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
5150       while (frag != NULL)
5151         {
5152           if (frag->tc_frag_data.is_first_loop_insn)
5153             {
5154               int op_size;
5155               addressT frag_addr;
5156               xtensa_format fmt;
5157
5158               if (frag->fr_fix == 0)
5159                 frag = next_non_empty_frag (frag);
5160
5161               if (frag)
5162                 {
5163                   xtensa_insnbuf_from_chars
5164                     (isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
5165                   fmt = xtensa_format_decode (isa, insnbuf);
5166                   op_size = xtensa_format_length (isa, fmt);
5167                   frag_addr = frag->fr_address % xtensa_fetch_width;
5168
5169                   if (frag_addr + op_size > xtensa_fetch_width)
5170                     as_warn_where (frag->fr_file, frag->fr_line,
5171                                    _("unaligned loop: %d bytes at 0x%lx"),
5172                                    op_size, (long) frag->fr_address);
5173                 }
5174             }
5175           frag = frag->fr_next;
5176         }
5177       xtensa_insnbuf_free (isa, insnbuf);
5178     }
5179 }
5180
5181
5182 static int
5183 xg_apply_fix_value (fixS *fixP, valueT val)
5184 {
5185   xtensa_isa isa = xtensa_default_isa;
5186   static xtensa_insnbuf insnbuf = NULL;
5187   static xtensa_insnbuf slotbuf = NULL;
5188   xtensa_format fmt;
5189   int slot;
5190   bool alt_reloc;
5191   xtensa_opcode opcode;
5192   char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5193
5194   if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc)
5195       || alt_reloc)
5196     as_fatal (_("unexpected fix"));
5197
5198   if (!insnbuf)
5199     {
5200       insnbuf = xtensa_insnbuf_alloc (isa);
5201       slotbuf = xtensa_insnbuf_alloc (isa);
5202     }
5203
5204   xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5205   fmt = xtensa_format_decode (isa, insnbuf);
5206   if (fmt == XTENSA_UNDEFINED)
5207     as_fatal (_("undecodable fix"));
5208   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5209   opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5210   if (opcode == XTENSA_UNDEFINED)
5211     as_fatal (_("undecodable fix"));
5212
5213   /* CONST16 immediates are not PC-relative, despite the fact that we
5214      reuse the normal PC-relative operand relocations for the low part
5215      of a CONST16 operand.  */
5216   if (opcode == xtensa_const16_opcode)
5217     return 0;
5218
5219   xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
5220                               get_relaxable_immed (opcode), val,
5221                               fixP->fx_file, fixP->fx_line);
5222
5223   xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
5224   xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
5225
5226   return 1;
5227 }
5228
5229 \f
5230 /* External Functions and Other GAS Hooks.  */
5231
5232 const char *
5233 xtensa_target_format (void)
5234 {
5235   return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
5236 }
5237
5238
5239 void
5240 xtensa_file_arch_init (bfd *abfd)
5241 {
5242   bfd_set_private_flags (abfd, 0x100 | 0x200);
5243 }
5244
5245
5246 void
5247 md_number_to_chars (char *buf, valueT val, int n)
5248 {
5249   if (target_big_endian)
5250     number_to_chars_bigendian (buf, val, n);
5251   else
5252     number_to_chars_littleendian (buf, val, n);
5253 }
5254
5255 static void
5256 xg_init_global_config (void)
5257 {
5258   target_big_endian = XCHAL_HAVE_BE;
5259
5260   density_supported = XCHAL_HAVE_DENSITY;
5261   absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
5262   xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
5263
5264   directive_state[directive_density] = XCHAL_HAVE_DENSITY;
5265   directive_state[directive_absolute_literals] = XSHAL_USE_ABSOLUTE_LITERALS;
5266
5267   microarch_earliest = XTENSA_MARCH_EARLIEST;
5268 }
5269
5270 void
5271 xtensa_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED)
5272 {
5273   xg_init_global_config ();
5274 }
5275
5276 /* This function is called once, at assembler startup time.  It should
5277    set up all the tables, etc. that the MD part of the assembler will
5278    need.  */
5279
5280 void
5281 md_begin (void)
5282 {
5283   segT current_section = now_seg;
5284   int current_subsec = now_subseg;
5285   xtensa_isa isa;
5286   int i;
5287
5288   xtensa_default_isa = xtensa_isa_init (0, 0);
5289   isa = xtensa_default_isa;
5290
5291   linkrelax = opt_linkrelax;
5292
5293   /* Set up the literal sections.  */
5294   memset (&default_lit_sections, 0, sizeof (default_lit_sections));
5295
5296   subseg_set (current_section, current_subsec);
5297
5298   xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
5299   xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
5300   xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
5301   xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4");
5302   xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8");
5303   xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12");
5304   xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0");
5305   xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
5306   xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
5307   xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
5308   xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
5309   xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
5310   xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui");
5311   xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
5312   xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
5313   xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
5314   xtensa_j_opcode = xtensa_opcode_lookup (isa, "j");
5315   xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
5316   xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
5317   xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
5318   xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
5319   xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
5320   xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
5321   xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
5322   xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
5323   xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
5324   xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
5325   xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
5326   xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
5327   xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
5328   xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
5329
5330   for (i = 0; i < xtensa_isa_num_formats (isa); i++)
5331     {
5332       int format_slots = xtensa_format_num_slots (isa, i);
5333       if (format_slots > config_max_slots)
5334         config_max_slots = format_slots;
5335     }
5336
5337   xg_init_vinsn (&cur_vinsn);
5338
5339   xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa);
5340
5341   init_op_placement_info_table ();
5342
5343   /* Set up the assembly state.  */
5344   if (!frag_now->tc_frag_data.is_assembly_state_set)
5345     xtensa_set_frag_assembly_state (frag_now);
5346
5347   if (!use_literal_section)
5348     xtensa_mark_literal_pool_location ();
5349 }
5350
5351
5352 /* TC_INIT_FIX_DATA hook */
5353
5354 void
5355 xtensa_init_fix_data (fixS *x)
5356 {
5357   x->tc_fix_data.slot = 0;
5358   x->tc_fix_data.X_add_symbol = NULL;
5359   x->tc_fix_data.X_add_number = 0;
5360 }
5361
5362
5363 /* tc_frob_label hook */
5364
5365 void
5366 xtensa_frob_label (symbolS *sym)
5367 {
5368   float freq;
5369
5370   if (cur_vinsn.inside_bundle)
5371     {
5372       as_bad (_("labels are not valid inside bundles"));
5373       return;
5374     }
5375
5376   freq = get_subseg_target_freq (now_seg, now_subseg);
5377
5378   /* Since the label was already attached to a frag associated with the
5379      previous basic block, it now needs to be reset to the current frag.  */
5380   symbol_set_frag (sym, frag_now);
5381   S_SET_VALUE (sym, (valueT) frag_now_fix ());
5382
5383   if (generating_literals)
5384     xtensa_add_literal_sym (sym);
5385   else
5386     xtensa_add_insn_label (sym);
5387
5388   if (symbol_get_tc (sym)->is_loop_target)
5389     {
5390       if ((get_last_insn_flags (now_seg, now_subseg)
5391           & FLAG_IS_BAD_LOOPEND) != 0)
5392         as_bad (_("invalid last instruction for a zero-overhead loop"));
5393
5394       xtensa_set_frag_assembly_state (frag_now);
5395       frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END,
5396                 frag_now->fr_symbol, frag_now->fr_offset, NULL);
5397
5398       xtensa_set_frag_assembly_state (frag_now);
5399       xtensa_move_labels (frag_now, 0);
5400     }
5401
5402   /* No target aligning in the absolute section.  */
5403   if (now_seg != absolute_section
5404       && !is_unaligned_label (sym)
5405       && !generating_literals)
5406     {
5407       xtensa_set_frag_assembly_state (frag_now);
5408
5409       if (do_align_targets ())
5410         frag_var (rs_machine_dependent, 0, (int) freq,
5411                   RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol,
5412                   frag_now->fr_offset, NULL);
5413       else
5414         frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
5415                   frag_now->fr_symbol, frag_now->fr_offset, NULL);
5416       xtensa_set_frag_assembly_state (frag_now);
5417       xtensa_move_labels (frag_now, 0);
5418     }
5419
5420   /* We need to mark the following properties even if we aren't aligning.  */
5421
5422   /* If the label is already known to be a branch target, i.e., a
5423      forward branch, mark the frag accordingly.  Backward branches
5424      are handled by xg_add_branch_and_loop_targets.  */
5425   if (symbol_get_tc (sym)->is_branch_target)
5426     symbol_get_frag (sym)->tc_frag_data.is_branch_target = true;
5427
5428   /* Loops only go forward, so they can be identified here.  */
5429   if (symbol_get_tc (sym)->is_loop_target)
5430     symbol_get_frag (sym)->tc_frag_data.is_loop_target = true;
5431
5432   dwarf2_emit_label (sym);
5433 }
5434
5435
5436 /* tc_unrecognized_line hook */
5437
5438 int
5439 xtensa_unrecognized_line (int ch)
5440 {
5441   switch (ch)
5442     {
5443     case '{' :
5444       if (cur_vinsn.inside_bundle == 0)
5445         {
5446           /* PR8110: Cannot emit line number info inside a FLIX bundle
5447              when using --gstabs.  Temporarily disable debug info.  */
5448           generate_lineno_debug ();
5449           if (debug_type == DEBUG_STABS)
5450             {
5451               xt_saved_debug_type = debug_type;
5452               debug_type = DEBUG_NONE;
5453             }
5454
5455           cur_vinsn.inside_bundle = 1;
5456         }
5457       else
5458         {
5459           as_bad (_("extra opening brace"));
5460           return 0;
5461         }
5462       break;
5463
5464     case '}' :
5465       if (cur_vinsn.inside_bundle)
5466         finish_vinsn (&cur_vinsn);
5467       else
5468         {
5469           as_bad (_("extra closing brace"));
5470           return 0;
5471         }
5472       break;
5473     default:
5474       as_bad (_("syntax error"));
5475       return 0;
5476     }
5477   return 1;
5478 }
5479
5480
5481 /* md_flush_pending_output hook */
5482
5483 void
5484 xtensa_flush_pending_output (void)
5485 {
5486   /* This line fixes a bug where automatically generated gstabs info
5487      separates a function label from its entry instruction, ending up
5488      with the literal position between the function label and the entry
5489      instruction and crashing code.  It only happens with --gstabs and
5490      --text-section-literals, and when several other obscure relaxation
5491      conditions are met.  */
5492   if (outputting_stabs_line_debug)
5493     return;
5494
5495   if (cur_vinsn.inside_bundle)
5496     as_bad (_("missing closing brace"));
5497
5498   /* If there is a non-zero instruction fragment, close it.  */
5499   if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
5500     {
5501       frag_wane (frag_now);
5502       frag_new (0);
5503       xtensa_set_frag_assembly_state (frag_now);
5504     }
5505   frag_now->tc_frag_data.is_insn = false;
5506
5507   xtensa_clear_insn_labels ();
5508 }
5509
5510
5511 /* We had an error while parsing an instruction.  The string might look
5512    like this: "insn arg1, arg2 }".  If so, we need to see the closing
5513    brace and reset some fields.  Otherwise, the vinsn never gets closed
5514    and the num_slots field will grow past the end of the array of slots,
5515    and bad things happen.  */
5516
5517 static void
5518 error_reset_cur_vinsn (void)
5519 {
5520   if (cur_vinsn.inside_bundle)
5521     {
5522       if (*input_line_pointer == '}'
5523           || *(input_line_pointer - 1) == '}'
5524           || *(input_line_pointer - 2) == '}')
5525         xg_clear_vinsn (&cur_vinsn);
5526     }
5527 }
5528
5529
5530 void
5531 md_assemble (char *str)
5532 {
5533   xtensa_isa isa = xtensa_default_isa;
5534   char *opname;
5535   unsigned opnamelen;
5536   bool has_underbar = false;
5537   char *arg_strings[MAX_INSN_ARGS];
5538   int num_args;
5539   TInsn orig_insn;              /* Original instruction from the input.  */
5540
5541   tinsn_init (&orig_insn);
5542
5543   /* Split off the opcode.  */
5544   opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5545   opname = xstrndup (str, opnamelen);
5546
5547   num_args = tokenize_arguments (arg_strings, str + opnamelen);
5548   if (num_args == -1)
5549     {
5550       as_bad (_("syntax error"));
5551       return;
5552     }
5553
5554   if (xg_translate_idioms (&opname, &num_args, arg_strings))
5555     return;
5556
5557   /* Check for an underbar prefix.  */
5558   if (*opname == '_')
5559     {
5560       has_underbar = true;
5561       opname += 1;
5562     }
5563
5564   orig_insn.insn_type = ITYPE_INSN;
5565   orig_insn.ntok = 0;
5566   orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
5567   orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
5568
5569   /* Special case: Check for "CALLXn.TLS" pseudo op.  If found, grab its
5570      extra argument and set the opcode to "CALLXn".  */
5571   if (orig_insn.opcode == XTENSA_UNDEFINED
5572       && strncasecmp (opname, "callx", 5) == 0)
5573     {
5574       unsigned long window_size;
5575       char *suffix;
5576
5577       window_size = strtoul (opname + 5, &suffix, 10);
5578       if (suffix != opname + 5
5579           && (window_size == 0
5580               || window_size == 4
5581               || window_size == 8
5582               || window_size == 12)
5583           && strcasecmp (suffix, ".tls") == 0)
5584         {
5585           switch (window_size)
5586             {
5587             case 0: orig_insn.opcode = xtensa_callx0_opcode; break;
5588             case 4: orig_insn.opcode = xtensa_callx4_opcode; break;
5589             case 8: orig_insn.opcode = xtensa_callx8_opcode; break;
5590             case 12: orig_insn.opcode = xtensa_callx12_opcode; break;
5591             }
5592
5593           if (num_args != 2)
5594             as_bad (_("wrong number of operands for '%s'"), opname);
5595           else
5596             {
5597               bfd_reloc_code_real_type reloc;
5598               char *old_input_line_pointer;
5599               expressionS *tok = &orig_insn.extra_arg;
5600
5601               old_input_line_pointer = input_line_pointer;
5602               input_line_pointer = arg_strings[num_args - 1];
5603
5604               expression (tok);
5605               if (tok->X_op == O_symbol
5606                   && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
5607                       == BFD_RELOC_XTENSA_TLS_CALL))
5608                 tok->X_op = map_suffix_reloc_to_operator (reloc);
5609               else
5610                 as_bad (_("bad relocation expression for '%s'"), opname);
5611
5612               input_line_pointer = old_input_line_pointer;
5613               num_args -= 1;
5614             }
5615         }
5616     }
5617
5618   /* Special case: Check for "j.l" pseudo op.  */
5619   if (orig_insn.opcode == XTENSA_UNDEFINED
5620       && strncasecmp (opname, "j.l", 3) == 0)
5621     {
5622       if (num_args != 2)
5623         as_bad (_("wrong number of operands for '%s'"), opname);
5624       else
5625         {
5626           char *old_input_line_pointer;
5627           expressionS *tok = &orig_insn.extra_arg;
5628
5629           old_input_line_pointer = input_line_pointer;
5630           input_line_pointer = arg_strings[num_args - 1];
5631
5632           expression_maybe_register (xtensa_jx_opcode, 0, tok);
5633           input_line_pointer = old_input_line_pointer;
5634
5635           num_args -= 1;
5636           orig_insn.opcode = xtensa_j_opcode;
5637         }
5638     }
5639
5640   if (orig_insn.opcode == XTENSA_UNDEFINED)
5641     {
5642       xtensa_format fmt = xtensa_format_lookup (isa, opname);
5643       if (fmt == XTENSA_UNDEFINED)
5644         {
5645           as_bad (_("unknown opcode or format name '%s'"), opname);
5646           error_reset_cur_vinsn ();
5647           return;
5648         }
5649       if (!cur_vinsn.inside_bundle)
5650         {
5651           as_bad (_("format names only valid inside bundles"));
5652           error_reset_cur_vinsn ();
5653           return;
5654         }
5655       if (cur_vinsn.format != XTENSA_UNDEFINED)
5656         as_warn (_("multiple formats specified for one bundle; using '%s'"),
5657                  opname);
5658       cur_vinsn.format = fmt;
5659       free (has_underbar ? opname - 1 : opname);
5660       error_reset_cur_vinsn ();
5661       return;
5662     }
5663
5664   /* Parse the arguments.  */
5665   if (parse_arguments (&orig_insn, num_args, arg_strings))
5666     {
5667       as_bad (_("syntax error"));
5668       error_reset_cur_vinsn ();
5669       return;
5670     }
5671
5672   /* Free the opcode and argument strings, now that they've been parsed.  */
5673   free (has_underbar ? opname - 1 : opname);
5674   opname = 0;
5675   while (num_args-- > 0)
5676     free (arg_strings[num_args]);
5677
5678   /* Get expressions for invisible operands.  */
5679   if (get_invisible_operands (&orig_insn))
5680     {
5681       error_reset_cur_vinsn ();
5682       return;
5683     }
5684
5685   /* Check for the right number and type of arguments.  */
5686   if (tinsn_check_arguments (&orig_insn))
5687     {
5688       error_reset_cur_vinsn ();
5689       return;
5690     }
5691
5692   /* Record the line number for each TInsn, because a FLIX bundle may be
5693      spread across multiple input lines and individual instructions may be
5694      moved around in some cases.  */
5695   orig_insn.loc_directive_seen = dwarf2_loc_directive_seen;
5696   dwarf2_where (&orig_insn.debug_line);
5697   dwarf2_consume_line_info ();
5698
5699   xg_add_branch_and_loop_targets (&orig_insn);
5700
5701   /* Check that immediate value for ENTRY is >= 16.  */
5702   if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3)
5703     {
5704       expressionS *exp = &orig_insn.tok[2];
5705       if (exp->X_op == O_constant && exp->X_add_number < 16)
5706         as_warn (_("entry instruction with stack decrement < 16"));
5707     }
5708
5709   /* Finish it off:
5710      assemble_tokens (opcode, tok, ntok);
5711      expand the tokens from the orig_insn into the
5712      stack of instructions that will not expand
5713      unless required at relaxation time.  */
5714
5715   if (!cur_vinsn.inside_bundle)
5716     emit_single_op (&orig_insn);
5717   else /* We are inside a bundle.  */
5718     {
5719       cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
5720       cur_vinsn.num_slots++;
5721       if (*input_line_pointer == '}'
5722           || *(input_line_pointer - 1) == '}'
5723           || *(input_line_pointer - 2) == '}')
5724         finish_vinsn (&cur_vinsn);
5725     }
5726
5727   /* We've just emitted a new instruction so clear the list of labels.  */
5728   xtensa_clear_insn_labels ();
5729
5730   xtensa_check_frag_count ();
5731 }
5732
5733
5734 /* HANDLE_ALIGN hook */
5735
5736 /* For a .align directive, we mark the previous block with the alignment
5737    information.  This will be placed in the object file in the
5738    property section corresponding to this section.  */
5739
5740 void
5741 xtensa_handle_align (fragS *fragP)
5742 {
5743   if (linkrelax
5744       && ! fragP->tc_frag_data.is_literal
5745       && (fragP->fr_type == rs_align
5746           || fragP->fr_type == rs_align_code)
5747       && fragP->fr_offset > 0
5748       && now_seg != bss_section)
5749     {
5750       fragP->tc_frag_data.is_align = true;
5751       fragP->tc_frag_data.alignment = fragP->fr_offset;
5752     }
5753
5754   if (fragP->fr_type == rs_align_test)
5755     {
5756       int count;
5757       count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5758       if (count != 0)
5759         as_bad_where (fragP->fr_file, fragP->fr_line,
5760                       _("unaligned entry instruction"));
5761     }
5762
5763   if (linkrelax && fragP->fr_type == rs_org)
5764     fragP->fr_subtype = RELAX_ORG;
5765 }
5766
5767
5768 /* TC_FRAG_INIT hook */
5769
5770 void
5771 xtensa_frag_init (fragS *frag)
5772 {
5773   xtensa_set_frag_assembly_state (frag);
5774 }
5775
5776
5777 symbolS *
5778 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5779 {
5780   return NULL;
5781 }
5782
5783
5784 /* Round up a section size to the appropriate boundary.  */
5785
5786 valueT
5787 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5788 {
5789   return size;                  /* Byte alignment is fine.  */
5790 }
5791
5792
5793 long
5794 md_pcrel_from (fixS *fixP)
5795 {
5796   char *insn_p;
5797   static xtensa_insnbuf insnbuf = NULL;
5798   static xtensa_insnbuf slotbuf = NULL;
5799   int opnum;
5800   uint32 opnd_value;
5801   xtensa_opcode opcode;
5802   xtensa_format fmt;
5803   int slot;
5804   xtensa_isa isa = xtensa_default_isa;
5805   valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
5806   bool alt_reloc;
5807
5808   if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
5809     return 0;
5810
5811   if (fixP->fx_r_type == BFD_RELOC_32_PCREL)
5812     return addr;
5813
5814   if (!insnbuf)
5815     {
5816       insnbuf = xtensa_insnbuf_alloc (isa);
5817       slotbuf = xtensa_insnbuf_alloc (isa);
5818     }
5819
5820   insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
5821   xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0);
5822   fmt = xtensa_format_decode (isa, insnbuf);
5823
5824   if (fmt == XTENSA_UNDEFINED)
5825     as_fatal (_("bad instruction format"));
5826
5827   if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
5828     as_fatal (_("invalid relocation"));
5829
5830   xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
5831   opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
5832
5833   /* Check for "alternate" relocations (operand not specified).  None
5834      of the current uses for these are really PC-relative.  */
5835   if (alt_reloc || opcode == xtensa_const16_opcode)
5836     {
5837       if (opcode != xtensa_l32r_opcode
5838           && opcode != xtensa_const16_opcode)
5839         as_fatal (_("invalid relocation for '%s' instruction"),
5840                   xtensa_opcode_name (isa, opcode));
5841       return 0;
5842     }
5843
5844   opnum = get_relaxable_immed (opcode);
5845   opnd_value = 0;
5846   if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
5847       || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
5848     {
5849       as_bad_where (fixP->fx_file,
5850                     fixP->fx_line,
5851                     _("invalid relocation for operand %d of '%s'"),
5852                     opnum, xtensa_opcode_name (isa, opcode));
5853       return 0;
5854     }
5855   return 0 - opnd_value;
5856 }
5857
5858
5859 /* TC_FORCE_RELOCATION hook */
5860
5861 int
5862 xtensa_force_relocation (fixS *fix)
5863 {
5864   switch (fix->fx_r_type)
5865     {
5866     case BFD_RELOC_XTENSA_ASM_EXPAND:
5867     case BFD_RELOC_XTENSA_SLOT0_ALT:
5868     case BFD_RELOC_XTENSA_SLOT1_ALT:
5869     case BFD_RELOC_XTENSA_SLOT2_ALT:
5870     case BFD_RELOC_XTENSA_SLOT3_ALT:
5871     case BFD_RELOC_XTENSA_SLOT4_ALT:
5872     case BFD_RELOC_XTENSA_SLOT5_ALT:
5873     case BFD_RELOC_XTENSA_SLOT6_ALT:
5874     case BFD_RELOC_XTENSA_SLOT7_ALT:
5875     case BFD_RELOC_XTENSA_SLOT8_ALT:
5876     case BFD_RELOC_XTENSA_SLOT9_ALT:
5877     case BFD_RELOC_XTENSA_SLOT10_ALT:
5878     case BFD_RELOC_XTENSA_SLOT11_ALT:
5879     case BFD_RELOC_XTENSA_SLOT12_ALT:
5880     case BFD_RELOC_XTENSA_SLOT13_ALT:
5881     case BFD_RELOC_XTENSA_SLOT14_ALT:
5882       return 1;
5883     default:
5884       break;
5885     }
5886
5887   if (linkrelax && fix->fx_addsy
5888       && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
5889     return 1;
5890
5891   return generic_force_reloc (fix);
5892 }
5893
5894
5895 /* TC_VALIDATE_FIX_SUB hook */
5896
5897 int
5898 xtensa_validate_fix_sub (fixS *fix)
5899 {
5900   segT add_symbol_segment, sub_symbol_segment;
5901
5902   /* The difference of two symbols should be resolved by the assembler when
5903      linkrelax is not set.  If the linker may relax the section containing
5904      the symbols, then an Xtensa DIFF relocation must be generated so that
5905      the linker knows to adjust the difference value.  */
5906   if (!linkrelax || fix->fx_addsy == NULL)
5907     return 0;
5908
5909   /* Make sure both symbols are in the same segment, and that segment is
5910      "normal" and relaxable.  If the segment is not "normal", then the
5911      fix is not valid.  If the segment is not "relaxable", then the fix
5912      should have been handled earlier.  */
5913   add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
5914   if (! SEG_NORMAL (add_symbol_segment) ||
5915       ! relaxable_section (add_symbol_segment))
5916     return 0;
5917   sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
5918   return (sub_symbol_segment == add_symbol_segment);
5919 }
5920
5921
5922 /* NO_PSEUDO_DOT hook */
5923
5924 /* This function has nothing to do with pseudo dots, but this is the
5925    nearest macro to where the check needs to take place.  FIXME: This
5926    seems wrong.  */
5927
5928 bool
5929 xtensa_check_inside_bundle (void)
5930 {
5931   if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
5932     as_bad (_("directives are not valid inside bundles"));
5933
5934   /* This function must always return FALSE because it is called via a
5935      macro that has nothing to do with bundling.  */
5936   return false;
5937 }
5938
5939
5940 /* md_elf_section_change_hook */
5941
5942 void
5943 xtensa_elf_section_change_hook (void)
5944 {
5945   /* Set up the assembly state.  */
5946   if (!frag_now->tc_frag_data.is_assembly_state_set)
5947     xtensa_set_frag_assembly_state (frag_now);
5948
5949   if (!use_literal_section
5950       && seg_info (now_seg)->tc_segment_info_data.literal_pool_loc == NULL
5951       && !xtensa_is_init_fini (now_seg))
5952     xtensa_mark_literal_pool_location ();
5953 }
5954
5955
5956 /* tc_fix_adjustable hook */
5957
5958 bool
5959 xtensa_fix_adjustable (fixS *fixP)
5960 {
5961   /* We need the symbol name for the VTABLE entries.  */
5962   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5963       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5964     return 0;
5965
5966   return 1;
5967 }
5968
5969
5970 /* tc_symbol_new_hook */
5971
5972 symbolS *expr_symbols = NULL;
5973
5974 void
5975 xtensa_symbol_new_hook (symbolS *sym)
5976 {
5977   if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section)
5978     {
5979       symbol_get_tc (sym)->next_expr_symbol = expr_symbols;
5980       expr_symbols = sym;
5981     }
5982 }
5983
5984
5985 void
5986 md_apply_fix (fixS *fixP, valueT *valP, segT seg)
5987 {
5988   char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
5989   valueT val = 0;
5990
5991   /* Subtracted symbols are only allowed for a few relocation types, and
5992      unless linkrelax is enabled, they should not make it to this point.  */
5993   if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32
5994                                         || fixP->fx_r_type == BFD_RELOC_16
5995                                         || fixP->fx_r_type == BFD_RELOC_8)))
5996     as_bad_subtract (fixP);
5997
5998   switch (fixP->fx_r_type)
5999     {
6000     case BFD_RELOC_32_PCREL:
6001     case BFD_RELOC_32:
6002     case BFD_RELOC_16:
6003     case BFD_RELOC_8:
6004       if (fixP->fx_subsy)
6005         {
6006           bool neg = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
6007                       < S_GET_VALUE (fixP->fx_subsy));
6008
6009           switch (fixP->fx_r_type)
6010             {
6011             case BFD_RELOC_8:
6012               fixP->fx_r_type = neg
6013                 ? BFD_RELOC_XTENSA_NDIFF8 : BFD_RELOC_XTENSA_PDIFF8;
6014               fixP->fx_signed = 0;
6015               break;
6016             case BFD_RELOC_16:
6017               fixP->fx_r_type = neg
6018                 ? BFD_RELOC_XTENSA_NDIFF16 : BFD_RELOC_XTENSA_PDIFF16;
6019               fixP->fx_signed = 0;
6020               break;
6021             case BFD_RELOC_32:
6022               fixP->fx_r_type = neg
6023                 ? BFD_RELOC_XTENSA_NDIFF32 : BFD_RELOC_XTENSA_PDIFF32;
6024               fixP->fx_signed = 0;
6025               break;
6026             default:
6027               break;
6028             }
6029
6030           val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
6031                  - S_GET_VALUE (fixP->fx_subsy));
6032
6033           /* The difference value gets written out, and the DIFF reloc
6034              identifies the address of the subtracted symbol (i.e., the one
6035              with the lowest address).  */
6036           *valP = val;
6037           fixP->fx_offset -= val;
6038           fixP->fx_subsy = NULL;
6039         }
6040       else if (! fixP->fx_addsy)
6041         {
6042           val = *valP;
6043           fixP->fx_done = 1;
6044         }
6045       else if (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section)
6046         {
6047           val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
6048           *valP = val;
6049           fixP->fx_done = 1;
6050         }
6051       /* fall through */
6052
6053     case BFD_RELOC_XTENSA_PLT:
6054       md_number_to_chars (fixpos, val, fixP->fx_size);
6055       fixP->fx_no_overflow = 0; /* Use the standard overflow check.  */
6056       break;
6057
6058     case BFD_RELOC_XTENSA_TLSDESC_FN:
6059     case BFD_RELOC_XTENSA_TLSDESC_ARG:
6060     case BFD_RELOC_XTENSA_TLS_TPOFF:
6061     case BFD_RELOC_XTENSA_TLS_DTPOFF:
6062       S_SET_THREAD_LOCAL (fixP->fx_addsy);
6063       md_number_to_chars (fixpos, 0, fixP->fx_size);
6064       fixP->fx_no_overflow = 0; /* Use the standard overflow check.  */
6065       break;
6066
6067     case BFD_RELOC_XTENSA_SLOT0_OP:
6068     case BFD_RELOC_XTENSA_SLOT1_OP:
6069     case BFD_RELOC_XTENSA_SLOT2_OP:
6070     case BFD_RELOC_XTENSA_SLOT3_OP:
6071     case BFD_RELOC_XTENSA_SLOT4_OP:
6072     case BFD_RELOC_XTENSA_SLOT5_OP:
6073     case BFD_RELOC_XTENSA_SLOT6_OP:
6074     case BFD_RELOC_XTENSA_SLOT7_OP:
6075     case BFD_RELOC_XTENSA_SLOT8_OP:
6076     case BFD_RELOC_XTENSA_SLOT9_OP:
6077     case BFD_RELOC_XTENSA_SLOT10_OP:
6078     case BFD_RELOC_XTENSA_SLOT11_OP:
6079     case BFD_RELOC_XTENSA_SLOT12_OP:
6080     case BFD_RELOC_XTENSA_SLOT13_OP:
6081     case BFD_RELOC_XTENSA_SLOT14_OP:
6082       if (linkrelax)
6083         {
6084           /* Write the tentative value of a PC-relative relocation to a
6085              local symbol into the instruction.  The value will be ignored
6086              by the linker, and it makes the object file disassembly
6087              readable when all branch targets are encoded in relocations.  */
6088
6089           gas_assert (fixP->fx_addsy);
6090           if (S_GET_SEGMENT (fixP->fx_addsy) == seg
6091               && !S_FORCE_RELOC (fixP->fx_addsy, 1))
6092             {
6093               val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
6094                      - md_pcrel_from (fixP));
6095               (void) xg_apply_fix_value (fixP, val);
6096             }
6097         }
6098       else if (! fixP->fx_addsy)
6099         {
6100           val = *valP;
6101           if (xg_apply_fix_value (fixP, val))
6102             fixP->fx_done = 1;
6103         }
6104       break;
6105
6106     case BFD_RELOC_XTENSA_ASM_EXPAND:
6107     case BFD_RELOC_XTENSA_TLS_FUNC:
6108     case BFD_RELOC_XTENSA_TLS_ARG:
6109     case BFD_RELOC_XTENSA_TLS_CALL:
6110     case BFD_RELOC_XTENSA_SLOT0_ALT:
6111     case BFD_RELOC_XTENSA_SLOT1_ALT:
6112     case BFD_RELOC_XTENSA_SLOT2_ALT:
6113     case BFD_RELOC_XTENSA_SLOT3_ALT:
6114     case BFD_RELOC_XTENSA_SLOT4_ALT:
6115     case BFD_RELOC_XTENSA_SLOT5_ALT:
6116     case BFD_RELOC_XTENSA_SLOT6_ALT:
6117     case BFD_RELOC_XTENSA_SLOT7_ALT:
6118     case BFD_RELOC_XTENSA_SLOT8_ALT:
6119     case BFD_RELOC_XTENSA_SLOT9_ALT:
6120     case BFD_RELOC_XTENSA_SLOT10_ALT:
6121     case BFD_RELOC_XTENSA_SLOT11_ALT:
6122     case BFD_RELOC_XTENSA_SLOT12_ALT:
6123     case BFD_RELOC_XTENSA_SLOT13_ALT:
6124     case BFD_RELOC_XTENSA_SLOT14_ALT:
6125       /* These all need to be resolved at link-time.  Do nothing now.  */
6126       break;
6127
6128     case BFD_RELOC_VTABLE_INHERIT:
6129     case BFD_RELOC_VTABLE_ENTRY:
6130       fixP->fx_done = 0;
6131       break;
6132
6133     default:
6134       as_bad (_("unhandled local relocation fix %s"),
6135               bfd_get_reloc_code_name (fixP->fx_r_type));
6136     }
6137 }
6138
6139
6140 const char *
6141 md_atof (int type, char *litP, int *sizeP)
6142 {
6143   return ieee_md_atof (type, litP, sizeP, target_big_endian);
6144 }
6145
6146
6147 int
6148 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
6149 {
6150   return total_frag_text_expansion (fragP);
6151 }
6152
6153
6154 /* Translate internal representation of relocation info to BFD target
6155    format.  */
6156
6157 arelent *
6158 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
6159 {
6160   arelent *reloc;
6161
6162   reloc = XNEW (arelent);
6163   reloc->sym_ptr_ptr = XNEW (asymbol *);
6164   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6165   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6166
6167   /* Make sure none of our internal relocations make it this far.
6168      They'd better have been fully resolved by this point.  */
6169   gas_assert ((int) fixp->fx_r_type > 0);
6170
6171   reloc->addend = fixp->fx_offset;
6172
6173   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
6174   if (reloc->howto == NULL)
6175     {
6176       as_bad_where (fixp->fx_file, fixp->fx_line,
6177                     _("cannot represent `%s' relocation in object file"),
6178                     bfd_get_reloc_code_name (fixp->fx_r_type));
6179       free (reloc->sym_ptr_ptr);
6180       free (reloc);
6181       return NULL;
6182     }
6183
6184   if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
6185     as_fatal (_("internal error; cannot generate `%s' relocation"),
6186               bfd_get_reloc_code_name (fixp->fx_r_type));
6187
6188   return reloc;
6189 }
6190
6191 \f
6192 /* Checks for resource conflicts between instructions.  */
6193
6194 /* The func unit stuff could be implemented as bit-vectors rather
6195    than the iterative approach here.  If it ends up being too
6196    slow, we will switch it.  */
6197
6198 resource_table *
6199 new_resource_table (void *data,
6200                     int cycles,
6201                     int nu,
6202                     unit_num_copies_func uncf,
6203                     opcode_num_units_func onuf,
6204                     opcode_funcUnit_use_unit_func ouuf,
6205                     opcode_funcUnit_use_stage_func ousf)
6206 {
6207   int i;
6208   resource_table *rt = XNEW (resource_table);
6209   rt->data = data;
6210   rt->cycles = cycles;
6211   rt->allocated_cycles = cycles;
6212   rt->num_units = nu;
6213   rt->unit_num_copies = uncf;
6214   rt->opcode_num_units = onuf;
6215   rt->opcode_unit_use = ouuf;
6216   rt->opcode_unit_stage = ousf;
6217
6218   rt->units = XCNEWVEC (unsigned char *, cycles);
6219   for (i = 0; i < cycles; i++)
6220     rt->units[i] = XCNEWVEC (unsigned char, nu);
6221
6222   return rt;
6223 }
6224
6225
6226 void
6227 clear_resource_table (resource_table *rt)
6228 {
6229   int i, j;
6230   for (i = 0; i < rt->allocated_cycles; i++)
6231     for (j = 0; j < rt->num_units; j++)
6232       rt->units[i][j] = 0;
6233 }
6234
6235
6236 /* We never shrink it, just fake it into thinking so.  */
6237
6238 void
6239 resize_resource_table (resource_table *rt, int cycles)
6240 {
6241   int i, old_cycles;
6242
6243   rt->cycles = cycles;
6244   if (cycles <= rt->allocated_cycles)
6245     return;
6246
6247   old_cycles = rt->allocated_cycles;
6248   rt->allocated_cycles = cycles;
6249
6250   rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles);
6251   for (i = 0; i < old_cycles; i++)
6252     rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units);
6253   for (i = old_cycles; i < cycles; i++)
6254     rt->units[i] = XCNEWVEC (unsigned char, rt->num_units);
6255 }
6256
6257
6258 bool
6259 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
6260 {
6261   int i;
6262   int uses = (rt->opcode_num_units) (rt->data, opcode);
6263
6264   for (i = 0; i < uses; i++)
6265     {
6266       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6267       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6268       int copies_in_use = rt->units[stage + cycle][unit];
6269       int copies = (rt->unit_num_copies) (rt->data, unit);
6270       if (copies_in_use >= copies)
6271         return false;
6272     }
6273   return true;
6274 }
6275
6276
6277 void
6278 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6279 {
6280   int i;
6281   int uses = (rt->opcode_num_units) (rt->data, opcode);
6282
6283   for (i = 0; i < uses; i++)
6284     {
6285       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6286       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6287       /* Note that this allows resources to be oversubscribed.  That's
6288          essential to the way the optional scheduler works.
6289          resources_available reports when a resource is over-subscribed,
6290          so it's easy to tell.  */
6291       rt->units[stage + cycle][unit]++;
6292     }
6293 }
6294
6295
6296 void
6297 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
6298 {
6299   int i;
6300   int uses = (rt->opcode_num_units) (rt->data, opcode);
6301
6302   for (i = 0; i < uses; i++)
6303     {
6304       xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
6305       int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
6306       gas_assert (rt->units[stage + cycle][unit] > 0);
6307       rt->units[stage + cycle][unit]--;
6308     }
6309 }
6310
6311
6312 /* Wrapper functions make parameterized resource reservation
6313    more convenient.  */
6314
6315 int
6316 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
6317 {
6318   xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6319   return use->unit;
6320 }
6321
6322
6323 int
6324 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
6325 {
6326   xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
6327   return use->stage;
6328 }
6329
6330
6331 /* Note that this function does not check issue constraints, but
6332    solely whether the hardware is available to execute the given
6333    instructions together.  It also doesn't check if the tinsns
6334    write the same state, or access the same tieports.  That is
6335    checked by check_t1_t2_reads_and_writes.  */
6336
6337 static bool
6338 resources_conflict (vliw_insn *vinsn)
6339 {
6340   int i;
6341   static resource_table *rt = NULL;
6342
6343   /* This is the most common case by far.  Optimize it.  */
6344   if (vinsn->num_slots == 1)
6345     return false;
6346
6347   if (rt == NULL)
6348     {
6349       xtensa_isa isa = xtensa_default_isa;
6350       rt = new_resource_table
6351         (isa, xtensa_num_pipe_stages,
6352          xtensa_isa_num_funcUnits (isa),
6353          (unit_num_copies_func) xtensa_funcUnit_num_copies,
6354          (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
6355          opcode_funcUnit_use_unit,
6356          opcode_funcUnit_use_stage);
6357     }
6358
6359   clear_resource_table (rt);
6360
6361   for (i = 0; i < vinsn->num_slots; i++)
6362     {
6363       if (!resources_available (rt, vinsn->slots[i].opcode, 0))
6364         return true;
6365       reserve_resources (rt, vinsn->slots[i].opcode, 0);
6366     }
6367
6368   return false;
6369 }
6370
6371 \f
6372 /* finish_vinsn, emit_single_op and helper functions.  */
6373
6374 static bool find_vinsn_conflicts (vliw_insn *);
6375 static xtensa_format xg_find_narrowest_format (vliw_insn *);
6376 static void xg_assemble_vliw_tokens (vliw_insn *);
6377
6378
6379 /* We have reached the end of a bundle; emit into the frag.  */
6380
6381 static void
6382 finish_vinsn (vliw_insn *vinsn)
6383 {
6384   IStack slotstack;
6385   int i;
6386   int slots;
6387
6388   if (find_vinsn_conflicts (vinsn))
6389     {
6390       xg_clear_vinsn (vinsn);
6391       return;
6392     }
6393
6394   /* First, find a format that works.  */
6395   if (vinsn->format == XTENSA_UNDEFINED)
6396     vinsn->format = xg_find_narrowest_format (vinsn);
6397
6398   slots = xtensa_format_num_slots (xtensa_default_isa, vinsn->format);
6399   if (slots > 1
6400       && produce_flix == FLIX_NONE)
6401     {
6402       as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6403       xg_clear_vinsn (vinsn);
6404       return;
6405     }
6406
6407   if (vinsn->format == XTENSA_UNDEFINED)
6408     {
6409       as_bad (_("couldn't find a valid instruction format"));
6410       fprintf (stderr, _("    ops were: "));
6411       for (i = 0; i < vinsn->num_slots; i++)
6412         fprintf (stderr, _(" %s;"),
6413                  xtensa_opcode_name (xtensa_default_isa,
6414                                      vinsn->slots[i].opcode));
6415       fprintf (stderr, _("\n"));
6416       xg_clear_vinsn (vinsn);
6417       return;
6418     }
6419
6420   if (vinsn->num_slots != slots)
6421     {
6422       as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"),
6423               xtensa_format_name (xtensa_default_isa, vinsn->format),
6424               slots, vinsn->num_slots);
6425       xg_clear_vinsn (vinsn);
6426       return;
6427     }
6428
6429   if (resources_conflict (vinsn))
6430     {
6431       as_bad (_("illegal resource usage in bundle"));
6432       fprintf (stderr, "    ops were: ");
6433       for (i = 0; i < vinsn->num_slots; i++)
6434         fprintf (stderr, " %s;",
6435                  xtensa_opcode_name (xtensa_default_isa,
6436                                      vinsn->slots[i].opcode));
6437       fprintf (stderr, "\n");
6438       xg_clear_vinsn (vinsn);
6439       return;
6440     }
6441
6442   for (i = 0; i < vinsn->num_slots; i++)
6443     {
6444       if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
6445         {
6446           symbolS *lit_sym = NULL;
6447           int j;
6448           bool e = false;
6449           bool saved_density = density_supported;
6450
6451           /* We don't want to narrow ops inside multi-slot bundles.  */
6452           if (vinsn->num_slots > 1)
6453             density_supported = false;
6454
6455           istack_init (&slotstack);
6456           if (vinsn->slots[i].opcode == xtensa_nop_opcode)
6457             {
6458               vinsn->slots[i].opcode =
6459                 xtensa_format_slot_nop_opcode (xtensa_default_isa,
6460                                                vinsn->format, i);
6461               vinsn->slots[i].ntok = 0;
6462             }
6463
6464           if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
6465             {
6466               e = true;
6467               continue;
6468             }
6469
6470           density_supported = saved_density;
6471
6472           if (e)
6473             {
6474               xg_clear_vinsn (vinsn);
6475               return;
6476             }
6477
6478           for (j = 0; j < slotstack.ninsn; j++)
6479             {
6480               TInsn *insn = &slotstack.insn[j];
6481               if (insn->insn_type == ITYPE_LITERAL)
6482                 {
6483                   gas_assert (lit_sym == NULL);
6484                   lit_sym = xg_assemble_literal (insn);
6485                 }
6486               else
6487                 {
6488                   gas_assert (insn->insn_type == ITYPE_INSN);
6489                   if (lit_sym)
6490                     xg_resolve_literals (insn, lit_sym);
6491                   if (j != slotstack.ninsn - 1)
6492                     emit_single_op (insn);
6493                 }
6494             }
6495
6496           if (vinsn->num_slots > 1)
6497             {
6498               if (opcode_fits_format_slot
6499                   (slotstack.insn[slotstack.ninsn - 1].opcode,
6500                    vinsn->format, i))
6501                 {
6502                   vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
6503                 }
6504               else
6505                 {
6506                   emit_single_op (&slotstack.insn[slotstack.ninsn - 1]);
6507                   if (vinsn->format == XTENSA_UNDEFINED)
6508                     vinsn->slots[i].opcode = xtensa_nop_opcode;
6509                   else
6510                     vinsn->slots[i].opcode
6511                       = xtensa_format_slot_nop_opcode (xtensa_default_isa,
6512                                                        vinsn->format, i);
6513
6514                   vinsn->slots[i].ntok = 0;
6515                 }
6516             }
6517           else
6518             {
6519               vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
6520               vinsn->format = XTENSA_UNDEFINED;
6521             }
6522         }
6523     }
6524
6525   /* Now check resource conflicts on the modified bundle.  */
6526   if (resources_conflict (vinsn))
6527     {
6528       as_bad (_("illegal resource usage in bundle"));
6529       fprintf (stderr, "    ops were: ");
6530       for (i = 0; i < vinsn->num_slots; i++)
6531         fprintf (stderr, " %s;",
6532                  xtensa_opcode_name (xtensa_default_isa,
6533                                      vinsn->slots[i].opcode));
6534       fprintf (stderr, "\n");
6535       xg_clear_vinsn (vinsn);
6536       return;
6537     }
6538
6539   /* First, find a format that works.  */
6540   if (vinsn->format == XTENSA_UNDEFINED)
6541       vinsn->format = xg_find_narrowest_format (vinsn);
6542
6543   xg_assemble_vliw_tokens (vinsn);
6544
6545   xg_clear_vinsn (vinsn);
6546
6547   xtensa_check_frag_count ();
6548 }
6549
6550
6551 /* Given an vliw instruction, what conflicts are there in register
6552    usage and in writes to states and queues?
6553
6554    This function does two things:
6555    1. Reports an error when a vinsn contains illegal combinations
6556       of writes to registers states or queues.
6557    2. Marks individual tinsns as not relaxable if the combination
6558       contains antidependencies.
6559
6560    Job 2 handles things like swap semantics in instructions that need
6561    to be relaxed.  For example,
6562
6563         addi a0, a1, 100000
6564
6565    normally would be relaxed to
6566
6567         l32r a0, some_label
6568         add a0, a1, a0
6569
6570    _but_, if the above instruction is bundled with an a0 reader, e.g.,
6571
6572         { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6573
6574    then we can't relax it into
6575
6576         l32r a0, some_label
6577         { add a0, a1, a0 ; add a2, a0, a4 ; }
6578
6579    because the value of a0 is trashed before the second add can read it.  */
6580
6581 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
6582
6583 static bool
6584 find_vinsn_conflicts (vliw_insn *vinsn)
6585 {
6586   int i, j;
6587   int branches = 0;
6588   xtensa_isa isa = xtensa_default_isa;
6589
6590   gas_assert (!past_xtensa_md_finish);
6591
6592   for (i = 0 ; i < vinsn->num_slots; i++)
6593     {
6594       TInsn *op1 = &vinsn->slots[i];
6595       if (op1->is_specific_opcode)
6596         op1->keep_wide = true;
6597       else
6598         op1->keep_wide = false;
6599     }
6600
6601   for (i = 0 ; i < vinsn->num_slots; i++)
6602     {
6603       TInsn *op1 = &vinsn->slots[i];
6604
6605       if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
6606         branches++;
6607
6608       for (j = 0; j < vinsn->num_slots; j++)
6609         {
6610           if (i != j)
6611             {
6612               TInsn *op2 = &vinsn->slots[j];
6613               char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
6614               switch (conflict_type)
6615                 {
6616                 case 'c':
6617                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6618                           xtensa_opcode_name (isa, op1->opcode), i,
6619                           xtensa_opcode_name (isa, op2->opcode), j);
6620                   return true;
6621                 case 'd':
6622                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6623                           xtensa_opcode_name (isa, op1->opcode), i,
6624                           xtensa_opcode_name (isa, op2->opcode), j);
6625                   return true;
6626                 case 'e':
6627                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6628                           xtensa_opcode_name (isa, op1->opcode), i,
6629                           xtensa_opcode_name (isa, op2->opcode), j);
6630                   return true;
6631                 case 'f':
6632                   as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6633                           xtensa_opcode_name (isa, op1->opcode), i,
6634                           xtensa_opcode_name (isa, op2->opcode), j);
6635                   return true;
6636                 default:
6637                   /* Everything is OK.  */
6638                   break;
6639                 }
6640               op2->is_specific_opcode = (op2->is_specific_opcode
6641                                          || conflict_type == 'a');
6642             }
6643         }
6644     }
6645
6646   if (branches > 1)
6647     {
6648       as_bad (_("multiple branches or jumps in the same bundle"));
6649       return true;
6650     }
6651
6652   return false;
6653 }
6654
6655
6656 /* Check how the state used by t1 and t2 relate.
6657    Cases found are:
6658
6659    case A: t1 reads a register t2 writes (an antidependency within a bundle)
6660    case B: no relationship between what is read and written (both could
6661            read the same reg though)
6662    case C: t1 writes a register t2 writes (a register conflict within a
6663            bundle)
6664    case D: t1 writes a state that t2 also writes
6665    case E: t1 writes a tie queue that t2 also writes
6666    case F: two volatile queue accesses
6667 */
6668
6669 static char
6670 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
6671 {
6672   xtensa_isa isa = xtensa_default_isa;
6673   xtensa_regfile t1_regfile, t2_regfile;
6674   int t1_reg, t2_reg;
6675   int t1_base_reg, t1_last_reg;
6676   int t2_base_reg, t2_last_reg;
6677   char t1_inout, t2_inout;
6678   int i, j;
6679   char conflict = 'b';
6680   int t1_states;
6681   int t2_states;
6682   int t1_interfaces;
6683   int t2_interfaces;
6684   bool t1_volatile = false;
6685   bool t2_volatile = false;
6686
6687   /* Check registers.  */
6688   for (j = 0; j < t2->ntok; j++)
6689     {
6690       if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
6691         continue;
6692
6693       t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
6694       t2_base_reg = t2->tok[j].X_add_number;
6695       t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
6696
6697       for (i = 0; i < t1->ntok; i++)
6698         {
6699           if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
6700             continue;
6701
6702           t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
6703
6704           if (t1_regfile != t2_regfile)
6705             continue;
6706
6707           t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
6708           t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
6709
6710           if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
6711               || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
6712             {
6713               if (t1_inout == 'm' || t1_inout == 'o'
6714                   || t2_inout == 'm' || t2_inout == 'o')
6715                 {
6716                   conflict = 'a';
6717                   continue;
6718                 }
6719             }
6720
6721           t1_base_reg = t1->tok[i].X_add_number;
6722           t1_last_reg = (t1_base_reg
6723                          + xtensa_operand_num_regs (isa, t1->opcode, i));
6724
6725           for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
6726             {
6727               for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
6728                 {
6729                   if (t1_reg != t2_reg)
6730                     continue;
6731
6732                   if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6733                     {
6734                       conflict = 'a';
6735                       continue;
6736                     }
6737
6738                   if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6739                     {
6740                       conflict = 'a';
6741                       continue;
6742                     }
6743
6744                   if (t1_inout != 'i' && t2_inout != 'i')
6745                     return 'c';
6746                 }
6747             }
6748         }
6749     }
6750
6751   /* Check states.  */
6752   t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
6753   t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
6754   for (j = 0; j < t2_states; j++)
6755     {
6756       xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
6757       t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
6758       for (i = 0; i < t1_states; i++)
6759         {
6760           xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
6761           t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
6762           if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1)
6763             continue;
6764
6765           if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
6766             {
6767               conflict = 'a';
6768               continue;
6769             }
6770
6771           if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
6772             {
6773               conflict = 'a';
6774               continue;
6775             }
6776
6777           if (t1_inout != 'i' && t2_inout != 'i')
6778             return 'd';
6779         }
6780     }
6781
6782   /* Check tieports.  */
6783   t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
6784   t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
6785   for (j = 0; j < t2_interfaces; j++)
6786     {
6787       xtensa_interface t2_int
6788         = xtensa_interfaceOperand_interface (isa, t2->opcode, j);
6789       int t2_class = xtensa_interface_class_id (isa, t2_int);
6790
6791       t2_inout = xtensa_interface_inout (isa, t2_int);
6792       if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
6793         t2_volatile = true;
6794
6795       for (i = 0; i < t1_interfaces; i++)
6796         {
6797           xtensa_interface t1_int
6798             = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
6799           int t1_class = xtensa_interface_class_id (isa, t1_int);
6800
6801           t1_inout = xtensa_interface_inout (isa, t1_int);
6802           if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
6803             t1_volatile = true;
6804
6805           if (t1_volatile && t2_volatile && (t1_class == t2_class))
6806             return 'f';
6807
6808           if (t1_int != t2_int)
6809             continue;
6810
6811           if (t2_inout == 'i' && t1_inout == 'o')
6812             {
6813               conflict = 'a';
6814               continue;
6815             }
6816
6817           if (t1_inout == 'i' && t2_inout == 'o')
6818             {
6819               conflict = 'a';
6820               continue;
6821             }
6822
6823           if (t1_inout != 'i' && t2_inout != 'i')
6824             return 'e';
6825         }
6826     }
6827
6828   return conflict;
6829 }
6830
6831
6832 static xtensa_format
6833 xg_find_narrowest_format (vliw_insn *vinsn)
6834 {
6835   /* Right now we assume that the ops within the vinsn are properly
6836      ordered for the slots that the programmer wanted them in.  In
6837      other words, we don't rearrange the ops in hopes of finding a
6838      better format.  The scheduler handles that.  */
6839
6840   xtensa_isa isa = xtensa_default_isa;
6841   xtensa_format format;
6842   xtensa_opcode nop_opcode = xtensa_nop_opcode;
6843
6844   if (vinsn->num_slots == 1)
6845     return xg_get_single_format (vinsn->slots[0].opcode);
6846
6847   for (format = 0; format < xtensa_isa_num_formats (isa); format++)
6848     {
6849       vliw_insn v_copy;
6850       xg_copy_vinsn (&v_copy, vinsn);
6851       if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
6852         {
6853           int slot;
6854           int fit = 0;
6855           for (slot = 0; slot < v_copy.num_slots; slot++)
6856             {
6857               if (v_copy.slots[slot].opcode == nop_opcode)
6858                 {
6859                   v_copy.slots[slot].opcode =
6860                     xtensa_format_slot_nop_opcode (isa, format, slot);
6861                   v_copy.slots[slot].ntok = 0;
6862                 }
6863
6864               if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
6865                                            format, slot))
6866                 fit++;
6867               else if (v_copy.num_slots > 1)
6868                 {
6869                   TInsn widened;
6870                   /* Try the widened version.  */
6871                   if (!v_copy.slots[slot].keep_wide
6872                       && !v_copy.slots[slot].is_specific_opcode
6873                       && xg_is_single_relaxable_insn (&v_copy.slots[slot],
6874                                                       &widened, true)
6875                       && opcode_fits_format_slot (widened.opcode,
6876                                                   format, slot))
6877                     {
6878                       v_copy.slots[slot] = widened;
6879                       fit++;
6880                     }
6881                 }
6882             }
6883           if (fit == v_copy.num_slots)
6884             {
6885               xg_copy_vinsn (vinsn, &v_copy);
6886               xtensa_format_encode (isa, format, vinsn->insnbuf);
6887               vinsn->format = format;
6888               break;
6889             }
6890         }
6891     }
6892
6893   if (format == xtensa_isa_num_formats (isa))
6894     return XTENSA_UNDEFINED;
6895
6896   return format;
6897 }
6898
6899
6900 /* Return the additional space needed in a frag
6901    for possible relaxations of any ops in a VLIW insn.
6902    Also fill out the relaxations that might be required of
6903    each tinsn in the vinsn.  */
6904
6905 static int
6906 relaxation_requirements (vliw_insn *vinsn, bool *pfinish_frag)
6907 {
6908   bool finish_frag = false;
6909   int extra_space = 0;
6910   int slot;
6911
6912   for (slot = 0; slot < vinsn->num_slots; slot++)
6913     {
6914       TInsn *tinsn = &vinsn->slots[slot];
6915       if (!tinsn_has_symbolic_operands (tinsn))
6916         {
6917           /* A narrow instruction could be widened later to help
6918              alignment issues.  */
6919           if (xg_is_single_relaxable_insn (tinsn, 0, true)
6920               && !tinsn->is_specific_opcode
6921               && vinsn->num_slots == 1)
6922             {
6923               /* Difference in bytes between narrow and wide insns...  */
6924               extra_space += 1;
6925               tinsn->subtype = RELAX_NARROW;
6926             }
6927         }
6928       else
6929         {
6930           if (workaround_b_j_loop_end
6931               && tinsn->opcode == xtensa_jx_opcode
6932               && use_transform ())
6933             {
6934               /* Add 2 of these.  */
6935               extra_space += 3; /* for the nop size */
6936               tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
6937             }
6938
6939           /* Need to assemble it with space for the relocation.  */
6940           if (xg_is_relaxable_insn (tinsn, 0)
6941               && !tinsn->is_specific_opcode)
6942             {
6943               int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
6944               int max_literal_size =
6945                 xg_get_max_insn_widen_literal_size (tinsn->opcode);
6946
6947               tinsn->literal_space = max_literal_size;
6948
6949               tinsn->subtype = RELAX_IMMED;
6950               extra_space += max_size;
6951             }
6952           else
6953             {
6954               /* A fix record will be added for this instruction prior
6955                  to relaxation, so make it end the frag.  */
6956               finish_frag = true;
6957             }
6958         }
6959     }
6960   *pfinish_frag = finish_frag;
6961   return extra_space;
6962 }
6963
6964
6965 static void
6966 bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn)
6967 {
6968   xtensa_isa isa = xtensa_default_isa;
6969   int slot, chosen_slot;
6970
6971   vinsn->format = xg_get_single_format (tinsn->opcode);
6972   gas_assert (vinsn->format != XTENSA_UNDEFINED);
6973   vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format);
6974
6975   chosen_slot = xg_get_single_slot (tinsn->opcode);
6976   for (slot = 0; slot < vinsn->num_slots; slot++)
6977     {
6978       if (slot == chosen_slot)
6979         vinsn->slots[slot] = *tinsn;
6980       else
6981         {
6982           vinsn->slots[slot].opcode =
6983             xtensa_format_slot_nop_opcode (isa, vinsn->format, slot);
6984           vinsn->slots[slot].ntok = 0;
6985           vinsn->slots[slot].insn_type = ITYPE_INSN;
6986         }
6987     }
6988 }
6989
6990
6991 static bool
6992 emit_single_op (TInsn *orig_insn)
6993 {
6994   int i;
6995   IStack istack;                /* put instructions into here */
6996   symbolS *lit_sym = NULL;
6997   symbolS *label_sym = NULL;
6998
6999   istack_init (&istack);
7000
7001   /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
7002      Because the scheduling and bundling characteristics of movi and
7003      l32r or const16 are so different, we can do much better if we relax
7004      it prior to scheduling and bundling, rather than after.  */
7005   if ((orig_insn->opcode == xtensa_movi_opcode
7006        || orig_insn->opcode == xtensa_movi_n_opcode)
7007       && !cur_vinsn.inside_bundle
7008       && (orig_insn->tok[1].X_op == O_symbol
7009           || orig_insn->tok[1].X_op == O_pltrel
7010           || orig_insn->tok[1].X_op == O_tlsfunc
7011           || orig_insn->tok[1].X_op == O_tlsarg
7012           || orig_insn->tok[1].X_op == O_tpoff
7013           || orig_insn->tok[1].X_op == O_dtpoff)
7014       && !orig_insn->is_specific_opcode && use_transform ())
7015     xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
7016   else
7017     if (xg_expand_assembly_insn (&istack, orig_insn))
7018       return true;
7019
7020   for (i = 0; i < istack.ninsn; i++)
7021     {
7022       TInsn *insn = &istack.insn[i];
7023       switch (insn->insn_type)
7024         {
7025         case ITYPE_LITERAL:
7026           gas_assert (lit_sym == NULL);
7027           lit_sym = xg_assemble_literal (insn);
7028           break;
7029         case ITYPE_LABEL:
7030           {
7031             static int relaxed_sym_idx = 0;
7032             char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12);
7033             sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
7034             colon (label);
7035             gas_assert (label_sym == NULL);
7036             label_sym = symbol_find_or_make (label);
7037             gas_assert (label_sym);
7038             free (label);
7039           }
7040           break;
7041         case ITYPE_INSN:
7042           {
7043             vliw_insn v;
7044             if (lit_sym)
7045               xg_resolve_literals (insn, lit_sym);
7046             if (label_sym)
7047               xg_resolve_labels (insn, label_sym);
7048             xg_init_vinsn (&v);
7049             bundle_tinsn (insn, &v);
7050             finish_vinsn (&v);
7051             xg_free_vinsn (&v);
7052           }
7053           break;
7054         default:
7055           gas_assert (0);
7056           break;
7057         }
7058     }
7059   return false;
7060 }
7061
7062
7063 static int
7064 total_frag_text_expansion (fragS *fragP)
7065 {
7066   int slot;
7067   int total_expansion = 0;
7068
7069   for (slot = 0; slot < config_max_slots; slot++)
7070     total_expansion += fragP->tc_frag_data.text_expansion[slot];
7071
7072   return total_expansion;
7073 }
7074
7075
7076 /* Emit a vliw instruction to the current fragment.  */
7077
7078 static void
7079 xg_assemble_vliw_tokens (vliw_insn *vinsn)
7080 {
7081   bool finish_frag;
7082   bool is_jump = false;
7083   bool is_branch = false;
7084   xtensa_isa isa = xtensa_default_isa;
7085   int insn_size;
7086   int extra_space;
7087   char *f = NULL;
7088   int slot;
7089   struct dwarf2_line_info debug_line;
7090   bool loc_directive_seen = false;
7091   TInsn *tinsn;
7092
7093   memset (&debug_line, 0, sizeof (struct dwarf2_line_info));
7094
7095   if (generating_literals)
7096     {
7097       static int reported = 0;
7098       if (reported < 4)
7099         as_bad_where (frag_now->fr_file, frag_now->fr_line,
7100                       _("cannot assemble into a literal fragment"));
7101       if (reported == 3)
7102         as_bad (_("..."));
7103       reported++;
7104       return;
7105     }
7106
7107   if (frag_now_fix () != 0
7108       && (! frag_now->tc_frag_data.is_insn
7109           || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7110           || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform
7111           || (directive_state[directive_longcalls]
7112               != frag_now->tc_frag_data.use_longcalls)
7113           || (directive_state[directive_absolute_literals]
7114               != frag_now->tc_frag_data.use_absolute_literals)))
7115     {
7116       frag_wane (frag_now);
7117       frag_new (0);
7118       xtensa_set_frag_assembly_state (frag_now);
7119     }
7120
7121   if (workaround_a0_b_retw
7122       && vinsn->num_slots == 1
7123       && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
7124       && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
7125       && use_transform ())
7126     {
7127       has_a0_b_retw = true;
7128
7129       /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7130          After the first assembly pass we will check all of them and
7131          add a nop if needed.  */
7132       frag_now->tc_frag_data.is_insn = true;
7133       frag_var (rs_machine_dependent, 4, 4,
7134                 RELAX_ADD_NOP_IF_A0_B_RETW,
7135                 frag_now->fr_symbol,
7136                 frag_now->fr_offset,
7137                 NULL);
7138       xtensa_set_frag_assembly_state (frag_now);
7139       frag_now->tc_frag_data.is_insn = true;
7140       frag_var (rs_machine_dependent, 4, 4,
7141                 RELAX_ADD_NOP_IF_A0_B_RETW,
7142                 frag_now->fr_symbol,
7143                 frag_now->fr_offset,
7144                 NULL);
7145       xtensa_set_frag_assembly_state (frag_now);
7146     }
7147
7148   for (slot = 0; slot < vinsn->num_slots; slot++)
7149     {
7150       tinsn = &vinsn->slots[slot];
7151
7152       /* See if the instruction implies an aligned section.  */
7153       if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1)
7154         record_alignment (now_seg, 2);
7155
7156       /* Determine the best line number for debug info.  */
7157       if ((tinsn->loc_directive_seen || !loc_directive_seen)
7158           && (tinsn->debug_line.filenum != debug_line.filenum
7159               || tinsn->debug_line.line < debug_line.line
7160               || tinsn->debug_line.column < debug_line.column))
7161         debug_line = tinsn->debug_line;
7162       if (tinsn->loc_directive_seen)
7163         loc_directive_seen = true;
7164     }
7165
7166   /* Special cases for instructions that force an alignment... */
7167   /* None of these opcodes are bundle-able.  */
7168   if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
7169     {
7170       int max_fill;
7171
7172       /* Remember the symbol that marks the end of the loop in the frag
7173          that marks the start of the loop.  This way we can easily find
7174          the end of the loop at the beginning, without adding special code
7175          to mark the loop instructions themselves.  */
7176       symbolS *target_sym = NULL;
7177       if (vinsn->slots[0].tok[1].X_op == O_symbol)
7178         target_sym = vinsn->slots[0].tok[1].X_add_symbol;
7179
7180       xtensa_set_frag_assembly_state (frag_now);
7181       frag_now->tc_frag_data.is_insn = true;
7182
7183       max_fill = get_text_align_max_fill_size
7184         (get_text_align_power (xtensa_fetch_width),
7185          true, frag_now->tc_frag_data.is_no_density);
7186
7187       if (use_transform ())
7188         frag_var (rs_machine_dependent, max_fill, max_fill,
7189                   RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
7190       else
7191         frag_var (rs_machine_dependent, 0, 0,
7192                   RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
7193       xtensa_set_frag_assembly_state (frag_now);
7194     }
7195
7196   if (vinsn->slots[0].opcode == xtensa_entry_opcode
7197       && !vinsn->slots[0].is_specific_opcode)
7198     {
7199       xtensa_mark_literal_pool_location ();
7200       xtensa_move_labels (frag_now, 0);
7201       frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
7202     }
7203
7204   if (vinsn->num_slots == 1)
7205     {
7206       if (workaround_a0_b_retw && use_transform ())
7207         set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
7208                              is_register_writer (&vinsn->slots[0], "a", 0));
7209
7210       set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
7211                            is_bad_loopend_opcode (&vinsn->slots[0]));
7212     }
7213   else
7214     set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, false);
7215
7216   insn_size = xtensa_format_length (isa, vinsn->format);
7217
7218   extra_space = relaxation_requirements (vinsn, &finish_frag);
7219
7220   /* vinsn_to_insnbuf will produce the error.  */
7221   if (vinsn->format != XTENSA_UNDEFINED)
7222     {
7223       f = frag_more (insn_size + extra_space);
7224       xtensa_set_frag_assembly_state (frag_now);
7225       frag_now->tc_frag_data.is_insn = true;
7226     }
7227
7228   vinsn_to_insnbuf (vinsn, f, frag_now, false);
7229   if (vinsn->format == XTENSA_UNDEFINED)
7230     return;
7231
7232   xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0);
7233
7234   if (debug_type == DEBUG_DWARF2 || loc_directive_seen)
7235     dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space),
7236                           &debug_line);
7237
7238   for (slot = 0; slot < vinsn->num_slots; slot++)
7239     {
7240       tinsn = &vinsn->slots[slot];
7241       frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
7242       frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
7243       frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
7244       frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
7245       if (tinsn->opcode == xtensa_l32r_opcode)
7246         frag_now->tc_frag_data.literal_frags[slot]
7247           = symbol_get_frag (tinsn->tok[1].X_add_symbol);
7248       if (tinsn->literal_space != 0)
7249         xg_assemble_literal_space (tinsn->literal_space, slot);
7250       frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg;
7251
7252       if (tinsn->subtype == RELAX_NARROW)
7253         gas_assert (vinsn->num_slots == 1);
7254       if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
7255         is_jump = true;
7256       if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
7257         is_branch = true;
7258
7259       if (tinsn->subtype || tinsn->symbol || tinsn->offset
7260           || tinsn->literal_frag || is_jump || is_branch)
7261         finish_frag = true;
7262     }
7263
7264   if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7265     frag_now->tc_frag_data.is_specific_opcode = true;
7266
7267   if (finish_frag)
7268     {
7269       frag_variant (rs_machine_dependent,
7270                     extra_space, extra_space, RELAX_SLOTS,
7271                     frag_now->fr_symbol, frag_now->fr_offset, f);
7272       xtensa_set_frag_assembly_state (frag_now);
7273     }
7274
7275   /* Special cases for loops:
7276      close_loop_end should be inserted AFTER short_loop.
7277      Make sure that CLOSE loops are processed BEFORE short_loops
7278      when converting them.  */
7279
7280   /* "short_loop": Add a NOP if the loop is < 4 bytes.  */
7281   if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1
7282       && !vinsn->slots[0].is_specific_opcode)
7283     {
7284       if (workaround_short_loop && use_transform ())
7285         {
7286           maybe_has_short_loop = true;
7287           frag_now->tc_frag_data.is_insn = true;
7288           frag_var (rs_machine_dependent, 4, 4,
7289                     RELAX_ADD_NOP_IF_SHORT_LOOP,
7290                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7291           frag_now->tc_frag_data.is_insn = true;
7292           frag_var (rs_machine_dependent, 4, 4,
7293                     RELAX_ADD_NOP_IF_SHORT_LOOP,
7294                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7295         }
7296
7297       /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7298          loop at least 12 bytes away from another loop's end.  */
7299       if (workaround_close_loop_end && use_transform ())
7300         {
7301           maybe_has_close_loop_end = true;
7302           frag_now->tc_frag_data.is_insn = true;
7303           frag_var (rs_machine_dependent, 12, 12,
7304                     RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
7305                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7306         }
7307     }
7308
7309   if (use_transform ())
7310     {
7311       if (is_jump)
7312         {
7313           gas_assert (finish_frag);
7314           frag_var (rs_machine_dependent,
7315                     xtensa_fetch_width, xtensa_fetch_width,
7316                     RELAX_UNREACHABLE,
7317                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7318           xtensa_set_frag_assembly_state (frag_now);
7319           xtensa_maybe_create_trampoline_frag ();
7320           /* Always create one here.  */
7321           xtensa_maybe_create_literal_pool_frag (true, false);
7322         }
7323       else if (is_branch && do_align_targets ())
7324         {
7325           gas_assert (finish_frag);
7326           frag_var (rs_machine_dependent,
7327                     xtensa_fetch_width, xtensa_fetch_width,
7328                     RELAX_MAYBE_UNREACHABLE,
7329                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7330           xtensa_set_frag_assembly_state (frag_now);
7331           frag_var (rs_machine_dependent,
7332                     0, 0,
7333                     RELAX_MAYBE_DESIRE_ALIGN,
7334                     frag_now->fr_symbol, frag_now->fr_offset, NULL);
7335           xtensa_set_frag_assembly_state (frag_now);
7336         }
7337     }
7338
7339   /* Now, if the original opcode was a call...  */
7340   if (do_align_targets ()
7341       && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
7342     {
7343       float freq = get_subseg_total_freq (now_seg, now_subseg);
7344       frag_now->tc_frag_data.is_insn = true;
7345       frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
7346                 frag_now->fr_symbol, frag_now->fr_offset, NULL);
7347       xtensa_set_frag_assembly_state (frag_now);
7348     }
7349
7350   if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
7351     {
7352       frag_wane (frag_now);
7353       frag_new (0);
7354       xtensa_set_frag_assembly_state (frag_now);
7355     }
7356 }
7357
7358 \f
7359 /* xtensa_md_finish and helper functions.  */
7360
7361 static void xtensa_cleanup_align_frags (void);
7362 static void xtensa_fix_target_frags (void);
7363 static void xtensa_mark_narrow_branches (void);
7364 static void xtensa_mark_zcl_first_insns (void);
7365 static void xtensa_mark_difference_of_two_symbols (void);
7366 static void xtensa_fix_a0_b_retw_frags (void);
7367 static void xtensa_fix_b_j_loop_end_frags (void);
7368 static void xtensa_fix_close_loop_end_frags (void);
7369 static void xtensa_fix_short_loop_frags (void);
7370 static void xtensa_sanity_check (void);
7371 static void xtensa_add_config_info (void);
7372
7373 void
7374 xtensa_md_finish (void)
7375 {
7376   directive_balance ();
7377   xtensa_flush_pending_output ();
7378
7379   past_xtensa_md_finish = true;
7380
7381   xtensa_move_literals ();
7382
7383   xtensa_reorder_segments ();
7384   xtensa_cleanup_align_frags ();
7385   xtensa_fix_target_frags ();
7386   if (workaround_a0_b_retw && has_a0_b_retw)
7387     xtensa_fix_a0_b_retw_frags ();
7388   if (workaround_b_j_loop_end)
7389     xtensa_fix_b_j_loop_end_frags ();
7390
7391   /* "close_loop_end" should be processed BEFORE "short_loop".  */
7392   if (workaround_close_loop_end && maybe_has_close_loop_end)
7393     xtensa_fix_close_loop_end_frags ();
7394
7395   if (workaround_short_loop && maybe_has_short_loop)
7396     xtensa_fix_short_loop_frags ();
7397   if (align_targets)
7398     xtensa_mark_narrow_branches ();
7399   xtensa_mark_zcl_first_insns ();
7400
7401   xtensa_sanity_check ();
7402
7403   xtensa_add_config_info ();
7404
7405   xtensa_check_frag_count ();
7406 }
7407
7408 struct trampoline_chain_entry
7409 {
7410   symbolS *sym;
7411   addressT offset;
7412 };
7413
7414 /* Trampoline chain for a given (sym, offset) pair is a sorted array
7415    of locations of trampoline jumps leading there.  Jumps are represented
7416    as pairs (sym, offset): trampoline frag symbol and offset of the jump
7417    inside the frag.  */
7418 struct trampoline_chain
7419 {
7420   struct trampoline_chain_entry target;
7421   struct trampoline_chain_entry *entry;
7422   size_t n_entries;
7423   size_t n_max;
7424   bool needs_sorting;
7425 };
7426
7427 struct trampoline_chain_index
7428 {
7429   struct trampoline_chain *entry;
7430   size_t n_entries;
7431   size_t n_max;
7432   bool needs_sorting;
7433 };
7434
7435 struct trampoline_index
7436 {
7437   fragS **entry;
7438   size_t n_entries;
7439   size_t n_max;
7440 };
7441
7442 struct trampoline_seg
7443 {
7444   struct trampoline_seg *next;
7445   asection *seg;
7446   /* Trampolines ordered by their frag fr_address */
7447   struct trampoline_index index;
7448   /* Known trampoline chains ordered by (sym, offset) pair */
7449   struct trampoline_chain_index chain_index;
7450 };
7451
7452 static struct trampoline_seg trampoline_seg_list;
7453 #define J_RANGE (128 * 1024)
7454 #define J_MARGIN 4096
7455
7456 static int unreachable_count = 0;
7457
7458
7459 static void
7460 xtensa_maybe_create_trampoline_frag (void)
7461 {
7462   if (!use_trampolines)
7463     return;
7464
7465   /* We create an area for possible trampolines every 10 unreachable frags.
7466      These are preferred over the ones not preceded by an unreachable frag,
7467      because we don't have to jump around them. This function is called after
7468      each RELAX_UNREACHABLE frag is created.  */
7469
7470   if (++unreachable_count > 10)
7471     {
7472       xtensa_create_trampoline_frag (false);
7473       clear_frag_count ();
7474       unreachable_count = 0;
7475     }
7476 }
7477
7478 static void
7479 xtensa_check_frag_count (void)
7480 {
7481   if (!use_trampolines || frag_now->tc_frag_data.is_no_transform)
7482     return;
7483
7484   /* We create an area for possible trampolines every 8000 frags or so. This
7485      is an estimate based on the max range of a "j" insn (+/-128K) divided
7486      by a typical frag byte count (16), minus a few for safety. This function
7487      is called after each source line is processed.  */
7488
7489   if (get_frag_count () > 8000)
7490     {
7491       xtensa_create_trampoline_frag (true);
7492       clear_frag_count ();
7493       unreachable_count = 0;
7494     }
7495
7496   /* We create an area for a possible literal pool every N (default 5000)
7497      frags or so.  */
7498   xtensa_maybe_create_literal_pool_frag (true, true);
7499 }
7500
7501 static xtensa_insnbuf trampoline_buf = NULL;
7502 static xtensa_insnbuf trampoline_slotbuf = NULL;
7503
7504 static xtensa_insnbuf litpool_buf = NULL;
7505 static xtensa_insnbuf litpool_slotbuf = NULL;
7506
7507 #define TRAMPOLINE_FRAG_SIZE 3000
7508
7509 static struct trampoline_seg *
7510 find_trampoline_seg (asection *seg)
7511 {
7512   struct trampoline_seg *ts = trampoline_seg_list.next;
7513   static struct trampoline_seg *mr;
7514
7515   if (mr && mr->seg == seg)
7516     return mr;
7517
7518   for ( ; ts; ts = ts->next)
7519     {
7520       if (ts->seg == seg)
7521         {
7522           mr = ts;
7523           return ts;
7524         }
7525     }
7526
7527   return NULL;
7528 }
7529
7530 static size_t xg_find_trampoline (const struct trampoline_index *idx,
7531                                   addressT addr)
7532 {
7533   size_t a = 0;
7534   size_t b = idx->n_entries;
7535
7536   while (b - a > 1)
7537     {
7538       size_t c = (a + b) / 2;
7539
7540       if (idx->entry[c]->fr_address <= addr)
7541         a = c;
7542       else
7543         b = c;
7544     }
7545   return a;
7546 }
7547
7548 static void xg_add_trampoline_to_index (struct trampoline_index *idx,
7549                                         fragS *fragP)
7550 {
7551   if (idx->n_entries == idx->n_max)
7552     {
7553       idx->n_max = (idx->n_entries + 1) * 2;
7554       idx->entry = xrealloc (idx->entry,
7555                              sizeof (*idx->entry) * idx->n_max);
7556     }
7557   idx->entry[idx->n_entries] = fragP;
7558   ++idx->n_entries;
7559 }
7560
7561 static void xg_remove_trampoline_from_index (struct trampoline_index *idx,
7562                                              size_t i)
7563 {
7564   gas_assert (i < idx->n_entries);
7565   memmove (idx->entry + i, idx->entry + i + 1,
7566            (idx->n_entries - i - 1) * sizeof (*idx->entry));
7567   --idx->n_entries;
7568 }
7569
7570 static void xg_add_trampoline_to_seg (struct trampoline_seg *ts,
7571                                       fragS *fragP)
7572 {
7573   xg_add_trampoline_to_index (&ts->index, fragP);
7574 }
7575
7576 static void
7577 xtensa_create_trampoline_frag (bool needs_jump_around)
7578 {
7579   /* Emit a frag where we can place intermediate jump instructions,
7580      in case we need to jump farther than 128K bytes.
7581      Each jump instruction takes three bytes.
7582      We allocate enough for 1000 trampolines in each frag.
7583      If that's not enough, oh well.  */
7584
7585   struct trampoline_seg *ts = find_trampoline_seg (now_seg);
7586   char *varP;
7587   fragS *fragP;
7588   int size = TRAMPOLINE_FRAG_SIZE;
7589
7590   if (ts == NULL)
7591     {
7592       ts = XCNEW(struct trampoline_seg);
7593       ts->next = trampoline_seg_list.next;
7594       trampoline_seg_list.next = ts;
7595       ts->seg = now_seg;
7596     }
7597
7598   frag_wane (frag_now);
7599   frag_new (0);
7600   xtensa_set_frag_assembly_state (frag_now);
7601   varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL);
7602   fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG);
7603   if (trampoline_buf == NULL)
7604     {
7605       trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa);
7606       trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
7607     }
7608   fragP->tc_frag_data.needs_jump_around = needs_jump_around;
7609   xg_add_trampoline_to_seg (ts, fragP);
7610 }
7611
7612 static bool xg_is_trampoline_frag_full (const fragS *fragP)
7613 {
7614   return fragP->fr_var < 3;
7615 }
7616
7617 static int xg_order_trampoline_chain_entry (const void *a, const void *b)
7618 {
7619   const struct trampoline_chain_entry *pa = a;
7620   const struct trampoline_chain_entry *pb = b;
7621
7622   if (pa->sym != pb->sym)
7623     {
7624       valueT aval = S_GET_VALUE (pa->sym);
7625       valueT bval = S_GET_VALUE (pb->sym);
7626
7627       if (aval != bval)
7628         return aval < bval ? -1 : 1;
7629     }
7630   if (pa->offset != pb->offset)
7631     return pa->offset < pb->offset ? -1 : 1;
7632   return 0;
7633 }
7634
7635 static void xg_sort_trampoline_chain (struct trampoline_chain *tc)
7636 {
7637   qsort (tc->entry, tc->n_entries, sizeof (*tc->entry),
7638          xg_order_trampoline_chain_entry);
7639   tc->needs_sorting = false;
7640 }
7641
7642 /* Find entry index in the given chain with maximal address <= source.  */
7643 static size_t xg_find_chain_entry (struct trampoline_chain *tc,
7644                                    addressT source)
7645 {
7646   size_t a = 0;
7647   size_t b = tc->n_entries;
7648
7649   if (tc->needs_sorting)
7650     xg_sort_trampoline_chain (tc);
7651
7652   while (b - a > 1)
7653     {
7654       size_t c = (a + b) / 2;
7655       struct trampoline_chain_entry *e = tc->entry + c;
7656
7657       if (S_GET_VALUE(e->sym) + e->offset <= source)
7658         a = c;
7659       else
7660         b = c;
7661     }
7662   return a;
7663 }
7664
7665 /* Find the best jump target for the source in the given trampoline chain.
7666    The best jump target is the one that results in the shortest path to the
7667    final target, it's the location of the jump closest to the final target,
7668    but within the J_RANGE - J_MARGIN from the source.  */
7669 static struct trampoline_chain_entry *
7670 xg_get_best_chain_entry (struct trampoline_chain *tc, addressT source)
7671 {
7672   addressT target = S_GET_VALUE(tc->target.sym) + tc->target.offset;
7673   size_t i = xg_find_chain_entry (tc, source);
7674   struct trampoline_chain_entry *e = tc->entry + i;
7675   int step = target < source ? -1 : 1;
7676   addressT chained_target;
7677   offsetT off;
7678
7679   if (target > source &&
7680       S_GET_VALUE(e->sym) + e->offset <= source &&
7681       i + 1 < tc->n_entries)
7682     ++i;
7683
7684   while (i + step < tc->n_entries)
7685     {
7686       struct trampoline_chain_entry *next = tc->entry + i + step;
7687
7688       chained_target = S_GET_VALUE(next->sym) + next->offset;
7689       off = source - chained_target;
7690
7691       if (labs (off) >= J_RANGE - J_MARGIN)
7692         break;
7693
7694       i += step;
7695     }
7696
7697   e = tc->entry + i;
7698   chained_target = S_GET_VALUE(e->sym) + e->offset;
7699   off = source - chained_target;
7700
7701   if (labs (off) < J_MARGIN ||
7702       labs (off) >= J_RANGE - J_MARGIN)
7703     return &tc->target;
7704   return tc->entry + i;
7705 }
7706
7707 static int xg_order_trampoline_chain (const void *a, const void *b)
7708 {
7709   const struct trampoline_chain *_pa = a;
7710   const struct trampoline_chain *_pb = b;
7711   const struct trampoline_chain_entry *pa = &_pa->target;
7712   const struct trampoline_chain_entry *pb = &_pb->target;
7713   symbolS *s1 = pa->sym;
7714   symbolS *s2 = pb->sym;
7715
7716   if (s1 != s2)
7717     {
7718       symbolS *tmp = symbol_symbolS (s1);
7719       if (tmp)
7720         s1 = tmp;
7721
7722       tmp = symbol_symbolS (s2);
7723       if (tmp)
7724         s2 = tmp;
7725
7726       if (s1 != s2)
7727         return s1 < s2 ? -1 : 1;
7728     }
7729
7730   if (pa->offset != pb->offset)
7731     return pa->offset < pb->offset ? -1 : 1;
7732   return 0;
7733 }
7734
7735 static struct trampoline_chain *
7736 xg_get_trampoline_chain (struct trampoline_seg *ts,
7737                          symbolS *sym,
7738                          addressT offset)
7739 {
7740   struct trampoline_chain_index *idx = &ts->chain_index;
7741   struct trampoline_chain c;
7742
7743   if (idx->n_entries == 0)
7744     return NULL;
7745
7746   if (idx->needs_sorting)
7747     {
7748       qsort (idx->entry, idx->n_entries, sizeof (*idx->entry),
7749              xg_order_trampoline_chain);
7750       idx->needs_sorting = false;
7751     }
7752   c.target.sym = sym;
7753   c.target.offset = offset;
7754   return bsearch (&c, idx->entry, idx->n_entries,
7755                   sizeof (struct trampoline_chain),
7756                   xg_order_trampoline_chain);
7757 }
7758
7759 /* Find trampoline chain in the given trampoline segment that is going
7760    to the *sym + *offset.  If found, replace *sym and *offset with the
7761    best jump target in that chain.  */
7762 static struct trampoline_chain *
7763 xg_find_best_eq_target (struct trampoline_seg *ts,
7764                         addressT source, symbolS **sym,
7765                         addressT *offset)
7766 {
7767   struct trampoline_chain *tc = xg_get_trampoline_chain (ts, *sym, *offset);
7768
7769   if (tc)
7770     {
7771       struct trampoline_chain_entry *e = xg_get_best_chain_entry (tc, source);
7772
7773       *sym = e->sym;
7774       *offset = e->offset;
7775     }
7776   return tc;
7777 }
7778
7779 static void xg_add_location_to_chain (struct trampoline_chain *tc,
7780                                       symbolS *sym, addressT offset)
7781 {
7782   struct trampoline_chain_entry *e;
7783
7784   if (tc->n_entries == tc->n_max)
7785     {
7786       tc->n_max = (tc->n_max + 1) * 2;
7787       tc->entry = xrealloc (tc->entry, sizeof (*tc->entry) * tc->n_max);
7788     }
7789   e = tc->entry + tc->n_entries;
7790   e->sym = sym;
7791   e->offset = offset;
7792   ++tc->n_entries;
7793   tc->needs_sorting = true;
7794 }
7795
7796 static struct trampoline_chain *
7797 xg_create_trampoline_chain (struct trampoline_seg *ts,
7798                             symbolS *sym, addressT offset)
7799 {
7800   struct trampoline_chain_index *idx = &ts->chain_index;
7801   struct trampoline_chain *tc;
7802
7803   if (idx->n_entries == idx->n_max)
7804     {
7805       idx->n_max = (idx->n_max + 1) * 2;
7806       idx->entry = xrealloc (idx->entry,
7807                              sizeof (*idx->entry) * idx->n_max);
7808     }
7809
7810   tc = idx->entry + idx->n_entries;
7811   tc->target.sym = sym;
7812   tc->target.offset = offset;
7813   tc->entry = NULL;
7814   tc->n_entries = 0;
7815   tc->n_max = 0;
7816   xg_add_location_to_chain (tc, sym, offset);
7817
7818   ++idx->n_entries;
7819   idx->needs_sorting = true;
7820
7821   return tc;
7822 }
7823
7824 void dump_trampolines (void);
7825
7826 void
7827 dump_trampolines (void)
7828 {
7829   struct trampoline_seg *ts = trampoline_seg_list.next;
7830
7831   for ( ; ts; ts = ts->next)
7832     {
7833       size_t i;
7834       asection *seg = ts->seg;
7835
7836       if (seg == NULL)
7837         continue;
7838       fprintf(stderr, "SECTION %s\n", seg->name);
7839
7840       for (i = 0; i < ts->index.n_entries; ++i)
7841         {
7842           fragS *tf = ts->index.entry[i];
7843
7844           fprintf(stderr, "   0x%08x: fix=%d, jump_around=%s\n",
7845                   (int)tf->fr_address, (int)tf->fr_fix,
7846                   tf->tc_frag_data.needs_jump_around ? "T" : "F");
7847         }
7848     }
7849 }
7850
7851 static void dump_litpools (void) __attribute__ ((unused));
7852
7853 static void
7854 dump_litpools (void)
7855 {
7856   struct litpool_seg *lps = litpool_seg_list.next;
7857   struct litpool_frag *lpf;
7858
7859   for ( ; lps ; lps = lps->next )
7860     {
7861       printf("litpool seg %s\n", lps->seg->name);
7862       for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next )
7863         {
7864           fragS *litfrag = lpf->fragP->fr_next;
7865           int count = 0;
7866           while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END)
7867             {
7868               if (litfrag->fr_fix == 4)
7869                 count++;
7870               litfrag = litfrag->fr_next;
7871             }
7872           printf("   %" PRId64 " <%d:%d> (%d) [%d]: ",
7873                  (int64_t) lpf->addr,
7874                  lpf->priority, lpf->original_priority,
7875                  lpf->fragP->fr_line, count);
7876           /* dump_frag(lpf->fragP);  */
7877         }
7878     }
7879 }
7880
7881 static void
7882 xtensa_maybe_create_literal_pool_frag (bool create, bool only_if_needed)
7883 {
7884   struct litpool_seg *lps = litpool_seg_list.next;
7885   fragS *fragP;
7886   struct litpool_frag *lpf;
7887   bool needed = false;
7888
7889   if (use_literal_section || !auto_litpools)
7890     return;
7891
7892   for ( ; lps ; lps = lps->next )
7893     {
7894       if (lps->seg == now_seg)
7895         break;
7896     }
7897
7898   if (lps == NULL)
7899     {
7900       lps = XCNEW (struct litpool_seg);
7901       lps->next = litpool_seg_list.next;
7902       litpool_seg_list.next = lps;
7903       lps->seg = now_seg;
7904       lps->frag_list.next = &lps->frag_list;
7905       lps->frag_list.prev = &lps->frag_list;
7906       /* Put candidate literal pool at the beginning of every section,
7907          so that even when section starts with literal load there's a
7908          literal pool available.  */
7909       lps->frag_count = auto_litpool_limit;
7910     }
7911
7912   lps->frag_count++;
7913
7914   if (create)
7915     {
7916       if (only_if_needed)
7917         {
7918           if (past_xtensa_md_finish || !use_transform() ||
7919               frag_now->tc_frag_data.is_no_transform)
7920             {
7921               return;
7922             }
7923           if (auto_litpool_limit <= 0)
7924             {
7925               /* Don't create a litpool based only on frag count.  */
7926               return;
7927             }
7928           else if (lps->frag_count > auto_litpool_limit)
7929             {
7930               needed = true;
7931             }
7932           else
7933             {
7934               return;
7935             }
7936         }
7937       else
7938         {
7939           needed = true;
7940         }
7941     }
7942
7943   if (needed)
7944     {
7945       int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn.  */
7946       /* Create a potential site for a literal pool.  */
7947       frag_wane (frag_now);
7948       frag_new (0);
7949       xtensa_set_frag_assembly_state (frag_now);
7950       fragP = frag_now;
7951       fragP->tc_frag_data.lit_frchain = frchain_now;
7952       fragP->tc_frag_data.literal_frag = fragP;
7953       frag_var (rs_machine_dependent, size, size,
7954                     (only_if_needed) ?
7955                         RELAX_LITERAL_POOL_CANDIDATE_BEGIN :
7956                         RELAX_LITERAL_POOL_BEGIN,
7957                     NULL, 0, NULL);
7958       frag_now->tc_frag_data.lit_seg = now_seg;
7959       frag_variant (rs_machine_dependent, 0, 0,
7960                     RELAX_LITERAL_POOL_END, NULL, 0, NULL);
7961       xtensa_set_frag_assembly_state (frag_now);
7962     }
7963   else
7964     {
7965       /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7966          just record it here.  */
7967       fragP = frag_now;
7968     }
7969
7970   lpf = XNEW (struct litpool_frag);
7971   /* Insert at tail of circular list.  */
7972   lpf->addr = 0;
7973   lps->frag_list.prev->next = lpf;
7974   lpf->next = &lps->frag_list;
7975   lpf->prev = lps->frag_list.prev;
7976   lps->frag_list.prev = lpf;
7977   lpf->fragP = fragP;
7978   lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1;
7979   lpf->original_priority = lpf->priority;
7980   lpf->literal_count = 0;
7981
7982   lps->frag_count = 0;
7983 }
7984
7985 static void
7986 xtensa_cleanup_align_frags (void)
7987 {
7988   frchainS *frchP;
7989   asection *s;
7990
7991   for (s = stdoutput->sections; s; s = s->next)
7992     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
7993       {
7994         fragS *fragP;
7995         /* Walk over all of the fragments in a subsection.  */
7996         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
7997           {
7998             if ((fragP->fr_type == rs_align
7999                  || fragP->fr_type == rs_align_code
8000                  || (fragP->fr_type == rs_machine_dependent
8001                      && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
8002                          || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
8003                 && fragP->fr_fix == 0)
8004               {
8005                 fragS *next = fragP->fr_next;
8006
8007                 while (next
8008                        && next->fr_fix == 0
8009                        && next->fr_type == rs_machine_dependent
8010                        && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
8011                   {
8012                     frag_wane (next);
8013                     next = next->fr_next;
8014                   }
8015               }
8016             /* If we don't widen branch targets, then they
8017                will be easier to align.  */
8018             if (fragP->tc_frag_data.is_branch_target
8019                 && fragP->fr_opcode == fragP->fr_literal
8020                 && fragP->fr_type == rs_machine_dependent
8021                 && fragP->fr_subtype == RELAX_SLOTS
8022                 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
8023               frag_wane (fragP);
8024             if (fragP->fr_type == rs_machine_dependent
8025                 && fragP->fr_subtype == RELAX_UNREACHABLE)
8026               fragP->tc_frag_data.is_unreachable = true;
8027           }
8028       }
8029 }
8030
8031
8032 /* Re-process all of the fragments looking to convert all of the
8033    RELAX_DESIRE_ALIGN_IF_TARGET fragments.  If there is a branch
8034    target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
8035    Otherwise, convert to a .fill 0.  */
8036
8037 static void
8038 xtensa_fix_target_frags (void)
8039 {
8040   frchainS *frchP;
8041   asection *s;
8042
8043   /* When this routine is called, all of the subsections are still intact
8044      so we walk over subsections instead of sections.  */
8045   for (s = stdoutput->sections; s; s = s->next)
8046     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8047       {
8048         fragS *fragP;
8049
8050         /* Walk over all of the fragments in a subsection.  */
8051         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8052           {
8053             if (fragP->fr_type == rs_machine_dependent
8054                 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
8055               {
8056                 if (next_frag_is_branch_target (fragP))
8057                   fragP->fr_subtype = RELAX_DESIRE_ALIGN;
8058                 else
8059                   frag_wane (fragP);
8060               }
8061           }
8062       }
8063 }
8064
8065
8066 static bool is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
8067
8068 static void
8069 xtensa_mark_narrow_branches (void)
8070 {
8071   frchainS *frchP;
8072   asection *s;
8073
8074   for (s = stdoutput->sections; s; s = s->next)
8075     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8076       {
8077         fragS *fragP;
8078         /* Walk over all of the fragments in a subsection.  */
8079         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8080           {
8081             if (fragP->fr_type == rs_machine_dependent
8082                 && fragP->fr_subtype == RELAX_SLOTS
8083                 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
8084               {
8085                 vliw_insn vinsn;
8086
8087                 vinsn_from_chars (&vinsn, fragP->fr_opcode);
8088                 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
8089
8090                 if (vinsn.num_slots == 1
8091                     && xtensa_opcode_is_branch (xtensa_default_isa,
8092                                                 vinsn.slots[0].opcode) == 1
8093                     && xg_get_single_size (vinsn.slots[0].opcode) == 2
8094                     && is_narrow_branch_guaranteed_in_range (fragP,
8095                                                              &vinsn.slots[0]))
8096                   {
8097                     fragP->fr_subtype = RELAX_SLOTS;
8098                     fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
8099                     fragP->tc_frag_data.is_aligning_branch = 1;
8100                   }
8101               }
8102           }
8103       }
8104 }
8105
8106
8107 /* A branch is typically widened only when its target is out of
8108    range.  However, we would like to widen them to align a subsequent
8109    branch target when possible.
8110
8111    Because the branch relaxation code is so convoluted, the optimal solution
8112    (combining the two cases) is difficult to get right in all circumstances.
8113    We therefore go with an "almost as good" solution, where we only
8114    use for alignment narrow branches that definitely will not expand to a
8115    jump and a branch.  These functions find and mark these cases.  */
8116
8117 /* The range in bytes of BNEZ.N and BEQZ.N.  The target operand is encoded
8118    as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
8119    We start counting beginning with the frag after the 2-byte branch, so the
8120    maximum offset is (4 - 2) + 63 = 65.  */
8121 #define MAX_IMMED6 65
8122
8123 static offsetT unrelaxed_frag_max_size (fragS *);
8124
8125 static bool
8126 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
8127 {
8128   const expressionS *exp = &tinsn->tok[1];
8129   symbolS *symbolP = exp->X_add_symbol;
8130   offsetT max_distance = exp->X_add_number;
8131   fragS *target_frag;
8132
8133   if (exp->X_op != O_symbol)
8134     return false;
8135
8136   target_frag = symbol_get_frag (symbolP);
8137
8138   max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
8139   if (is_branch_jmp_to_next (tinsn, fragP))
8140     return false;
8141
8142   /* The branch doesn't branch over it's own frag,
8143      but over the subsequent ones.  */
8144   fragP = fragP->fr_next;
8145   while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
8146     {
8147       max_distance += unrelaxed_frag_max_size (fragP);
8148       fragP = fragP->fr_next;
8149     }
8150   if (max_distance <= MAX_IMMED6 && fragP == target_frag)
8151     return true;
8152   return false;
8153 }
8154
8155
8156 static void
8157 xtensa_mark_zcl_first_insns (void)
8158 {
8159   frchainS *frchP;
8160   asection *s;
8161
8162   for (s = stdoutput->sections; s; s = s->next)
8163     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8164       {
8165         fragS *fragP;
8166         /* Walk over all of the fragments in a subsection.  */
8167         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8168           {
8169             if (fragP->fr_type == rs_machine_dependent
8170                 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
8171                     || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
8172               {
8173                 /* Find the loop frag.  */
8174                 fragS *loop_frag = next_non_empty_frag (fragP);
8175                 /* Find the first insn frag.  */
8176                 fragS *targ_frag = next_non_empty_frag (loop_frag);
8177
8178               /* Handle a corner case that comes up in hardware
8179                  diagnostics.  The original assembly looks like this:
8180
8181                  loop aX, LabelA
8182                  <empty_frag>--not found by next_non_empty_frag
8183                  loop aY, LabelB
8184
8185                  Depending on the start address, the assembler may or
8186                  may not change it to look something like this:
8187
8188                  loop aX, LabelA
8189                  nop--frag isn't empty anymore
8190                  loop aY, LabelB
8191
8192                  So set up to check the alignment of the nop if it
8193                  exists  */
8194                 while (loop_frag != targ_frag)
8195                   {
8196                     if (loop_frag->fr_type == rs_machine_dependent
8197                         && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
8198                             || loop_frag->fr_subtype
8199                             == RELAX_CHECK_ALIGN_NEXT_OPCODE))
8200                       targ_frag = loop_frag;
8201                     else
8202                       loop_frag = loop_frag->fr_next;
8203                   }
8204
8205                 /* Of course, sometimes (mostly for toy test cases) a
8206                    zero-cost loop instruction is the last in a section.  */
8207                 if (targ_frag)
8208                   {
8209                     targ_frag->tc_frag_data.is_first_loop_insn = true;
8210                     /* Do not widen a frag that is the first instruction of a
8211                        zero-cost loop.  It makes that loop harder to align.  */
8212                     if (targ_frag->fr_type == rs_machine_dependent
8213                         && targ_frag->fr_subtype == RELAX_SLOTS
8214                         && (targ_frag->tc_frag_data.slot_subtypes[0]
8215                             == RELAX_NARROW))
8216                       {
8217                         if (targ_frag->tc_frag_data.is_aligning_branch)
8218                           targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
8219                         else
8220                           {
8221                             frag_wane (targ_frag);
8222                             targ_frag->tc_frag_data.slot_subtypes[0] = 0;
8223                           }
8224                       }
8225                   }
8226                 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
8227                   frag_wane (fragP);
8228               }
8229           }
8230       }
8231 }
8232
8233
8234 /* When a difference-of-symbols expression is encoded as a uleb128 or
8235    sleb128 value, the linker is unable to adjust that value to account for
8236    link-time relaxation.  Mark all the code between such symbols so that
8237    its size cannot be changed by linker relaxation.  */
8238
8239 static void
8240 xtensa_mark_difference_of_two_symbols (void)
8241 {
8242   symbolS *expr_sym;
8243
8244   for (expr_sym = expr_symbols; expr_sym;
8245        expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol)
8246     {
8247       expressionS *exp = symbol_get_value_expression (expr_sym);
8248
8249       if (exp->X_op == O_subtract)
8250         {
8251           symbolS *left = exp->X_add_symbol;
8252           symbolS *right = exp->X_op_symbol;
8253
8254           /* Difference of two symbols not in the same section
8255              are handled with relocations in the linker.  */
8256           if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right))
8257             {
8258               fragS *start;
8259               fragS *end;
8260               fragS *walk;
8261
8262               if (symbol_get_frag (left)->fr_address
8263                   <= symbol_get_frag (right)->fr_address)
8264                 {
8265                   start = symbol_get_frag (left);
8266                   end = symbol_get_frag (right);
8267                 }
8268               else
8269                 {
8270                   start = symbol_get_frag (right);
8271                   end = symbol_get_frag (left);
8272                 }
8273
8274               if (start->tc_frag_data.no_transform_end != NULL)
8275                 walk = start->tc_frag_data.no_transform_end;
8276               else
8277                 walk = start;
8278               do
8279                 {
8280                   walk->tc_frag_data.is_no_transform = 1;
8281                   walk = walk->fr_next;
8282                 }
8283               while (walk && walk->fr_address < end->fr_address);
8284
8285               start->tc_frag_data.no_transform_end = walk;
8286             }
8287         }
8288     }
8289 }
8290
8291
8292 /* Re-process all of the fragments looking to convert all of the
8293    RELAX_ADD_NOP_IF_A0_B_RETW.  If the next instruction is a
8294    conditional branch or a retw/retw.n, convert this frag to one that
8295    will generate a NOP.  In any case close it off with a .fill 0.  */
8296
8297 static bool next_instrs_are_b_retw (fragS *);
8298
8299 static void
8300 xtensa_fix_a0_b_retw_frags (void)
8301 {
8302   frchainS *frchP;
8303   asection *s;
8304
8305   /* When this routine is called, all of the subsections are still intact
8306      so we walk over subsections instead of sections.  */
8307   for (s = stdoutput->sections; s; s = s->next)
8308     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8309       {
8310         fragS *fragP;
8311
8312         /* Walk over all of the fragments in a subsection.  */
8313         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8314           {
8315             if (fragP->fr_type == rs_machine_dependent
8316                 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
8317               {
8318                 if (next_instrs_are_b_retw (fragP))
8319                   {
8320                     if (fragP->tc_frag_data.is_no_transform)
8321                       as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
8322                     else
8323                       relax_frag_add_nop (fragP);
8324                   }
8325                 frag_wane (fragP);
8326               }
8327           }
8328       }
8329 }
8330
8331
8332 static bool
8333 next_instrs_are_b_retw (fragS *fragP)
8334 {
8335   xtensa_opcode opcode;
8336   xtensa_format fmt;
8337   const fragS *next_fragP = next_non_empty_frag (fragP);
8338   static xtensa_insnbuf insnbuf = NULL;
8339   static xtensa_insnbuf slotbuf = NULL;
8340   xtensa_isa isa = xtensa_default_isa;
8341   unsigned int offset = 0;
8342   int slot;
8343   bool branch_seen = false;
8344
8345   if (!insnbuf)
8346     {
8347       insnbuf = xtensa_insnbuf_alloc (isa);
8348       slotbuf = xtensa_insnbuf_alloc (isa);
8349     }
8350
8351   if (next_fragP == NULL)
8352     return false;
8353
8354   /* Check for the conditional branch.  */
8355   xtensa_insnbuf_from_chars
8356     (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
8357   fmt = xtensa_format_decode (isa, insnbuf);
8358   if (fmt == XTENSA_UNDEFINED)
8359     return false;
8360
8361   for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8362     {
8363       xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
8364       opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
8365
8366       branch_seen = (branch_seen
8367                      || xtensa_opcode_is_branch (isa, opcode) == 1);
8368     }
8369
8370   if (!branch_seen)
8371     return false;
8372
8373   offset += xtensa_format_length (isa, fmt);
8374   if (offset == next_fragP->fr_fix)
8375     {
8376       next_fragP = next_non_empty_frag (next_fragP);
8377       offset = 0;
8378     }
8379
8380   if (next_fragP == NULL)
8381     return false;
8382
8383   /* Check for the retw/retw.n.  */
8384   xtensa_insnbuf_from_chars
8385     (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
8386   fmt = xtensa_format_decode (isa, insnbuf);
8387
8388   /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8389      have no problems.  */
8390   if (fmt == XTENSA_UNDEFINED
8391       || xtensa_format_num_slots (isa, fmt) != 1)
8392     return false;
8393
8394   xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
8395   opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
8396
8397   if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
8398     return true;
8399
8400   return false;
8401 }
8402
8403
8404 /* Re-process all of the fragments looking to convert all of the
8405    RELAX_ADD_NOP_IF_PRE_LOOP_END.  If there is one instruction and a
8406    loop end label, convert this frag to one that will generate a NOP.
8407    In any case close it off with a .fill 0.  */
8408
8409 static bool next_instr_is_loop_end (fragS *);
8410
8411 static void
8412 xtensa_fix_b_j_loop_end_frags (void)
8413 {
8414   frchainS *frchP;
8415   asection *s;
8416
8417   /* When this routine is called, all of the subsections are still intact
8418      so we walk over subsections instead of sections.  */
8419   for (s = stdoutput->sections; s; s = s->next)
8420     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8421       {
8422         fragS *fragP;
8423
8424         /* Walk over all of the fragments in a subsection.  */
8425         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8426           {
8427             if (fragP->fr_type == rs_machine_dependent
8428                 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
8429               {
8430                 if (next_instr_is_loop_end (fragP))
8431                   {
8432                     if (fragP->tc_frag_data.is_no_transform)
8433                       as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8434                     else
8435                       relax_frag_add_nop (fragP);
8436                   }
8437                 frag_wane (fragP);
8438               }
8439           }
8440       }
8441 }
8442
8443
8444 static bool
8445 next_instr_is_loop_end (fragS *fragP)
8446 {
8447   const fragS *next_fragP;
8448
8449   if (next_frag_is_loop_target (fragP))
8450     return false;
8451
8452   next_fragP = next_non_empty_frag (fragP);
8453   if (next_fragP == NULL)
8454     return false;
8455
8456   if (!next_frag_is_loop_target (next_fragP))
8457     return false;
8458
8459   /* If the size is >= 3 then there is more than one instruction here.
8460      The hardware bug will not fire.  */
8461   if (next_fragP->fr_fix > 3)
8462     return false;
8463
8464   return true;
8465 }
8466
8467
8468 /* Re-process all of the fragments looking to convert all of the
8469    RELAX_ADD_NOP_IF_CLOSE_LOOP_END.  If there is an loop end that is
8470    not MY loop's loop end within 12 bytes, add enough nops here to
8471    make it at least 12 bytes away.  In any case close it off with a
8472    .fill 0.  */
8473
8474 static offsetT min_bytes_to_other_loop_end
8475   (fragS *, fragS *, offsetT);
8476
8477 static void
8478 xtensa_fix_close_loop_end_frags (void)
8479 {
8480   frchainS *frchP;
8481   asection *s;
8482
8483   /* When this routine is called, all of the subsections are still intact
8484      so we walk over subsections instead of sections.  */
8485   for (s = stdoutput->sections; s; s = s->next)
8486     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8487       {
8488         fragS *fragP;
8489
8490         fragS *current_target = NULL;
8491
8492         /* Walk over all of the fragments in a subsection.  */
8493         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8494           {
8495             if (fragP->fr_type == rs_machine_dependent
8496                 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
8497                     || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
8498               current_target = symbol_get_frag (fragP->fr_symbol);
8499
8500             if (current_target
8501                 && fragP->fr_type == rs_machine_dependent
8502                 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
8503               {
8504                 offsetT min_bytes;
8505                 int bytes_added = 0;
8506
8507 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8508                 /* Max out at 12.  */
8509                 min_bytes = min_bytes_to_other_loop_end
8510                   (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES);
8511
8512                 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
8513                   {
8514                     if (fragP->tc_frag_data.is_no_transform)
8515                       as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8516                     else
8517                       {
8518                         while (min_bytes + bytes_added
8519                                < REQUIRED_LOOP_DIVIDING_BYTES)
8520                           {
8521                             int length = 3;
8522
8523                             if (fragP->fr_var < length)
8524                               as_fatal (_("fr_var %lu < length %d"),
8525                                         (long) fragP->fr_var, length);
8526                             else
8527                               {
8528                                 assemble_nop (length,
8529                                               fragP->fr_literal + fragP->fr_fix);
8530                                 fragP->fr_fix += length;
8531                                 fragP->fr_var -= length;
8532                               }
8533                             bytes_added += length;
8534                           }
8535                       }
8536                   }
8537                 frag_wane (fragP);
8538               }
8539             gas_assert (fragP->fr_type != rs_machine_dependent
8540                     || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
8541           }
8542       }
8543 }
8544
8545
8546 static offsetT unrelaxed_frag_min_size (fragS *);
8547
8548 static offsetT
8549 min_bytes_to_other_loop_end (fragS *fragP,
8550                              fragS *current_target,
8551                              offsetT max_size)
8552 {
8553   offsetT offset = 0;
8554   fragS *current_fragP;
8555
8556   for (current_fragP = fragP;
8557        current_fragP;
8558        current_fragP = current_fragP->fr_next)
8559     {
8560       if (current_fragP->tc_frag_data.is_loop_target
8561           && current_fragP != current_target)
8562         return offset;
8563
8564       offset += unrelaxed_frag_min_size (current_fragP);
8565
8566       if (offset >= max_size)
8567         return max_size;
8568     }
8569   return max_size;
8570 }
8571
8572
8573 static offsetT
8574 unrelaxed_frag_min_size (fragS *fragP)
8575 {
8576   offsetT size = fragP->fr_fix;
8577
8578   /* Add fill size.  */
8579   if (fragP->fr_type == rs_fill)
8580     size += fragP->fr_offset;
8581
8582   return size;
8583 }
8584
8585
8586 static offsetT
8587 unrelaxed_frag_max_size (fragS *fragP)
8588 {
8589   offsetT size = fragP->fr_fix;
8590   switch (fragP->fr_type)
8591     {
8592     case 0:
8593       /* Empty frags created by the obstack allocation scheme
8594          end up with type 0.  */
8595       break;
8596     case rs_fill:
8597     case rs_org:
8598     case rs_space:
8599       size += fragP->fr_offset;
8600       break;
8601     case rs_align:
8602     case rs_align_code:
8603     case rs_align_test:
8604     case rs_leb128:
8605     case rs_cfa:
8606     case rs_dwarf2dbg:
8607     case rs_sframe:
8608       /* No further adjustments needed.  */
8609       break;
8610     case rs_machine_dependent:
8611       if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
8612         size += fragP->fr_var;
8613       break;
8614     default:
8615       /* We had darn well better know how big it is.  */
8616       gas_assert (0);
8617       break;
8618     }
8619
8620   return size;
8621 }
8622
8623
8624 /* Re-process all of the fragments looking to convert all
8625    of the RELAX_ADD_NOP_IF_SHORT_LOOP.  If:
8626
8627    A)
8628      1) the instruction size count to the loop end label
8629         is too short (<= 2 instructions),
8630      2) loop has a jump or branch in it
8631
8632    or B)
8633      1) workaround_all_short_loops is TRUE
8634      2) The generating loop was a  'loopgtz' or 'loopnez'
8635      3) the instruction size count to the loop end label is too short
8636         (<= 2 instructions)
8637    then convert this frag (and maybe the next one) to generate a NOP.
8638    In any case close it off with a .fill 0.  */
8639
8640 static int count_insns_to_loop_end (fragS *, bool, int);
8641 static bool branch_before_loop_end (fragS *);
8642
8643 static void
8644 xtensa_fix_short_loop_frags (void)
8645 {
8646   frchainS *frchP;
8647   asection *s;
8648
8649   /* When this routine is called, all of the subsections are still intact
8650      so we walk over subsections instead of sections.  */
8651   for (s = stdoutput->sections; s; s = s->next)
8652     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8653       {
8654         fragS *fragP;
8655         xtensa_opcode current_opcode = XTENSA_UNDEFINED;
8656
8657         /* Walk over all of the fragments in a subsection.  */
8658         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8659           {
8660             if (fragP->fr_type == rs_machine_dependent
8661                 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
8662                     || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
8663               {
8664                 TInsn t_insn;
8665                 fragS *loop_frag = next_non_empty_frag (fragP);
8666                 tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0);
8667                 current_opcode = t_insn.opcode;
8668                 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa,
8669                                                current_opcode) == 1);
8670               }
8671
8672             if (fragP->fr_type == rs_machine_dependent
8673                 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8674               {
8675                 if (count_insns_to_loop_end (fragP->fr_next, true, 3) < 3
8676                     && (branch_before_loop_end (fragP->fr_next)
8677                         || (workaround_all_short_loops
8678                             && current_opcode != XTENSA_UNDEFINED
8679                             && current_opcode != xtensa_loop_opcode)))
8680                   {
8681                     if (fragP->tc_frag_data.is_no_transform)
8682                       as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8683                     else
8684                       relax_frag_add_nop (fragP);
8685                   }
8686                 frag_wane (fragP);
8687               }
8688           }
8689       }
8690 }
8691
8692
8693 static int unrelaxed_frag_min_insn_count (fragS *);
8694
8695 static int
8696 count_insns_to_loop_end (fragS *base_fragP,
8697                          bool count_relax_add,
8698                          int max_count)
8699 {
8700   fragS *fragP = NULL;
8701   int insn_count = 0;
8702
8703   fragP = base_fragP;
8704
8705   for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next)
8706     {
8707       insn_count += unrelaxed_frag_min_insn_count (fragP);
8708       if (insn_count >= max_count)
8709         return max_count;
8710
8711       if (count_relax_add)
8712         {
8713           if (fragP->fr_type == rs_machine_dependent
8714               && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
8715             {
8716               /* In order to add the appropriate number of
8717                  NOPs, we count an instruction for downstream
8718                  occurrences.  */
8719               insn_count++;
8720               if (insn_count >= max_count)
8721                 return max_count;
8722             }
8723         }
8724     }
8725   return insn_count;
8726 }
8727
8728
8729 static int
8730 unrelaxed_frag_min_insn_count (fragS *fragP)
8731 {
8732   xtensa_isa isa = xtensa_default_isa;
8733   static xtensa_insnbuf insnbuf = NULL;
8734   int insn_count = 0;
8735   unsigned int offset = 0;
8736
8737   if (!fragP->tc_frag_data.is_insn)
8738     return insn_count;
8739
8740   if (!insnbuf)
8741     insnbuf = xtensa_insnbuf_alloc (isa);
8742
8743   /* Decode the fixed instructions.  */
8744   while (offset < fragP->fr_fix)
8745     {
8746       xtensa_format fmt;
8747
8748       xtensa_insnbuf_from_chars
8749         (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
8750       fmt = xtensa_format_decode (isa, insnbuf);
8751
8752       if (fmt == XTENSA_UNDEFINED)
8753         {
8754           as_fatal (_("undecodable instruction in instruction frag"));
8755           return insn_count;
8756         }
8757       offset += xtensa_format_length (isa, fmt);
8758       insn_count++;
8759     }
8760
8761   return insn_count;
8762 }
8763
8764
8765 static bool unrelaxed_frag_has_b_j (fragS *);
8766
8767 static bool
8768 branch_before_loop_end (fragS *base_fragP)
8769 {
8770   fragS *fragP;
8771
8772   for (fragP = base_fragP;
8773        fragP && !fragP->tc_frag_data.is_loop_target;
8774        fragP = fragP->fr_next)
8775     {
8776       if (unrelaxed_frag_has_b_j (fragP))
8777         return true;
8778     }
8779   return false;
8780 }
8781
8782
8783 static bool
8784 unrelaxed_frag_has_b_j (fragS *fragP)
8785 {
8786   static xtensa_insnbuf insnbuf = NULL;
8787   xtensa_isa isa = xtensa_default_isa;
8788   unsigned int offset = 0;
8789
8790   if (!fragP->tc_frag_data.is_insn)
8791     return false;
8792
8793   if (!insnbuf)
8794     insnbuf = xtensa_insnbuf_alloc (isa);
8795
8796   /* Decode the fixed instructions.  */
8797   while (offset < fragP->fr_fix)
8798     {
8799       xtensa_format fmt;
8800       int slot;
8801
8802       xtensa_insnbuf_from_chars
8803         (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
8804       fmt = xtensa_format_decode (isa, insnbuf);
8805       if (fmt == XTENSA_UNDEFINED)
8806         return false;
8807
8808       for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
8809         {
8810           xtensa_opcode opcode =
8811             get_opcode_from_buf (fragP->fr_literal + offset, slot);
8812           if (xtensa_opcode_is_branch (isa, opcode) == 1
8813               || xtensa_opcode_is_jump (isa, opcode) == 1)
8814             return true;
8815         }
8816       offset += xtensa_format_length (isa, fmt);
8817     }
8818   return false;
8819 }
8820
8821
8822 /* Checks to be made after initial assembly but before relaxation.  */
8823
8824 static bool is_empty_loop (const TInsn *, fragS *);
8825 static bool is_local_forward_loop (const TInsn *, fragS *);
8826
8827 static void
8828 xtensa_sanity_check (void)
8829 {
8830   const char *file_name;
8831   unsigned line;
8832   frchainS *frchP;
8833   asection *s;
8834
8835   file_name = as_where (&line);
8836   for (s = stdoutput->sections; s; s = s->next)
8837     for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
8838       {
8839         fragS *fragP;
8840
8841         /* Walk over all of the fragments in a subsection.  */
8842         for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
8843           {
8844             if (fragP->fr_type == rs_machine_dependent
8845                 && fragP->fr_subtype == RELAX_SLOTS
8846                 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
8847               {
8848                 static xtensa_insnbuf insnbuf = NULL;
8849                 TInsn t_insn;
8850
8851                 if (fragP->fr_opcode != NULL)
8852                   {
8853                     if (!insnbuf)
8854                       insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
8855                     tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
8856                     tinsn_immed_from_frag (&t_insn, fragP, 0);
8857
8858                     if (xtensa_opcode_is_loop (xtensa_default_isa,
8859                                                t_insn.opcode) == 1)
8860                       {
8861                         if (is_empty_loop (&t_insn, fragP))
8862                           {
8863                             new_logical_line (fragP->fr_file, fragP->fr_line);
8864                             as_bad (_("invalid empty loop"));
8865                           }
8866                         if (!is_local_forward_loop (&t_insn, fragP))
8867                           {
8868                             new_logical_line (fragP->fr_file, fragP->fr_line);
8869                             as_bad (_("loop target does not follow "
8870                                       "loop instruction in section"));
8871                           }
8872                       }
8873                   }
8874               }
8875           }
8876       }
8877   new_logical_line (file_name, line);
8878 }
8879
8880
8881 #define LOOP_IMMED_OPN 1
8882
8883 /* Return TRUE if the loop target is the next non-zero fragment.  */
8884
8885 static bool
8886 is_empty_loop (const TInsn *insn, fragS *fragP)
8887 {
8888   const expressionS *exp;
8889   symbolS *symbolP;
8890   fragS *next_fragP;
8891
8892   if (insn->insn_type != ITYPE_INSN)
8893     return false;
8894
8895   if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8896     return false;
8897
8898   if (insn->ntok <= LOOP_IMMED_OPN)
8899     return false;
8900
8901   exp = &insn->tok[LOOP_IMMED_OPN];
8902
8903   if (exp->X_op != O_symbol)
8904     return false;
8905
8906   symbolP = exp->X_add_symbol;
8907   if (!symbolP)
8908     return false;
8909
8910   if (symbol_get_frag (symbolP) == NULL)
8911     return false;
8912
8913   if (S_GET_VALUE (symbolP) != 0)
8914     return false;
8915
8916   /* Walk through the zero-size fragments from this one.  If we find
8917      the target fragment, then this is a zero-size loop.  */
8918
8919   for (next_fragP = fragP->fr_next;
8920        next_fragP != NULL;
8921        next_fragP = next_fragP->fr_next)
8922     {
8923       if (next_fragP == symbol_get_frag (symbolP))
8924         return true;
8925       if (next_fragP->fr_fix != 0)
8926         return false;
8927     }
8928   return false;
8929 }
8930
8931
8932 static bool
8933 is_local_forward_loop (const TInsn *insn, fragS *fragP)
8934 {
8935   const expressionS *exp;
8936   symbolS *symbolP;
8937   fragS *next_fragP;
8938
8939   if (insn->insn_type != ITYPE_INSN)
8940     return false;
8941
8942   if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
8943     return false;
8944
8945   if (insn->ntok <= LOOP_IMMED_OPN)
8946     return false;
8947
8948   exp = &insn->tok[LOOP_IMMED_OPN];
8949
8950   if (exp->X_op != O_symbol)
8951     return false;
8952
8953   symbolP = exp->X_add_symbol;
8954   if (!symbolP)
8955     return false;
8956
8957   if (symbol_get_frag (symbolP) == NULL)
8958     return false;
8959
8960   /* Walk through fragments until we find the target.
8961      If we do not find the target, then this is an invalid loop.  */
8962
8963   for (next_fragP = fragP->fr_next;
8964        next_fragP != NULL;
8965        next_fragP = next_fragP->fr_next)
8966     {
8967       if (next_fragP == symbol_get_frag (symbolP))
8968         return true;
8969     }
8970
8971   return false;
8972 }
8973
8974 #define XTINFO_NAME "Xtensa_Info"
8975 #define XTINFO_NAMESZ 12
8976 #define XTINFO_TYPE 1
8977
8978 static void
8979 xtensa_add_config_info (void)
8980 {
8981   asection *info_sec;
8982   char *data, *p;
8983   int sz;
8984
8985   info_sec = subseg_new (".xtensa.info", 0);
8986   bfd_set_section_flags (info_sec, SEC_HAS_CONTENTS | SEC_READONLY);
8987
8988   data = XNEWVEC (char, 100);
8989   sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8990            XSHAL_USE_ABSOLUTE_LITERALS, xtensa_abi_choice ());
8991   sz = strlen (data) + 1;
8992
8993   /* Add enough null terminators to pad to a word boundary.  */
8994   do
8995     data[sz++] = 0;
8996   while ((sz & 3) != 0);
8997
8998   /* Follow the standard note section layout:
8999      First write the length of the name string.  */
9000   p = frag_more (4);
9001   md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4);
9002
9003   /* Next comes the length of the "descriptor", i.e., the actual data.  */
9004   p = frag_more (4);
9005   md_number_to_chars (p, (valueT) sz, 4);
9006
9007   /* Write the note type.  */
9008   p = frag_more (4);
9009   md_number_to_chars (p, (valueT) XTINFO_TYPE, 4);
9010
9011   /* Write the name field.  */
9012   p = frag_more (XTINFO_NAMESZ);
9013   memcpy (p, XTINFO_NAME, XTINFO_NAMESZ);
9014
9015   /* Finally, write the descriptor.  */
9016   p = frag_more (sz);
9017   memcpy (p, data, sz);
9018
9019   free (data);
9020 }
9021
9022 \f
9023 /* Alignment Functions.  */
9024
9025 static int
9026 get_text_align_power (unsigned target_size)
9027 {
9028   if (target_size <= 4)
9029     return 2;
9030
9031   if (target_size <= 8)
9032     return 3;
9033
9034   if (target_size <= 16)
9035     return 4;
9036
9037   if (target_size <= 32)
9038     return 5;
9039
9040   if (target_size <= 64)
9041     return 6;
9042
9043   if (target_size <= 128)
9044     return 7;
9045
9046   if (target_size <= 256)
9047     return 8;
9048
9049   if (target_size <= 512)
9050     return 9;
9051
9052   if (target_size <= 1024)
9053     return 10;
9054
9055   gas_assert (0);
9056   return 0;
9057 }
9058
9059
9060 static int
9061 get_text_align_max_fill_size (int align_pow,
9062                               bool use_nops,
9063                               bool use_no_density)
9064 {
9065   if (!use_nops)
9066     return (1 << align_pow);
9067   if (use_no_density)
9068     return 3 * (1 << align_pow);
9069
9070   return 1 + (1 << align_pow);
9071 }
9072
9073
9074 /* Calculate the minimum bytes of fill needed at "address" to align a
9075    target instruction of size "target_size" so that it does not cross a
9076    power-of-two boundary specified by "align_pow".  If "use_nops" is FALSE,
9077    the fill can be an arbitrary number of bytes.  Otherwise, the space must
9078    be filled by NOP instructions.  */
9079
9080 static int
9081 get_text_align_fill_size (addressT address,
9082                           int align_pow,
9083                           int target_size,
9084                           bool use_nops,
9085                           bool use_no_density)
9086 {
9087   addressT alignment, fill, fill_limit, fill_step;
9088   bool skip_one = false;
9089
9090   alignment = (1 << align_pow);
9091   gas_assert (target_size > 0 && alignment >= (addressT) target_size);
9092
9093   if (!use_nops)
9094     {
9095       fill_limit = alignment;
9096       fill_step = 1;
9097     }
9098   else if (!use_no_density)
9099     {
9100       /* Combine 2- and 3-byte NOPs to fill anything larger than one.  */
9101       fill_limit = alignment * 2;
9102       fill_step = 1;
9103       skip_one = true;
9104     }
9105   else
9106     {
9107       /* Fill with 3-byte NOPs -- can only fill multiples of 3.  */
9108       fill_limit = alignment * 3;
9109       fill_step = 3;
9110     }
9111
9112   /* Try all fill sizes until finding one that works.  */
9113   for (fill = 0; fill < fill_limit; fill += fill_step)
9114     {
9115       if (skip_one && fill == 1)
9116         continue;
9117       if ((address + fill) >> align_pow
9118           == (address + fill + target_size - 1) >> align_pow)
9119         return fill;
9120     }
9121   gas_assert (0);
9122   return 0;
9123 }
9124
9125
9126 static int
9127 branch_align_power (segT sec)
9128 {
9129   /* If the Xtensa processor has a fetch width of X, and
9130      the section is aligned to at least that boundary, then a branch
9131      target need only fit within that aligned block of memory to avoid
9132      a stall.  Otherwise, try to fit branch targets within 4-byte
9133      aligned blocks (which may be insufficient, e.g., if the section
9134      has no alignment, but it's good enough).  */
9135   int fetch_align = get_text_align_power(xtensa_fetch_width);
9136   int sec_align = get_recorded_alignment (sec);
9137
9138   if (sec_align >= fetch_align)
9139     return fetch_align;
9140
9141   return 2;
9142 }
9143
9144
9145 /* This will assert if it is not possible.  */
9146
9147 static int
9148 get_text_align_nop_count (offsetT fill_size, bool use_no_density)
9149 {
9150   int count = 0;
9151
9152   if (use_no_density)
9153     {
9154       gas_assert (fill_size % 3 == 0);
9155       return (fill_size / 3);
9156     }
9157
9158   gas_assert (fill_size != 1);  /* Bad argument.  */
9159
9160   while (fill_size > 1)
9161     {
9162       int insn_size = 3;
9163       if (fill_size == 2 || fill_size == 4)
9164         insn_size = 2;
9165       fill_size -= insn_size;
9166       count++;
9167     }
9168   gas_assert (fill_size != 1);  /* Bad algorithm.  */
9169   return count;
9170 }
9171
9172
9173 static int
9174 get_text_align_nth_nop_size (offsetT fill_size,
9175                              int n,
9176                              bool use_no_density)
9177 {
9178   int count = 0;
9179
9180   if (use_no_density)
9181     return 3;
9182
9183   gas_assert (fill_size != 1);  /* Bad argument.  */
9184
9185   while (fill_size > 1)
9186     {
9187       int insn_size = 3;
9188       if (fill_size == 2 || fill_size == 4)
9189         insn_size = 2;
9190       fill_size -= insn_size;
9191       count++;
9192       if (n + 1 == count)
9193         return insn_size;
9194     }
9195   gas_assert (0);
9196   return 0;
9197 }
9198
9199
9200 /* For the given fragment, find the appropriate address
9201    for it to begin at if we are using NOPs to align it.  */
9202
9203 static addressT
9204 get_noop_aligned_address (fragS *fragP, addressT address)
9205 {
9206   /* The rule is: get next fragment's FIRST instruction.  Find
9207      the smallest number of bytes that need to be added to
9208      ensure that the next fragment's FIRST instruction will fit
9209      in a single word.
9210
9211      E.G.,   2 bytes : 0, 1, 2 mod 4
9212              3 bytes: 0, 1 mod 4
9213
9214      If the FIRST instruction MIGHT be relaxed,
9215      assume that it will become a 3-byte instruction.
9216
9217      Note again here that LOOP instructions are not bundleable,
9218      and this relaxation only applies to LOOP opcodes.  */
9219
9220   int fill_size = 0;
9221   int first_insn_size;
9222   int loop_insn_size;
9223   addressT pre_opcode_bytes;
9224   int align_power;
9225   fragS *first_insn;
9226   xtensa_opcode opcode;
9227   bool is_loop;
9228
9229   gas_assert (fragP->fr_type == rs_machine_dependent);
9230   gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
9231
9232   /* Find the loop frag.  */
9233   first_insn = next_non_empty_frag (fragP);
9234   /* Now find the first insn frag.  */
9235   first_insn = next_non_empty_frag (first_insn);
9236
9237   is_loop = next_frag_opcode_is_loop (fragP, &opcode);
9238   gas_assert (is_loop);
9239   loop_insn_size = xg_get_single_size (opcode);
9240
9241   pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
9242   pre_opcode_bytes += loop_insn_size;
9243
9244   /* For loops, the alignment depends on the size of the
9245      instruction following the loop, not the LOOP instruction.  */
9246
9247   if (first_insn == NULL)
9248     first_insn_size = xtensa_fetch_width;
9249   else
9250     first_insn_size = get_loop_align_size (frag_format_size (first_insn));
9251
9252   /* If it was 8, then we'll need a larger alignment for the section.  */
9253   align_power = get_text_align_power (first_insn_size);
9254   record_alignment (now_seg, align_power);
9255
9256   fill_size = get_text_align_fill_size
9257     (address + pre_opcode_bytes, align_power, first_insn_size, true,
9258      fragP->tc_frag_data.is_no_density);
9259
9260   return address + fill_size;
9261 }
9262
9263
9264 /* 3 mechanisms for relaxing an alignment:
9265
9266    Align to a power of 2.
9267    Align so the next fragment's instruction does not cross a word boundary.
9268    Align the current instruction so that if the next instruction
9269        were 3 bytes, it would not cross a word boundary.
9270
9271    We can align with:
9272
9273    zeros    - This is easy; always insert zeros.
9274    nops     - 3-byte and 2-byte instructions
9275               2 - 2-byte nop
9276               3 - 3-byte nop
9277               4 - 2 2-byte nops
9278               >=5 : 3-byte instruction + fn (n-3)
9279    widening - widen previous instructions.  */
9280
9281 static offsetT
9282 get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff)
9283 {
9284   addressT target_address, loop_insn_offset;
9285   int target_size;
9286   xtensa_opcode loop_opcode;
9287   bool is_loop;
9288   int align_power;
9289   offsetT opt_diff;
9290   offsetT branch_align;
9291   fragS *loop_frag;
9292
9293   gas_assert (fragP->fr_type == rs_machine_dependent);
9294   switch (fragP->fr_subtype)
9295     {
9296     case RELAX_DESIRE_ALIGN:
9297       target_size = next_frag_format_size (fragP);
9298       if (target_size == XTENSA_UNDEFINED)
9299         target_size = 3;
9300       align_power = branch_align_power (now_seg);
9301       branch_align = 1 << align_power;
9302       /* Don't count on the section alignment being as large as the target.  */
9303       if (target_size > branch_align)
9304         target_size = branch_align;
9305       opt_diff = get_text_align_fill_size (address, align_power,
9306                                            target_size, false, false);
9307
9308       *max_diff = (opt_diff + branch_align
9309                    - (target_size + ((address + opt_diff) % branch_align)));
9310       gas_assert (*max_diff >= opt_diff);
9311       return opt_diff;
9312
9313     case RELAX_ALIGN_NEXT_OPCODE:
9314       /* The next non-empty frag after this one holds the LOOP instruction
9315          that needs to be aligned.  The required alignment depends on the
9316          size of the next non-empty frag after the loop frag, i.e., the
9317          first instruction in the loop.  */
9318       loop_frag = next_non_empty_frag (fragP);
9319       target_size = get_loop_align_size (next_frag_format_size (loop_frag));
9320       loop_insn_offset = 0;
9321       is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
9322       gas_assert (is_loop);
9323
9324       /* If the loop has been expanded then the LOOP instruction
9325          could be at an offset from this fragment.  */
9326       if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED)
9327         loop_insn_offset = get_expanded_loop_offset (loop_opcode);
9328
9329       /* In an ideal world, which is what we are shooting for here,
9330          we wouldn't need to use any NOPs immediately prior to the
9331          LOOP instruction.  If this approach fails, relax_frag_loop_align
9332          will call get_noop_aligned_address.  */
9333       target_address =
9334         address + loop_insn_offset + xg_get_single_size (loop_opcode);
9335       align_power = get_text_align_power (target_size);
9336       opt_diff = get_text_align_fill_size (target_address, align_power,
9337                                            target_size, false, false);
9338
9339       *max_diff = xtensa_fetch_width
9340         - ((target_address + opt_diff) % xtensa_fetch_width)
9341         - target_size + opt_diff;
9342       gas_assert (*max_diff >= opt_diff);
9343       return opt_diff;
9344
9345     default:
9346       break;
9347     }
9348   gas_assert (0);
9349   return 0;
9350 }
9351
9352 \f
9353 /* md_relax_frag Hook and Helper Functions.  */
9354
9355 static long relax_frag_loop_align (fragS *, long);
9356 static long relax_frag_for_align (fragS *, long);
9357 static long relax_frag_immed
9358   (segT, fragS *, long, int, xtensa_format, int, int *, bool);
9359
9360 /* Get projected address for the first fulcrum on a path from source to
9361    target.  */
9362 static addressT xg_get_fulcrum (addressT source, addressT target)
9363 {
9364   offsetT delta = target - source;
9365   int n;
9366
9367   n = (labs (delta) + J_RANGE - J_MARGIN - 1) / (J_RANGE - J_MARGIN);
9368   return source + delta / n;
9369 }
9370
9371 /* Given trampoline index, source and target of a jump find the best
9372    candidate trampoline for the first fulcrum.  The best trampoline is
9373    the one in the reach of "j' instruction from the source, closest to
9374    the projected fulcrum address, and preferrably w/o a jump around or
9375    with already initialized jump around.  */
9376 static size_t xg_find_best_trampoline (struct trampoline_index *idx,
9377                                        addressT source, addressT target)
9378 {
9379   addressT fulcrum = xg_get_fulcrum (source, target);
9380   size_t dist = 0;
9381   size_t best = -1;
9382   size_t base_tr = xg_find_trampoline (idx, fulcrum);
9383   int checked = 1;
9384
9385   /* Check trampoline frags around the base_tr to find the best.  */
9386   for (dist = 0; checked; ++dist)
9387     {
9388       int i;
9389       size_t tr = base_tr - dist;
9390
9391       checked = 0;
9392
9393       /* Trampolines are checked in the following order:
9394          base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2  */
9395       for (i = 0; i < 2; ++i, tr = base_tr + dist + 1)
9396         if (tr < idx->n_entries)
9397           {
9398             fragS *trampoline_frag = idx->entry[tr];
9399             offsetT off;
9400
9401             /* Don't check trampolines outside source - target interval.  */
9402             if ((trampoline_frag->fr_address < source &&
9403                  trampoline_frag->fr_address < target) ||
9404                 (trampoline_frag->fr_address > source &&
9405                  trampoline_frag->fr_address > target))
9406               continue;
9407
9408             /* Don't choose trampoline that contains the source.  */
9409             if (source >= trampoline_frag->fr_address
9410                 && source <= trampoline_frag->fr_address +
9411                 trampoline_frag->fr_fix)
9412               continue;
9413
9414             off = trampoline_frag->fr_address - fulcrum;
9415             /* Stop if some trampoline is found and the search is more than
9416                J_RANGE / 4 from the projected fulcrum.  A trampoline w/o jump
9417                around is nice, but it shouldn't have much overhead.  */
9418             if (best < idx->n_entries && labs (off) > J_RANGE / 4)
9419               return best;
9420
9421             off = trampoline_frag->fr_address - source;
9422             if (labs (off) < J_RANGE - J_MARGIN)
9423               {
9424                 ++checked;
9425                 /* Stop if a trampoline w/o jump around is found or initialized
9426                    trampoline with jump around is found.  */
9427                 if (!trampoline_frag->tc_frag_data.needs_jump_around ||
9428                     trampoline_frag->fr_fix)
9429                   return tr;
9430                 else if (best >= idx->n_entries)
9431                   best = tr;
9432               }
9433           }
9434     }
9435
9436   if (best < idx->n_entries)
9437     return best;
9438   else
9439     as_fatal (_("cannot find suitable trampoline"));
9440 }
9441
9442 static fixS *xg_relax_fixup (struct trampoline_index *idx, fixS *fixP)
9443 {
9444   symbolS *s = fixP->fx_addsy;
9445   addressT source = fixP->fx_frag->fr_address;
9446   addressT target = S_GET_VALUE (s) + fixP->fx_offset;
9447   size_t tr = xg_find_best_trampoline (idx, source, target);
9448   fragS *trampoline_frag = idx->entry[tr];
9449   fixS *newfixP;
9450
9451   init_trampoline_frag (trampoline_frag);
9452   newfixP = xg_append_jump (trampoline_frag,
9453                             fixP->fx_addsy, fixP->fx_offset);
9454
9455   /* Adjust the fixup for the original "j" instruction to
9456      point to the newly added jump.  */
9457   fixP->fx_addsy = trampoline_frag->fr_symbol;
9458   fixP->fx_offset = trampoline_frag->fr_fix - 3;
9459   fixP->tc_fix_data.X_add_symbol = trampoline_frag->fr_symbol;
9460   fixP->tc_fix_data.X_add_number = trampoline_frag->fr_fix - 3;
9461
9462   trampoline_frag->tc_frag_data.relax_seen = false;
9463
9464   if (xg_is_trampoline_frag_full (trampoline_frag))
9465     xg_remove_trampoline_from_index (idx, tr);
9466
9467   return newfixP;
9468 }
9469
9470 static bool xg_is_relaxable_fixup (fixS *fixP)
9471 {
9472   xtensa_isa isa = xtensa_default_isa;
9473   addressT addr = fixP->fx_frag->fr_address;
9474   addressT target;
9475   offsetT delta;
9476   symbolS *s = fixP->fx_addsy;
9477   int slot;
9478   xtensa_format fmt;
9479   xtensa_opcode opcode;
9480
9481   if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP ||
9482       fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP)
9483     return false;
9484
9485   target = S_GET_VALUE (s) + fixP->fx_offset;
9486   delta = target - addr;
9487
9488   if (labs (delta) < J_RANGE - J_MARGIN)
9489     return false;
9490
9491   xtensa_insnbuf_from_chars (isa, trampoline_buf,
9492                              (unsigned char *) fixP->fx_frag->fr_literal +
9493                              fixP->fx_where, 0);
9494   fmt = xtensa_format_decode (isa, trampoline_buf);
9495   gas_assert (fmt != XTENSA_UNDEFINED);
9496   slot = fixP->tc_fix_data.slot;
9497   xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf);
9498   opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf);
9499   return opcode == xtensa_j_opcode;
9500 }
9501
9502 static void xg_relax_fixups (struct trampoline_seg *ts)
9503 {
9504   struct trampoline_index *idx = &ts->index;
9505   segment_info_type *seginfo = seg_info (now_seg);
9506   fixS *fx;
9507
9508   for (fx = seginfo->fix_root; fx; fx = fx->fx_next)
9509     {
9510       fixS *fixP = fx;
9511       struct trampoline_chain *tc = NULL;
9512
9513       if (xg_is_relaxable_fixup (fixP))
9514         {
9515           tc = xg_find_best_eq_target (ts, fixP->fx_frag->fr_address,
9516                                        &fixP->fx_addsy, &fixP->fx_offset);
9517           if (!tc)
9518             tc = xg_create_trampoline_chain (ts, fixP->fx_addsy,
9519                                              fixP->fx_offset);
9520           gas_assert (tc);
9521         }
9522
9523       while (xg_is_relaxable_fixup (fixP))
9524         {
9525           fixP = xg_relax_fixup (idx, fixP);
9526           xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol,
9527                                     fixP->fx_where);
9528         }
9529     }
9530 }
9531
9532 /* Given a trampoline frag relax all jumps that might want to use this
9533    trampoline.  Only do real work once per relaxation cycle, when
9534    xg_relax_trampoline is called for the first trampoline in the now_seg.
9535    Don't use stretch, don't update new_stretch: place fulcrums with a
9536    slack to tolerate code movement.  In the worst case if a jump between
9537    two trampolines wouldn't reach the next relaxation pass will fix it.  */
9538 static void xg_relax_trampoline (fragS *fragP, long stretch ATTRIBUTE_UNUSED,
9539                                  long *new_stretch ATTRIBUTE_UNUSED)
9540 {
9541   struct trampoline_seg *ts = find_trampoline_seg (now_seg);
9542
9543   if (ts->index.n_entries && ts->index.entry[0] == fragP)
9544     xg_relax_fixups (ts);
9545 }
9546
9547 /* Return the number of bytes added to this fragment, given that the
9548    input has been stretched already by "stretch".  */
9549
9550 long
9551 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
9552 {
9553   xtensa_isa isa = xtensa_default_isa;
9554   int unreported = fragP->tc_frag_data.unreported_expansion;
9555   long new_stretch = 0;
9556   const char *file_name;
9557   unsigned line;
9558   int lit_size;
9559   static xtensa_insnbuf vbuf = NULL;
9560   int slot, num_slots;
9561   xtensa_format fmt;
9562
9563   file_name = as_where (&line);
9564   new_logical_line (fragP->fr_file, fragP->fr_line);
9565
9566   fragP->tc_frag_data.unreported_expansion = 0;
9567
9568   switch (fragP->fr_subtype)
9569     {
9570     case RELAX_ALIGN_NEXT_OPCODE:
9571       /* Always convert.  */
9572       if (fragP->tc_frag_data.relax_seen)
9573         new_stretch = relax_frag_loop_align (fragP, stretch);
9574       break;
9575
9576     case RELAX_LOOP_END:
9577       /* Do nothing.  */
9578       break;
9579
9580     case RELAX_LOOP_END_ADD_NOP:
9581       /* Add a NOP and switch to .fill 0.  */
9582       new_stretch = relax_frag_add_nop (fragP);
9583       frag_wane (fragP);
9584       break;
9585
9586     case RELAX_DESIRE_ALIGN:
9587       /* Do nothing. The narrowing before this frag will either align
9588          it or not.  */
9589       break;
9590
9591     case RELAX_LITERAL:
9592     case RELAX_LITERAL_FINAL:
9593       return 0;
9594
9595     case RELAX_LITERAL_NR:
9596       lit_size = 4;
9597       fragP->fr_subtype = RELAX_LITERAL_FINAL;
9598       gas_assert (unreported == lit_size);
9599       memset (&fragP->fr_literal[fragP->fr_fix], 0, 4);
9600       fragP->fr_var -= lit_size;
9601       fragP->fr_fix += lit_size;
9602       new_stretch = 4;
9603       break;
9604
9605     case RELAX_SLOTS:
9606       if (vbuf == NULL)
9607         vbuf = xtensa_insnbuf_alloc (isa);
9608
9609       xtensa_insnbuf_from_chars
9610         (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0);
9611       fmt = xtensa_format_decode (isa, vbuf);
9612       num_slots = xtensa_format_num_slots (isa, fmt);
9613
9614       for (slot = 0; slot < num_slots; slot++)
9615         {
9616           switch (fragP->tc_frag_data.slot_subtypes[slot])
9617             {
9618             case RELAX_NARROW:
9619               if (fragP->tc_frag_data.relax_seen)
9620                 new_stretch += relax_frag_for_align (fragP, stretch);
9621               break;
9622
9623             case RELAX_IMMED:
9624             case RELAX_IMMED_STEP1:
9625             case RELAX_IMMED_STEP2:
9626             case RELAX_IMMED_STEP3:
9627               /* Place the immediate.  */
9628               new_stretch += relax_frag_immed
9629                 (now_seg, fragP, stretch,
9630                  fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
9631                  fmt, slot, stretched_p, false);
9632               break;
9633
9634             default:
9635               /* This is OK; see the note in xg_assemble_vliw_tokens.  */
9636               break;
9637             }
9638         }
9639       break;
9640
9641     case RELAX_LITERAL_POOL_BEGIN:
9642       if (fragP->fr_var != 0)
9643         {
9644           /* We have a converted "candidate" literal pool;
9645              assemble a jump around it.  */
9646           TInsn insn;
9647           if (!litpool_slotbuf)
9648             {
9649               litpool_buf = xtensa_insnbuf_alloc (isa);
9650               litpool_slotbuf = xtensa_insnbuf_alloc (isa);
9651             }
9652           new_stretch += 3;
9653           fragP->tc_frag_data.relax_seen = false; /* Need another pass.  */
9654           fragP->tc_frag_data.is_insn = true;
9655           tinsn_init (&insn);
9656           insn.insn_type = ITYPE_INSN;
9657           insn.opcode = xtensa_j_opcode;
9658           insn.ntok = 1;
9659           set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol,
9660                                   fragP->fr_fix);
9661           fmt = xg_get_single_format (xtensa_j_opcode);
9662           tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf);
9663           xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf);
9664           xtensa_insnbuf_to_chars (isa, litpool_buf,
9665                                    (unsigned char *)fragP->fr_literal +
9666                                    fragP->fr_fix, 3);
9667           fragP->fr_fix += 3;
9668           fragP->fr_var -= 3;
9669           /* Add a fix-up.  */
9670           fix_new (fragP, 0, 3, fragP->fr_symbol, 0, true,
9671                    BFD_RELOC_XTENSA_SLOT0_OP);
9672         }
9673       break;
9674
9675     case RELAX_LITERAL_POOL_END:
9676     case RELAX_LITERAL_POOL_CANDIDATE_BEGIN:
9677     case RELAX_MAYBE_UNREACHABLE:
9678     case RELAX_MAYBE_DESIRE_ALIGN:
9679       /* No relaxation required.  */
9680       break;
9681
9682     case RELAX_FILL_NOP:
9683     case RELAX_UNREACHABLE:
9684       if (fragP->tc_frag_data.relax_seen)
9685         new_stretch += relax_frag_for_align (fragP, stretch);
9686       break;
9687
9688     case RELAX_TRAMPOLINE:
9689       if (fragP->tc_frag_data.relax_seen)
9690         xg_relax_trampoline (fragP, stretch, &new_stretch);
9691       break;
9692
9693     default:
9694       as_bad (_("bad relaxation state"));
9695     }
9696
9697   /* Tell gas we need another relaxation pass.  */
9698   if (! fragP->tc_frag_data.relax_seen)
9699     {
9700       fragP->tc_frag_data.relax_seen = true;
9701       *stretched_p = 1;
9702     }
9703
9704   new_logical_line (file_name, line);
9705   return new_stretch;
9706 }
9707
9708
9709 static long
9710 relax_frag_loop_align (fragS *fragP, long stretch)
9711 {
9712   addressT old_address, old_next_address, old_size;
9713   addressT new_address, new_next_address, new_size;
9714   addressT growth;
9715
9716   /* All the frags with relax_frag_for_alignment prior to this one in the
9717      section have been done, hopefully eliminating the need for a NOP here.
9718      But, this will put it in if necessary.  */
9719
9720   /* Calculate the old address of this fragment and the next fragment.  */
9721   old_address = fragP->fr_address - stretch;
9722   old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
9723                       fragP->tc_frag_data.text_expansion[0]);
9724   old_size = old_next_address - old_address;
9725
9726   /* Calculate the new address of this fragment and the next fragment.  */
9727   new_address = fragP->fr_address;
9728   new_next_address =
9729     get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix);
9730   new_size = new_next_address - new_address;
9731
9732   growth = new_size - old_size;
9733
9734   /* Fix up the text_expansion field and return the new growth.  */
9735   fragP->tc_frag_data.text_expansion[0] += growth;
9736   return growth;
9737 }
9738
9739
9740 /* Add a NOP instruction.  */
9741
9742 static long
9743 relax_frag_add_nop (fragS *fragP)
9744 {
9745   char *nop_buf = fragP->fr_literal + fragP->fr_fix;
9746   int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
9747   assemble_nop (length, nop_buf);
9748   fragP->tc_frag_data.is_insn = true;
9749
9750   if (fragP->fr_var < length)
9751     {
9752       as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length);
9753       return 0;
9754     }
9755
9756   fragP->fr_fix += length;
9757   fragP->fr_var -= length;
9758   return length;
9759 }
9760
9761
9762 static long future_alignment_required (fragS *, long);
9763
9764 static long
9765 relax_frag_for_align (fragS *fragP, long stretch)
9766 {
9767   /* Overview of the relaxation procedure for alignment:
9768      We can widen with NOPs or by widening instructions or by filling
9769      bytes after jump instructions.  Find the opportune places and widen
9770      them if necessary.  */
9771
9772   long stretch_me;
9773   long diff;
9774
9775   gas_assert (fragP->fr_subtype == RELAX_FILL_NOP
9776           || fragP->fr_subtype == RELAX_UNREACHABLE
9777           || (fragP->fr_subtype == RELAX_SLOTS
9778               && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
9779
9780   stretch_me = future_alignment_required (fragP, stretch);
9781   diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
9782   if (diff == 0)
9783     return 0;
9784
9785   if (diff < 0)
9786     {
9787       /* We expanded on a previous pass.  Can we shrink now?  */
9788       long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
9789       if (shrink <= stretch && stretch > 0)
9790         {
9791           fragP->tc_frag_data.text_expansion[0] = stretch_me;
9792           return -shrink;
9793         }
9794       return 0;
9795     }
9796
9797   /* Below here, diff > 0.  */
9798   fragP->tc_frag_data.text_expansion[0] = stretch_me;
9799
9800   return diff;
9801 }
9802
9803
9804 /* Return the address of the next frag that should be aligned.
9805
9806    By "address" we mean the address it _would_ be at if there
9807    is no action taken to align it between here and the target frag.
9808    In other words, if no narrows and no fill nops are used between
9809    here and the frag to align, _even_if_ some of the frags we use
9810    to align targets have already expanded on a previous relaxation
9811    pass.
9812
9813    Also, count each frag that may be used to help align the target.
9814
9815    Return 0 if there are no frags left in the chain that need to be
9816    aligned.  */
9817
9818 static addressT
9819 find_address_of_next_align_frag (fragS **fragPP,
9820                                  int *wide_nops,
9821                                  int *narrow_nops,
9822                                  int *widens,
9823                                  bool *paddable)
9824 {
9825   fragS *fragP = *fragPP;
9826   addressT address = fragP->fr_address;
9827
9828   /* Do not reset the counts to 0.  */
9829
9830   while (fragP)
9831     {
9832       /* Limit this to a small search.  */
9833       if (*widens >= (int) xtensa_fetch_width)
9834         {
9835           *fragPP = fragP;
9836           return 0;
9837         }
9838       address += fragP->fr_fix;
9839
9840       if (fragP->fr_type == rs_fill)
9841         address += fragP->fr_offset * fragP->fr_var;
9842       else if (fragP->fr_type == rs_machine_dependent)
9843         {
9844           switch (fragP->fr_subtype)
9845             {
9846             case RELAX_UNREACHABLE:
9847               *paddable = true;
9848               break;
9849
9850             case RELAX_FILL_NOP:
9851               (*wide_nops)++;
9852               if (!fragP->tc_frag_data.is_no_density)
9853                 (*narrow_nops)++;
9854               break;
9855
9856             case RELAX_SLOTS:
9857               if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
9858                 {
9859                   (*widens)++;
9860                   break;
9861                 }
9862               address += total_frag_text_expansion (fragP);
9863               break;
9864
9865             case RELAX_IMMED:
9866               address += fragP->tc_frag_data.text_expansion[0];
9867               break;
9868
9869             case RELAX_ALIGN_NEXT_OPCODE:
9870             case RELAX_DESIRE_ALIGN:
9871               *fragPP = fragP;
9872               return address;
9873
9874             case RELAX_MAYBE_UNREACHABLE:
9875             case RELAX_MAYBE_DESIRE_ALIGN:
9876               /* Do nothing.  */
9877               break;
9878
9879             default:
9880               /* Just punt if we don't know the type.  */
9881               *fragPP = fragP;
9882               return 0;
9883             }
9884         }
9885       else
9886         {
9887           /* Just punt if we don't know the type.  */
9888           *fragPP = fragP;
9889           return 0;
9890         }
9891       fragP = fragP->fr_next;
9892     }
9893
9894   *fragPP = fragP;
9895   return 0;
9896 }
9897
9898
9899 static long bytes_to_stretch (fragS *, int, int, int, int);
9900
9901 static long
9902 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
9903 {
9904   fragS *this_frag = fragP;
9905   long address;
9906   int num_widens = 0;
9907   int wide_nops = 0;
9908   int narrow_nops = 0;
9909   bool paddable = false;
9910   offsetT local_opt_diff;
9911   offsetT opt_diff;
9912   offsetT max_diff;
9913   int stretch_amount = 0;
9914   int local_stretch_amount;
9915   int global_stretch_amount;
9916
9917   address = find_address_of_next_align_frag
9918     (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
9919
9920   if (!address)
9921     {
9922       if (this_frag->tc_frag_data.is_aligning_branch)
9923         this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
9924       else
9925         frag_wane (this_frag);
9926     }
9927   else
9928     {
9929       local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
9930       opt_diff = local_opt_diff;
9931       gas_assert (opt_diff >= 0);
9932       gas_assert (max_diff >= opt_diff);
9933       if (max_diff == 0)
9934         return 0;
9935
9936       if (fragP)
9937         fragP = fragP->fr_next;
9938
9939       while (fragP && opt_diff < max_diff && address)
9940         {
9941           /* We only use these to determine if we can exit early
9942              because there will be plenty of ways to align future
9943              align frags.  */
9944           int glob_widens = 0;
9945           int dnn = 0;
9946           int dw = 0;
9947           bool glob_pad = 0;
9948           address = find_address_of_next_align_frag
9949             (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
9950           /* If there is a padable portion, then skip.  */
9951           if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg)))
9952             address = 0;
9953
9954           if (address)
9955             {
9956               offsetT next_m_diff;
9957               offsetT next_o_diff;
9958
9959               /* Downrange frags haven't had stretch added to them yet.  */
9960               address += stretch;
9961
9962               /* The address also includes any text expansion from this
9963                  frag in a previous pass, but we don't want that.  */
9964               address -= this_frag->tc_frag_data.text_expansion[0];
9965
9966               /* Assume we are going to move at least opt_diff.  In
9967                  reality, we might not be able to, but assuming that
9968                  we will helps catch cases where moving opt_diff pushes
9969                  the next target from aligned to unaligned.  */
9970               address += opt_diff;
9971
9972               next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
9973
9974               /* Now cleanup for the adjustments to address.  */
9975               next_o_diff += opt_diff;
9976               next_m_diff += opt_diff;
9977               if (next_o_diff <= max_diff && next_o_diff > opt_diff)
9978                 opt_diff = next_o_diff;
9979               if (next_m_diff < max_diff)
9980                 max_diff = next_m_diff;
9981               fragP = fragP->fr_next;
9982             }
9983         }
9984
9985       /* If there are enough wideners in between, do it.  */
9986       if (paddable)
9987         {
9988           if (this_frag->fr_subtype == RELAX_UNREACHABLE)
9989             {
9990               gas_assert (opt_diff <= (signed) xtensa_fetch_width);
9991               return opt_diff;
9992             }
9993           return 0;
9994         }
9995       local_stretch_amount
9996         = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
9997                             num_widens, local_opt_diff);
9998       global_stretch_amount
9999         = bytes_to_stretch (this_frag, wide_nops, narrow_nops,
10000                             num_widens, opt_diff);
10001       /* If the condition below is true, then the frag couldn't
10002          stretch the correct amount for the global case, so we just
10003          optimize locally.  We'll rely on the subsequent frags to get
10004          the correct alignment in the global case.  */
10005       if (global_stretch_amount < local_stretch_amount)
10006         stretch_amount = local_stretch_amount;
10007       else
10008         stretch_amount = global_stretch_amount;
10009
10010       if (this_frag->fr_subtype == RELAX_SLOTS
10011           && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
10012         gas_assert (stretch_amount <= 1);
10013       else if (this_frag->fr_subtype == RELAX_FILL_NOP)
10014         {
10015           if (this_frag->tc_frag_data.is_no_density)
10016             gas_assert (stretch_amount == 3 || stretch_amount == 0);
10017           else
10018             gas_assert (stretch_amount <= 3);
10019         }
10020     }
10021   return stretch_amount;
10022 }
10023
10024
10025 /* The idea: widen everything you can to get a target or loop aligned,
10026    then start using NOPs.
10027
10028    wide_nops   = the number of wide NOPs available for aligning
10029    narrow_nops = the number of narrow NOPs available for aligning
10030                  (a subset of wide_nops)
10031    widens      = the number of narrow instructions that should be widened
10032
10033 */
10034
10035 static long
10036 bytes_to_stretch (fragS *this_frag,
10037                   int wide_nops,
10038                   int narrow_nops,
10039                   int num_widens,
10040                   int desired_diff)
10041 {
10042   int nops_needed;
10043   int nop_bytes;
10044   int extra_bytes;
10045   int bytes_short = desired_diff - num_widens;
10046
10047   gas_assert (desired_diff >= 0
10048               && desired_diff < (signed) xtensa_fetch_width);
10049   if (desired_diff == 0)
10050     return 0;
10051
10052   gas_assert (wide_nops > 0 || num_widens > 0);
10053
10054   /* Always prefer widening to NOP-filling.  */
10055   if (bytes_short < 0)
10056     {
10057       /* There are enough RELAX_NARROW frags after this one
10058          to align the target without widening this frag in any way.  */
10059       return 0;
10060     }
10061
10062   if (bytes_short == 0)
10063     {
10064       /* Widen every narrow between here and the align target
10065          and the align target will be properly aligned.  */
10066       if (this_frag->fr_subtype == RELAX_FILL_NOP)
10067         return 0;
10068       else
10069         return 1;
10070     }
10071
10072   /* From here we will need at least one NOP to get an alignment.
10073      However, we may not be able to align at all, in which case,
10074      don't widen.  */
10075   nops_needed = desired_diff / 3;
10076
10077   /* If there aren't enough nops, don't widen.  */
10078   if (nops_needed > wide_nops)
10079     return 0;
10080
10081   /* First try it with all wide nops.  */
10082   nop_bytes = nops_needed * 3;
10083   extra_bytes = desired_diff - nop_bytes;
10084
10085   if (nop_bytes + num_widens >= desired_diff)
10086     {
10087       if (this_frag->fr_subtype == RELAX_FILL_NOP)
10088         return 3;
10089       else if (num_widens == extra_bytes)
10090         return 1;
10091       return 0;
10092     }
10093
10094   /* Add a narrow nop.  */
10095   nops_needed++;
10096   nop_bytes += 2;
10097   extra_bytes -= 2;
10098   if (narrow_nops == 0 || nops_needed > wide_nops)
10099     return 0;
10100
10101   if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0)
10102     {
10103       if (this_frag->fr_subtype == RELAX_FILL_NOP)
10104         return !this_frag->tc_frag_data.is_no_density ? 2 : 3;
10105       else if (num_widens == extra_bytes)
10106         return 1;
10107       return 0;
10108     }
10109
10110   /* Replace a wide nop with a narrow nop--we can get here if
10111      extra_bytes was negative in the previous conditional.  */
10112   if (narrow_nops == 1)
10113     return 0;
10114   nop_bytes--;
10115   extra_bytes++;
10116   if (nop_bytes + num_widens >= desired_diff)
10117     {
10118       if (this_frag->fr_subtype == RELAX_FILL_NOP)
10119         return !this_frag->tc_frag_data.is_no_density ? 2 : 3;
10120       else if (num_widens == extra_bytes)
10121         return 1;
10122       return 0;
10123     }
10124
10125   /* If we can't satisfy any of the above cases, then we can't align
10126      using padding or fill nops.  */
10127   return 0;
10128 }
10129
10130
10131 static fragS *
10132 xg_find_best_trampoline_for_tinsn (TInsn *tinsn, fragS *fragP)
10133 {
10134   symbolS *sym = tinsn->tok[0].X_add_symbol;
10135   addressT source = fragP->fr_address;
10136   addressT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number;
10137   struct trampoline_seg *ts = find_trampoline_seg (now_seg);
10138   size_t i;
10139
10140   if (!ts || !ts->index.n_entries)
10141     return NULL;
10142
10143   i = xg_find_best_trampoline (&ts->index, source, target);
10144
10145   return ts->index.entry[i];
10146 }
10147
10148
10149 /* Append jump to sym + offset to the end of the trampoline frag fragP.
10150    Adjust fragP's jump around if it's present.  Adjust fragP's fr_fix/fr_var
10151    and finish the frag if it's full (but don't remove it from the trampoline
10152    frag index).  Return fixup for the newly created jump.  */
10153 static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset)
10154 {
10155   fixS *fixP;
10156   TInsn insn;
10157   xtensa_format fmt;
10158   xtensa_isa isa = xtensa_default_isa;
10159
10160   gas_assert (fragP->fr_var >= 3);
10161   tinsn_init (&insn);
10162   insn.insn_type = ITYPE_INSN;
10163   insn.opcode = xtensa_j_opcode;
10164   insn.ntok = 1;
10165   set_expr_symbol_offset (&insn.tok[0], sym, offset);
10166   fmt = xg_get_single_format (xtensa_j_opcode);
10167   tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf);
10168   xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf);
10169   xtensa_insnbuf_to_chars (isa, trampoline_buf,
10170                            (unsigned char *)fragP->fr_literal + fragP->fr_fix, 3);
10171   fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, true,
10172                   BFD_RELOC_XTENSA_SLOT0_OP);
10173   fixP->tc_fix_data.slot = 0;
10174
10175   fragP->fr_fix += 3;
10176   fragP->fr_var -= 3;
10177
10178   /* Adjust the jump around this trampoline (if present).  */
10179   if (fragP->tc_frag_data.jump_around_fix)
10180     fragP->tc_frag_data.jump_around_fix->fx_offset += 3;
10181
10182   /* Do we have room for more? */
10183   if (xg_is_trampoline_frag_full (fragP))
10184     {
10185       frag_wane (fragP);
10186       fragP->fr_subtype = 0;
10187     }
10188
10189   return fixP;
10190 }
10191
10192
10193 static int
10194 init_trampoline_frag (fragS *fp)
10195 {
10196   int growth = 0;
10197
10198   if (fp->fr_fix == 0)
10199     {
10200       symbolS *lsym;
10201       char label[10 + 2 * sizeof(fp)];
10202
10203       sprintf (label, ".L0_TR_%p", fp);
10204       lsym = (symbolS *) local_symbol_make (label, now_seg, fp, 0);
10205       fp->fr_symbol = lsym;
10206       if (fp->tc_frag_data.needs_jump_around)
10207         {
10208           fp->tc_frag_data.jump_around_fix = xg_append_jump (fp, lsym, 3);
10209           growth = 3;
10210         }
10211     }
10212   return growth;
10213 }
10214
10215 static int
10216 xg_get_single_symbol_slot (fragS *fragP)
10217 {
10218   int i;
10219   int slot = -1;
10220
10221   for (i = 0; i < MAX_SLOTS; ++i)
10222     if (fragP->tc_frag_data.slot_symbols[i])
10223       {
10224         gas_assert (slot == -1);
10225         slot = i;
10226       }
10227
10228   gas_assert (slot >= 0 && slot < MAX_SLOTS);
10229
10230   return slot;
10231 }
10232
10233 static fixS *
10234 add_jump_to_trampoline (fragS *tramp, fragS *origfrag)
10235 {
10236   int slot = xg_get_single_symbol_slot (origfrag);
10237   fixS *fixP;
10238
10239   /* Assemble a jump to the target label in the trampoline frag.  */
10240   fixP = xg_append_jump (tramp,
10241                          origfrag->tc_frag_data.slot_symbols[slot],
10242                          origfrag->tc_frag_data.slot_offsets[slot]);
10243
10244   /* Modify the original j to point here.  */
10245   origfrag->tc_frag_data.slot_symbols[slot] = tramp->fr_symbol;
10246   origfrag->tc_frag_data.slot_offsets[slot] = tramp->fr_fix - 3;
10247
10248   /* If trampoline is full, remove it from the list.  */
10249   if (xg_is_trampoline_frag_full (tramp))
10250     {
10251       struct trampoline_seg *ts = find_trampoline_seg (now_seg);
10252       size_t tr = xg_find_trampoline (&ts->index, tramp->fr_address);
10253
10254       gas_assert (ts->index.entry[tr] == tramp);
10255       xg_remove_trampoline_from_index (&ts->index, tr);
10256     }
10257
10258   return fixP;
10259 }
10260
10261
10262 static long
10263 relax_frag_immed (segT segP,
10264                   fragS *fragP,
10265                   long stretch,
10266                   int min_steps,
10267                   xtensa_format fmt,
10268                   int slot,
10269                   int *stretched_p,
10270                   bool estimate_only)
10271 {
10272   TInsn tinsn;
10273   int old_size;
10274   bool negatable_branch = false;
10275   bool branch_jmp_to_next = false;
10276   bool from_wide_insn = false;
10277   xtensa_isa isa = xtensa_default_isa;
10278   IStack istack;
10279   offsetT frag_offset;
10280   int num_steps;
10281   int num_text_bytes, num_literal_bytes;
10282   int literal_diff, total_text_diff, this_text_diff;
10283
10284   gas_assert (fragP->fr_opcode != NULL);
10285
10286   xg_clear_vinsn (&cur_vinsn);
10287   vinsn_from_chars (&cur_vinsn, fragP->fr_opcode);
10288   if (cur_vinsn.num_slots > 1)
10289     from_wide_insn = true;
10290
10291   tinsn = cur_vinsn.slots[slot];
10292   tinsn_immed_from_frag (&tinsn, fragP, slot);
10293
10294   if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1)
10295     return 0;
10296
10297   if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
10298     branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
10299
10300   negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
10301
10302   old_size = xtensa_format_length (isa, fmt);
10303
10304   /* Special case: replace a branch to the next instruction with a NOP.
10305      This is required to work around a hardware bug in T1040.0 and also
10306      serves as an optimization.  */
10307
10308   if (branch_jmp_to_next
10309       && ((old_size == 2) || (old_size == 3))
10310       && !next_frag_is_loop_target (fragP))
10311     return 0;
10312
10313   /* Here is the fun stuff: Get the immediate field from this
10314      instruction.  If it fits, we are done.  If not, find the next
10315      instruction sequence that fits.  */
10316
10317   frag_offset = fragP->fr_opcode - fragP->fr_literal;
10318   istack_init (&istack);
10319   num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
10320                                  min_steps, stretch);
10321   gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
10322
10323   fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
10324
10325   /* Figure out the number of bytes needed.  */
10326   num_literal_bytes = get_num_stack_literal_bytes (&istack);
10327   literal_diff
10328     = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
10329   num_text_bytes = get_num_stack_text_bytes (&istack);
10330
10331   if (from_wide_insn)
10332     {
10333       int first = 0;
10334       while (istack.insn[first].opcode == XTENSA_UNDEFINED)
10335         first++;
10336
10337       num_text_bytes += old_size;
10338       if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
10339         num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
10340       else
10341         {
10342           /* The first instruction in the relaxed sequence will go after
10343              the current wide instruction, and thus its symbolic immediates
10344              might not fit.  */
10345
10346           istack_init (&istack);
10347           num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP,
10348                                          frag_offset + old_size,
10349                                          min_steps, stretch + old_size);
10350           gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS);
10351
10352           fragP->tc_frag_data.slot_subtypes[slot]
10353             = (int) RELAX_IMMED + num_steps;
10354
10355           num_literal_bytes = get_num_stack_literal_bytes (&istack);
10356           literal_diff
10357             = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
10358
10359           num_text_bytes = get_num_stack_text_bytes (&istack) + old_size;
10360         }
10361     }
10362
10363   total_text_diff = num_text_bytes - old_size;
10364   this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
10365
10366   /* It MUST get larger.  If not, we could get an infinite loop.  */
10367   gas_assert (num_text_bytes >= 0);
10368   gas_assert (literal_diff >= 0);
10369   gas_assert (total_text_diff >= 0);
10370
10371   fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
10372   fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
10373   gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
10374   gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
10375
10376   /* Find the associated expandable literal for this.  */
10377   if (literal_diff != 0)
10378     {
10379       fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot];
10380       if (lit_fragP)
10381         {
10382           gas_assert (literal_diff == 4);
10383           lit_fragP->tc_frag_data.unreported_expansion += literal_diff;
10384
10385           /* We expect that the literal section state has NOT been
10386              modified yet.  */
10387           gas_assert (lit_fragP->fr_type == rs_machine_dependent
10388                   && lit_fragP->fr_subtype == RELAX_LITERAL);
10389           lit_fragP->fr_subtype = RELAX_LITERAL_NR;
10390
10391           /* We need to mark this section for another iteration
10392              of relaxation.  */
10393           (*stretched_p)++;
10394         }
10395     }
10396
10397   if (negatable_branch && istack.ninsn > 1)
10398     update_next_frag_state (fragP);
10399
10400   /* If last insn is a jump, and it cannot reach its target, try to find a trampoline.  */
10401   if (istack.ninsn > 2 &&
10402       istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL &&
10403       istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN &&
10404       istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode)
10405     {
10406       TInsn *jinsn = &istack.insn[istack.ninsn - 2];
10407       struct trampoline_seg *ts = find_trampoline_seg (segP);
10408       struct trampoline_chain *tc = NULL;
10409
10410       if (ts &&
10411           !xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset,
10412                                    total_text_diff))
10413         {
10414           int s = xg_get_single_symbol_slot (fragP);
10415           addressT offset = fragP->tc_frag_data.slot_offsets[s];
10416
10417           tc = xg_find_best_eq_target (ts, fragP->fr_address,
10418                                        &fragP->tc_frag_data.slot_symbols[s],
10419                                        &offset);
10420
10421           if (!tc)
10422             tc = xg_create_trampoline_chain (ts,
10423                                              fragP->tc_frag_data.slot_symbols[s],
10424                                              offset);
10425           fragP->tc_frag_data.slot_offsets[s] = offset;
10426           tinsn_immed_from_frag (jinsn, fragP, s);
10427         }
10428
10429       if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset,
10430                                    total_text_diff))
10431         {
10432           fragS *tf = xg_find_best_trampoline_for_tinsn (jinsn, fragP);
10433
10434           if (tf)
10435             {
10436               fixS *fixP;
10437
10438               this_text_diff += init_trampoline_frag (tf) + 3;
10439               fixP = add_jump_to_trampoline (tf, fragP);
10440               xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol,
10441                                         fixP->fx_where);
10442               fragP->tc_frag_data.relax_seen = false;
10443             }
10444           else
10445             {
10446               /* If target symbol is undefined, assume it will reach once linked.  */
10447               expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0];
10448
10449               if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol))
10450                 {
10451                   as_bad_where (fragP->fr_file, fragP->fr_line,
10452                     _("jump target out of range; no usable trampoline found"));
10453                 }
10454             }
10455         }
10456     }
10457
10458   return this_text_diff;
10459 }
10460
10461 \f
10462 /* md_convert_frag Hook and Helper Functions.  */
10463
10464 static void convert_frag_align_next_opcode (fragS *);
10465 static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
10466 static void convert_frag_fill_nop (fragS *);
10467 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
10468
10469 void
10470 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
10471 {
10472   static xtensa_insnbuf vbuf = NULL;
10473   xtensa_isa isa = xtensa_default_isa;
10474   int slot;
10475   int num_slots;
10476   xtensa_format fmt;
10477   const char *file_name;
10478   unsigned line;
10479
10480   file_name = as_where (&line);
10481   new_logical_line (fragp->fr_file, fragp->fr_line);
10482
10483   switch (fragp->fr_subtype)
10484     {
10485     case RELAX_ALIGN_NEXT_OPCODE:
10486       /* Always convert.  */
10487       convert_frag_align_next_opcode (fragp);
10488       break;
10489
10490     case RELAX_DESIRE_ALIGN:
10491       /* Do nothing.  If not aligned already, too bad.  */
10492       break;
10493
10494     case RELAX_LITERAL:
10495     case RELAX_LITERAL_FINAL:
10496       break;
10497
10498     case RELAX_SLOTS:
10499       if (vbuf == NULL)
10500         vbuf = xtensa_insnbuf_alloc (isa);
10501
10502       xtensa_insnbuf_from_chars
10503         (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0);
10504       fmt = xtensa_format_decode (isa, vbuf);
10505       num_slots = xtensa_format_num_slots (isa, fmt);
10506
10507       for (slot = 0; slot < num_slots; slot++)
10508         {
10509           switch (fragp->tc_frag_data.slot_subtypes[slot])
10510             {
10511             case RELAX_NARROW:
10512               convert_frag_narrow (sec, fragp, fmt, slot);
10513               break;
10514
10515             case RELAX_IMMED:
10516             case RELAX_IMMED_STEP1:
10517             case RELAX_IMMED_STEP2:
10518             case RELAX_IMMED_STEP3:
10519               /* Place the immediate.  */
10520               convert_frag_immed
10521                 (sec, fragp,
10522                  fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
10523                  fmt, slot);
10524               break;
10525
10526             default:
10527               /* This is OK because some slots could have
10528                  relaxations and others have none.  */
10529               break;
10530             }
10531         }
10532       break;
10533
10534     case RELAX_UNREACHABLE:
10535       memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
10536       fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
10537       fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
10538       frag_wane (fragp);
10539       break;
10540
10541     case RELAX_MAYBE_UNREACHABLE:
10542     case RELAX_MAYBE_DESIRE_ALIGN:
10543       frag_wane (fragp);
10544       break;
10545
10546     case RELAX_FILL_NOP:
10547       convert_frag_fill_nop (fragp);
10548       break;
10549
10550     case RELAX_LITERAL_NR:
10551       if (use_literal_section)
10552         {
10553           /* This should have been handled during relaxation.  When
10554              relaxing a code segment, literals sometimes need to be
10555              added to the corresponding literal segment.  If that
10556              literal segment has already been relaxed, then we end up
10557              in this situation.  Marking the literal segments as data
10558              would make this happen less often (since GAS always relaxes
10559              code before data), but we could still get into trouble if
10560              there are instructions in a segment that is not marked as
10561              containing code.  Until we can implement a better solution,
10562              cheat and adjust the addresses of all the following frags.
10563              This could break subsequent alignments, but the linker's
10564              literal coalescing will do that anyway.  */
10565
10566           fragS *f;
10567           fragp->fr_subtype = RELAX_LITERAL_FINAL;
10568           gas_assert (fragp->tc_frag_data.unreported_expansion == 4);
10569           memset (&fragp->fr_literal[fragp->fr_fix], 0, 4);
10570           fragp->fr_var -= 4;
10571           fragp->fr_fix += 4;
10572           for (f = fragp->fr_next; f; f = f->fr_next)
10573             f->fr_address += 4;
10574         }
10575       else
10576         as_bad (_("invalid relaxation fragment result"));
10577       break;
10578
10579     case RELAX_TRAMPOLINE:
10580       break;
10581     }
10582
10583   fragp->fr_var = 0;
10584   new_logical_line (file_name, line);
10585 }
10586
10587
10588 static void
10589 convert_frag_align_next_opcode (fragS *fragp)
10590 {
10591   char *nop_buf;                /* Location for Writing.  */
10592   bool use_no_density = fragp->tc_frag_data.is_no_density;
10593   addressT aligned_address;
10594   offsetT fill_size;
10595   int nop, nop_count;
10596
10597   aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
10598                                               fragp->fr_fix);
10599   fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix);
10600   nop_count = get_text_align_nop_count (fill_size, use_no_density);
10601   nop_buf = fragp->fr_literal + fragp->fr_fix;
10602
10603   for (nop = 0; nop < nop_count; nop++)
10604     {
10605       int nop_size;
10606       nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density);
10607
10608       assemble_nop (nop_size, nop_buf);
10609       nop_buf += nop_size;
10610     }
10611
10612   fragp->fr_fix += fill_size;
10613   fragp->fr_var -= fill_size;
10614 }
10615
10616
10617 static void
10618 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
10619 {
10620   TInsn tinsn, single_target;
10621   int size, old_size, diff;
10622   offsetT frag_offset;
10623
10624   gas_assert (slot == 0);
10625   tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
10626
10627   if (fragP->tc_frag_data.is_aligning_branch == 1)
10628     {
10629       gas_assert (fragP->tc_frag_data.text_expansion[0] == 1
10630               || fragP->tc_frag_data.text_expansion[0] == 0);
10631       convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
10632                           fmt, slot);
10633       return;
10634     }
10635
10636   if (fragP->tc_frag_data.text_expansion[0] == 0)
10637     {
10638       /* No conversion.  */
10639       fragP->fr_var = 0;
10640       return;
10641     }
10642
10643   gas_assert (fragP->fr_opcode != NULL);
10644
10645   /* Frags in this relaxation state should only contain
10646      single instruction bundles.  */
10647   tinsn_immed_from_frag (&tinsn, fragP, 0);
10648
10649   /* Just convert it to a wide form....  */
10650   size = 0;
10651   old_size = xg_get_single_size (tinsn.opcode);
10652
10653   tinsn_init (&single_target);
10654   frag_offset = fragP->fr_opcode - fragP->fr_literal;
10655
10656   if (! xg_is_single_relaxable_insn (&tinsn, &single_target, false))
10657     {
10658       as_bad (_("unable to widen instruction"));
10659       return;
10660     }
10661
10662   size = xg_get_single_size (single_target.opcode);
10663   xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP,
10664                        frag_offset, true);
10665
10666   diff = size - old_size;
10667   gas_assert (diff >= 0);
10668   gas_assert (diff <= fragP->fr_var);
10669   fragP->fr_var -= diff;
10670   fragP->fr_fix += diff;
10671
10672   /* clean it up */
10673   fragP->fr_var = 0;
10674 }
10675
10676
10677 static void
10678 convert_frag_fill_nop (fragS *fragP)
10679 {
10680   char *loc = &fragP->fr_literal[fragP->fr_fix];
10681   int size = fragP->tc_frag_data.text_expansion[0];
10682   gas_assert ((unsigned) size == (fragP->fr_next->fr_address
10683                               - fragP->fr_address - fragP->fr_fix));
10684   if (size == 0)
10685     {
10686       /* No conversion.  */
10687       fragP->fr_var = 0;
10688       return;
10689     }
10690   assemble_nop (size, loc);
10691   fragP->tc_frag_data.is_insn = true;
10692   fragP->fr_var -= size;
10693   fragP->fr_fix += size;
10694   frag_wane (fragP);
10695 }
10696
10697
10698 static fixS *fix_new_exp_in_seg
10699   (segT, subsegT, fragS *, int, int, expressionS *, int,
10700    bfd_reloc_code_real_type);
10701
10702 static void
10703 convert_frag_immed (segT segP,
10704                     fragS *fragP,
10705                     int min_steps,
10706                     xtensa_format fmt,
10707                     int slot)
10708 {
10709   char *immed_instr = fragP->fr_opcode;
10710   TInsn orig_tinsn;
10711   bool expanded = false;
10712   bool branch_jmp_to_next = false;
10713   char *fr_opcode = fragP->fr_opcode;
10714   xtensa_isa isa = xtensa_default_isa;
10715   bool from_wide_insn = false;
10716   int bytes;
10717   bool is_loop;
10718
10719   gas_assert (fr_opcode != NULL);
10720
10721   xg_clear_vinsn (&cur_vinsn);
10722
10723   vinsn_from_chars (&cur_vinsn, fr_opcode);
10724   if (cur_vinsn.num_slots > 1)
10725     from_wide_insn = true;
10726
10727   orig_tinsn = cur_vinsn.slots[slot];
10728   tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
10729
10730   is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
10731
10732   if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
10733     branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
10734
10735   if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
10736     {
10737       /* Conversion just inserts a NOP and marks the fix as completed.  */
10738       bytes = xtensa_format_length (isa, fmt);
10739       if (bytes >= 4)
10740         {
10741           cur_vinsn.slots[slot].opcode =
10742             xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot);
10743           cur_vinsn.slots[slot].ntok = 0;
10744         }
10745       else
10746         {
10747           bytes += fragP->tc_frag_data.text_expansion[0];
10748           gas_assert (bytes == 2 || bytes == 3);
10749           build_nop (&cur_vinsn.slots[0], bytes);
10750           fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
10751         }
10752       vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, true);
10753       xtensa_insnbuf_to_chars
10754         (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0);
10755       fragP->fr_var = 0;
10756     }
10757   else
10758     {
10759       /* Here is the fun stuff:  Get the immediate field from this
10760          instruction.  If it fits, we're done.  If not, find the next
10761          instruction sequence that fits.  */
10762
10763       IStack istack;
10764       int i;
10765       symbolS *lit_sym = NULL;
10766       int total_size = 0;
10767       int target_offset = 0;
10768       int old_size;
10769       int diff;
10770       symbolS *gen_label = NULL;
10771       offsetT frag_offset;
10772       bool first = true;
10773
10774       /* It does not fit.  Find something that does and
10775          convert immediately.  */
10776       frag_offset = fr_opcode - fragP->fr_literal;
10777       istack_init (&istack);
10778       xg_assembly_relax (&istack, &orig_tinsn,
10779                          segP, fragP, frag_offset, min_steps, 0);
10780
10781       old_size = xtensa_format_length (isa, fmt);
10782
10783       /* Assemble this right inline.  */
10784
10785       /* First, create the mapping from a label name to the REAL label.  */
10786       target_offset = 0;
10787       for (i = 0; i < istack.ninsn; i++)
10788         {
10789           TInsn *tinsn = &istack.insn[i];
10790           fragS *lit_frag;
10791
10792           switch (tinsn->insn_type)
10793             {
10794             case ITYPE_LITERAL:
10795               if (lit_sym != NULL)
10796                 as_bad (_("multiple literals in expansion"));
10797               /* First find the appropriate space in the literal pool.  */
10798               lit_frag = fragP->tc_frag_data.literal_frags[slot];
10799               if (lit_frag == NULL)
10800                 as_bad (_("no registered fragment for literal"));
10801               if (tinsn->ntok != 1)
10802                 as_bad (_("number of literal tokens != 1"));
10803
10804               /* Set the literal symbol and add a fixup.  */
10805               lit_sym = lit_frag->fr_symbol;
10806               break;
10807
10808             case ITYPE_LABEL:
10809               if (align_targets && !is_loop)
10810                 {
10811                   fragS *unreach = fragP->fr_next;
10812                   while (!(unreach->fr_type == rs_machine_dependent
10813                            && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10814                                || unreach->fr_subtype == RELAX_UNREACHABLE)))
10815                     {
10816                       unreach = unreach->fr_next;
10817                     }
10818
10819                   gas_assert (unreach->fr_type == rs_machine_dependent
10820                           && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
10821                               || unreach->fr_subtype == RELAX_UNREACHABLE));
10822
10823                   target_offset += unreach->tc_frag_data.text_expansion[0];
10824                 }
10825               gas_assert (gen_label == NULL);
10826               gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, fragP,
10827                                       fr_opcode - fragP->fr_literal
10828                                       + target_offset);
10829               break;
10830
10831             case ITYPE_INSN:
10832               if (first && from_wide_insn)
10833                 {
10834                   target_offset += xtensa_format_length (isa, fmt);
10835                   first = false;
10836                   if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10837                     target_offset += xg_get_single_size (tinsn->opcode);
10838                 }
10839               else
10840                 target_offset += xg_get_single_size (tinsn->opcode);
10841               break;
10842             }
10843         }
10844
10845       total_size = 0;
10846       first = true;
10847       for (i = 0; i < istack.ninsn; i++)
10848         {
10849           TInsn *tinsn = &istack.insn[i];
10850           fragS *lit_frag;
10851           int size;
10852           segT target_seg;
10853           bfd_reloc_code_real_type reloc_type;
10854
10855           switch (tinsn->insn_type)
10856             {
10857             case ITYPE_LITERAL:
10858               lit_frag = fragP->tc_frag_data.literal_frags[slot];
10859               /* Already checked.  */
10860               gas_assert (lit_frag != NULL);
10861               gas_assert (lit_sym != NULL);
10862               gas_assert (tinsn->ntok == 1);
10863               /* Add a fixup.  */
10864               target_seg = S_GET_SEGMENT (lit_sym);
10865               gas_assert (target_seg);
10866               reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, true);
10867               fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
10868                                   &tinsn->tok[0], false, reloc_type);
10869               break;
10870
10871             case ITYPE_LABEL:
10872               break;
10873
10874             case ITYPE_INSN:
10875               xg_resolve_labels (tinsn, gen_label);
10876               xg_resolve_literals (tinsn, lit_sym);
10877               if (from_wide_insn && first)
10878                 {
10879                   first = false;
10880                   if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10881                     {
10882                       cur_vinsn.slots[slot] = *tinsn;
10883                     }
10884                   else
10885                     {
10886                       cur_vinsn.slots[slot].opcode =
10887                         xtensa_format_slot_nop_opcode (isa, fmt, slot);
10888                       cur_vinsn.slots[slot].ntok = 0;
10889                     }
10890                   vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, true);
10891                   xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf,
10892                                            (unsigned char *) immed_instr, 0);
10893                   fragP->tc_frag_data.is_insn = true;
10894                   size = xtensa_format_length (isa, fmt);
10895                   if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
10896                     {
10897                       xg_emit_insn_to_buf
10898                         (tinsn, immed_instr + size, fragP,
10899                          immed_instr - fragP->fr_literal + size, true);
10900                       size += xg_get_single_size (tinsn->opcode);
10901                     }
10902                 }
10903               else
10904                 {
10905                   size = xg_get_single_size (tinsn->opcode);
10906                   xg_emit_insn_to_buf (tinsn, immed_instr, fragP,
10907                                        immed_instr - fragP->fr_literal, true);
10908                 }
10909               immed_instr += size;
10910               total_size += size;
10911               break;
10912             }
10913         }
10914
10915       diff = total_size - old_size;
10916       gas_assert (diff >= 0);
10917       if (diff != 0)
10918         expanded = true;
10919       gas_assert (diff <= fragP->fr_var);
10920       fragP->fr_var -= diff;
10921       fragP->fr_fix += diff;
10922     }
10923
10924   /* Check for undefined immediates in LOOP instructions.  */
10925   if (is_loop)
10926     {
10927       symbolS *sym;
10928       sym = orig_tinsn.tok[1].X_add_symbol;
10929       if (sym != NULL && !S_IS_DEFINED (sym))
10930         {
10931           as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10932           return;
10933         }
10934       sym = orig_tinsn.tok[1].X_op_symbol;
10935       if (sym != NULL && !S_IS_DEFINED (sym))
10936         {
10937           as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
10938           return;
10939         }
10940     }
10941
10942   if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
10943     {
10944       /* Add an expansion note on the expanded instruction.  */
10945       fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
10946                           &orig_tinsn.tok[0], true,
10947                           BFD_RELOC_XTENSA_ASM_EXPAND);
10948     }
10949 }
10950
10951
10952 /* Add a new fix expression into the desired segment.  We have to
10953    switch to that segment to do this.  */
10954
10955 static fixS *
10956 fix_new_exp_in_seg (segT new_seg,
10957                     subsegT new_subseg,
10958                     fragS *frag,
10959                     int where,
10960                     int size,
10961                     expressionS *exp,
10962                     int pcrel,
10963                     bfd_reloc_code_real_type r_type)
10964 {
10965   fixS *new_fix;
10966   segT seg = now_seg;
10967   subsegT subseg = now_subseg;
10968
10969   gas_assert (new_seg != 0);
10970   subseg_set (new_seg, new_subseg);
10971
10972   new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
10973   subseg_set (seg, subseg);
10974   return new_fix;
10975 }
10976
10977
10978 \f
10979 /* A map that keeps information on a per-subsegment basis.  This is
10980    maintained during initial assembly, but is invalid once the
10981    subsegments are smashed together.  I.E., it cannot be used during
10982    the relaxation.  */
10983
10984 typedef struct subseg_map_struct
10985 {
10986   /* the key */
10987   segT seg;
10988   subsegT subseg;
10989
10990   /* the data */
10991   unsigned flags;
10992   float total_freq;     /* fall-through + branch target frequency */
10993   float target_freq;    /* branch target frequency alone */
10994
10995   struct subseg_map_struct *next;
10996 } subseg_map;
10997
10998
10999 static subseg_map *sseg_map = NULL;
11000
11001 static subseg_map *
11002 get_subseg_info (segT seg, subsegT subseg)
11003 {
11004   subseg_map *subseg_e;
11005
11006   for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
11007     {
11008       if (seg == subseg_e->seg && subseg == subseg_e->subseg)
11009         break;
11010     }
11011   return subseg_e;
11012 }
11013
11014
11015 static subseg_map *
11016 add_subseg_info (segT seg, subsegT subseg)
11017 {
11018   subseg_map *subseg_e = XNEW (subseg_map);
11019   memset (subseg_e, 0, sizeof (subseg_map));
11020   subseg_e->seg = seg;
11021   subseg_e->subseg = subseg;
11022   subseg_e->flags = 0;
11023   /* Start off considering every branch target very important.  */
11024   subseg_e->target_freq = 1.0;
11025   subseg_e->total_freq = 1.0;
11026   subseg_e->next = sseg_map;
11027   sseg_map = subseg_e;
11028   return subseg_e;
11029 }
11030
11031
11032 static unsigned
11033 get_last_insn_flags (segT seg, subsegT subseg)
11034 {
11035   subseg_map *subseg_e = get_subseg_info (seg, subseg);
11036   if (subseg_e)
11037     return subseg_e->flags;
11038   return 0;
11039 }
11040
11041
11042 static void
11043 set_last_insn_flags (segT seg,
11044                      subsegT subseg,
11045                      unsigned fl,
11046                      bool val)
11047 {
11048   subseg_map *subseg_e = get_subseg_info (seg, subseg);
11049   if (! subseg_e)
11050     subseg_e = add_subseg_info (seg, subseg);
11051   if (val)
11052     subseg_e->flags |= fl;
11053   else
11054     subseg_e->flags &= ~fl;
11055 }
11056
11057
11058 static float
11059 get_subseg_total_freq (segT seg, subsegT subseg)
11060 {
11061   subseg_map *subseg_e = get_subseg_info (seg, subseg);
11062   if (subseg_e)
11063     return subseg_e->total_freq;
11064   return 1.0;
11065 }
11066
11067
11068 static float
11069 get_subseg_target_freq (segT seg, subsegT subseg)
11070 {
11071   subseg_map *subseg_e = get_subseg_info (seg, subseg);
11072   if (subseg_e)
11073     return subseg_e->target_freq;
11074   return 1.0;
11075 }
11076
11077
11078 static void
11079 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
11080 {
11081   subseg_map *subseg_e = get_subseg_info (seg, subseg);
11082   if (! subseg_e)
11083     subseg_e = add_subseg_info (seg, subseg);
11084   subseg_e->total_freq = total_f;
11085   subseg_e->target_freq = target_f;
11086 }
11087
11088 \f
11089 /* Segment Lists and emit_state Stuff.  */
11090
11091 static void
11092 xtensa_move_seg_list_to_beginning (seg_list *head)
11093 {
11094   head = head->next;
11095   while (head)
11096     {
11097       segT literal_section = head->seg;
11098
11099       /* Move the literal section to the front of the section list.  */
11100       gas_assert (literal_section);
11101       if (literal_section != stdoutput->sections)
11102         {
11103           bfd_section_list_remove (stdoutput, literal_section);
11104           bfd_section_list_prepend (stdoutput, literal_section);
11105         }
11106       head = head->next;
11107     }
11108 }
11109
11110
11111 static void mark_literal_frags (seg_list *);
11112
11113 static void
11114 xg_promote_candidate_litpool (struct litpool_seg *lps,
11115                               struct litpool_frag *lp)
11116 {
11117   fragS *poolbeg;
11118   fragS *poolend;
11119   symbolS *lsym;
11120   char label[10 + 2 * sizeof (fragS *)];
11121
11122   poolbeg = lp->fragP;
11123   lp->priority = 1;
11124   poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN;
11125   poolend = poolbeg->fr_next;
11126   gas_assert (poolend->fr_type == rs_machine_dependent &&
11127               poolend->fr_subtype == RELAX_LITERAL_POOL_END);
11128   /* Create a local symbol pointing to the
11129      end of the pool.  */
11130   sprintf (label, ".L0_LT_%p", poolbeg);
11131   lsym = (symbolS *) local_symbol_make (label, lps->seg, poolend, 0);
11132   poolbeg->fr_symbol = lsym;
11133   /* Rest is done in xtensa_relax_frag.  */
11134 }
11135
11136 static struct litpool_frag *xg_find_litpool (struct litpool_seg *lps,
11137                                              struct litpool_frag *lpf,
11138                                              addressT addr)
11139 {
11140   struct litpool_frag *lp = lpf->prev;
11141
11142   gas_assert (lp->fragP);
11143
11144   while (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
11145     {
11146       lp = lp->prev;
11147       if (lp->fragP == NULL)
11148         {
11149           /* End of list; have to bite the bullet.
11150              Take the nearest.  */
11151           lp = lpf->prev;
11152           break;
11153         }
11154       /* Does it (conservatively) reach?  */
11155       if (addr - lp->addr <= 128 * 1024)
11156         {
11157           if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN &&
11158               lp->literal_count < MAX_POOL_LITERALS)
11159             {
11160               /* Found a good one.  */
11161               break;
11162             }
11163           else if (lp->prev->fragP &&
11164                    addr - lp->prev->addr > 128 * 1024 &&
11165                    lp->prev->literal_count < MAX_POOL_LITERALS)
11166             {
11167               /* This is still a "candidate" but the next one
11168                  will be too far away, so revert to the nearest
11169                  one, convert it and add the jump around.  */
11170               lp = lpf->prev;
11171               break;
11172             }
11173         }
11174     }
11175
11176   if (lp->literal_count >= MAX_POOL_LITERALS)
11177     {
11178       lp = lpf->prev;
11179       while (lp && lp->fragP && lp->literal_count >= MAX_POOL_LITERALS)
11180         {
11181           lp = lp->prev;
11182         }
11183       gas_assert (lp);
11184     }
11185
11186   gas_assert (lp && lp->fragP && lp->literal_count < MAX_POOL_LITERALS);
11187   ++lp->literal_count;
11188
11189   /* Convert candidate and add the jump around.  */
11190   if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)
11191     xg_promote_candidate_litpool (lps, lp);
11192
11193   return lp;
11194 }
11195
11196 static bool xtensa_is_init_fini (segT seg)
11197 {
11198   if (!seg)
11199     return 0;
11200   return strcmp (segment_name (seg), INIT_SECTION_NAME) == 0
11201     || strcmp (segment_name (seg), FINI_SECTION_NAME) == 0;
11202 }
11203
11204 static void
11205 xtensa_assign_litpool_addresses (void)
11206 {
11207   struct litpool_seg *lps;
11208
11209   for (lps = litpool_seg_list.next; lps; lps = lps->next)
11210     {
11211       frchainS *frchP = seg_info (lps->seg)->frchainP;
11212       struct litpool_frag *lpf = lps->frag_list.next;
11213       addressT addr = 0;
11214
11215       if (xtensa_is_init_fini (lps->seg))
11216         continue;
11217
11218       for ( ; frchP; frchP = frchP->frch_next)
11219         {
11220           fragS *fragP;
11221           for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
11222             {
11223               if (lpf && fragP == lpf->fragP)
11224                 {
11225                   gas_assert(fragP->fr_type == rs_machine_dependent &&
11226                              (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN ||
11227                               fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN));
11228                   /* Found a litpool location.  */
11229                   lpf->addr = addr;
11230                   lpf = lpf->next;
11231                 }
11232               if (fragP->fr_type == rs_machine_dependent &&
11233                   fragP->fr_subtype == RELAX_SLOTS)
11234                 {
11235                   int slot;
11236                   for (slot = 0; slot < MAX_SLOTS; slot++)
11237                     {
11238                       fragS *litfrag = fragP->tc_frag_data.literal_frags[slot];
11239
11240                       if (litfrag
11241                           && litfrag->tc_frag_data.is_literal
11242                           && !litfrag->tc_frag_data.literal_frag)
11243                         {
11244                           /* L32R referring .literal or generated as a result
11245                              of relaxation.  Point its literal to the nearest
11246                              litpool preferring non-"candidate" positions to
11247                              avoid the jump-around.  */
11248
11249                           struct litpool_frag *lp;
11250
11251                           lp = xg_find_litpool (lps, lpf, addr);
11252                           /* Take earliest use of this literal to avoid
11253                              forward refs.  */
11254                           litfrag->tc_frag_data.literal_frag = lp->fragP;
11255                         }
11256                     }
11257                 }
11258               addr += fragP->fr_fix;
11259               if (fragP->fr_type == rs_fill)
11260                 addr += fragP->fr_offset;
11261             }
11262         }
11263     }
11264 }
11265
11266 static void
11267 xtensa_move_literals (void)
11268 {
11269   seg_list *segment;
11270   frchainS *frchain_from, *frchain_to;
11271   fragS *search_frag, *next_frag, *literal_pool, *insert_after;
11272   fragS **frag_splice;
11273   emit_state state;
11274   segT dest_seg;
11275   fixS *fix, *next_fix, **fix_splice;
11276   sym_list *lit;
11277   const char *init_name = INIT_SECTION_NAME;
11278   const char *fini_name = FINI_SECTION_NAME;
11279   int init_name_len = strlen(init_name);
11280   int fini_name_len = strlen(fini_name);
11281
11282   mark_literal_frags (literal_head->next);
11283
11284   if (use_literal_section)
11285     return;
11286
11287   /* Assign addresses (rough estimates) to the potential literal pool locations
11288      and create new ones if the gaps are too large.  */
11289
11290   xtensa_assign_litpool_addresses ();
11291
11292   /* Walk through the literal segments.  */
11293   for (segment = literal_head->next; segment; segment = segment->next)
11294     {
11295       const char *seg_name = segment_name (segment->seg);
11296
11297       /* Keep the literals for .init and .fini in separate sections.  */
11298       if ((!memcmp (seg_name, init_name, init_name_len) &&
11299            !strcmp (seg_name + init_name_len, ".literal")) ||
11300           (!memcmp (seg_name, fini_name, fini_name_len) &&
11301            !strcmp (seg_name + fini_name_len, ".literal")))
11302         continue;
11303
11304       frchain_from = seg_info (segment->seg)->frchainP;
11305       search_frag = frchain_from->frch_root;
11306       literal_pool = NULL;
11307       frchain_to = NULL;
11308       frag_splice = &(frchain_from->frch_root);
11309
11310       while (search_frag && !search_frag->tc_frag_data.literal_frag)
11311         {
11312           gas_assert (search_frag->fr_fix == 0
11313                   || search_frag->fr_type == rs_align);
11314           search_frag = search_frag->fr_next;
11315         }
11316
11317       if (!search_frag)
11318         continue;
11319
11320       gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype
11321               == RELAX_LITERAL_POOL_BEGIN);
11322       xtensa_switch_section_emit_state (&state, segment->seg, 0);
11323
11324       /* Make sure that all the frags in this series are closed, and
11325          that there is at least one left over of zero-size.  This
11326          prevents us from making a segment with an frchain without any
11327          frags in it.  */
11328       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11329       xtensa_set_frag_assembly_state (frag_now);
11330       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11331       xtensa_set_frag_assembly_state (frag_now);
11332
11333       while (search_frag != frag_now)
11334         {
11335           next_frag = search_frag->fr_next;
11336           if (search_frag->tc_frag_data.literal_frag)
11337             {
11338               literal_pool = search_frag->tc_frag_data.literal_frag;
11339               gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
11340               frchain_to = literal_pool->tc_frag_data.lit_frchain;
11341               gas_assert (frchain_to);
11342             }
11343
11344           if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0)
11345             {
11346               /* Skip empty fill frags.  */
11347               *frag_splice = next_frag;
11348               search_frag = next_frag;
11349               continue;
11350             }
11351
11352           if (search_frag->fr_type == rs_align)
11353             {
11354               /* Skip alignment frags, because the pool as a whole will be
11355                  aligned if used, and we don't want to force alignment if the
11356                  pool is unused.  */
11357               *frag_splice = next_frag;
11358               search_frag = next_frag;
11359               continue;
11360             }
11361
11362           /* First, move the frag out of the literal section and
11363              to the appropriate place.  */
11364
11365           /* Insert an alignment frag at start of pool.  */
11366           if (literal_pool->fr_next->fr_type == rs_machine_dependent &&
11367               literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END)
11368             {
11369               segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg;
11370               emit_state prev_state;
11371               fragS *prev_frag;
11372               fragS *align_frag;
11373               xtensa_switch_section_emit_state (&prev_state, pool_seg, 0);
11374               prev_frag = frag_now;
11375               frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11376               align_frag = frag_now;
11377               frag_align (2, 0, 0);
11378               /* Splice it into the right place.  */
11379               prev_frag->fr_next = align_frag->fr_next;
11380               align_frag->fr_next = literal_pool->fr_next;
11381               literal_pool->fr_next = align_frag;
11382               /* Insert after this one.  */
11383               literal_pool->tc_frag_data.literal_frag = align_frag;
11384               xtensa_restore_emit_state (&prev_state);
11385             }
11386           insert_after = literal_pool->tc_frag_data.literal_frag;
11387           dest_seg = insert_after->fr_next->tc_frag_data.lit_seg;
11388           /* Skip align frag.  */
11389           if (insert_after->fr_next->fr_type == rs_align)
11390             {
11391               insert_after = insert_after->fr_next;
11392             }
11393
11394           *frag_splice = next_frag;
11395           search_frag->fr_next = insert_after->fr_next;
11396           insert_after->fr_next = search_frag;
11397           search_frag->tc_frag_data.lit_seg = dest_seg;
11398           literal_pool->tc_frag_data.literal_frag = search_frag;
11399
11400           /* Now move any fixups associated with this frag to the
11401              right section.  */
11402           fix = frchain_from->fix_root;
11403           fix_splice = &(frchain_from->fix_root);
11404           while (fix)
11405             {
11406               next_fix = fix->fx_next;
11407               if (fix->fx_frag == search_frag)
11408                 {
11409                   *fix_splice = next_fix;
11410                   fix->fx_next = frchain_to->fix_root;
11411                   frchain_to->fix_root = fix;
11412                   if (frchain_to->fix_tail == NULL)
11413                     frchain_to->fix_tail = fix;
11414                 }
11415               else
11416                 fix_splice = &(fix->fx_next);
11417               fix = next_fix;
11418             }
11419           search_frag = next_frag;
11420         }
11421
11422       if (frchain_from->fix_root != NULL)
11423         {
11424           frchain_from = seg_info (segment->seg)->frchainP;
11425           as_warn (_("fixes not all moved from %s"), segment->seg->name);
11426
11427           gas_assert (frchain_from->fix_root == NULL);
11428         }
11429       frchain_from->fix_tail = NULL;
11430       xtensa_restore_emit_state (&state);
11431     }
11432
11433   /* Now fix up the SEGMENT value for all the literal symbols.  */
11434   for (lit = literal_syms; lit; lit = lit->next)
11435     {
11436       symbolS *lit_sym = lit->sym;
11437       segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
11438       if (dseg)
11439         S_SET_SEGMENT (lit_sym, dseg);
11440     }
11441 }
11442
11443
11444 /* Walk over all the frags for segments in a list and mark them as
11445    containing literals.  As clunky as this is, we can't rely on frag_var
11446    and frag_variant to get called in all situations.  */
11447
11448 static void
11449 mark_literal_frags (seg_list *segment)
11450 {
11451   frchainS *frchain_from;
11452   fragS *search_frag;
11453
11454   while (segment)
11455     {
11456       frchain_from = seg_info (segment->seg)->frchainP;
11457       search_frag = frchain_from->frch_root;
11458       while (search_frag)
11459         {
11460           search_frag->tc_frag_data.is_literal = true;
11461           search_frag = search_frag->fr_next;
11462         }
11463       segment = segment->next;
11464     }
11465 }
11466
11467
11468 static void
11469 xtensa_reorder_seg_list (seg_list *head, segT after)
11470 {
11471   /* Move all of the sections in the section list to come
11472      after "after" in the gnu segment list.  */
11473
11474   head = head->next;
11475   while (head)
11476     {
11477       segT literal_section = head->seg;
11478
11479       /* Move the literal section after "after".  */
11480       gas_assert (literal_section);
11481       if (literal_section != after)
11482         {
11483           bfd_section_list_remove (stdoutput, literal_section);
11484           bfd_section_list_insert_after (stdoutput, after, literal_section);
11485         }
11486
11487       head = head->next;
11488     }
11489 }
11490
11491
11492 /* Push all the literal segments to the end of the gnu list.  */
11493
11494 static void
11495 xtensa_reorder_segments (void)
11496 {
11497   segT sec;
11498   segT last_sec = 0;
11499   int old_count = 0;
11500   int new_count = 0;
11501
11502   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
11503     {
11504       last_sec = sec;
11505       old_count++;
11506     }
11507
11508   /* Now that we have the last section, push all the literal
11509      sections to the end.  */
11510   xtensa_reorder_seg_list (literal_head, last_sec);
11511
11512   /* Now perform the final error check.  */
11513   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
11514     new_count++;
11515   gas_assert (new_count == old_count);
11516 }
11517
11518
11519 /* Change the emit state (seg, subseg, and frag related stuff) to the
11520    correct location.  Return a emit_state which can be passed to
11521    xtensa_restore_emit_state to return to current fragment.  */
11522
11523 static void
11524 xtensa_switch_to_literal_fragment (emit_state *result)
11525 {
11526   if (directive_state[directive_absolute_literals])
11527     {
11528       segT lit4_seg = cache_literal_section (true);
11529       xtensa_switch_section_emit_state (result, lit4_seg, 0);
11530     }
11531   else
11532     xtensa_switch_to_non_abs_literal_fragment (result);
11533
11534   /* Do a 4-byte align here.  */
11535   frag_align (2, 0, 0);
11536   record_alignment (now_seg, 2);
11537 }
11538
11539
11540 static void
11541 xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
11542 {
11543   fragS *pool_location = get_literal_pool_location (now_seg);
11544   segT lit_seg;
11545   bool is_init_fini = xtensa_is_init_fini (now_seg);
11546
11547   if (pool_location == NULL
11548       && !use_literal_section
11549       && !is_init_fini)
11550     {
11551       if (!auto_litpools)
11552         {
11553           as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11554         }
11555       xtensa_maybe_create_literal_pool_frag (true, true);
11556       pool_location = get_literal_pool_location (now_seg);
11557     }
11558
11559   lit_seg = cache_literal_section (false);
11560   xtensa_switch_section_emit_state (result, lit_seg, 0);
11561
11562   if (!use_literal_section
11563       && !is_init_fini
11564       && get_literal_pool_location (now_seg) != pool_location)
11565     {
11566       /* Close whatever frag is there.  */
11567       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11568       xtensa_set_frag_assembly_state (frag_now);
11569       frag_now->tc_frag_data.literal_frag = pool_location;
11570       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
11571       xtensa_set_frag_assembly_state (frag_now);
11572     }
11573 }
11574
11575
11576 /* Call this function before emitting data into the literal section.
11577    This is a helper function for xtensa_switch_to_literal_fragment.
11578    This is similar to a .section new_now_seg subseg. */
11579
11580 static void
11581 xtensa_switch_section_emit_state (emit_state *state,
11582                                   segT new_now_seg,
11583                                   subsegT new_now_subseg)
11584 {
11585   state->name = now_seg->name;
11586   state->now_seg = now_seg;
11587   state->now_subseg = now_subseg;
11588   state->generating_literals = generating_literals;
11589   generating_literals++;
11590   subseg_set (new_now_seg, new_now_subseg);
11591 }
11592
11593
11594 /* Use to restore the emitting into the normal place.  */
11595
11596 static void
11597 xtensa_restore_emit_state (emit_state *state)
11598 {
11599   generating_literals = state->generating_literals;
11600   subseg_set (state->now_seg, state->now_subseg);
11601 }
11602
11603
11604 /* Predicate function used to look up a section in a particular group.  */
11605
11606 static bool
11607 match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
11608 {
11609   const char *gname = inf;
11610   const char *group_name = elf_group_name (sec);
11611
11612   return (group_name == gname
11613           || (group_name != NULL
11614               && gname != NULL
11615               && strcmp (group_name, gname) == 0));
11616 }
11617
11618
11619 /* Get the literal section to be used for the current text section.
11620    The result may be cached in the default_lit_sections structure.  */
11621
11622 static segT
11623 cache_literal_section (bool use_abs_literals)
11624 {
11625   const char *text_name, *group_name = 0;
11626   const char *base_name, *suffix;
11627   char *name;
11628   segT *pcached;
11629   segT seg, current_section;
11630   int current_subsec;
11631   bool linkonce = false;
11632
11633   /* Save the current section/subsection.  */
11634   current_section = now_seg;
11635   current_subsec = now_subseg;
11636
11637   /* Clear the cached values if they are no longer valid.  */
11638   if (now_seg != default_lit_sections.current_text_seg)
11639     {
11640       default_lit_sections.current_text_seg = now_seg;
11641       default_lit_sections.lit_seg = NULL;
11642       default_lit_sections.lit4_seg = NULL;
11643     }
11644
11645   /* Check if the literal section is already cached.  */
11646   if (use_abs_literals)
11647     pcached = &default_lit_sections.lit4_seg;
11648   else
11649     pcached = &default_lit_sections.lit_seg;
11650
11651   if (*pcached)
11652     return *pcached;
11653
11654   text_name = default_lit_sections.lit_prefix;
11655   if (! text_name || ! *text_name)
11656     {
11657       text_name = segment_name (current_section);
11658       group_name = elf_group_name (current_section);
11659       linkonce = (current_section->flags & SEC_LINK_ONCE) != 0;
11660     }
11661
11662   base_name = use_abs_literals ? ".lit4" : ".literal";
11663   if (group_name)
11664     {
11665       name = concat (base_name, ".", group_name, (char *) NULL);
11666     }
11667   else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0)
11668     {
11669       suffix = strchr (text_name + linkonce_len, '.');
11670
11671       name = concat (".gnu.linkonce", base_name, suffix ? suffix : "",
11672                      (char *) NULL);
11673       linkonce = true;
11674     }
11675   else
11676     {
11677       /* If the section name begins or ends with ".text", then replace
11678          that portion instead of appending an additional suffix.  */
11679       size_t len = strlen (text_name);
11680       if (len >= 5
11681           && (strcmp (text_name + len - 5, ".text") == 0
11682               || startswith (text_name, ".text")))
11683         len -= 5;
11684
11685       name = XNEWVEC (char, len + strlen (base_name) + 1);
11686       if (startswith (text_name, ".text"))
11687         {
11688           strcpy (name, base_name);
11689           strcat (name, text_name + 5);
11690         }
11691       else
11692         {
11693           strcpy (name, text_name);
11694           strcpy (name + len, base_name);
11695         }
11696     }
11697
11698   /* Canonicalize section names to allow renaming literal sections.
11699      The group name, if any, came from the current text section and
11700      has already been canonicalized.  */
11701   name = tc_canonicalize_symbol_name (name);
11702
11703   seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group,
11704                                     (void *) group_name);
11705   if (! seg)
11706     {
11707       flagword flags;
11708
11709       seg = subseg_force_new (name, 0);
11710
11711       if (! use_abs_literals)
11712         {
11713           /* Add the newly created literal segment to the list.  */
11714           seg_list *n = XNEW (seg_list);
11715           n->seg = seg;
11716           n->next = literal_head->next;
11717           literal_head->next = n;
11718         }
11719
11720       flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD
11721                | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0)
11722                | (use_abs_literals ? SEC_DATA : SEC_CODE));
11723
11724       elf_group_name (seg) = group_name;
11725
11726       bfd_set_section_flags (seg, flags);
11727       bfd_set_section_alignment (seg, 2);
11728     }
11729
11730   *pcached = seg;
11731   subseg_set (current_section, current_subsec);
11732   return seg;
11733 }
11734
11735 \f
11736 /* Property Tables Stuff.  */
11737
11738 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11739 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11740 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11741
11742 typedef bool (*frag_predicate) (const fragS *);
11743 typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
11744
11745 static bool get_frag_is_literal (const fragS *);
11746 static void xtensa_create_property_segments
11747   (frag_predicate, frag_predicate, const char *, xt_section_type);
11748 static void xtensa_create_xproperty_segments
11749   (frag_flags_fn, const char *, xt_section_type);
11750 static bool exclude_section_from_property_tables (segT);
11751 static bool section_has_property (segT, frag_predicate);
11752 static bool section_has_xproperty (segT, frag_flags_fn);
11753 static void add_xt_block_frags
11754   (segT, xtensa_block_info **, frag_predicate, frag_predicate);
11755 static bool xtensa_frag_flags_is_empty (const frag_flags *);
11756 static void xtensa_frag_flags_init (frag_flags *);
11757 static void get_frag_property_flags (const fragS *, frag_flags *);
11758 static flagword frag_flags_to_number (const frag_flags *);
11759 static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn);
11760
11761 /* Set up property tables after relaxation.  */
11762
11763 void
11764 xtensa_post_relax_hook (void)
11765 {
11766   xtensa_move_seg_list_to_beginning (literal_head);
11767
11768   xtensa_find_unmarked_state_frags ();
11769   xtensa_mark_frags_for_org ();
11770   xtensa_mark_difference_of_two_symbols ();
11771
11772   xtensa_create_property_segments (get_frag_is_literal,
11773                                    NULL,
11774                                    XTENSA_LIT_SEC_NAME,
11775                                    xt_literal_sec);
11776   xtensa_create_xproperty_segments (get_frag_property_flags,
11777                                     XTENSA_PROP_SEC_NAME,
11778                                     xt_prop_sec);
11779
11780   if (warn_unaligned_branch_targets)
11781     bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
11782   bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
11783 }
11784
11785
11786 /* This function is only meaningful after xtensa_move_literals.  */
11787
11788 static bool
11789 get_frag_is_literal (const fragS *fragP)
11790 {
11791   gas_assert (fragP != NULL);
11792   return fragP->tc_frag_data.is_literal;
11793 }
11794
11795
11796 static void
11797 xtensa_create_property_segments (frag_predicate property_function,
11798                                  frag_predicate end_property_function,
11799                                  const char *section_name_base,
11800                                  xt_section_type sec_type)
11801 {
11802   segT *seclist;
11803
11804   /* Walk over all of the current segments.
11805      Walk over each fragment
11806      For each non-empty fragment,
11807      Build a property record (append where possible).  */
11808
11809   for (seclist = &stdoutput->sections;
11810        seclist && *seclist;
11811        seclist = &(*seclist)->next)
11812     {
11813       segT sec = *seclist;
11814
11815       if (exclude_section_from_property_tables (sec))
11816         continue;
11817
11818       if (section_has_property (sec, property_function))
11819         {
11820           segment_info_type *xt_seg_info;
11821           xtensa_block_info **xt_blocks;
11822           segT prop_sec = xtensa_make_property_section (sec, section_name_base);
11823
11824           prop_sec->output_section = prop_sec;
11825           subseg_set (prop_sec, 0);
11826           xt_seg_info = seg_info (prop_sec);
11827           xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
11828
11829           /* Walk over all of the frchains here and add new sections.  */
11830           add_xt_block_frags (sec, xt_blocks, property_function,
11831                               end_property_function);
11832         }
11833     }
11834
11835   /* Now we fill them out....  */
11836
11837   for (seclist = &stdoutput->sections;
11838        seclist && *seclist;
11839        seclist = &(*seclist)->next)
11840     {
11841       segment_info_type *seginfo;
11842       xtensa_block_info *block;
11843       segT sec = *seclist;
11844
11845       seginfo = seg_info (sec);
11846       block = seginfo->tc_segment_info_data.blocks[sec_type];
11847
11848       if (block)
11849         {
11850           xtensa_block_info *cur_block;
11851           int num_recs = 0;
11852           bfd_size_type rec_size;
11853
11854           for (cur_block = block; cur_block; cur_block = cur_block->next)
11855             num_recs++;
11856
11857           rec_size = num_recs * 8;
11858           bfd_set_section_size (sec, rec_size);
11859
11860           if (num_recs)
11861             {
11862               char *frag_data;
11863               int i;
11864
11865               subseg_set (sec, 0);
11866               frag_data = frag_more (rec_size);
11867               cur_block = block;
11868               for (i = 0; i < num_recs; i++)
11869                 {
11870                   fixS *fix;
11871
11872                   /* Write the fixup.  */
11873                   gas_assert (cur_block);
11874                   fix = fix_new (frag_now, i * 8, 4,
11875                                  section_symbol (cur_block->sec),
11876                                  cur_block->offset,
11877                                  false, BFD_RELOC_32);
11878                   fix->fx_file = "<internal>";
11879                   fix->fx_line = 0;
11880
11881                   /* Write the length.  */
11882                   md_number_to_chars (&frag_data[4 + i * 8],
11883                                       cur_block->size, 4);
11884                   cur_block = cur_block->next;
11885                 }
11886               frag_wane (frag_now);
11887               frag_new (0);
11888               frag_wane (frag_now);
11889             }
11890         }
11891     }
11892 }
11893
11894
11895 static void
11896 xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
11897                                   const char *section_name_base,
11898                                   xt_section_type sec_type)
11899 {
11900   segT *seclist;
11901
11902   /* Walk over all of the current segments.
11903      Walk over each fragment.
11904      For each fragment that has instructions,
11905      build an instruction record (append where possible).  */
11906
11907   for (seclist = &stdoutput->sections;
11908        seclist && *seclist;
11909        seclist = &(*seclist)->next)
11910     {
11911       segT sec = *seclist;
11912
11913       if (exclude_section_from_property_tables (sec))
11914         continue;
11915
11916       if (section_has_xproperty (sec, flag_fn))
11917         {
11918           segment_info_type *xt_seg_info;
11919           xtensa_block_info **xt_blocks;
11920           segT prop_sec = xtensa_make_property_section (sec, section_name_base);
11921
11922           prop_sec->output_section = prop_sec;
11923           subseg_set (prop_sec, 0);
11924           xt_seg_info = seg_info (prop_sec);
11925           xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type];
11926
11927           /* Walk over all of the frchains here and add new sections.  */
11928           add_xt_prop_frags (sec, xt_blocks, flag_fn);
11929         }
11930     }
11931
11932   /* Now we fill them out....  */
11933
11934   for (seclist = &stdoutput->sections;
11935        seclist && *seclist;
11936        seclist = &(*seclist)->next)
11937     {
11938       segment_info_type *seginfo;
11939       xtensa_block_info *block;
11940       segT sec = *seclist;
11941
11942       seginfo = seg_info (sec);
11943       block = seginfo->tc_segment_info_data.blocks[sec_type];
11944
11945       if (block)
11946         {
11947           xtensa_block_info *cur_block;
11948           int num_recs = 0;
11949           bfd_size_type rec_size;
11950
11951           for (cur_block = block; cur_block; cur_block = cur_block->next)
11952             num_recs++;
11953
11954           rec_size = num_recs * (8 + 4);
11955           bfd_set_section_size (sec, rec_size);
11956           /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11957
11958           if (num_recs)
11959             {
11960               char *frag_data;
11961               int i;
11962
11963               subseg_set (sec, 0);
11964               frag_data = frag_more (rec_size);
11965               cur_block = block;
11966               for (i = 0; i < num_recs; i++)
11967                 {
11968                   fixS *fix;
11969
11970                   /* Write the fixup.  */
11971                   gas_assert (cur_block);
11972                   fix = fix_new (frag_now, i * 12, 4,
11973                                  section_symbol (cur_block->sec),
11974                                  cur_block->offset,
11975                                  false, BFD_RELOC_32);
11976                   fix->fx_file = "<internal>";
11977                   fix->fx_line = 0;
11978
11979                   /* Write the length.  */
11980                   md_number_to_chars (&frag_data[4 + i * 12],
11981                                       cur_block->size, 4);
11982                   md_number_to_chars (&frag_data[8 + i * 12],
11983                                       frag_flags_to_number (&cur_block->flags),
11984                                       sizeof (flagword));
11985                   cur_block = cur_block->next;
11986                 }
11987               frag_wane (frag_now);
11988               frag_new (0);
11989               frag_wane (frag_now);
11990             }
11991         }
11992     }
11993 }
11994
11995
11996 static bool
11997 exclude_section_from_property_tables (segT sec)
11998 {
11999   flagword flags = bfd_section_flags (sec);
12000
12001   /* Sections that don't contribute to the memory footprint are excluded.  */
12002   if ((flags & SEC_DEBUGGING)
12003       || !(flags & SEC_ALLOC)
12004       || (flags & SEC_MERGE))
12005     return true;
12006
12007   /* Linker cie and fde optimizations mess up property entries for
12008      eh_frame sections, but there is nothing inside them relevant to
12009      property tables anyway.  */
12010   if (strcmp (sec->name, ".eh_frame") == 0)
12011     return true;
12012
12013   return false;
12014 }
12015
12016
12017 static bool
12018 section_has_property (segT sec, frag_predicate property_function)
12019 {
12020   segment_info_type *seginfo = seg_info (sec);
12021   fragS *fragP;
12022
12023   if (seginfo && seginfo->frchainP)
12024     {
12025       for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
12026         {
12027           if (property_function (fragP)
12028               && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
12029             return true;
12030         }
12031     }
12032   return false;
12033 }
12034
12035
12036 static bool
12037 section_has_xproperty (segT sec, frag_flags_fn property_function)
12038 {
12039   segment_info_type *seginfo = seg_info (sec);
12040   fragS *fragP;
12041
12042   if (seginfo && seginfo->frchainP)
12043     {
12044       for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
12045         {
12046           frag_flags prop_flags;
12047           property_function (fragP, &prop_flags);
12048           if (!xtensa_frag_flags_is_empty (&prop_flags))
12049             return true;
12050         }
12051     }
12052   return false;
12053 }
12054
12055
12056 /* Two types of block sections exist right now: literal and insns.  */
12057
12058 static void
12059 add_xt_block_frags (segT sec,
12060                     xtensa_block_info **xt_block,
12061                     frag_predicate property_function,
12062                     frag_predicate end_property_function)
12063 {
12064   fragS *fragP;
12065
12066   /* Build it if needed.  */
12067   while (*xt_block != NULL)
12068     xt_block = &(*xt_block)->next;
12069   /* We are either at NULL at the beginning or at the end.  */
12070
12071   /* Walk through the frags.  */
12072   if (seg_info (sec)->frchainP)
12073     {
12074       for (fragP = seg_info (sec)->frchainP->frch_root;
12075            fragP;
12076            fragP = fragP->fr_next)
12077         {
12078           if (property_function (fragP)
12079               && (fragP->fr_type != rs_fill || fragP->fr_fix != 0))
12080             {
12081               if (*xt_block != NULL)
12082                 {
12083                   if ((*xt_block)->offset + (*xt_block)->size
12084                       == fragP->fr_address)
12085                     (*xt_block)->size += fragP->fr_fix;
12086                   else
12087                     xt_block = &((*xt_block)->next);
12088                 }
12089               if (*xt_block == NULL)
12090                 {
12091                   xtensa_block_info *new_block = XNEW (xtensa_block_info);
12092                   new_block->sec = sec;
12093                   new_block->offset = fragP->fr_address;
12094                   new_block->size = fragP->fr_fix;
12095                   new_block->next = NULL;
12096                   xtensa_frag_flags_init (&new_block->flags);
12097                   *xt_block = new_block;
12098                 }
12099               if (end_property_function
12100                   && end_property_function (fragP))
12101                 {
12102                   xt_block = &((*xt_block)->next);
12103                 }
12104             }
12105         }
12106     }
12107 }
12108
12109
12110 /* Break the encapsulation of add_xt_prop_frags here.  */
12111
12112 static bool
12113 xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
12114 {
12115   if (prop_flags->is_literal
12116       || prop_flags->is_insn
12117       || prop_flags->is_data
12118       || prop_flags->is_unreachable)
12119     return false;
12120   return true;
12121 }
12122
12123
12124 static void
12125 xtensa_frag_flags_init (frag_flags *prop_flags)
12126 {
12127   memset (prop_flags, 0, sizeof (frag_flags));
12128 }
12129
12130
12131 static void
12132 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
12133 {
12134   xtensa_frag_flags_init (prop_flags);
12135   if (fragP->tc_frag_data.is_literal)
12136     prop_flags->is_literal = true;
12137   if (fragP->tc_frag_data.is_specific_opcode
12138       || fragP->tc_frag_data.is_no_transform)
12139     {
12140       prop_flags->is_no_transform = true;
12141       if (xtensa_frag_flags_is_empty (prop_flags))
12142         prop_flags->is_data = true;
12143     }
12144   if (fragP->tc_frag_data.is_unreachable)
12145     prop_flags->is_unreachable = true;
12146   else if (fragP->tc_frag_data.is_insn)
12147     {
12148       prop_flags->is_insn = true;
12149       if (fragP->tc_frag_data.is_loop_target)
12150         prop_flags->insn.is_loop_target = true;
12151       if (fragP->tc_frag_data.is_branch_target)
12152         prop_flags->insn.is_branch_target = true;
12153       if (fragP->tc_frag_data.is_no_density)
12154         prop_flags->insn.is_no_density = true;
12155       if (fragP->tc_frag_data.use_absolute_literals)
12156         prop_flags->insn.is_abslit = true;
12157     }
12158   if (fragP->tc_frag_data.is_align)
12159     {
12160       prop_flags->is_align = true;
12161       prop_flags->alignment = fragP->tc_frag_data.alignment;
12162       if (xtensa_frag_flags_is_empty (prop_flags))
12163         prop_flags->is_data = true;
12164     }
12165 }
12166
12167
12168 static flagword
12169 frag_flags_to_number (const frag_flags *prop_flags)
12170 {
12171   flagword num = 0;
12172   if (prop_flags->is_literal)
12173     num |= XTENSA_PROP_LITERAL;
12174   if (prop_flags->is_insn)
12175     num |= XTENSA_PROP_INSN;
12176   if (prop_flags->is_data)
12177     num |= XTENSA_PROP_DATA;
12178   if (prop_flags->is_unreachable)
12179     num |= XTENSA_PROP_UNREACHABLE;
12180   if (prop_flags->insn.is_loop_target)
12181     num |= XTENSA_PROP_INSN_LOOP_TARGET;
12182   if (prop_flags->insn.is_branch_target)
12183     {
12184       num |= XTENSA_PROP_INSN_BRANCH_TARGET;
12185       num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
12186     }
12187
12188   if (prop_flags->insn.is_no_density)
12189     num |= XTENSA_PROP_INSN_NO_DENSITY;
12190   if (prop_flags->is_no_transform)
12191     num |= XTENSA_PROP_NO_TRANSFORM;
12192   if (prop_flags->insn.is_no_reorder)
12193     num |= XTENSA_PROP_INSN_NO_REORDER;
12194   if (prop_flags->insn.is_abslit)
12195     num |= XTENSA_PROP_INSN_ABSLIT;
12196
12197   if (prop_flags->is_align)
12198     {
12199       num |= XTENSA_PROP_ALIGN;
12200       num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
12201     }
12202
12203   return num;
12204 }
12205
12206
12207 static bool
12208 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
12209                               const frag_flags *prop_flags_2)
12210 {
12211   /* Cannot combine with an end marker.  */
12212
12213   if (prop_flags_1->is_literal != prop_flags_2->is_literal)
12214     return false;
12215   if (prop_flags_1->is_insn != prop_flags_2->is_insn)
12216     return false;
12217   if (prop_flags_1->is_data != prop_flags_2->is_data)
12218     return false;
12219
12220   if (prop_flags_1->is_insn)
12221     {
12222       /* Properties of the beginning of the frag.  */
12223       if (prop_flags_2->insn.is_loop_target)
12224         return false;
12225       if (prop_flags_2->insn.is_branch_target)
12226         return false;
12227       if (prop_flags_1->insn.is_no_density !=
12228           prop_flags_2->insn.is_no_density)
12229         return false;
12230       if (prop_flags_1->is_no_transform !=
12231           prop_flags_2->is_no_transform)
12232         return false;
12233       if (prop_flags_1->insn.is_no_reorder !=
12234           prop_flags_2->insn.is_no_reorder)
12235         return false;
12236       if (prop_flags_1->insn.is_abslit !=
12237           prop_flags_2->insn.is_abslit)
12238         return false;
12239     }
12240
12241   if (prop_flags_1->is_align)
12242     return false;
12243
12244   return true;
12245 }
12246
12247
12248 static bfd_vma
12249 xt_block_aligned_size (const xtensa_block_info *xt_block)
12250 {
12251   bfd_vma end_addr;
12252   unsigned align_bits;
12253
12254   if (!xt_block->flags.is_align)
12255     return xt_block->size;
12256
12257   end_addr = xt_block->offset + xt_block->size;
12258   align_bits = xt_block->flags.alignment;
12259   end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
12260   return end_addr - xt_block->offset;
12261 }
12262
12263
12264 static bool
12265 xtensa_xt_block_combine (xtensa_block_info *xt_block,
12266                          const xtensa_block_info *xt_block_2)
12267 {
12268   if (xt_block->sec != xt_block_2->sec)
12269     return false;
12270   if (xt_block->offset + xt_block_aligned_size (xt_block)
12271       != xt_block_2->offset)
12272     return false;
12273
12274   if (xt_block_2->size == 0
12275       && (!xt_block_2->flags.is_unreachable
12276           || xt_block->flags.is_unreachable))
12277     {
12278       if (xt_block_2->flags.is_align
12279           && xt_block->flags.is_align)
12280         {
12281           /* Nothing needed.  */
12282           if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
12283             return true;
12284         }
12285       else
12286         {
12287           if (xt_block_2->flags.is_align)
12288             {
12289               /* Push alignment to previous entry.  */
12290               xt_block->flags.is_align = xt_block_2->flags.is_align;
12291               xt_block->flags.alignment = xt_block_2->flags.alignment;
12292             }
12293           return true;
12294         }
12295     }
12296   if (!xtensa_frag_flags_combinable (&xt_block->flags,
12297                                      &xt_block_2->flags))
12298     return false;
12299
12300   xt_block->size += xt_block_2->size;
12301
12302   if (xt_block_2->flags.is_align)
12303     {
12304       xt_block->flags.is_align = true;
12305       xt_block->flags.alignment = xt_block_2->flags.alignment;
12306     }
12307
12308   return true;
12309 }
12310
12311
12312 static void
12313 add_xt_prop_frags (segT sec,
12314                    xtensa_block_info **xt_block,
12315                    frag_flags_fn property_function)
12316 {
12317   fragS *fragP;
12318
12319   /* Build it if needed.  */
12320   while (*xt_block != NULL)
12321     {
12322       xt_block = &(*xt_block)->next;
12323     }
12324   /* We are either at NULL at the beginning or at the end.  */
12325
12326   /* Walk through the frags.  */
12327   if (seg_info (sec)->frchainP)
12328     {
12329       for (fragP = seg_info (sec)->frchainP->frch_root; fragP;
12330            fragP = fragP->fr_next)
12331         {
12332           xtensa_block_info tmp_block;
12333           tmp_block.sec = sec;
12334           tmp_block.offset = fragP->fr_address;
12335           tmp_block.size = fragP->fr_fix;
12336           tmp_block.next = NULL;
12337           property_function (fragP, &tmp_block.flags);
12338
12339           if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
12340             /* && fragP->fr_fix != 0) */
12341             {
12342               if ((*xt_block) == NULL
12343                   || !xtensa_xt_block_combine (*xt_block, &tmp_block))
12344                 {
12345                   xtensa_block_info *new_block;
12346                   if ((*xt_block) != NULL)
12347                     xt_block = &(*xt_block)->next;
12348                   new_block = XNEW (xtensa_block_info);
12349                   *new_block = tmp_block;
12350                   *xt_block = new_block;
12351                 }
12352             }
12353         }
12354     }
12355 }
12356
12357 \f
12358 /* op_placement_info_table */
12359
12360 /* op_placement_info makes it easier to determine which
12361    ops can go in which slots.  */
12362
12363 static void
12364 init_op_placement_info_table (void)
12365 {
12366   xtensa_isa isa = xtensa_default_isa;
12367   xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
12368   xtensa_opcode opcode;
12369   xtensa_format fmt;
12370   int slot;
12371   int num_opcodes = xtensa_isa_num_opcodes (isa);
12372
12373   op_placement_table = XNEWVEC (op_placement_info, num_opcodes);
12374   gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
12375
12376   for (opcode = 0; opcode < num_opcodes; opcode++)
12377     {
12378       op_placement_info *opi = &op_placement_table[opcode];
12379       /* FIXME: Make tinsn allocation dynamic.  */
12380       if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS)
12381         as_fatal (_("too many operands in instruction"));
12382       opi->narrowest = XTENSA_UNDEFINED;
12383       opi->narrowest_size = 0x7F;
12384       opi->narrowest_slot = 0;
12385       opi->formats = 0;
12386       opi->num_formats = 0;
12387       opi->issuef = 0;
12388       for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
12389         {
12390           opi->slots[fmt] = 0;
12391           for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
12392             {
12393               if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
12394                 {
12395                   int fmt_length = xtensa_format_length (isa, fmt);
12396                   opi->issuef++;
12397                   set_bit (fmt, opi->formats);
12398                   set_bit (slot, opi->slots[fmt]);
12399                   if (fmt_length < opi->narrowest_size
12400                       || (fmt_length == opi->narrowest_size
12401                           && (xtensa_format_num_slots (isa, fmt)
12402                               < xtensa_format_num_slots (isa,
12403                                                          opi->narrowest))))
12404                     {
12405                       opi->narrowest = fmt;
12406                       opi->narrowest_size = fmt_length;
12407                       opi->narrowest_slot = slot;
12408                     }
12409                 }
12410             }
12411           if (opi->formats)
12412             opi->num_formats++;
12413         }
12414     }
12415   xtensa_insnbuf_free (isa, ibuf);
12416 }
12417
12418
12419 bool
12420 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
12421 {
12422   return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
12423 }
12424
12425
12426 /* If the opcode is available in a single slot format, return its size.  */
12427
12428 static int
12429 xg_get_single_size (xtensa_opcode opcode)
12430 {
12431   return op_placement_table[opcode].narrowest_size;
12432 }
12433
12434
12435 static xtensa_format
12436 xg_get_single_format (xtensa_opcode opcode)
12437 {
12438   return op_placement_table[opcode].narrowest;
12439 }
12440
12441
12442 static int
12443 xg_get_single_slot (xtensa_opcode opcode)
12444 {
12445   return op_placement_table[opcode].narrowest_slot;
12446 }
12447
12448 \f
12449 /* Instruction Stack Functions (from "xtensa-istack.h").  */
12450
12451 void
12452 istack_init (IStack *stack)
12453 {
12454   stack->ninsn = 0;
12455 }
12456
12457
12458 bool
12459 istack_empty (IStack *stack)
12460 {
12461   return (stack->ninsn == 0);
12462 }
12463
12464
12465 bool
12466 istack_full (IStack *stack)
12467 {
12468   return (stack->ninsn == MAX_ISTACK);
12469 }
12470
12471
12472 /* Return a pointer to the top IStack entry.
12473    It is an error to call this if istack_empty () is TRUE. */
12474
12475 TInsn *
12476 istack_top (IStack *stack)
12477 {
12478   int rec = stack->ninsn - 1;
12479   gas_assert (!istack_empty (stack));
12480   return &stack->insn[rec];
12481 }
12482
12483
12484 /* Add a new TInsn to an IStack.
12485    It is an error to call this if istack_full () is TRUE.  */
12486
12487 void
12488 istack_push (IStack *stack, TInsn *insn)
12489 {
12490   int rec = stack->ninsn;
12491   gas_assert (!istack_full (stack));
12492   stack->insn[rec] = *insn;
12493   stack->ninsn++;
12494 }
12495
12496
12497 /* Clear space for the next TInsn on the IStack and return a pointer
12498    to it.  It is an error to call this if istack_full () is TRUE.  */
12499
12500 TInsn *
12501 istack_push_space (IStack *stack)
12502 {
12503   int rec = stack->ninsn;
12504   TInsn *insn;
12505   gas_assert (!istack_full (stack));
12506   insn = &stack->insn[rec];
12507   tinsn_init (insn);
12508   stack->ninsn++;
12509   return insn;
12510 }
12511
12512
12513 /* Remove the last pushed instruction.  It is an error to call this if
12514    istack_empty () returns TRUE.  */
12515
12516 void
12517 istack_pop (IStack *stack)
12518 {
12519   int rec = stack->ninsn - 1;
12520   gas_assert (!istack_empty (stack));
12521   stack->ninsn--;
12522   tinsn_init (&stack->insn[rec]);
12523 }
12524
12525 \f
12526 /* TInsn functions.  */
12527
12528 void
12529 tinsn_init (TInsn *dst)
12530 {
12531   memset (dst, 0, sizeof (TInsn));
12532 }
12533
12534
12535 /* Return TRUE if ANY of the operands in the insn are symbolic.  */
12536
12537 static bool
12538 tinsn_has_symbolic_operands (const TInsn *insn)
12539 {
12540   int i;
12541   int n = insn->ntok;
12542
12543   gas_assert (insn->insn_type == ITYPE_INSN);
12544
12545   for (i = 0; i < n; ++i)
12546     {
12547       switch (insn->tok[i].X_op)
12548         {
12549         case O_register:
12550         case O_constant:
12551           break;
12552         default:
12553           return true;
12554         }
12555     }
12556   return false;
12557 }
12558
12559
12560 bool
12561 tinsn_has_invalid_symbolic_operands (const TInsn *insn)
12562 {
12563   xtensa_isa isa = xtensa_default_isa;
12564   int i;
12565   int n = insn->ntok;
12566
12567   gas_assert (insn->insn_type == ITYPE_INSN);
12568
12569   for (i = 0; i < n; ++i)
12570     {
12571       switch (insn->tok[i].X_op)
12572         {
12573         case O_register:
12574         case O_constant:
12575           break;
12576         case O_big:
12577         case O_illegal:
12578         case O_absent:
12579           /* Errors for these types are caught later.  */
12580           break;
12581         case O_hi16:
12582         case O_lo16:
12583         default:
12584           /* Symbolic immediates are only allowed on the last immediate
12585              operand.  At this time, CONST16 is the only opcode where we
12586              support non-PC-relative relocations.  */
12587           if (i != get_relaxable_immed (insn->opcode)
12588               || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
12589                   && insn->opcode != xtensa_const16_opcode))
12590             {
12591               as_bad (_("invalid symbolic operand"));
12592               return true;
12593             }
12594         }
12595     }
12596   return false;
12597 }
12598
12599
12600 /* For assembly code with complex expressions (e.g. subtraction),
12601    we have to build them in the literal pool so that
12602    their results are calculated correctly after relaxation.
12603    The relaxation only handles expressions that
12604    boil down to SYMBOL + OFFSET.  */
12605
12606 static bool
12607 tinsn_has_complex_operands (const TInsn *insn)
12608 {
12609   int i;
12610   int n = insn->ntok;
12611   gas_assert (insn->insn_type == ITYPE_INSN);
12612   for (i = 0; i < n; ++i)
12613     {
12614       switch (insn->tok[i].X_op)
12615         {
12616         case O_register:
12617         case O_constant:
12618         case O_symbol:
12619         case O_lo16:
12620         case O_hi16:
12621           break;
12622         default:
12623           return true;
12624         }
12625     }
12626   return false;
12627 }
12628
12629
12630 /* Encode a TInsn opcode and its constant operands into slotbuf.
12631    Return TRUE if there is a symbol in the immediate field.  This
12632    function assumes that:
12633    1) The number of operands are correct.
12634    2) The insn_type is ITYPE_INSN.
12635    3) The opcode can be encoded in the specified format and slot.
12636    4) Operands are either O_constant or O_symbol, and all constants fit.  */
12637
12638 static bool
12639 tinsn_to_slotbuf (xtensa_format fmt,
12640                   int slot,
12641                   TInsn *tinsn,
12642                   xtensa_insnbuf slotbuf)
12643 {
12644   xtensa_isa isa = xtensa_default_isa;
12645   xtensa_opcode opcode = tinsn->opcode;
12646   bool has_fixup = false;
12647   int noperands = xtensa_opcode_num_operands (isa, opcode);
12648   int i;
12649
12650   gas_assert (tinsn->insn_type == ITYPE_INSN);
12651   if (noperands != tinsn->ntok)
12652     as_fatal (_("operand number mismatch"));
12653
12654   if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
12655     {
12656       as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12657               xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
12658       return false;
12659     }
12660
12661   for (i = 0; i < noperands; i++)
12662     {
12663       expressionS *exp = &tinsn->tok[i];
12664       int rc;
12665       unsigned line;
12666       const char *file_name;
12667       uint32 opnd_value;
12668
12669       switch (exp->X_op)
12670         {
12671         case O_register:
12672           if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12673             break;
12674           /* The register number has already been checked in
12675              expression_maybe_register, so we don't need to check here.  */
12676           opnd_value = exp->X_add_number;
12677           (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
12678           rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
12679                                          opnd_value);
12680           if (rc != 0)
12681             as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
12682           break;
12683
12684         case O_constant:
12685           if (xtensa_operand_is_visible (isa, opcode, i) == 0)
12686             break;
12687           file_name = as_where (&line);
12688           /* It is a constant and we called this function
12689              then we have to try to fit it.  */
12690           xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
12691                                       exp->X_add_number, file_name, line);
12692           break;
12693
12694         default:
12695           has_fixup = true;
12696           break;
12697         }
12698     }
12699
12700   return has_fixup;
12701 }
12702
12703
12704 /* Encode a single TInsn into an insnbuf.  If the opcode can only be encoded
12705    into a multi-slot instruction, fill the other slots with NOPs.
12706    Return TRUE if there is a symbol in the immediate field.  See also the
12707    assumptions listed for tinsn_to_slotbuf.  */
12708
12709 static bool
12710 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
12711 {
12712   static xtensa_insnbuf slotbuf = 0;
12713   static vliw_insn vinsn;
12714   xtensa_isa isa = xtensa_default_isa;
12715   bool has_fixup = false;
12716   int i;
12717
12718   if (!slotbuf)
12719     {
12720       slotbuf = xtensa_insnbuf_alloc (isa);
12721       xg_init_vinsn (&vinsn);
12722     }
12723
12724   xg_clear_vinsn (&vinsn);
12725
12726   bundle_tinsn (tinsn, &vinsn);
12727
12728   xtensa_format_encode (isa, vinsn.format, insnbuf);
12729
12730   for (i = 0; i < vinsn.num_slots; i++)
12731     {
12732       /* Only one slot may have a fix-up because the rest contains NOPs.  */
12733       has_fixup |=
12734         tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]);
12735       xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]);
12736     }
12737
12738   return has_fixup;
12739 }
12740
12741
12742 /* Check the instruction arguments.  Return TRUE on failure.  */
12743
12744 static bool
12745 tinsn_check_arguments (const TInsn *insn)
12746 {
12747   xtensa_isa isa = xtensa_default_isa;
12748   xtensa_opcode opcode = insn->opcode;
12749   xtensa_regfile t1_regfile, t2_regfile;
12750   int t1_reg, t2_reg;
12751   int t1_base_reg, t1_last_reg;
12752   int t2_base_reg, t2_last_reg;
12753   char t1_inout, t2_inout;
12754   int i, j;
12755
12756   if (opcode == XTENSA_UNDEFINED)
12757     {
12758       as_bad (_("invalid opcode"));
12759       return true;
12760     }
12761
12762   if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
12763     {
12764       as_bad (_("too few operands"));
12765       return true;
12766     }
12767
12768   if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
12769     {
12770       as_bad (_("too many operands"));
12771       return true;
12772     }
12773
12774   /* Check registers.  */
12775   for (j = 0; j < insn->ntok; j++)
12776     {
12777       if (xtensa_operand_is_register (isa, insn->opcode, j) != 1)
12778         continue;
12779
12780       t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j);
12781       t2_base_reg = insn->tok[j].X_add_number;
12782       t2_last_reg
12783         = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j);
12784
12785       for (i = 0; i < insn->ntok; i++)
12786         {
12787           if (i == j)
12788             continue;
12789
12790           if (xtensa_operand_is_register (isa, insn->opcode, i) != 1)
12791             continue;
12792
12793           t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i);
12794
12795           if (t1_regfile != t2_regfile)
12796             continue;
12797
12798           t1_inout = xtensa_operand_inout (isa, insn->opcode, i);
12799           t2_inout = xtensa_operand_inout (isa, insn->opcode, j);
12800
12801           t1_base_reg = insn->tok[i].X_add_number;
12802           t1_last_reg = (t1_base_reg
12803                          + xtensa_operand_num_regs (isa, insn->opcode, i));
12804
12805           for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
12806             {
12807               for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
12808                 {
12809                   if (t1_reg != t2_reg)
12810                     continue;
12811
12812                   if (t1_inout != 'i' && t2_inout != 'i')
12813                     {
12814                       as_bad (_("multiple writes to the same register"));
12815                       return true;
12816                     }
12817                 }
12818             }
12819         }
12820     }
12821   return false;
12822 }
12823
12824
12825 /* Load an instruction from its encoded form.  */
12826
12827 static void
12828 tinsn_from_chars (TInsn *tinsn, char *f, int slot)
12829 {
12830   vliw_insn vinsn;
12831
12832   xg_init_vinsn (&vinsn);
12833   vinsn_from_chars (&vinsn, f);
12834
12835   *tinsn = vinsn.slots[slot];
12836   xg_free_vinsn (&vinsn);
12837 }
12838
12839
12840 static void
12841 tinsn_from_insnbuf (TInsn *tinsn,
12842                     xtensa_insnbuf slotbuf,
12843                     xtensa_format fmt,
12844                     int slot)
12845 {
12846   int i;
12847   xtensa_isa isa = xtensa_default_isa;
12848
12849   /* Find the immed.  */
12850   tinsn_init (tinsn);
12851   tinsn->insn_type = ITYPE_INSN;
12852   tinsn->is_specific_opcode = false;    /* must not be specific */
12853   tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
12854   tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
12855   for (i = 0; i < tinsn->ntok; i++)
12856     {
12857       set_expr_const (&tinsn->tok[i],
12858                       xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
12859                                                   tinsn->opcode, i));
12860     }
12861 }
12862
12863
12864 /* Read the value of the relaxable immed from the fr_symbol and fr_offset.  */
12865
12866 static void
12867 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
12868 {
12869   xtensa_opcode opcode = tinsn->opcode;
12870   int opnum;
12871
12872   if (fragP->tc_frag_data.slot_symbols[slot])
12873     {
12874       opnum = get_relaxable_immed (opcode);
12875       gas_assert (opnum >= 0);
12876       set_expr_symbol_offset (&tinsn->tok[opnum],
12877                               fragP->tc_frag_data.slot_symbols[slot],
12878                               fragP->tc_frag_data.slot_offsets[slot]);
12879     }
12880   tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot];
12881 }
12882
12883
12884 static int
12885 get_num_stack_text_bytes (IStack *istack)
12886 {
12887   int i;
12888   int text_bytes = 0;
12889
12890   for (i = 0; i < istack->ninsn; i++)
12891     {
12892       TInsn *tinsn = &istack->insn[i];
12893       if (tinsn->insn_type == ITYPE_INSN)
12894         text_bytes += xg_get_single_size (tinsn->opcode);
12895     }
12896   return text_bytes;
12897 }
12898
12899
12900 static int
12901 get_num_stack_literal_bytes (IStack *istack)
12902 {
12903   int i;
12904   int lit_bytes = 0;
12905
12906   for (i = 0; i < istack->ninsn; i++)
12907     {
12908       TInsn *tinsn = &istack->insn[i];
12909       if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
12910         lit_bytes += 4;
12911     }
12912   return lit_bytes;
12913 }
12914
12915 \f
12916 /* vliw_insn functions.  */
12917
12918 static void
12919 xg_init_vinsn (vliw_insn *v)
12920 {
12921   int i;
12922   xtensa_isa isa = xtensa_default_isa;
12923
12924   xg_clear_vinsn (v);
12925
12926   v->insnbuf = xtensa_insnbuf_alloc (isa);
12927   if (v->insnbuf == NULL)
12928     as_fatal (_("out of memory"));
12929
12930   for (i = 0; i < config_max_slots; i++)
12931     {
12932       v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
12933       if (v->slotbuf[i] == NULL)
12934         as_fatal (_("out of memory"));
12935     }
12936 }
12937
12938
12939 static void
12940 xg_clear_vinsn (vliw_insn *v)
12941 {
12942   int i;
12943
12944   memset (v, 0, offsetof (vliw_insn, slots)
12945                 + sizeof(TInsn) * config_max_slots);
12946
12947   v->format = XTENSA_UNDEFINED;
12948   v->num_slots = 0;
12949   v->inside_bundle = false;
12950
12951   if (xt_saved_debug_type != DEBUG_NONE)
12952     debug_type = xt_saved_debug_type;
12953
12954   for (i = 0; i < config_max_slots; i++)
12955     v->slots[i].opcode = XTENSA_UNDEFINED;
12956 }
12957
12958
12959 static void
12960 xg_copy_vinsn (vliw_insn *dst, vliw_insn *src)
12961 {
12962   memcpy (dst, src,
12963           offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn));
12964   dst->insnbuf = src->insnbuf;
12965   memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf));
12966 }
12967
12968
12969 static bool
12970 vinsn_has_specific_opcodes (vliw_insn *v)
12971 {
12972   int i;
12973
12974   for (i = 0; i < v->num_slots; i++)
12975     {
12976       if (v->slots[i].is_specific_opcode)
12977         return true;
12978     }
12979   return false;
12980 }
12981
12982
12983 static void
12984 xg_free_vinsn (vliw_insn *v)
12985 {
12986   int i;
12987   xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
12988   for (i = 0; i < config_max_slots; i++)
12989     xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
12990 }
12991
12992
12993 /* Encode a vliw_insn into an insnbuf.  Return TRUE if there are any symbolic
12994    operands.  See also the assumptions listed for tinsn_to_slotbuf.  */
12995
12996 static bool
12997 vinsn_to_insnbuf (vliw_insn *vinsn,
12998                   char *frag_offset,
12999                   fragS *fragP,
13000                   bool record_fixup)
13001 {
13002   xtensa_isa isa = xtensa_default_isa;
13003   xtensa_format fmt = vinsn->format;
13004   xtensa_insnbuf insnbuf = vinsn->insnbuf;
13005   int slot;
13006   bool has_fixup = false;
13007
13008   xtensa_format_encode (isa, fmt, insnbuf);
13009
13010   for (slot = 0; slot < vinsn->num_slots; slot++)
13011     {
13012       TInsn *tinsn = &vinsn->slots[slot];
13013       expressionS *extra_arg = &tinsn->extra_arg;
13014       bool tinsn_has_fixup =
13015         tinsn_to_slotbuf (vinsn->format, slot, tinsn,
13016                           vinsn->slotbuf[slot]);
13017
13018       xtensa_format_set_slot (isa, fmt, slot,
13019                               insnbuf, vinsn->slotbuf[slot]);
13020       if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register)
13021         {
13022           if (vinsn->num_slots != 1)
13023             as_bad (_("TLS relocation not allowed in FLIX bundle"));
13024           else if (record_fixup)
13025             /* Instructions that generate TLS relocations should always be
13026                relaxed in the front-end.  If "record_fixup" is set, then this
13027                function is being called during back-end relaxation, so flag
13028                the unexpected behavior as an error.  */
13029             as_bad (_("unexpected TLS relocation"));
13030           else
13031             fix_new (fragP, frag_offset - fragP->fr_literal,
13032                      xtensa_format_length (isa, fmt),
13033                      extra_arg->X_add_symbol, extra_arg->X_add_number,
13034                      false, map_operator_to_reloc (extra_arg->X_op, false));
13035         }
13036       if (tinsn_has_fixup)
13037         {
13038           int i;
13039           xtensa_opcode opcode = tinsn->opcode;
13040           int noperands = xtensa_opcode_num_operands (isa, opcode);
13041           has_fixup = true;
13042
13043           for (i = 0; i < noperands; i++)
13044             {
13045               expressionS* exp = &tinsn->tok[i];
13046               switch (exp->X_op)
13047                 {
13048                 case O_symbol:
13049                 case O_lo16:
13050                 case O_hi16:
13051                   if (get_relaxable_immed (opcode) == i)
13052                     {
13053                       /* Add a fix record for the instruction, except if this
13054                          function is being called prior to relaxation, i.e.,
13055                          if record_fixup is false, and the instruction might
13056                          be relaxed later.  */
13057                       if (record_fixup
13058                           || tinsn->is_specific_opcode
13059                           || !xg_is_relaxable_insn (tinsn, 0))
13060                         {
13061                           xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP,
13062                                              frag_offset - fragP->fr_literal);
13063                         }
13064                       else
13065                         {
13066                           if (exp->X_op != O_symbol)
13067                             as_bad (_("invalid operand"));
13068                           tinsn->symbol = exp->X_add_symbol;
13069                           tinsn->offset = exp->X_add_number;
13070                         }
13071                     }
13072                   else
13073                     as_bad (_("symbolic operand not allowed"));
13074                   break;
13075
13076                 case O_constant:
13077                 case O_register:
13078                   break;
13079
13080                 default:
13081                   as_bad (_("expression too complex"));
13082                   break;
13083                 }
13084             }
13085         }
13086     }
13087
13088   return has_fixup;
13089 }
13090
13091
13092 static void
13093 vinsn_from_chars (vliw_insn *vinsn, char *f)
13094 {
13095   static xtensa_insnbuf insnbuf = NULL;
13096   static xtensa_insnbuf slotbuf = NULL;
13097   int i;
13098   xtensa_format fmt;
13099   xtensa_isa isa = xtensa_default_isa;
13100
13101   if (!insnbuf)
13102     {
13103       insnbuf = xtensa_insnbuf_alloc (isa);
13104       slotbuf = xtensa_insnbuf_alloc (isa);
13105     }
13106
13107   xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0);
13108   fmt = xtensa_format_decode (isa, insnbuf);
13109   if (fmt == XTENSA_UNDEFINED)
13110     as_fatal (_("cannot decode instruction format"));
13111   vinsn->format = fmt;
13112   vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
13113
13114   for (i = 0; i < vinsn->num_slots; i++)
13115     {
13116       TInsn *tinsn = &vinsn->slots[i];
13117       xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
13118       tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
13119     }
13120 }
13121
13122 \f
13123 /* Expression utilities.  */
13124
13125 /* Return TRUE if the expression is an integer constant.  */
13126
13127 bool
13128 expr_is_const (const expressionS *s)
13129 {
13130   return (s->X_op == O_constant);
13131 }
13132
13133
13134 /* Get the expression constant.
13135    Calling this is illegal if expr_is_const () returns TRUE.  */
13136
13137 offsetT
13138 get_expr_const (const expressionS *s)
13139 {
13140   gas_assert (expr_is_const (s));
13141   return s->X_add_number;
13142 }
13143
13144
13145 /* Set the expression to a constant value.  */
13146
13147 void
13148 set_expr_const (expressionS *s, offsetT val)
13149 {
13150   s->X_op = O_constant;
13151   s->X_add_number = val;
13152   s->X_add_symbol = NULL;
13153   s->X_op_symbol = NULL;
13154 }
13155
13156
13157 bool
13158 expr_is_register (const expressionS *s)
13159 {
13160   return (s->X_op == O_register);
13161 }
13162
13163
13164 /* Get the expression constant.
13165    Calling this is illegal if expr_is_const () returns TRUE.  */
13166
13167 offsetT
13168 get_expr_register (const expressionS *s)
13169 {
13170   gas_assert (expr_is_register (s));
13171   return s->X_add_number;
13172 }
13173
13174
13175 /* Set the expression to a symbol + constant offset.  */
13176
13177 void
13178 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
13179 {
13180   s->X_op = O_symbol;
13181   s->X_add_symbol = sym;
13182   s->X_op_symbol = NULL;        /* unused */
13183   s->X_add_number = offset;
13184 }
13185
13186
13187 /* Return TRUE if the two expressions are equal.  */
13188
13189 bool
13190 expr_is_equal (expressionS *s1, expressionS *s2)
13191 {
13192   if (s1->X_op != s2->X_op)
13193     return false;
13194   if (s1->X_add_symbol != s2->X_add_symbol)
13195     return false;
13196   if (s1->X_op_symbol != s2->X_op_symbol)
13197     return false;
13198   if (s1->X_add_number != s2->X_add_number)
13199     return false;
13200   return true;
13201 }
13202
13203
13204 static void
13205 copy_expr (expressionS *dst, const expressionS *src)
13206 {
13207   memcpy (dst, src, sizeof (expressionS));
13208 }
13209
13210 \f
13211 /* Support for the "--rename-section" option.  */
13212
13213 struct rename_section_struct
13214 {
13215   const char *old_name;
13216   char *new_name;
13217   struct rename_section_struct *next;
13218 };
13219
13220 static struct rename_section_struct *section_rename;
13221
13222
13223 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13224    entries to the section_rename list.  Note: Specifying multiple
13225    renamings separated by colons is not documented and is retained only
13226    for backward compatibility.  */
13227
13228 static void
13229 build_section_rename (const char *arg)
13230 {
13231   struct rename_section_struct *r;
13232   char *this_arg = NULL;
13233   char *next_arg = NULL;
13234
13235   for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
13236     {
13237       char *old_name, *new_name;
13238
13239       if (this_arg)
13240         {
13241           next_arg = strchr (this_arg, ':');
13242           if (next_arg)
13243             {
13244               *next_arg = '\0';
13245               next_arg++;
13246             }
13247         }
13248
13249       old_name = this_arg;
13250       new_name = strchr (this_arg, '=');
13251
13252       if (*old_name == '\0')
13253         {
13254           as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13255           continue;
13256         }
13257       if (!new_name || new_name[1] == '\0')
13258         {
13259           as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13260                    old_name);
13261           continue;
13262         }
13263       *new_name = '\0';
13264       new_name++;
13265
13266       /* Check for invalid section renaming.  */
13267       for (r = section_rename; r != NULL; r = r->next)
13268         {
13269           if (strcmp (r->old_name, old_name) == 0)
13270             as_bad (_("section %s renamed multiple times"), old_name);
13271           if (strcmp (r->new_name, new_name) == 0)
13272             as_bad (_("multiple sections remapped to output section %s"),
13273                     new_name);
13274         }
13275
13276       /* Now add it.  */
13277       r = XNEW (struct rename_section_struct);
13278       r->old_name = xstrdup (old_name);
13279       r->new_name = xstrdup (new_name);
13280       r->next = section_rename;
13281       section_rename = r;
13282     }
13283 }
13284
13285
13286 char *
13287 xtensa_section_rename (const char *name)
13288 {
13289   struct rename_section_struct *r = section_rename;
13290
13291   for (r = section_rename; r != NULL; r = r->next)
13292     {
13293       if (strcmp (r->old_name, name) == 0)
13294         return r->new_name;
13295     }
13296
13297   return (char *) name;
13298 }