1 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-dis.c (OP_E_memory): Without base nor index registers,
5 32-bit displacement to 64 bits.
7 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
9 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
10 faulty double register pair is detected.
12 2020-07-14 Jan Beulich <jbeulich@suse.com>
14 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
16 2020-07-14 Jan Beulich <jbeulich@suse.com>
18 * i386-dis.c (OP_R, Rm): Delete.
19 (MOD_0F24, MOD_0F26): Rename to ...
20 (X86_64_0F24, X86_64_0F26): ... respectively.
21 (dis386): Update 'L' and 'Z' comments.
22 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
24 (mod_table): Move opcode 0F24 and 0F26 entries ...
25 (x86_64_table): ... here.
26 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
29 2020-07-14 Jan Beulich <jbeulich@suse.com>
31 * i386-dis.c (Rd, Rdq, MaskR): Delete.
32 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
33 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
34 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
35 MOD_EVEX_0F387C): New enumerators.
36 (reg_table): Use Edq for rdssp.
37 (prefix_table): Use Edq for incssp.
38 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
39 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
40 ktest*, and kshift*. Use Edq / MaskE for kmov*.
41 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
42 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
43 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
44 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
45 0F3828_P_1 and 0F3838_P_1.
46 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
47 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
49 2020-07-14 Jan Beulich <jbeulich@suse.com>
51 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
52 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
53 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
54 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
55 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
56 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
57 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
58 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
59 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
60 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
61 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
62 (reg_table, prefix_table, three_byte_table, vex_table,
63 vex_len_table, mod_table, rm_table): Replace / remove respective
65 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
66 of PREFIX_DATA in used_prefixes.
68 2020-07-14 Jan Beulich <jbeulich@suse.com>
70 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
71 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
72 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
73 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
74 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
75 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
76 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
77 VEX_W_0F3A33_L_0): Delete.
78 (dis386): Adjust "BW" description.
79 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
80 0F3A31, 0F3A32, and 0F3A33.
81 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
83 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
86 2020-07-14 Jan Beulich <jbeulich@suse.com>
88 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
89 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
90 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
91 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
92 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
93 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
94 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
95 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
96 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
97 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
98 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
99 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
100 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
101 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
102 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
103 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
104 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
105 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
106 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
107 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
108 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
109 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
110 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
111 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
112 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
113 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
114 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
115 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
116 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
117 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
118 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
119 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
120 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
121 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
122 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
123 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
124 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
125 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
126 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
127 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
128 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
129 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
130 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
131 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
132 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
133 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
134 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
135 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
136 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
137 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
138 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
139 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
140 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
141 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
142 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
143 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
144 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
145 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
146 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
147 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
148 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
149 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
150 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
151 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
152 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
153 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
154 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
155 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
156 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
157 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
158 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
159 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
160 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
161 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
162 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
163 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
164 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
165 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
166 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
167 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
168 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
169 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
170 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
171 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
172 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
173 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
174 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
175 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
176 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
177 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
178 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
179 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
180 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
181 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
182 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
183 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
184 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
185 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
186 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
187 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
188 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
189 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
190 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
191 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
192 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
193 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
194 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
195 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
196 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
197 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
198 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
199 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
200 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
201 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
202 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
203 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
204 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
205 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
206 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
207 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
208 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
209 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
210 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
211 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
212 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
213 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
214 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
215 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
216 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
217 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
218 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
219 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
220 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
221 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
222 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
223 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
224 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
225 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
226 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
227 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
228 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
229 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
230 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
231 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
232 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
233 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
234 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
235 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
236 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
237 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
238 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
239 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
240 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
241 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
242 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
243 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
244 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
245 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
246 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
247 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
248 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
249 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
250 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
251 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
252 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
253 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
254 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
255 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
256 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
257 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
258 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
259 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
260 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
261 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
262 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
263 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
264 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
265 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
266 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
267 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
268 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
269 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
270 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
271 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
272 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
273 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
274 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
275 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
276 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
277 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
278 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
279 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
280 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
281 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
282 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
283 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
284 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
285 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
286 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
287 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
288 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
289 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
290 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
291 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
292 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
293 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
294 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
295 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
296 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
297 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
298 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
299 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
300 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
301 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
302 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
303 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
304 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
305 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
306 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
307 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
308 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
309 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
310 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
311 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
312 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
313 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
314 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
315 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
316 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
317 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
318 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
319 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
320 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
321 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
322 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
323 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
324 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
325 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
326 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
327 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
328 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
329 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
330 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
331 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
332 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
333 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
334 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
335 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
336 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
337 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
338 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
339 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
340 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
341 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
342 EVEX_W_0F3A72_P_2): Rename to ...
343 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
344 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
345 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
346 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
347 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
348 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
349 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
350 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
351 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
352 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
353 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
354 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
355 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
356 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
357 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
358 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
359 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
360 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
361 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
362 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
363 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
364 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
365 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
366 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
367 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
368 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
369 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
370 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
371 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
372 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
373 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
374 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
375 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
376 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
377 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
378 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
379 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
380 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
381 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
382 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
383 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
384 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
385 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
386 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
387 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
388 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
389 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
390 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
391 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
392 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
393 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
394 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
395 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
396 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
397 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
398 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
399 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
400 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
401 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
402 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
403 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
404 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
405 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
406 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
407 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
408 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
409 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
410 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
411 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
412 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
413 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
414 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
416 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
417 vex_w_table, mod_table): Replace / remove respective entries.
418 (print_insn): Move up dp->prefix_requirement handling. Handle
420 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
421 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
422 Replace / remove respective entries.
424 2020-07-14 Jan Beulich <jbeulich@suse.com>
426 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
427 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
428 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
429 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
430 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
432 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
433 0F2C, 0F2D, 0F2E, and 0F2F.
434 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
437 2020-07-14 Jan Beulich <jbeulich@suse.com>
439 * i386-dis.c (OP_VexR, VexScalarR): New.
440 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
441 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
442 need_vex_reg): Delete.
443 (prefix_table): Replace VexScalar by VexScalarR and
444 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
445 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
446 (vex_len_table): Replace EXqVexScalarS by EXqS.
447 (get_valid_dis386): Don't set need_vex_reg.
448 (print_insn): Don't initialize need_vex_reg.
449 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
450 q_scalar_swap_mode cases.
451 (OP_EX): Don't check for d_scalar_swap_mode and
453 (OP_VEX): Done check need_vex_reg.
454 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
455 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
456 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
458 2020-07-14 Jan Beulich <jbeulich@suse.com>
460 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
461 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
462 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
463 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
464 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
465 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
466 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
467 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
468 (vex_table): Replace Vex128 by Vex.
469 (vex_len_table): Likewise. Adjust referenced enum names.
470 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
471 referenced enum names.
472 (OP_VEX): Drop vex128_mode and vex256_mode cases.
473 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
475 2020-07-14 Jan Beulich <jbeulich@suse.com>
477 * i386-dis.c (dis386): "LW" description now applies to "DQ".
478 (putop): Handle "DQ". Don't handle "LW" anymore.
479 (prefix_table, mod_table): Replace %LW by %DQ.
480 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
482 2020-07-14 Jan Beulich <jbeulich@suse.com>
484 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
485 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
486 d_scalar_swap_mode case handling. Move shift adjsutment into
487 the case its applicable to.
489 2020-07-14 Jan Beulich <jbeulich@suse.com>
491 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
492 (EXbScalar, EXwScalar): Fold to ...
493 (EXbwUnit): ... this.
494 (b_scalar_mode, w_scalar_mode): Fold to ...
495 (bw_unit_mode): ... this.
496 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
497 w_scalar_mode handling by bw_unit_mode one.
498 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
500 * i386-dis-evex-prefix.h: ... here.
502 2020-07-14 Jan Beulich <jbeulich@suse.com>
504 * i386-dis.c (PCMPESTR_Fixup): Delete.
505 (dis386): Adjust "LQ" description.
506 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
507 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
508 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
509 vpcmpestrm, and vpcmpestri.
510 (putop): Honor "cond" when handling LQ.
511 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
512 vcvtsi2ss and vcvtusi2ss.
513 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
514 vcvtsi2sd and vcvtusi2sd.
516 2020-07-14 Jan Beulich <jbeulich@suse.com>
518 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
519 (simd_cmp_op): Add const.
520 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
521 (CMP_Fixup): Handle VEX case.
522 (prefix_table): Replace VCMP by CMP.
523 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
525 2020-07-14 Jan Beulich <jbeulich@suse.com>
527 * i386-dis.c (MOVBE_Fixup): Delete.
529 (prefix_table): Use Mv for movbe entries.
531 2020-07-14 Jan Beulich <jbeulich@suse.com>
533 * i386-dis.c (CRC32_Fixup): Delete.
534 (prefix_table): Use Eb/Ev for crc32 entries.
536 2020-07-14 Jan Beulich <jbeulich@suse.com>
538 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
539 Conditionalize invocations of "USED_REX (0)".
541 2020-07-14 Jan Beulich <jbeulich@suse.com>
543 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
544 CH, DH, BH, AX, DX): Delete.
545 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
546 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
547 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
549 2020-07-10 Lili Cui <lili.cui@intel.com>
551 * i386-dis.c (TMM): New.
554 (MVexSIBMEM): Likewise.
555 (tmm_mode): Likewise.
556 (vex_sibmem_mode): Likewise.
557 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
558 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
559 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
560 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
561 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
562 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
563 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
564 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
565 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
566 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
567 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
568 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
569 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
570 (PREFIX_VEX_0F3849_X86_64): Likewise.
571 (PREFIX_VEX_0F384B_X86_64): Likewise.
572 (PREFIX_VEX_0F385C_X86_64): Likewise.
573 (PREFIX_VEX_0F385E_X86_64): Likewise.
574 (X86_64_VEX_0F3849): Likewise.
575 (X86_64_VEX_0F384B): Likewise.
576 (X86_64_VEX_0F385C): Likewise.
577 (X86_64_VEX_0F385E): Likewise.
578 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
579 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
580 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
581 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
582 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
583 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
584 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
585 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
586 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
587 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
588 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
589 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
590 (VEX_W_0F3849_X86_64_P_0): Likewise.
591 (VEX_W_0F3849_X86_64_P_2): Likewise.
592 (VEX_W_0F3849_X86_64_P_3): Likewise.
593 (VEX_W_0F384B_X86_64_P_1): Likewise.
594 (VEX_W_0F384B_X86_64_P_2): Likewise.
595 (VEX_W_0F384B_X86_64_P_3): Likewise.
596 (VEX_W_0F385C_X86_64_P_1): Likewise.
597 (VEX_W_0F385E_X86_64_P_0): Likewise.
598 (VEX_W_0F385E_X86_64_P_1): Likewise.
599 (VEX_W_0F385E_X86_64_P_2): Likewise.
600 (VEX_W_0F385E_X86_64_P_3): Likewise.
601 (names_tmm): Likewise.
602 (att_names_tmm): Likewise.
603 (intel_operand_size): Handle void_mode.
604 (OP_XMM): Handle tmm_mode.
607 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
608 CpuAMX_BF16 and CpuAMX_TILE.
609 (operand_type_shorthands): Add RegTMM.
610 (operand_type_init): Likewise.
611 (operand_types): Add Tmmword.
612 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
613 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
614 * i386-opc.h (CpuAMX_INT8): New.
615 (CpuAMX_BF16): Likewise.
616 (CpuAMX_TILE): Likewise.
619 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
620 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
621 (i386_operand_type): Add tmmword.
622 * i386-opc.tbl: Add AMX instructions.
623 * i386-reg.tbl: Add AMX registers.
624 * i386-init.h: Regenerated.
625 * i386-tbl.h: Likewise.
627 2020-07-08 Jan Beulich <jbeulich@suse.com>
629 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
630 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
632 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
633 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
635 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
636 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
637 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
638 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
639 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
640 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
641 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
642 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
643 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
644 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
645 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
646 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
647 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
648 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
649 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
650 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
651 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
652 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
653 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
654 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
655 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
656 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
657 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
658 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
659 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
660 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
661 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
662 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
663 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
664 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
665 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
666 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
667 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
668 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
669 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
670 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
671 (reg_table): Re-order XOP entries. Adjust their operands.
672 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
673 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
674 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
675 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
676 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
677 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
678 entries by references ...
679 (vex_len_table): ... to resepctive new entries here. For several
680 new and existing entries reference ...
681 (vex_w_table): ... new entries here.
682 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
684 2020-07-08 Jan Beulich <jbeulich@suse.com>
686 * i386-dis.c (XMVexScalarI4): Define.
687 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
688 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
689 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
690 (vex_len_table): Move scalar FMA4 entries ...
691 (prefix_table): ... here.
692 (OP_REG_VexI4): Handle scalar_mode.
693 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
694 * i386-tbl.h: Re-generate.
696 2020-07-08 Jan Beulich <jbeulich@suse.com>
698 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
700 (OP_VexW, VexW): New.
701 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
702 for shifts and rotates by register.
704 2020-07-08 Jan Beulich <jbeulich@suse.com>
706 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
707 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
708 OP_EX_VexReg): Delete.
709 (OP_VexI4, VexI4): New.
710 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
711 (prefix_table): ... here.
712 (print_insn): Drop setting of vex_w_done.
714 2020-07-08 Jan Beulich <jbeulich@suse.com>
716 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
717 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
718 (xop_table): Replace operands of 4-operand insns.
719 (OP_REG_VexI4): Move VEX.W based operand swaping here.
721 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
723 * arc-opc.c (insert_rbd): New function.
726 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
729 2020-07-07 Jan Beulich <jbeulich@suse.com>
731 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
732 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
733 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
734 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
736 (putop): Handle "BW".
737 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
738 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
740 * i386-dis-evex-prefix.h: ... here.
742 2020-07-06 Jan Beulich <jbeulich@suse.com>
744 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
745 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
746 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
747 VEX_W_0FXOP_09_83): New enumerators.
748 (xop_table): Reference the above.
749 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
750 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
751 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
752 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
754 2020-07-06 Jan Beulich <jbeulich@suse.com>
756 * i386-dis.c (EVEX_W_0F3838_P_1,
757 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
758 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
759 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
760 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
761 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
762 (putop): Centralize management of last[]. Delete SAVE_LAST.
763 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
764 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
765 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
766 * i386-dis-evex-prefix.h: here.
768 2020-07-06 Jan Beulich <jbeulich@suse.com>
770 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
771 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
772 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
773 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
775 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
776 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
777 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
778 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
779 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
780 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
781 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
782 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
784 * i386-dis-evex-len.h: Adjust comments.
785 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
786 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
787 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
788 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
789 MOD_EVEX_0F385B_P_2_W_1 table entries.
790 * i386-dis-evex-w.h: Reference mod_table[] for
791 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
794 2020-07-06 Jan Beulich <jbeulich@suse.com>
796 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
797 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
799 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
800 Likewise. Mark 256-bit entries invalid.
802 2020-07-06 Jan Beulich <jbeulich@suse.com>
804 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
805 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
806 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
807 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
808 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
809 PREFIX_EVEX_0F382B): Delete.
810 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
811 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
812 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
813 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
814 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
816 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
817 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
818 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
819 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
821 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
822 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
823 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
824 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
825 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
826 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
827 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
828 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
829 PREFIX_EVEX_0F382B): Remove table entries.
830 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
831 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
832 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
834 2020-07-06 Jan Beulich <jbeulich@suse.com>
836 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
837 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
839 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
840 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
841 EVEX_LEN_0F3A01_P_2_W_1 table entries.
842 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
845 2020-07-06 Jan Beulich <jbeulich@suse.com>
847 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
848 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
849 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
850 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
851 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
852 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
853 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
854 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
855 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
858 2020-07-06 Jan Beulich <jbeulich@suse.com>
860 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
861 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
862 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
864 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
866 * i386-dis-evex.h (evex_table): Reference VEX table entry for
868 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
870 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
872 2020-07-06 Jan Beulich <jbeulich@suse.com>
874 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
875 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
876 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
877 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
878 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
879 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
880 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
881 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
882 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
883 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
884 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
885 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
886 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
887 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
888 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
889 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
890 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
891 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
892 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
893 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
894 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
895 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
896 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
897 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
898 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
899 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
900 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
901 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
902 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
903 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
904 (prefix_table): Add EXxEVexR to FMA table entries.
905 (OP_Rounding): Move abort() invocation.
906 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
907 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
908 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
909 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
910 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
911 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
912 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
913 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
914 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
915 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
917 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
918 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
919 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
920 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
921 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
922 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
923 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
924 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
925 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
926 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
927 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
928 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
929 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
930 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
931 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
932 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
933 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
934 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
935 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
936 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
937 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
938 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
939 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
940 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
941 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
942 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
943 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
944 Delete table entries.
945 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
946 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
947 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
950 2020-07-06 Jan Beulich <jbeulich@suse.com>
952 * i386-dis.c (EXqScalarS): Delete.
953 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
954 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
956 2020-07-06 Jan Beulich <jbeulich@suse.com>
958 * i386-dis.c (safe-ctype.h): Include.
959 (EXdScalar, EXqScalar): Delete.
960 (d_scalar_mode, q_scalar_mode): Delete.
961 (prefix_table, vex_len_table): Use EXxmm_md in place of
962 EXdScalar and EXxmm_mq in place of EXqScalar.
963 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
964 d_scalar_mode and q_scalar_mode.
965 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
966 (vmovsd): Use EXxmm_mq.
968 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
971 * arc-dis.c: Fix spelling mistake.
972 * po/opcodes.pot: Regenerate.
974 2020-07-06 Nick Clifton <nickc@redhat.com>
976 * po/pt_BR.po: Updated Brazilian Portugugese translation.
977 * po/uk.po: Updated Ukranian translation.
979 2020-07-04 Nick Clifton <nickc@redhat.com>
981 * configure: Regenerate.
982 * po/opcodes.pot: Regenerate.
984 2020-07-04 Nick Clifton <nickc@redhat.com>
986 Binutils 2.35 branch created.
988 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
990 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
991 * i386-opc.h (VexSwapSources): New.
992 (i386_opcode_modifier): Add vexswapsources.
993 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
994 with two source operands swapped.
995 * i386-tbl.h: Regenerated.
997 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
999 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1000 unprivileged CSR can also be initialized.
1002 2020-06-29 Alan Modra <amodra@gmail.com>
1004 * arm-dis.c: Use C style comments.
1005 * cr16-opc.c: Likewise.
1006 * ft32-dis.c: Likewise.
1007 * moxie-opc.c: Likewise.
1008 * tic54x-dis.c: Likewise.
1009 * s12z-opc.c: Remove useless comment.
1010 * xgate-dis.c: Likewise.
1012 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1014 * i386-opc.tbl: Add a blank line.
1016 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1018 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1019 (VecSIB128): Renamed to ...
1021 (VecSIB256): Renamed to ...
1023 (VecSIB512): Renamed to ...
1025 (VecSIB): Renamed to ...
1027 (i386_opcode_modifier): Replace vecsib with sib.
1028 * i386-opc.tbl (VecSIB128): New.
1029 (VecSIB256): Likewise.
1030 (VecSIB512): Likewise.
1031 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1032 and VecSIB512, respectively.
1034 2020-06-26 Jan Beulich <jbeulich@suse.com>
1036 * i386-dis.c: Adjust description of I macro.
1037 (x86_64_table): Drop use of I.
1038 (float_mem): Replace use of I.
1039 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1041 2020-06-26 Jan Beulich <jbeulich@suse.com>
1043 * i386-dis.c: (print_insn): Avoid straight assignment to
1044 priv.orig_sizeflag when processing -M sub-options.
1046 2020-06-25 Jan Beulich <jbeulich@suse.com>
1048 * i386-dis.c: Adjust description of J macro.
1049 (dis386, x86_64_table, mod_table): Replace J.
1050 (putop): Remove handling of J.
1052 2020-06-25 Jan Beulich <jbeulich@suse.com>
1054 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1056 2020-06-25 Jan Beulich <jbeulich@suse.com>
1058 * i386-dis.c: Adjust description of "LQ" macro.
1059 (dis386_twobyte): Use LQ for sysret.
1060 (putop): Adjust handling of LQ.
1062 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1064 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1065 * riscv-dis.c: Include elfxx-riscv.h.
1067 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1069 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1071 2020-06-17 Lili Cui <lili.cui@intel.com>
1073 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1075 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1078 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1079 * i386-opc.tbl: Likewise.
1080 * i386-tbl.h: Regenerated.
1082 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1084 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1086 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1088 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1089 (SR_CORE): Likewise.
1090 (SR_FEAT): Likewise.
1092 (SR_V8_1): Likewise.
1093 (SR_V8_2): Likewise.
1094 (SR_V8_3): Likewise.
1095 (SR_V8_4): Likewise.
1098 (SR_SSBS): Likewise.
1100 (SR_ID_PFR2): Likewise.
1101 (SR_PROFILE): Likewise.
1102 (SR_MEMTAG): Likewise.
1103 (SR_SCXTNUM): Likewise.
1104 (aarch64_sys_regs): Refactor to store feature information in the table.
1105 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1106 that now describe their own features.
1107 (aarch64_pstatefield_supported_p): Likewise.
1109 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1111 * i386-dis.c (prefix_table): Fix a typo in comments.
1113 2020-06-09 Jan Beulich <jbeulich@suse.com>
1115 * i386-dis.c (rex_ignored): Delete.
1116 (ckprefix): Drop rex_ignored initialization.
1117 (get_valid_dis386): Drop setting of rex_ignored.
1118 (print_insn): Drop checking of rex_ignored. Don't record data
1119 size prefix as used with VEX-and-alike encodings.
1121 2020-06-09 Jan Beulich <jbeulich@suse.com>
1123 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1124 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1125 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1126 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1127 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1128 VEX_0F12, and VEX_0F16.
1129 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1130 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1131 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1132 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1133 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1134 MOD_VEX_0F16_PREFIX_2 entries.
1136 2020-06-09 Jan Beulich <jbeulich@suse.com>
1138 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1139 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1140 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1141 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1142 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1143 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1144 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1145 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1146 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1147 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1148 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1149 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1150 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1151 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1152 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1153 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1154 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1155 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1156 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1157 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1158 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1159 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1160 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1161 EVEX_W_0FC6_P_2): Delete.
1162 (print_insn): Add EVEX.W vs embedded prefix consistency check
1163 to prefix validation.
1164 * i386-dis-evex.h (evex_table): Don't further descend for
1165 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1166 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1168 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1169 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1170 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1171 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1172 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1173 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1174 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1175 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1176 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1177 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1178 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1179 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1180 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1181 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1182 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1183 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1184 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1185 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1186 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1187 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1188 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1189 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1190 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1191 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1192 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1193 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1194 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1196 2020-06-09 Jan Beulich <jbeulich@suse.com>
1198 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1199 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1200 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1202 (print_insn): Drop pointless check against bad_opcode. Split
1203 prefix validation into legacy and VEX-and-alike parts.
1204 (putop): Re-work 'X' macro handling.
1206 2020-06-09 Jan Beulich <jbeulich@suse.com>
1208 * i386-dis.c (MOD_0F51): Rename to ...
1209 (MOD_0F50): ... this.
1211 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1213 * arm-dis.c (arm_opcodes): Add dfb.
1214 (thumb32_opcodes): Add dfb.
1216 2020-06-08 Jan Beulich <jbeulich@suse.com>
1218 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1220 2020-06-06 Alan Modra <amodra@gmail.com>
1222 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1224 2020-06-05 Alan Modra <amodra@gmail.com>
1226 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1227 size is large enough.
1229 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1231 * disassemble.c (disassemble_init_for_target): Set endian_code for
1233 * bpf-desc.c: Regenerate.
1234 * bpf-opc.c: Likewise.
1235 * bpf-dis.c: Likewise.
1237 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1239 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1240 (cgen_put_insn_value): Likewise.
1241 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1242 * cgen-dis.in (print_insn): Likewise.
1243 * cgen-ibld.in (insert_1): Likewise.
1244 (insert_1): Likewise.
1245 (insert_insn_normal): Likewise.
1246 (extract_1): Likewise.
1247 * bpf-dis.c: Regenerate.
1248 * bpf-ibld.c: Likewise.
1249 * bpf-ibld.c: Likewise.
1250 * cgen-dis.in: Likewise.
1251 * cgen-ibld.in: Likewise.
1252 * cgen-opc.c: Likewise.
1253 * epiphany-dis.c: Likewise.
1254 * epiphany-ibld.c: Likewise.
1255 * fr30-dis.c: Likewise.
1256 * fr30-ibld.c: Likewise.
1257 * frv-dis.c: Likewise.
1258 * frv-ibld.c: Likewise.
1259 * ip2k-dis.c: Likewise.
1260 * ip2k-ibld.c: Likewise.
1261 * iq2000-dis.c: Likewise.
1262 * iq2000-ibld.c: Likewise.
1263 * lm32-dis.c: Likewise.
1264 * lm32-ibld.c: Likewise.
1265 * m32c-dis.c: Likewise.
1266 * m32c-ibld.c: Likewise.
1267 * m32r-dis.c: Likewise.
1268 * m32r-ibld.c: Likewise.
1269 * mep-dis.c: Likewise.
1270 * mep-ibld.c: Likewise.
1271 * mt-dis.c: Likewise.
1272 * mt-ibld.c: Likewise.
1273 * or1k-dis.c: Likewise.
1274 * or1k-ibld.c: Likewise.
1275 * xc16x-dis.c: Likewise.
1276 * xc16x-ibld.c: Likewise.
1277 * xstormy16-dis.c: Likewise.
1278 * xstormy16-ibld.c: Likewise.
1280 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1282 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1283 (print_insn_): Handle instruction endian.
1284 * bpf-dis.c: Regenerate.
1285 * bpf-desc.c: Regenerate.
1286 * epiphany-dis.c: Likewise.
1287 * epiphany-desc.c: Likewise.
1288 * fr30-dis.c: Likewise.
1289 * fr30-desc.c: Likewise.
1290 * frv-dis.c: Likewise.
1291 * frv-desc.c: Likewise.
1292 * ip2k-dis.c: Likewise.
1293 * ip2k-desc.c: Likewise.
1294 * iq2000-dis.c: Likewise.
1295 * iq2000-desc.c: Likewise.
1296 * lm32-dis.c: Likewise.
1297 * lm32-desc.c: Likewise.
1298 * m32c-dis.c: Likewise.
1299 * m32c-desc.c: Likewise.
1300 * m32r-dis.c: Likewise.
1301 * m32r-desc.c: Likewise.
1302 * mep-dis.c: Likewise.
1303 * mep-desc.c: Likewise.
1304 * mt-dis.c: Likewise.
1305 * mt-desc.c: Likewise.
1306 * or1k-dis.c: Likewise.
1307 * or1k-desc.c: Likewise.
1308 * xc16x-dis.c: Likewise.
1309 * xc16x-desc.c: Likewise.
1310 * xstormy16-dis.c: Likewise.
1311 * xstormy16-desc.c: Likewise.
1313 2020-06-03 Nick Clifton <nickc@redhat.com>
1315 * po/sr.po: Updated Serbian translation.
1317 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1319 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1320 (riscv_get_priv_spec_class): Likewise.
1322 2020-06-01 Alan Modra <amodra@gmail.com>
1324 * bpf-desc.c: Regenerate.
1326 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1327 David Faust <david.faust@oracle.com>
1329 * bpf-desc.c: Regenerate.
1330 * bpf-opc.h: Likewise.
1331 * bpf-opc.c: Likewise.
1332 * bpf-dis.c: Likewise.
1334 2020-05-28 Alan Modra <amodra@gmail.com>
1336 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1339 2020-05-28 Alan Modra <amodra@gmail.com>
1341 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1343 (print_insn_ns32k): Revert last change.
1345 2020-05-28 Nick Clifton <nickc@redhat.com>
1347 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1350 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1352 Fix extraction of signed constants in nios2 disassembler (again).
1354 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1355 extractions of signed fields.
1357 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1359 * s390-opc.txt: Relocate vector load/store instructions with
1360 additional alignment parameter and change architecture level
1361 constraint from z14 to z13.
1363 2020-05-21 Alan Modra <amodra@gmail.com>
1365 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1366 * sparc-dis.c: Likewise.
1367 * tic4x-dis.c: Likewise.
1368 * xtensa-dis.c: Likewise.
1369 * bpf-desc.c: Regenerate.
1370 * epiphany-desc.c: Regenerate.
1371 * fr30-desc.c: Regenerate.
1372 * frv-desc.c: Regenerate.
1373 * ip2k-desc.c: Regenerate.
1374 * iq2000-desc.c: Regenerate.
1375 * lm32-desc.c: Regenerate.
1376 * m32c-desc.c: Regenerate.
1377 * m32r-desc.c: Regenerate.
1378 * mep-asm.c: Regenerate.
1379 * mep-desc.c: Regenerate.
1380 * mt-desc.c: Regenerate.
1381 * or1k-desc.c: Regenerate.
1382 * xc16x-desc.c: Regenerate.
1383 * xstormy16-desc.c: Regenerate.
1385 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1387 * riscv-opc.c (riscv_ext_version_table): The table used to store
1388 all information about the supported spec and the corresponding ISA
1389 versions. Currently, only Zicsr is supported to verify the
1390 correctness of Z sub extension settings. Others will be supported
1391 in the future patches.
1392 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1393 classes and the corresponding strings.
1394 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1395 spec class by giving a ISA spec string.
1396 * riscv-opc.c (struct priv_spec_t): New structure.
1397 (struct priv_spec_t priv_specs): List for all supported privilege spec
1398 classes and the corresponding strings.
1399 (riscv_get_priv_spec_class): New function. Get the corresponding
1400 privilege spec class by giving a spec string.
1401 (riscv_get_priv_spec_name): New function. Get the corresponding
1402 privilege spec string by giving a CSR version class.
1403 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1404 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1405 according to the chosen version. Build a hash table riscv_csr_hash to
1406 store the valid CSR for the chosen pirv verison. Dump the direct
1407 CSR address rather than it's name if it is invalid.
1408 (parse_riscv_dis_option_without_args): New function. Parse the options
1410 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1411 parse the options without arguments first, and then handle the options
1412 with arguments. Add the new option -Mpriv-spec, which has argument.
1413 * riscv-dis.c (print_riscv_disassembler_options): Add description
1414 about the new OBJDUMP option.
1416 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1418 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1419 WC values on POWER10 sync, dcbf and wait instructions.
1420 (insert_pl, extract_pl): New functions.
1421 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1422 (LS3): New , 3-bit L for sync.
1423 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1424 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1425 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1426 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1427 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1428 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1429 <wait>: Enable PL operand on POWER10.
1430 <dcbf>: Enable L3OPT operand on POWER10.
1431 <sync>: Enable SC2 operand on POWER10.
1433 2020-05-19 Stafford Horne <shorne@gmail.com>
1436 * or1k-asm.c: Regenerate.
1437 * or1k-desc.c: Regenerate.
1438 * or1k-desc.h: Regenerate.
1439 * or1k-dis.c: Regenerate.
1440 * or1k-ibld.c: Regenerate.
1441 * or1k-opc.c: Regenerate.
1442 * or1k-opc.h: Regenerate.
1443 * or1k-opinst.c: Regenerate.
1445 2020-05-11 Alan Modra <amodra@gmail.com>
1447 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1450 2020-05-11 Alan Modra <amodra@gmail.com>
1452 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1453 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1455 2020-05-11 Alan Modra <amodra@gmail.com>
1457 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1459 2020-05-11 Alan Modra <amodra@gmail.com>
1461 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1462 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1464 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1466 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1469 2020-05-11 Alan Modra <amodra@gmail.com>
1471 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1472 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1473 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1474 (prefix_opcodes): Add xxeval.
1476 2020-05-11 Alan Modra <amodra@gmail.com>
1478 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1479 xxgenpcvwm, xxgenpcvdm.
1481 2020-05-11 Alan Modra <amodra@gmail.com>
1483 * ppc-opc.c (MP, VXVAM_MASK): Define.
1484 (VXVAPS_MASK): Use VXVA_MASK.
1485 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1486 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1487 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1488 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1490 2020-05-11 Alan Modra <amodra@gmail.com>
1491 Peter Bergner <bergner@linux.ibm.com>
1493 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1495 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1496 YMSK2, XA6a, XA6ap, XB6a entries.
1497 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1498 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1500 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1501 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1502 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1503 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1504 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1505 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1506 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1507 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1508 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1509 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1510 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1511 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1512 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1513 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1515 2020-05-11 Alan Modra <amodra@gmail.com>
1517 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1518 (insert_xts, extract_xts): New functions.
1519 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1520 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1521 (VXRC_MASK, VXSH_MASK): Define.
1522 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1523 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1524 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1525 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1526 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1527 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1528 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1530 2020-05-11 Alan Modra <amodra@gmail.com>
1532 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1533 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1534 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1535 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1536 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1538 2020-05-11 Alan Modra <amodra@gmail.com>
1540 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1541 (XTP, DQXP, DQXP_MASK): Define.
1542 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1543 (prefix_opcodes): Add plxvp and pstxvp.
1545 2020-05-11 Alan Modra <amodra@gmail.com>
1547 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1548 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1549 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1551 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1553 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1555 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1557 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1559 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1561 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1563 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1565 2020-05-11 Alan Modra <amodra@gmail.com>
1567 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1569 2020-05-11 Alan Modra <amodra@gmail.com>
1571 * ppc-dis.c (ppc_opts): Add "power10" entry.
1572 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1573 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1575 2020-05-11 Nick Clifton <nickc@redhat.com>
1577 * po/fr.po: Updated French translation.
1579 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1581 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1582 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1583 (operand_general_constraint_met_p): validate
1584 AARCH64_OPND_UNDEFINED.
1585 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1587 * aarch64-asm-2.c: Regenerated.
1588 * aarch64-dis-2.c: Regenerated.
1589 * aarch64-opc-2.c: Regenerated.
1591 2020-04-29 Nick Clifton <nickc@redhat.com>
1594 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1597 2020-04-29 Nick Clifton <nickc@redhat.com>
1599 * po/sv.po: Updated Swedish translation.
1601 2020-04-29 Nick Clifton <nickc@redhat.com>
1604 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1605 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1606 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1609 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1612 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1613 cmpi only on m68020up and cpu32.
1615 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1617 * aarch64-asm.c (aarch64_ins_none): New.
1618 * aarch64-asm.h (ins_none): New declaration.
1619 * aarch64-dis.c (aarch64_ext_none): New.
1620 * aarch64-dis.h (ext_none): New declaration.
1621 * aarch64-opc.c (aarch64_print_operand): Update case for
1622 AARCH64_OPND_BARRIER_PSB.
1623 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1624 (AARCH64_OPERANDS): Update inserter/extracter for
1625 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1626 * aarch64-asm-2.c: Regenerated.
1627 * aarch64-dis-2.c: Regenerated.
1628 * aarch64-opc-2.c: Regenerated.
1630 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1632 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1633 (aarch64_feature_ras, RAS): Likewise.
1634 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1635 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1636 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1637 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1638 * aarch64-asm-2.c: Regenerated.
1639 * aarch64-dis-2.c: Regenerated.
1640 * aarch64-opc-2.c: Regenerated.
1642 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1644 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1645 (print_insn_neon): Support disassembly of conditional
1648 2020-02-16 David Faust <david.faust@oracle.com>
1650 * bpf-desc.c: Regenerate.
1651 * bpf-desc.h: Likewise.
1652 * bpf-opc.c: Regenerate.
1653 * bpf-opc.h: Likewise.
1655 2020-04-07 Lili Cui <lili.cui@intel.com>
1657 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1658 (prefix_table): New instructions (see prefixes above).
1659 (rm_table): Likewise
1660 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1661 CPU_ANY_TSXLDTRK_FLAGS.
1662 (cpu_flags): Add CpuTSXLDTRK.
1663 * i386-opc.h (enum): Add CpuTSXLDTRK.
1664 (i386_cpu_flags): Add cputsxldtrk.
1665 * i386-opc.tbl: Add XSUSPLDTRK insns.
1666 * i386-init.h: Regenerate.
1667 * i386-tbl.h: Likewise.
1669 2020-04-02 Lili Cui <lili.cui@intel.com>
1671 * i386-dis.c (prefix_table): New instructions serialize.
1672 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1673 CPU_ANY_SERIALIZE_FLAGS.
1674 (cpu_flags): Add CpuSERIALIZE.
1675 * i386-opc.h (enum): Add CpuSERIALIZE.
1676 (i386_cpu_flags): Add cpuserialize.
1677 * i386-opc.tbl: Add SERIALIZE insns.
1678 * i386-init.h: Regenerate.
1679 * i386-tbl.h: Likewise.
1681 2020-03-26 Alan Modra <amodra@gmail.com>
1683 * disassemble.h (opcodes_assert): Declare.
1684 (OPCODES_ASSERT): Define.
1685 * disassemble.c: Don't include assert.h. Include opintl.h.
1686 (opcodes_assert): New function.
1687 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1688 (bfd_h8_disassemble): Reduce size of data array. Correctly
1689 calculate maxlen. Omit insn decoding when insn length exceeds
1690 maxlen. Exit from nibble loop when looking for E, before
1691 accessing next data byte. Move processing of E outside loop.
1692 Replace tests of maxlen in loop with assertions.
1694 2020-03-26 Alan Modra <amodra@gmail.com>
1696 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1698 2020-03-25 Alan Modra <amodra@gmail.com>
1700 * z80-dis.c (suffix): Init mybuf.
1702 2020-03-22 Alan Modra <amodra@gmail.com>
1704 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1705 successflly read from section.
1707 2020-03-22 Alan Modra <amodra@gmail.com>
1709 * arc-dis.c (find_format): Use ISO C string concatenation rather
1710 than line continuation within a string. Don't access needs_limm
1711 before testing opcode != NULL.
1713 2020-03-22 Alan Modra <amodra@gmail.com>
1715 * ns32k-dis.c (print_insn_arg): Update comment.
1716 (print_insn_ns32k): Reduce size of index_offset array, and
1717 initialize, passing -1 to print_insn_arg for args that are not
1718 an index. Don't exit arg loop early. Abort on bad arg number.
1720 2020-03-22 Alan Modra <amodra@gmail.com>
1722 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1723 * s12z-opc.c: Formatting.
1724 (operands_f): Return an int.
1725 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1726 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1727 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1728 (exg_sex_discrim): Likewise.
1729 (create_immediate_operand, create_bitfield_operand),
1730 (create_register_operand_with_size, create_register_all_operand),
1731 (create_register_all16_operand, create_simple_memory_operand),
1732 (create_memory_operand, create_memory_auto_operand): Don't
1733 segfault on malloc failure.
1734 (z_ext24_decode): Return an int status, negative on fail, zero
1736 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1737 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1738 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1739 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1740 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1741 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1742 (loop_primitive_decode, shift_decode, psh_pul_decode),
1743 (bit_field_decode): Similarly.
1744 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1745 to return value, update callers.
1746 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1747 Don't segfault on NULL operand.
1748 (decode_operation): Return OP_INVALID on first fail.
1749 (decode_s12z): Check all reads, returning -1 on fail.
1751 2020-03-20 Alan Modra <amodra@gmail.com>
1753 * metag-dis.c (print_insn_metag): Don't ignore status from
1756 2020-03-20 Alan Modra <amodra@gmail.com>
1758 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1759 Initialize parts of buffer not written when handling a possible
1760 2-byte insn at end of section. Don't attempt decoding of such
1761 an insn by the 4-byte machinery.
1763 2020-03-20 Alan Modra <amodra@gmail.com>
1765 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1766 partially filled buffer. Prevent lookup of 4-byte insns when
1767 only VLE 2-byte insns are possible due to section size. Print
1768 ".word" rather than ".long" for 2-byte leftovers.
1770 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1773 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1775 2020-03-13 Jan Beulich <jbeulich@suse.com>
1777 * i386-dis.c (X86_64_0D): Rename to ...
1778 (X86_64_0E): ... this.
1780 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1782 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1783 * Makefile.in: Regenerated.
1785 2020-03-09 Jan Beulich <jbeulich@suse.com>
1787 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1789 * i386-tbl.h: Re-generate.
1791 2020-03-09 Jan Beulich <jbeulich@suse.com>
1793 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1794 vprot*, vpsha*, and vpshl*.
1795 * i386-tbl.h: Re-generate.
1797 2020-03-09 Jan Beulich <jbeulich@suse.com>
1799 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1800 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1801 * i386-tbl.h: Re-generate.
1803 2020-03-09 Jan Beulich <jbeulich@suse.com>
1805 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1806 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1807 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1808 * i386-tbl.h: Re-generate.
1810 2020-03-09 Jan Beulich <jbeulich@suse.com>
1812 * i386-gen.c (struct template_arg, struct template_instance,
1813 struct template_param, struct template, templates,
1814 parse_template, expand_templates): New.
1815 (process_i386_opcodes): Various local variables moved to
1816 expand_templates. Call parse_template and expand_templates.
1817 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1818 * i386-tbl.h: Re-generate.
1820 2020-03-06 Jan Beulich <jbeulich@suse.com>
1822 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1823 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1824 register and memory source templates. Replace VexW= by VexW*
1826 * i386-tbl.h: Re-generate.
1828 2020-03-06 Jan Beulich <jbeulich@suse.com>
1830 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1831 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1832 * i386-tbl.h: Re-generate.
1834 2020-03-06 Jan Beulich <jbeulich@suse.com>
1836 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1837 * i386-tbl.h: Re-generate.
1839 2020-03-06 Jan Beulich <jbeulich@suse.com>
1841 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1842 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1843 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1844 VexW0 on SSE2AVX variants.
1845 (vmovq): Drop NoRex64 from XMM/XMM variants.
1846 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1847 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1848 applicable use VexW0.
1849 * i386-tbl.h: Re-generate.
1851 2020-03-06 Jan Beulich <jbeulich@suse.com>
1853 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1854 * i386-opc.h (Rex64): Delete.
1855 (struct i386_opcode_modifier): Remove rex64 field.
1856 * i386-opc.tbl (crc32): Drop Rex64.
1857 Replace Rex64 with Size64 everywhere else.
1858 * i386-tbl.h: Re-generate.
1860 2020-03-06 Jan Beulich <jbeulich@suse.com>
1862 * i386-dis.c (OP_E_memory): Exclude recording of used address
1863 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1864 addressed memory operands for MPX insns.
1866 2020-03-06 Jan Beulich <jbeulich@suse.com>
1868 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1869 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1870 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1871 (ptwrite): Split into non-64-bit and 64-bit forms.
1872 * i386-tbl.h: Re-generate.
1874 2020-03-06 Jan Beulich <jbeulich@suse.com>
1876 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1878 * i386-tbl.h: Re-generate.
1880 2020-03-04 Jan Beulich <jbeulich@suse.com>
1882 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1883 (prefix_table): Move vmmcall here. Add vmgexit.
1884 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1885 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1886 (cpu_flags): Add CpuSEV_ES entry.
1887 * i386-opc.h (CpuSEV_ES): New.
1888 (union i386_cpu_flags): Add cpusev_es field.
1889 * i386-opc.tbl (vmgexit): New.
1890 * i386-init.h, i386-tbl.h: Re-generate.
1892 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1894 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1896 * i386-opc.h (IGNORESIZE): New.
1897 (DEFAULTSIZE): Likewise.
1898 (IgnoreSize): Removed.
1899 (DefaultSize): Likewise.
1900 (MnemonicSize): New.
1901 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1903 * i386-opc.tbl (IgnoreSize): New.
1904 (DefaultSize): Likewise.
1905 * i386-tbl.h: Regenerated.
1907 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1910 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1913 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1916 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1917 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1918 * i386-tbl.h: Regenerated.
1920 2020-02-26 Alan Modra <amodra@gmail.com>
1922 * aarch64-asm.c: Indent labels correctly.
1923 * aarch64-dis.c: Likewise.
1924 * aarch64-gen.c: Likewise.
1925 * aarch64-opc.c: Likewise.
1926 * alpha-dis.c: Likewise.
1927 * i386-dis.c: Likewise.
1928 * nds32-asm.c: Likewise.
1929 * nfp-dis.c: Likewise.
1930 * visium-dis.c: Likewise.
1932 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1934 * arc-regs.h (int_vector_base): Make it available for all ARC
1937 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
1939 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1942 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
1944 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1945 c.mv/c.li if rs1 is zero.
1947 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1949 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1950 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1952 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1953 * i386-opc.h (CpuABM): Removed.
1955 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1956 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1957 popcnt. Remove CpuABM from lzcnt.
1958 * i386-init.h: Regenerated.
1959 * i386-tbl.h: Likewise.
1961 2020-02-17 Jan Beulich <jbeulich@suse.com>
1963 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1964 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1965 VexW1 instead of open-coding them.
1966 * i386-tbl.h: Re-generate.
1968 2020-02-17 Jan Beulich <jbeulich@suse.com>
1970 * i386-opc.tbl (AddrPrefixOpReg): Define.
1971 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1972 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1973 templates. Drop NoRex64.
1974 * i386-tbl.h: Re-generate.
1976 2020-02-17 Jan Beulich <jbeulich@suse.com>
1979 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1980 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1981 into Intel syntax instance (with Unpsecified) and AT&T one
1983 (vcvtneps2bf16): Likewise, along with folding the two so far
1985 * i386-tbl.h: Re-generate.
1987 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1989 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1990 CPU_ANY_SSE4A_FLAGS.
1992 2020-02-17 Alan Modra <amodra@gmail.com>
1994 * i386-gen.c (cpu_flag_init): Correct last change.
1996 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1998 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2001 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2003 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2006 2020-02-14 Jan Beulich <jbeulich@suse.com>
2009 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2010 destination for Cpu64-only variant.
2011 (movzx): Fold patterns.
2012 * i386-tbl.h: Re-generate.
2014 2020-02-13 Jan Beulich <jbeulich@suse.com>
2016 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2017 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2018 CPU_ANY_SSE4_FLAGS entry.
2019 * i386-init.h: Re-generate.
2021 2020-02-12 Jan Beulich <jbeulich@suse.com>
2023 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2024 with Unspecified, making the present one AT&T syntax only.
2025 * i386-tbl.h: Re-generate.
2027 2020-02-12 Jan Beulich <jbeulich@suse.com>
2029 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2030 * i386-tbl.h: Re-generate.
2032 2020-02-12 Jan Beulich <jbeulich@suse.com>
2035 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2036 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2037 Amd64 and Intel64 templates.
2038 (call, jmp): Likewise for far indirect variants. Dro
2040 * i386-tbl.h: Re-generate.
2042 2020-02-11 Jan Beulich <jbeulich@suse.com>
2044 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2045 * i386-opc.h (ShortForm): Delete.
2046 (struct i386_opcode_modifier): Remove shortform field.
2047 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2048 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2049 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2050 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2052 * i386-tbl.h: Re-generate.
2054 2020-02-11 Jan Beulich <jbeulich@suse.com>
2056 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2057 fucompi): Drop ShortForm from operand-less templates.
2058 * i386-tbl.h: Re-generate.
2060 2020-02-11 Alan Modra <amodra@gmail.com>
2062 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2063 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2064 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2065 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2066 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2068 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2070 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2071 (cde_opcodes): Add VCX* instructions.
2073 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2074 Matthew Malcomson <matthew.malcomson@arm.com>
2076 * arm-dis.c (struct cdeopcode32): New.
2077 (CDE_OPCODE): New macro.
2078 (cde_opcodes): New disassembly table.
2079 (regnames): New option to table.
2080 (cde_coprocs): New global variable.
2081 (print_insn_cde): New
2082 (print_insn_thumb32): Use print_insn_cde.
2083 (parse_arm_disassembler_options): Parse coprocN args.
2085 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2088 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2090 * i386-opc.h (AMD64): Removed.
2091 (Intel64): Likewose.
2093 (INTEL64): Likewise.
2094 (INTEL64ONLY): Likewise.
2095 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2096 * i386-opc.tbl (Amd64): New.
2097 (Intel64): Likewise.
2098 (Intel64Only): Likewise.
2099 Replace AMD64 with Amd64. Update sysenter/sysenter with
2100 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2101 * i386-tbl.h: Regenerated.
2103 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2106 * z80-dis.c: Add support for GBZ80 opcodes.
2108 2020-02-04 Alan Modra <amodra@gmail.com>
2110 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2112 2020-02-03 Alan Modra <amodra@gmail.com>
2114 * m32c-ibld.c: Regenerate.
2116 2020-02-01 Alan Modra <amodra@gmail.com>
2118 * frv-ibld.c: Regenerate.
2120 2020-01-31 Jan Beulich <jbeulich@suse.com>
2122 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2123 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2124 (OP_E_memory): Replace xmm_mdq_mode case label by
2125 vex_scalar_w_dq_mode one.
2126 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2128 2020-01-31 Jan Beulich <jbeulich@suse.com>
2130 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2131 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2132 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2133 (intel_operand_size): Drop vex_w_dq_mode case label.
2135 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2137 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2138 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2140 2020-01-30 Alan Modra <amodra@gmail.com>
2142 * m32c-ibld.c: Regenerate.
2144 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2146 * bpf-opc.c: Regenerate.
2148 2020-01-30 Jan Beulich <jbeulich@suse.com>
2150 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2151 (dis386): Use them to replace C2/C3 table entries.
2152 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2153 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2154 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2155 * i386-tbl.h: Re-generate.
2157 2020-01-30 Jan Beulich <jbeulich@suse.com>
2159 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2161 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2163 * i386-tbl.h: Re-generate.
2165 2020-01-30 Alan Modra <amodra@gmail.com>
2167 * tic4x-dis.c (tic4x_dp): Make unsigned.
2169 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2170 Jan Beulich <jbeulich@suse.com>
2173 * i386-dis.c (MOVSXD_Fixup): New function.
2174 (movsxd_mode): New enum.
2175 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2176 (intel_operand_size): Handle movsxd_mode.
2177 (OP_E_register): Likewise.
2179 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2180 register on movsxd. Add movsxd with 16-bit destination register
2181 for AMD64 and Intel64 ISAs.
2182 * i386-tbl.h: Regenerated.
2184 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2187 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2188 * aarch64-asm-2.c: Regenerate
2189 * aarch64-dis-2.c: Likewise.
2190 * aarch64-opc-2.c: Likewise.
2192 2020-01-21 Jan Beulich <jbeulich@suse.com>
2194 * i386-opc.tbl (sysret): Drop DefaultSize.
2195 * i386-tbl.h: Re-generate.
2197 2020-01-21 Jan Beulich <jbeulich@suse.com>
2199 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2201 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2202 * i386-tbl.h: Re-generate.
2204 2020-01-20 Nick Clifton <nickc@redhat.com>
2206 * po/de.po: Updated German translation.
2207 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2208 * po/uk.po: Updated Ukranian translation.
2210 2020-01-20 Alan Modra <amodra@gmail.com>
2212 * hppa-dis.c (fput_const): Remove useless cast.
2214 2020-01-20 Alan Modra <amodra@gmail.com>
2216 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2218 2020-01-18 Nick Clifton <nickc@redhat.com>
2220 * configure: Regenerate.
2221 * po/opcodes.pot: Regenerate.
2223 2020-01-18 Nick Clifton <nickc@redhat.com>
2225 Binutils 2.34 branch created.
2227 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2229 * opintl.h: Fix spelling error (seperate).
2231 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2233 * i386-opc.tbl: Add {vex} pseudo prefix.
2234 * i386-tbl.h: Regenerated.
2236 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2239 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2240 (neon_opcodes): Likewise.
2241 (select_arm_features): Make sure we enable MVE bits when selecting
2242 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2245 2020-01-16 Jan Beulich <jbeulich@suse.com>
2247 * i386-opc.tbl: Drop stale comment from XOP section.
2249 2020-01-16 Jan Beulich <jbeulich@suse.com>
2251 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2252 (extractps): Add VexWIG to SSE2AVX forms.
2253 * i386-tbl.h: Re-generate.
2255 2020-01-16 Jan Beulich <jbeulich@suse.com>
2257 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2258 Size64 from and use VexW1 on SSE2AVX forms.
2259 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2260 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2261 * i386-tbl.h: Re-generate.
2263 2020-01-15 Alan Modra <amodra@gmail.com>
2265 * tic4x-dis.c (tic4x_version): Make unsigned long.
2266 (optab, optab_special, registernames): New file scope vars.
2267 (tic4x_print_register): Set up registernames rather than
2268 malloc'd registertable.
2269 (tic4x_disassemble): Delete optable and optable_special. Use
2270 optab and optab_special instead. Throw away old optab,
2271 optab_special and registernames when info->mach changes.
2273 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2276 * z80-dis.c (suffix): Use .db instruction to generate double
2279 2020-01-14 Alan Modra <amodra@gmail.com>
2281 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2282 values to unsigned before shifting.
2284 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2286 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2288 (print_insn_thumb16, print_insn_thumb32): Likewise.
2289 (print_insn): Initialize the insn info.
2290 * i386-dis.c (print_insn): Initialize the insn info fields, and
2293 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2295 * arc-opc.c (C_NE): Make it required.
2297 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2299 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2300 reserved register name.
2302 2020-01-13 Alan Modra <amodra@gmail.com>
2304 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2305 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2307 2020-01-13 Alan Modra <amodra@gmail.com>
2309 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2310 result of wasm_read_leb128 in a uint64_t and check that bits
2311 are not lost when copying to other locals. Use uint32_t for
2312 most locals. Use PRId64 when printing int64_t.
2314 2020-01-13 Alan Modra <amodra@gmail.com>
2316 * score-dis.c: Formatting.
2317 * score7-dis.c: Formatting.
2319 2020-01-13 Alan Modra <amodra@gmail.com>
2321 * score-dis.c (print_insn_score48): Use unsigned variables for
2322 unsigned values. Don't left shift negative values.
2323 (print_insn_score32): Likewise.
2324 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2326 2020-01-13 Alan Modra <amodra@gmail.com>
2328 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2330 2020-01-13 Alan Modra <amodra@gmail.com>
2332 * fr30-ibld.c: Regenerate.
2334 2020-01-13 Alan Modra <amodra@gmail.com>
2336 * xgate-dis.c (print_insn): Don't left shift signed value.
2337 (ripBits): Formatting, use 1u.
2339 2020-01-10 Alan Modra <amodra@gmail.com>
2341 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2342 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2344 2020-01-10 Alan Modra <amodra@gmail.com>
2346 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2347 and XRREG value earlier to avoid a shift with negative exponent.
2348 * m10200-dis.c (disassemble): Similarly.
2350 2020-01-09 Nick Clifton <nickc@redhat.com>
2353 * z80-dis.c (ld_ii_ii): Use correct cast.
2355 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2358 * z80-dis.c (ld_ii_ii): Use character constant when checking
2361 2020-01-09 Jan Beulich <jbeulich@suse.com>
2363 * i386-dis.c (SEP_Fixup): New.
2365 (dis386_twobyte): Use it for sysenter/sysexit.
2366 (enum x86_64_isa): Change amd64 enumerator to value 1.
2367 (OP_J): Compare isa64 against intel64 instead of amd64.
2368 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2370 * i386-tbl.h: Re-generate.
2372 2020-01-08 Alan Modra <amodra@gmail.com>
2374 * z8k-dis.c: Include libiberty.h
2375 (instr_data_s): Make max_fetched unsigned.
2376 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2377 Don't exceed byte_info bounds.
2378 (output_instr): Make num_bytes unsigned.
2379 (unpack_instr): Likewise for nibl_count and loop.
2380 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2382 * z8k-opc.h: Regenerate.
2384 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2386 * arc-tbl.h (llock): Use 'LLOCK' as class.
2388 (scond): Use 'SCOND' as class.
2390 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2393 2020-01-06 Alan Modra <amodra@gmail.com>
2395 * m32c-ibld.c: Regenerate.
2397 2020-01-06 Alan Modra <amodra@gmail.com>
2400 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2401 Peek at next byte to prevent recursion on repeated prefix bytes.
2402 Ensure uninitialised "mybuf" is not accessed.
2403 (print_insn_z80): Don't zero n_fetch and n_used here,..
2404 (print_insn_z80_buf): ..do it here instead.
2406 2020-01-04 Alan Modra <amodra@gmail.com>
2408 * m32r-ibld.c: Regenerate.
2410 2020-01-04 Alan Modra <amodra@gmail.com>
2412 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2414 2020-01-04 Alan Modra <amodra@gmail.com>
2416 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2418 2020-01-04 Alan Modra <amodra@gmail.com>
2420 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2422 2020-01-03 Jan Beulich <jbeulich@suse.com>
2424 * aarch64-tbl.h (aarch64_opcode_table): Use
2425 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2427 2020-01-03 Jan Beulich <jbeulich@suse.com>
2429 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2430 forms of SUDOT and USDOT.
2432 2020-01-03 Jan Beulich <jbeulich@suse.com>
2434 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2436 * opcodes/aarch64-dis-2.c: Re-generate.
2438 2020-01-03 Jan Beulich <jbeulich@suse.com>
2440 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2442 * opcodes/aarch64-dis-2.c: Re-generate.
2444 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2446 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2448 2020-01-01 Alan Modra <amodra@gmail.com>
2450 Update year range in copyright notice of all files.
2452 For older changes see ChangeLog-2019
2454 Copyright (C) 2020 Free Software Foundation, Inc.
2456 Copying and distribution of this file, with or without modification,
2457 are permitted in any medium without royalty provided the copyright
2458 notice and this notice are preserved.
2464 version-control: never
projects / thirdparty / binutils-gdb.git / blob