1 2020-09-10 Nick Clifton <nickc@redhat.com>
3 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
4 for hidden, local, no-type symbols.
5 (disassemble_init_powerpc): Point the symbol_is_valid field in the
6 info structure at the new function.
8 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
10 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
11 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
14 2020-09-10 Nick Clifton <nickc@redhat.com>
16 * csky-dis.c (csky_output_operand): Coerce the immediate values to
19 2020-09-10 Alan Modra <amodra@gmail.com>
21 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
23 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
25 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
28 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
30 * csky-dis.c (csky_output_operand): Add handlers for
31 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
32 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
33 to support FPUV3 instructions.
34 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
35 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
36 OPRND_TYPE_DFLOAT_FMOVI.
37 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
38 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
39 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
40 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
41 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
42 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
43 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
44 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
45 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
46 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
47 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
48 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
49 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
50 (csky_v2_opcodes): Add FPUV3 instructions.
52 2020-09-08 Alex Coplan <alex.coplan@arm.com>
54 * aarch64-dis.c (print_operands): Pass CPU features to
55 aarch64_print_operand().
56 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
57 preferred disassembly of system registers.
58 (SR_RNG): Refactor to use new SR_FEAT2 macro.
65 (SR_EXPAND_EL12): New.
66 (aarch64_sys_regs): Specify which registers are only on
67 A-profile, add R-profile system registers.
71 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
74 2020-09-08 Alex Coplan <alex.coplan@arm.com>
76 * aarch64-tbl.h (aarch64_feature_v8_r): New.
79 (aarch64_opcode_table): Add dfb.
80 * aarch64-opc-2.c: Regenerate.
81 * aarch64-asm-2.c: Regenerate.
82 * aarch64-dis-2.c: Regenerate.
84 2020-09-08 Alex Coplan <alex.coplan@arm.com>
86 * aarch64-dis.c (arch_variant): New.
87 (determine_disassembling_preference): Disassemble according to
89 (select_aarch64_variant): New.
90 (print_insn_aarch64): Set feature set.
92 2020-09-02 Alan Modra <amodra@gmail.com>
94 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
95 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
96 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
97 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
98 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
99 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
100 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
101 for value parameter and update code to suit.
102 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
103 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
105 2020-09-02 Alan Modra <amodra@gmail.com>
107 * i386-dis.c (OP_E_memory): Don't cast to signed type when
109 (get32, get32s): Use unsigned types in shift expressions.
111 2020-09-02 Alan Modra <amodra@gmail.com>
113 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
115 2020-09-02 Alan Modra <amodra@gmail.com>
117 * crx-dis.c: Whitespace.
118 (print_arg): Use unsigned type for longdisp and mask variables,
119 and for left shift constant.
121 2020-09-02 Alan Modra <amodra@gmail.com>
123 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
124 * bpf-ibld.c: Regenerate.
125 * epiphany-ibld.c: Regenerate.
126 * fr30-ibld.c: Regenerate.
127 * frv-ibld.c: Regenerate.
128 * ip2k-ibld.c: Regenerate.
129 * iq2000-ibld.c: Regenerate.
130 * lm32-ibld.c: Regenerate.
131 * m32c-ibld.c: Regenerate.
132 * m32r-ibld.c: Regenerate.
133 * mep-ibld.c: Regenerate.
134 * mt-ibld.c: Regenerate.
135 * or1k-ibld.c: Regenerate.
136 * xc16x-ibld.c: Regenerate.
137 * xstormy16-ibld.c: Regenerate.
139 2020-09-02 Alan Modra <amodra@gmail.com>
141 * bfin-dis.c (MASKBITS): Use SIGNBIT.
143 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
145 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
146 to CSKYV2_ISA_3E3R3 instruction set.
148 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
150 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
152 2020-09-01 Alan Modra <amodra@gmail.com>
154 * mep-ibld.c: Regenerate.
156 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
158 * csky-dis.c (csky_output_operand): Assign dis_info.value for
161 2020-08-30 Alan Modra <amodra@gmail.com>
163 * cr16-dis.c: Formatting.
164 (parameter): Delete struct typedef. Use dwordU instead
166 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
168 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
170 2020-08-29 Alan Modra <amodra@gmail.com>
173 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
174 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
176 2020-08-28 Alan Modra <amodra@gmail.com>
180 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
181 (extract_normal): Likewise.
182 (insert_normal): Likewise, and move past zero length test.
183 (put_insn_int_value): Handle mask for zero length, use 1UL.
184 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
185 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
186 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
187 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
189 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
191 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
192 (csky_dis_info): Add member isa.
193 (csky_find_inst_info): Skip instructions that do not belong to
195 (csky_get_disassembler): Get infomation from attribute section.
196 (print_insn_csky): Set defualt ISA flag.
197 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
198 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
199 isa_flag32'type to unsigned 64 bits.
201 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
203 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
205 2020-08-26 David Faust <david.faust@oracle.com>
207 * bpf-desc.c: Regenerate.
208 * bpf-desc.h: Likewise.
209 * bpf-opc.c: Likewise.
210 * bpf-opc.h: Likewise.
211 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
212 ISA when appropriate.
214 2020-08-25 Alan Modra <amodra@gmail.com>
217 * vax-dis.c (parse_disassembler_options): Always add at least one
218 to entry_addr_total_slots.
220 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
222 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
223 in other CPUs to speed up disassembling.
224 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
225 Change plsli.u16 to plsli.16, change sync's operand format.
227 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
229 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
231 2020-08-21 Nick Clifton <nickc@redhat.com>
233 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
236 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
238 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
240 2020-08-19 Alan Modra <amodra@gmail.com>
242 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
245 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
247 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
248 <xvcvbf16spn>: ...to this.
250 2020-08-12 Alex Coplan <alex.coplan@arm.com>
252 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
254 2020-08-12 Nick Clifton <nickc@redhat.com>
256 * po/sr.po: Updated Serbian translation.
258 2020-08-11 Alan Modra <amodra@gmail.com>
260 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
262 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
264 * aarch64-opc.c (aarch64_print_operand):
265 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
266 (aarch64_sys_reg_supported_p): Function removed.
267 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
268 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
271 2020-08-10 Alan Modra <amodra@gmail.com>
273 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
276 2020-08-10 Alan Modra <amodra@gmail.com>
278 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
279 Enable icbt for power5, miso for power8.
281 2020-08-10 Alan Modra <amodra@gmail.com>
283 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
284 mtvsrd, and similarly for mfvsrd.
286 2020-08-04 Christian Groessler <chris@groessler.org>
287 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
289 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
290 opcodes (special "out" to absolute address).
291 * z8k-opc.h: Regenerate.
293 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
296 * i386-opc.h (Prefix_Disp8): New.
297 (Prefix_Disp16): Likewise.
298 (Prefix_Disp32): Likewise.
299 (Prefix_Load): Likewise.
300 (Prefix_Store): Likewise.
301 (Prefix_VEX): Likewise.
302 (Prefix_VEX3): Likewise.
303 (Prefix_EVEX): Likewise.
304 (Prefix_REX): Likewise.
305 (Prefix_NoOptimize): Likewise.
306 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
307 * i386-tbl.h: Regenerated.
309 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
311 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
312 default case with abort() instead of printing an error message and
313 continuing, to avoid a maybe-uninitialized warning.
315 2020-07-24 Nick Clifton <nickc@redhat.com>
317 * po/de.po: Updated German translation.
319 2020-07-21 Jan Beulich <jbeulich@suse.com>
321 * i386-dis.c (OP_E_memory): Revert previous change.
323 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
326 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
327 without base nor index registers.
329 2020-07-15 Jan Beulich <jbeulich@suse.com>
331 * i386-dis.c (putop): Move 'V' and 'W' handling.
333 2020-07-15 Jan Beulich <jbeulich@suse.com>
335 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
336 construct for push/pop of register.
337 (putop): Honor cond when handling 'P'. Drop handling of plain
340 2020-07-15 Jan Beulich <jbeulich@suse.com>
342 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
343 description. Drop '&' description. Use P for push of immediate,
344 pushf/popf, enter, and leave. Use %LP for lret/retf.
345 (dis386_twobyte): Use P for push/pop of fs/gs.
346 (reg_table): Use P for push/pop. Use @ for near call/jmp.
347 (x86_64_table): Use P for far call/jmp.
348 (putop): Drop handling of 'U' and '&'. Move and adjust handling
349 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
351 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
352 and dqw_mode (unconditional).
354 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
357 * i386-dis.c (OP_E_memory): Without base nor index registers,
358 32-bit displacement to 64 bits.
360 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
362 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
363 faulty double register pair is detected.
365 2020-07-14 Jan Beulich <jbeulich@suse.com>
367 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
369 2020-07-14 Jan Beulich <jbeulich@suse.com>
371 * i386-dis.c (OP_R, Rm): Delete.
372 (MOD_0F24, MOD_0F26): Rename to ...
373 (X86_64_0F24, X86_64_0F26): ... respectively.
374 (dis386): Update 'L' and 'Z' comments.
375 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
377 (mod_table): Move opcode 0F24 and 0F26 entries ...
378 (x86_64_table): ... here.
379 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
382 2020-07-14 Jan Beulich <jbeulich@suse.com>
384 * i386-dis.c (Rd, Rdq, MaskR): Delete.
385 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
386 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
387 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
388 MOD_EVEX_0F387C): New enumerators.
389 (reg_table): Use Edq for rdssp.
390 (prefix_table): Use Edq for incssp.
391 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
392 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
393 ktest*, and kshift*. Use Edq / MaskE for kmov*.
394 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
395 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
396 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
397 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
398 0F3828_P_1 and 0F3838_P_1.
399 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
400 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
402 2020-07-14 Jan Beulich <jbeulich@suse.com>
404 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
405 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
406 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
407 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
408 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
409 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
410 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
411 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
412 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
413 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
414 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
415 (reg_table, prefix_table, three_byte_table, vex_table,
416 vex_len_table, mod_table, rm_table): Replace / remove respective
418 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
419 of PREFIX_DATA in used_prefixes.
421 2020-07-14 Jan Beulich <jbeulich@suse.com>
423 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
424 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
425 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
426 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
427 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
428 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
429 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
430 VEX_W_0F3A33_L_0): Delete.
431 (dis386): Adjust "BW" description.
432 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
433 0F3A31, 0F3A32, and 0F3A33.
434 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
436 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
439 2020-07-14 Jan Beulich <jbeulich@suse.com>
441 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
442 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
443 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
444 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
445 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
446 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
447 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
448 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
449 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
450 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
451 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
452 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
453 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
454 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
455 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
456 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
457 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
458 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
459 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
460 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
461 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
462 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
463 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
464 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
465 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
466 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
467 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
468 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
469 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
470 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
471 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
472 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
473 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
474 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
475 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
476 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
477 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
478 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
479 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
480 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
481 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
482 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
483 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
484 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
485 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
486 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
487 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
488 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
489 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
490 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
491 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
492 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
493 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
494 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
495 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
496 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
497 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
498 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
499 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
500 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
501 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
502 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
503 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
504 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
505 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
506 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
507 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
508 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
509 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
510 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
511 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
512 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
513 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
514 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
515 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
516 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
517 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
518 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
519 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
520 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
521 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
522 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
523 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
524 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
525 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
526 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
527 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
528 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
529 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
530 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
531 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
532 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
533 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
534 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
535 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
536 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
537 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
538 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
539 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
540 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
541 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
542 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
543 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
544 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
545 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
546 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
547 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
548 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
549 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
550 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
551 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
552 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
553 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
554 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
555 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
556 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
557 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
558 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
559 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
560 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
561 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
562 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
563 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
564 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
565 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
566 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
567 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
568 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
569 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
570 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
571 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
572 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
573 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
574 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
575 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
576 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
577 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
578 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
579 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
580 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
581 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
582 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
583 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
584 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
585 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
586 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
587 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
588 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
589 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
590 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
591 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
592 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
593 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
594 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
595 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
596 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
597 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
598 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
599 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
600 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
601 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
602 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
603 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
604 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
605 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
606 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
607 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
608 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
609 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
610 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
611 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
612 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
613 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
614 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
615 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
616 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
617 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
618 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
619 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
620 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
621 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
622 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
623 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
624 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
625 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
626 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
627 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
628 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
629 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
630 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
631 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
632 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
633 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
634 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
635 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
636 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
637 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
638 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
639 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
640 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
641 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
642 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
643 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
644 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
645 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
646 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
647 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
648 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
649 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
650 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
651 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
652 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
653 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
654 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
655 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
656 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
657 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
658 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
659 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
660 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
661 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
662 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
663 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
664 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
665 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
666 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
667 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
668 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
669 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
670 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
671 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
672 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
673 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
674 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
675 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
676 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
677 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
678 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
679 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
680 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
681 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
682 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
683 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
684 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
685 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
686 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
687 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
688 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
689 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
690 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
691 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
692 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
693 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
694 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
695 EVEX_W_0F3A72_P_2): Rename to ...
696 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
697 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
698 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
699 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
700 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
701 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
702 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
703 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
704 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
705 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
706 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
707 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
708 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
709 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
710 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
711 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
712 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
713 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
714 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
715 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
716 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
717 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
718 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
719 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
720 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
721 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
722 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
723 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
724 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
725 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
726 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
727 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
728 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
729 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
730 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
731 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
732 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
733 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
734 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
735 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
736 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
737 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
738 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
739 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
740 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
741 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
742 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
743 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
744 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
745 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
746 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
747 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
748 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
749 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
750 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
751 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
752 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
753 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
754 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
755 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
756 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
757 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
758 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
759 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
760 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
761 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
762 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
763 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
764 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
765 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
766 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
767 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
769 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
770 vex_w_table, mod_table): Replace / remove respective entries.
771 (print_insn): Move up dp->prefix_requirement handling. Handle
773 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
774 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
775 Replace / remove respective entries.
777 2020-07-14 Jan Beulich <jbeulich@suse.com>
779 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
780 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
781 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
782 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
783 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
785 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
786 0F2C, 0F2D, 0F2E, and 0F2F.
787 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
790 2020-07-14 Jan Beulich <jbeulich@suse.com>
792 * i386-dis.c (OP_VexR, VexScalarR): New.
793 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
794 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
795 need_vex_reg): Delete.
796 (prefix_table): Replace VexScalar by VexScalarR and
797 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
798 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
799 (vex_len_table): Replace EXqVexScalarS by EXqS.
800 (get_valid_dis386): Don't set need_vex_reg.
801 (print_insn): Don't initialize need_vex_reg.
802 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
803 q_scalar_swap_mode cases.
804 (OP_EX): Don't check for d_scalar_swap_mode and
806 (OP_VEX): Done check need_vex_reg.
807 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
808 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
809 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
811 2020-07-14 Jan Beulich <jbeulich@suse.com>
813 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
814 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
815 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
816 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
817 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
818 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
819 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
820 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
821 (vex_table): Replace Vex128 by Vex.
822 (vex_len_table): Likewise. Adjust referenced enum names.
823 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
824 referenced enum names.
825 (OP_VEX): Drop vex128_mode and vex256_mode cases.
826 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
828 2020-07-14 Jan Beulich <jbeulich@suse.com>
830 * i386-dis.c (dis386): "LW" description now applies to "DQ".
831 (putop): Handle "DQ". Don't handle "LW" anymore.
832 (prefix_table, mod_table): Replace %LW by %DQ.
833 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
835 2020-07-14 Jan Beulich <jbeulich@suse.com>
837 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
838 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
839 d_scalar_swap_mode case handling. Move shift adjsutment into
840 the case its applicable to.
842 2020-07-14 Jan Beulich <jbeulich@suse.com>
844 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
845 (EXbScalar, EXwScalar): Fold to ...
846 (EXbwUnit): ... this.
847 (b_scalar_mode, w_scalar_mode): Fold to ...
848 (bw_unit_mode): ... this.
849 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
850 w_scalar_mode handling by bw_unit_mode one.
851 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
853 * i386-dis-evex-prefix.h: ... here.
855 2020-07-14 Jan Beulich <jbeulich@suse.com>
857 * i386-dis.c (PCMPESTR_Fixup): Delete.
858 (dis386): Adjust "LQ" description.
859 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
860 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
861 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
862 vpcmpestrm, and vpcmpestri.
863 (putop): Honor "cond" when handling LQ.
864 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
865 vcvtsi2ss and vcvtusi2ss.
866 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
867 vcvtsi2sd and vcvtusi2sd.
869 2020-07-14 Jan Beulich <jbeulich@suse.com>
871 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
872 (simd_cmp_op): Add const.
873 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
874 (CMP_Fixup): Handle VEX case.
875 (prefix_table): Replace VCMP by CMP.
876 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
878 2020-07-14 Jan Beulich <jbeulich@suse.com>
880 * i386-dis.c (MOVBE_Fixup): Delete.
882 (prefix_table): Use Mv for movbe entries.
884 2020-07-14 Jan Beulich <jbeulich@suse.com>
886 * i386-dis.c (CRC32_Fixup): Delete.
887 (prefix_table): Use Eb/Ev for crc32 entries.
889 2020-07-14 Jan Beulich <jbeulich@suse.com>
891 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
892 Conditionalize invocations of "USED_REX (0)".
894 2020-07-14 Jan Beulich <jbeulich@suse.com>
896 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
897 CH, DH, BH, AX, DX): Delete.
898 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
899 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
900 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
902 2020-07-10 Lili Cui <lili.cui@intel.com>
904 * i386-dis.c (TMM): New.
907 (MVexSIBMEM): Likewise.
908 (tmm_mode): Likewise.
909 (vex_sibmem_mode): Likewise.
910 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
911 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
912 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
913 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
914 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
915 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
916 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
917 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
918 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
919 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
920 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
921 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
922 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
923 (PREFIX_VEX_0F3849_X86_64): Likewise.
924 (PREFIX_VEX_0F384B_X86_64): Likewise.
925 (PREFIX_VEX_0F385C_X86_64): Likewise.
926 (PREFIX_VEX_0F385E_X86_64): Likewise.
927 (X86_64_VEX_0F3849): Likewise.
928 (X86_64_VEX_0F384B): Likewise.
929 (X86_64_VEX_0F385C): Likewise.
930 (X86_64_VEX_0F385E): Likewise.
931 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
932 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
933 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
934 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
935 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
936 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
937 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
938 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
939 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
940 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
941 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
942 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
943 (VEX_W_0F3849_X86_64_P_0): Likewise.
944 (VEX_W_0F3849_X86_64_P_2): Likewise.
945 (VEX_W_0F3849_X86_64_P_3): Likewise.
946 (VEX_W_0F384B_X86_64_P_1): Likewise.
947 (VEX_W_0F384B_X86_64_P_2): Likewise.
948 (VEX_W_0F384B_X86_64_P_3): Likewise.
949 (VEX_W_0F385C_X86_64_P_1): Likewise.
950 (VEX_W_0F385E_X86_64_P_0): Likewise.
951 (VEX_W_0F385E_X86_64_P_1): Likewise.
952 (VEX_W_0F385E_X86_64_P_2): Likewise.
953 (VEX_W_0F385E_X86_64_P_3): Likewise.
954 (names_tmm): Likewise.
955 (att_names_tmm): Likewise.
956 (intel_operand_size): Handle void_mode.
957 (OP_XMM): Handle tmm_mode.
960 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
961 CpuAMX_BF16 and CpuAMX_TILE.
962 (operand_type_shorthands): Add RegTMM.
963 (operand_type_init): Likewise.
964 (operand_types): Add Tmmword.
965 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
966 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
967 * i386-opc.h (CpuAMX_INT8): New.
968 (CpuAMX_BF16): Likewise.
969 (CpuAMX_TILE): Likewise.
972 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
973 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
974 (i386_operand_type): Add tmmword.
975 * i386-opc.tbl: Add AMX instructions.
976 * i386-reg.tbl: Add AMX registers.
977 * i386-init.h: Regenerated.
978 * i386-tbl.h: Likewise.
980 2020-07-08 Jan Beulich <jbeulich@suse.com>
982 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
983 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
985 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
986 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
988 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
989 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
990 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
991 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
992 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
993 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
994 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
995 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
996 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
997 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
998 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
999 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1000 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1001 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1002 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1003 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1004 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1005 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1006 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1007 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1008 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1009 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1010 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1011 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1012 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1013 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1014 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1015 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1016 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1017 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1018 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1019 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1020 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1021 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1022 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1023 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1024 (reg_table): Re-order XOP entries. Adjust their operands.
1025 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1026 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1027 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1028 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1029 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1030 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1031 entries by references ...
1032 (vex_len_table): ... to resepctive new entries here. For several
1033 new and existing entries reference ...
1034 (vex_w_table): ... new entries here.
1035 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1037 2020-07-08 Jan Beulich <jbeulich@suse.com>
1039 * i386-dis.c (XMVexScalarI4): Define.
1040 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1041 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1042 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1043 (vex_len_table): Move scalar FMA4 entries ...
1044 (prefix_table): ... here.
1045 (OP_REG_VexI4): Handle scalar_mode.
1046 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1047 * i386-tbl.h: Re-generate.
1049 2020-07-08 Jan Beulich <jbeulich@suse.com>
1051 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1052 Vex_2src_2): Delete.
1053 (OP_VexW, VexW): New.
1054 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1055 for shifts and rotates by register.
1057 2020-07-08 Jan Beulich <jbeulich@suse.com>
1059 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1060 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1061 OP_EX_VexReg): Delete.
1062 (OP_VexI4, VexI4): New.
1063 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1064 (prefix_table): ... here.
1065 (print_insn): Drop setting of vex_w_done.
1067 2020-07-08 Jan Beulich <jbeulich@suse.com>
1069 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1070 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1071 (xop_table): Replace operands of 4-operand insns.
1072 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1074 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1076 * arc-opc.c (insert_rbd): New function.
1079 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1082 2020-07-07 Jan Beulich <jbeulich@suse.com>
1084 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1085 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1086 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1087 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1089 (putop): Handle "BW".
1090 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1091 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1093 * i386-dis-evex-prefix.h: ... here.
1095 2020-07-06 Jan Beulich <jbeulich@suse.com>
1097 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1098 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1099 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1100 VEX_W_0FXOP_09_83): New enumerators.
1101 (xop_table): Reference the above.
1102 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1103 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1104 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1105 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1107 2020-07-06 Jan Beulich <jbeulich@suse.com>
1109 * i386-dis.c (EVEX_W_0F3838_P_1,
1110 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1111 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1112 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1113 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1114 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1115 (putop): Centralize management of last[]. Delete SAVE_LAST.
1116 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1117 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1118 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1119 * i386-dis-evex-prefix.h: here.
1121 2020-07-06 Jan Beulich <jbeulich@suse.com>
1123 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1124 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1125 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1126 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1128 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1129 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1130 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1131 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1132 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1133 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1134 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1135 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1136 these, respectively.
1137 * i386-dis-evex-len.h: Adjust comments.
1138 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1139 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1140 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1141 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1142 MOD_EVEX_0F385B_P_2_W_1 table entries.
1143 * i386-dis-evex-w.h: Reference mod_table[] for
1144 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1147 2020-07-06 Jan Beulich <jbeulich@suse.com>
1149 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1150 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1152 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1153 Likewise. Mark 256-bit entries invalid.
1155 2020-07-06 Jan Beulich <jbeulich@suse.com>
1157 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1158 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1159 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1160 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1161 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1162 PREFIX_EVEX_0F382B): Delete.
1163 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1164 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1165 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1166 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1167 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1169 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1170 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1171 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1172 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1174 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1175 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1176 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1177 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1178 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1179 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1180 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1181 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1182 PREFIX_EVEX_0F382B): Remove table entries.
1183 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1184 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1185 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1187 2020-07-06 Jan Beulich <jbeulich@suse.com>
1189 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1190 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1192 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1193 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1194 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1195 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1198 2020-07-06 Jan Beulich <jbeulich@suse.com>
1200 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1201 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1202 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1203 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1204 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1205 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1206 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1207 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1208 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1211 2020-07-06 Jan Beulich <jbeulich@suse.com>
1213 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1214 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1215 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1217 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1219 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1221 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1223 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1225 2020-07-06 Jan Beulich <jbeulich@suse.com>
1227 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1228 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1229 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1230 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1231 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1232 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1233 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1234 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1235 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1236 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1237 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1238 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1239 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1240 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1241 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1242 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1243 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1244 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1245 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1246 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1247 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1248 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1249 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1250 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1251 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1252 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1253 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1254 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1255 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1256 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1257 (prefix_table): Add EXxEVexR to FMA table entries.
1258 (OP_Rounding): Move abort() invocation.
1259 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1260 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1261 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1262 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1263 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1264 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1265 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1266 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1267 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1268 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1270 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1271 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1272 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1273 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1274 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1275 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1276 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1277 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1278 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1279 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1280 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1281 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1282 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1283 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1284 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1285 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1286 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1287 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1288 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1289 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1290 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1291 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1292 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1293 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1294 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1295 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1296 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1297 Delete table entries.
1298 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1299 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1300 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1303 2020-07-06 Jan Beulich <jbeulich@suse.com>
1305 * i386-dis.c (EXqScalarS): Delete.
1306 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1307 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1309 2020-07-06 Jan Beulich <jbeulich@suse.com>
1311 * i386-dis.c (safe-ctype.h): Include.
1312 (EXdScalar, EXqScalar): Delete.
1313 (d_scalar_mode, q_scalar_mode): Delete.
1314 (prefix_table, vex_len_table): Use EXxmm_md in place of
1315 EXdScalar and EXxmm_mq in place of EXqScalar.
1316 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1317 d_scalar_mode and q_scalar_mode.
1318 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1319 (vmovsd): Use EXxmm_mq.
1321 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1324 * arc-dis.c: Fix spelling mistake.
1325 * po/opcodes.pot: Regenerate.
1327 2020-07-06 Nick Clifton <nickc@redhat.com>
1329 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1330 * po/uk.po: Updated Ukranian translation.
1332 2020-07-04 Nick Clifton <nickc@redhat.com>
1334 * configure: Regenerate.
1335 * po/opcodes.pot: Regenerate.
1337 2020-07-04 Nick Clifton <nickc@redhat.com>
1339 Binutils 2.35 branch created.
1341 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1343 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1344 * i386-opc.h (VexSwapSources): New.
1345 (i386_opcode_modifier): Add vexswapsources.
1346 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1347 with two source operands swapped.
1348 * i386-tbl.h: Regenerated.
1350 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1352 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1353 unprivileged CSR can also be initialized.
1355 2020-06-29 Alan Modra <amodra@gmail.com>
1357 * arm-dis.c: Use C style comments.
1358 * cr16-opc.c: Likewise.
1359 * ft32-dis.c: Likewise.
1360 * moxie-opc.c: Likewise.
1361 * tic54x-dis.c: Likewise.
1362 * s12z-opc.c: Remove useless comment.
1363 * xgate-dis.c: Likewise.
1365 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1367 * i386-opc.tbl: Add a blank line.
1369 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1371 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1372 (VecSIB128): Renamed to ...
1374 (VecSIB256): Renamed to ...
1376 (VecSIB512): Renamed to ...
1378 (VecSIB): Renamed to ...
1380 (i386_opcode_modifier): Replace vecsib with sib.
1381 * i386-opc.tbl (VecSIB128): New.
1382 (VecSIB256): Likewise.
1383 (VecSIB512): Likewise.
1384 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1385 and VecSIB512, respectively.
1387 2020-06-26 Jan Beulich <jbeulich@suse.com>
1389 * i386-dis.c: Adjust description of I macro.
1390 (x86_64_table): Drop use of I.
1391 (float_mem): Replace use of I.
1392 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1394 2020-06-26 Jan Beulich <jbeulich@suse.com>
1396 * i386-dis.c: (print_insn): Avoid straight assignment to
1397 priv.orig_sizeflag when processing -M sub-options.
1399 2020-06-25 Jan Beulich <jbeulich@suse.com>
1401 * i386-dis.c: Adjust description of J macro.
1402 (dis386, x86_64_table, mod_table): Replace J.
1403 (putop): Remove handling of J.
1405 2020-06-25 Jan Beulich <jbeulich@suse.com>
1407 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1409 2020-06-25 Jan Beulich <jbeulich@suse.com>
1411 * i386-dis.c: Adjust description of "LQ" macro.
1412 (dis386_twobyte): Use LQ for sysret.
1413 (putop): Adjust handling of LQ.
1415 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1417 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1418 * riscv-dis.c: Include elfxx-riscv.h.
1420 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1422 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1424 2020-06-17 Lili Cui <lili.cui@intel.com>
1426 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1428 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1431 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1432 * i386-opc.tbl: Likewise.
1433 * i386-tbl.h: Regenerated.
1435 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1437 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1439 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1441 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1442 (SR_CORE): Likewise.
1443 (SR_FEAT): Likewise.
1445 (SR_V8_1): Likewise.
1446 (SR_V8_2): Likewise.
1447 (SR_V8_3): Likewise.
1448 (SR_V8_4): Likewise.
1451 (SR_SSBS): Likewise.
1453 (SR_ID_PFR2): Likewise.
1454 (SR_PROFILE): Likewise.
1455 (SR_MEMTAG): Likewise.
1456 (SR_SCXTNUM): Likewise.
1457 (aarch64_sys_regs): Refactor to store feature information in the table.
1458 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1459 that now describe their own features.
1460 (aarch64_pstatefield_supported_p): Likewise.
1462 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1464 * i386-dis.c (prefix_table): Fix a typo in comments.
1466 2020-06-09 Jan Beulich <jbeulich@suse.com>
1468 * i386-dis.c (rex_ignored): Delete.
1469 (ckprefix): Drop rex_ignored initialization.
1470 (get_valid_dis386): Drop setting of rex_ignored.
1471 (print_insn): Drop checking of rex_ignored. Don't record data
1472 size prefix as used with VEX-and-alike encodings.
1474 2020-06-09 Jan Beulich <jbeulich@suse.com>
1476 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1477 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1478 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1479 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1480 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1481 VEX_0F12, and VEX_0F16.
1482 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1483 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1484 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1485 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1486 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1487 MOD_VEX_0F16_PREFIX_2 entries.
1489 2020-06-09 Jan Beulich <jbeulich@suse.com>
1491 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1492 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1493 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1494 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1495 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1496 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1497 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1498 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1499 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1500 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1501 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1502 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1503 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1504 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1505 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1506 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1507 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1508 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1509 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1510 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1511 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1512 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1513 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1514 EVEX_W_0FC6_P_2): Delete.
1515 (print_insn): Add EVEX.W vs embedded prefix consistency check
1516 to prefix validation.
1517 * i386-dis-evex.h (evex_table): Don't further descend for
1518 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1519 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1521 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1522 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1523 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1524 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1525 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1526 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1527 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1528 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1529 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1530 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1531 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1532 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1533 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1534 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1535 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1536 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1537 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1538 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1539 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1540 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1541 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1542 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1543 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1544 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1545 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1546 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1547 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1549 2020-06-09 Jan Beulich <jbeulich@suse.com>
1551 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1552 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1553 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1555 (print_insn): Drop pointless check against bad_opcode. Split
1556 prefix validation into legacy and VEX-and-alike parts.
1557 (putop): Re-work 'X' macro handling.
1559 2020-06-09 Jan Beulich <jbeulich@suse.com>
1561 * i386-dis.c (MOD_0F51): Rename to ...
1562 (MOD_0F50): ... this.
1564 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1566 * arm-dis.c (arm_opcodes): Add dfb.
1567 (thumb32_opcodes): Add dfb.
1569 2020-06-08 Jan Beulich <jbeulich@suse.com>
1571 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1573 2020-06-06 Alan Modra <amodra@gmail.com>
1575 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1577 2020-06-05 Alan Modra <amodra@gmail.com>
1579 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1580 size is large enough.
1582 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1584 * disassemble.c (disassemble_init_for_target): Set endian_code for
1586 * bpf-desc.c: Regenerate.
1587 * bpf-opc.c: Likewise.
1588 * bpf-dis.c: Likewise.
1590 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1592 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1593 (cgen_put_insn_value): Likewise.
1594 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1595 * cgen-dis.in (print_insn): Likewise.
1596 * cgen-ibld.in (insert_1): Likewise.
1597 (insert_1): Likewise.
1598 (insert_insn_normal): Likewise.
1599 (extract_1): Likewise.
1600 * bpf-dis.c: Regenerate.
1601 * bpf-ibld.c: Likewise.
1602 * bpf-ibld.c: Likewise.
1603 * cgen-dis.in: Likewise.
1604 * cgen-ibld.in: Likewise.
1605 * cgen-opc.c: Likewise.
1606 * epiphany-dis.c: Likewise.
1607 * epiphany-ibld.c: Likewise.
1608 * fr30-dis.c: Likewise.
1609 * fr30-ibld.c: Likewise.
1610 * frv-dis.c: Likewise.
1611 * frv-ibld.c: Likewise.
1612 * ip2k-dis.c: Likewise.
1613 * ip2k-ibld.c: Likewise.
1614 * iq2000-dis.c: Likewise.
1615 * iq2000-ibld.c: Likewise.
1616 * lm32-dis.c: Likewise.
1617 * lm32-ibld.c: Likewise.
1618 * m32c-dis.c: Likewise.
1619 * m32c-ibld.c: Likewise.
1620 * m32r-dis.c: Likewise.
1621 * m32r-ibld.c: Likewise.
1622 * mep-dis.c: Likewise.
1623 * mep-ibld.c: Likewise.
1624 * mt-dis.c: Likewise.
1625 * mt-ibld.c: Likewise.
1626 * or1k-dis.c: Likewise.
1627 * or1k-ibld.c: Likewise.
1628 * xc16x-dis.c: Likewise.
1629 * xc16x-ibld.c: Likewise.
1630 * xstormy16-dis.c: Likewise.
1631 * xstormy16-ibld.c: Likewise.
1633 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1635 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1636 (print_insn_): Handle instruction endian.
1637 * bpf-dis.c: Regenerate.
1638 * bpf-desc.c: Regenerate.
1639 * epiphany-dis.c: Likewise.
1640 * epiphany-desc.c: Likewise.
1641 * fr30-dis.c: Likewise.
1642 * fr30-desc.c: Likewise.
1643 * frv-dis.c: Likewise.
1644 * frv-desc.c: Likewise.
1645 * ip2k-dis.c: Likewise.
1646 * ip2k-desc.c: Likewise.
1647 * iq2000-dis.c: Likewise.
1648 * iq2000-desc.c: Likewise.
1649 * lm32-dis.c: Likewise.
1650 * lm32-desc.c: Likewise.
1651 * m32c-dis.c: Likewise.
1652 * m32c-desc.c: Likewise.
1653 * m32r-dis.c: Likewise.
1654 * m32r-desc.c: Likewise.
1655 * mep-dis.c: Likewise.
1656 * mep-desc.c: Likewise.
1657 * mt-dis.c: Likewise.
1658 * mt-desc.c: Likewise.
1659 * or1k-dis.c: Likewise.
1660 * or1k-desc.c: Likewise.
1661 * xc16x-dis.c: Likewise.
1662 * xc16x-desc.c: Likewise.
1663 * xstormy16-dis.c: Likewise.
1664 * xstormy16-desc.c: Likewise.
1666 2020-06-03 Nick Clifton <nickc@redhat.com>
1668 * po/sr.po: Updated Serbian translation.
1670 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1672 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1673 (riscv_get_priv_spec_class): Likewise.
1675 2020-06-01 Alan Modra <amodra@gmail.com>
1677 * bpf-desc.c: Regenerate.
1679 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1680 David Faust <david.faust@oracle.com>
1682 * bpf-desc.c: Regenerate.
1683 * bpf-opc.h: Likewise.
1684 * bpf-opc.c: Likewise.
1685 * bpf-dis.c: Likewise.
1687 2020-05-28 Alan Modra <amodra@gmail.com>
1689 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1692 2020-05-28 Alan Modra <amodra@gmail.com>
1694 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1696 (print_insn_ns32k): Revert last change.
1698 2020-05-28 Nick Clifton <nickc@redhat.com>
1700 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1703 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1705 Fix extraction of signed constants in nios2 disassembler (again).
1707 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1708 extractions of signed fields.
1710 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1712 * s390-opc.txt: Relocate vector load/store instructions with
1713 additional alignment parameter and change architecture level
1714 constraint from z14 to z13.
1716 2020-05-21 Alan Modra <amodra@gmail.com>
1718 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1719 * sparc-dis.c: Likewise.
1720 * tic4x-dis.c: Likewise.
1721 * xtensa-dis.c: Likewise.
1722 * bpf-desc.c: Regenerate.
1723 * epiphany-desc.c: Regenerate.
1724 * fr30-desc.c: Regenerate.
1725 * frv-desc.c: Regenerate.
1726 * ip2k-desc.c: Regenerate.
1727 * iq2000-desc.c: Regenerate.
1728 * lm32-desc.c: Regenerate.
1729 * m32c-desc.c: Regenerate.
1730 * m32r-desc.c: Regenerate.
1731 * mep-asm.c: Regenerate.
1732 * mep-desc.c: Regenerate.
1733 * mt-desc.c: Regenerate.
1734 * or1k-desc.c: Regenerate.
1735 * xc16x-desc.c: Regenerate.
1736 * xstormy16-desc.c: Regenerate.
1738 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1740 * riscv-opc.c (riscv_ext_version_table): The table used to store
1741 all information about the supported spec and the corresponding ISA
1742 versions. Currently, only Zicsr is supported to verify the
1743 correctness of Z sub extension settings. Others will be supported
1744 in the future patches.
1745 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1746 classes and the corresponding strings.
1747 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1748 spec class by giving a ISA spec string.
1749 * riscv-opc.c (struct priv_spec_t): New structure.
1750 (struct priv_spec_t priv_specs): List for all supported privilege spec
1751 classes and the corresponding strings.
1752 (riscv_get_priv_spec_class): New function. Get the corresponding
1753 privilege spec class by giving a spec string.
1754 (riscv_get_priv_spec_name): New function. Get the corresponding
1755 privilege spec string by giving a CSR version class.
1756 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1757 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1758 according to the chosen version. Build a hash table riscv_csr_hash to
1759 store the valid CSR for the chosen pirv verison. Dump the direct
1760 CSR address rather than it's name if it is invalid.
1761 (parse_riscv_dis_option_without_args): New function. Parse the options
1763 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1764 parse the options without arguments first, and then handle the options
1765 with arguments. Add the new option -Mpriv-spec, which has argument.
1766 * riscv-dis.c (print_riscv_disassembler_options): Add description
1767 about the new OBJDUMP option.
1769 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1771 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1772 WC values on POWER10 sync, dcbf and wait instructions.
1773 (insert_pl, extract_pl): New functions.
1774 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1775 (LS3): New , 3-bit L for sync.
1776 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1777 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1778 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1779 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1780 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1781 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1782 <wait>: Enable PL operand on POWER10.
1783 <dcbf>: Enable L3OPT operand on POWER10.
1784 <sync>: Enable SC2 operand on POWER10.
1786 2020-05-19 Stafford Horne <shorne@gmail.com>
1789 * or1k-asm.c: Regenerate.
1790 * or1k-desc.c: Regenerate.
1791 * or1k-desc.h: Regenerate.
1792 * or1k-dis.c: Regenerate.
1793 * or1k-ibld.c: Regenerate.
1794 * or1k-opc.c: Regenerate.
1795 * or1k-opc.h: Regenerate.
1796 * or1k-opinst.c: Regenerate.
1798 2020-05-11 Alan Modra <amodra@gmail.com>
1800 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1803 2020-05-11 Alan Modra <amodra@gmail.com>
1805 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1806 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1808 2020-05-11 Alan Modra <amodra@gmail.com>
1810 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1812 2020-05-11 Alan Modra <amodra@gmail.com>
1814 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1815 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1817 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1819 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1822 2020-05-11 Alan Modra <amodra@gmail.com>
1824 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1825 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1826 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1827 (prefix_opcodes): Add xxeval.
1829 2020-05-11 Alan Modra <amodra@gmail.com>
1831 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1832 xxgenpcvwm, xxgenpcvdm.
1834 2020-05-11 Alan Modra <amodra@gmail.com>
1836 * ppc-opc.c (MP, VXVAM_MASK): Define.
1837 (VXVAPS_MASK): Use VXVA_MASK.
1838 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1839 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1840 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1841 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1843 2020-05-11 Alan Modra <amodra@gmail.com>
1844 Peter Bergner <bergner@linux.ibm.com>
1846 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1848 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1849 YMSK2, XA6a, XA6ap, XB6a entries.
1850 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1851 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1853 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1854 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1855 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1856 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1857 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1858 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1859 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1860 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1861 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1862 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1863 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1864 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1865 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1866 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1868 2020-05-11 Alan Modra <amodra@gmail.com>
1870 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1871 (insert_xts, extract_xts): New functions.
1872 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1873 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1874 (VXRC_MASK, VXSH_MASK): Define.
1875 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1876 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1877 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1878 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1879 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1880 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1881 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1883 2020-05-11 Alan Modra <amodra@gmail.com>
1885 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1886 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1887 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1888 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1889 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1891 2020-05-11 Alan Modra <amodra@gmail.com>
1893 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1894 (XTP, DQXP, DQXP_MASK): Define.
1895 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1896 (prefix_opcodes): Add plxvp and pstxvp.
1898 2020-05-11 Alan Modra <amodra@gmail.com>
1900 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1901 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1902 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1904 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1906 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1908 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1910 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1912 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1914 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1916 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1918 2020-05-11 Alan Modra <amodra@gmail.com>
1920 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1922 2020-05-11 Alan Modra <amodra@gmail.com>
1924 * ppc-dis.c (ppc_opts): Add "power10" entry.
1925 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1926 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1928 2020-05-11 Nick Clifton <nickc@redhat.com>
1930 * po/fr.po: Updated French translation.
1932 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1934 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1935 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1936 (operand_general_constraint_met_p): validate
1937 AARCH64_OPND_UNDEFINED.
1938 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1940 * aarch64-asm-2.c: Regenerated.
1941 * aarch64-dis-2.c: Regenerated.
1942 * aarch64-opc-2.c: Regenerated.
1944 2020-04-29 Nick Clifton <nickc@redhat.com>
1947 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1950 2020-04-29 Nick Clifton <nickc@redhat.com>
1952 * po/sv.po: Updated Swedish translation.
1954 2020-04-29 Nick Clifton <nickc@redhat.com>
1957 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1958 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1959 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1962 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1965 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1966 cmpi only on m68020up and cpu32.
1968 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1970 * aarch64-asm.c (aarch64_ins_none): New.
1971 * aarch64-asm.h (ins_none): New declaration.
1972 * aarch64-dis.c (aarch64_ext_none): New.
1973 * aarch64-dis.h (ext_none): New declaration.
1974 * aarch64-opc.c (aarch64_print_operand): Update case for
1975 AARCH64_OPND_BARRIER_PSB.
1976 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1977 (AARCH64_OPERANDS): Update inserter/extracter for
1978 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1979 * aarch64-asm-2.c: Regenerated.
1980 * aarch64-dis-2.c: Regenerated.
1981 * aarch64-opc-2.c: Regenerated.
1983 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1985 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1986 (aarch64_feature_ras, RAS): Likewise.
1987 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1988 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1989 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1990 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1991 * aarch64-asm-2.c: Regenerated.
1992 * aarch64-dis-2.c: Regenerated.
1993 * aarch64-opc-2.c: Regenerated.
1995 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1997 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1998 (print_insn_neon): Support disassembly of conditional
2001 2020-02-16 David Faust <david.faust@oracle.com>
2003 * bpf-desc.c: Regenerate.
2004 * bpf-desc.h: Likewise.
2005 * bpf-opc.c: Regenerate.
2006 * bpf-opc.h: Likewise.
2008 2020-04-07 Lili Cui <lili.cui@intel.com>
2010 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2011 (prefix_table): New instructions (see prefixes above).
2012 (rm_table): Likewise
2013 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2014 CPU_ANY_TSXLDTRK_FLAGS.
2015 (cpu_flags): Add CpuTSXLDTRK.
2016 * i386-opc.h (enum): Add CpuTSXLDTRK.
2017 (i386_cpu_flags): Add cputsxldtrk.
2018 * i386-opc.tbl: Add XSUSPLDTRK insns.
2019 * i386-init.h: Regenerate.
2020 * i386-tbl.h: Likewise.
2022 2020-04-02 Lili Cui <lili.cui@intel.com>
2024 * i386-dis.c (prefix_table): New instructions serialize.
2025 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2026 CPU_ANY_SERIALIZE_FLAGS.
2027 (cpu_flags): Add CpuSERIALIZE.
2028 * i386-opc.h (enum): Add CpuSERIALIZE.
2029 (i386_cpu_flags): Add cpuserialize.
2030 * i386-opc.tbl: Add SERIALIZE insns.
2031 * i386-init.h: Regenerate.
2032 * i386-tbl.h: Likewise.
2034 2020-03-26 Alan Modra <amodra@gmail.com>
2036 * disassemble.h (opcodes_assert): Declare.
2037 (OPCODES_ASSERT): Define.
2038 * disassemble.c: Don't include assert.h. Include opintl.h.
2039 (opcodes_assert): New function.
2040 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2041 (bfd_h8_disassemble): Reduce size of data array. Correctly
2042 calculate maxlen. Omit insn decoding when insn length exceeds
2043 maxlen. Exit from nibble loop when looking for E, before
2044 accessing next data byte. Move processing of E outside loop.
2045 Replace tests of maxlen in loop with assertions.
2047 2020-03-26 Alan Modra <amodra@gmail.com>
2049 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2051 2020-03-25 Alan Modra <amodra@gmail.com>
2053 * z80-dis.c (suffix): Init mybuf.
2055 2020-03-22 Alan Modra <amodra@gmail.com>
2057 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2058 successflly read from section.
2060 2020-03-22 Alan Modra <amodra@gmail.com>
2062 * arc-dis.c (find_format): Use ISO C string concatenation rather
2063 than line continuation within a string. Don't access needs_limm
2064 before testing opcode != NULL.
2066 2020-03-22 Alan Modra <amodra@gmail.com>
2068 * ns32k-dis.c (print_insn_arg): Update comment.
2069 (print_insn_ns32k): Reduce size of index_offset array, and
2070 initialize, passing -1 to print_insn_arg for args that are not
2071 an index. Don't exit arg loop early. Abort on bad arg number.
2073 2020-03-22 Alan Modra <amodra@gmail.com>
2075 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2076 * s12z-opc.c: Formatting.
2077 (operands_f): Return an int.
2078 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2079 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2080 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2081 (exg_sex_discrim): Likewise.
2082 (create_immediate_operand, create_bitfield_operand),
2083 (create_register_operand_with_size, create_register_all_operand),
2084 (create_register_all16_operand, create_simple_memory_operand),
2085 (create_memory_operand, create_memory_auto_operand): Don't
2086 segfault on malloc failure.
2087 (z_ext24_decode): Return an int status, negative on fail, zero
2089 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2090 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2091 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2092 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2093 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2094 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2095 (loop_primitive_decode, shift_decode, psh_pul_decode),
2096 (bit_field_decode): Similarly.
2097 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2098 to return value, update callers.
2099 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2100 Don't segfault on NULL operand.
2101 (decode_operation): Return OP_INVALID on first fail.
2102 (decode_s12z): Check all reads, returning -1 on fail.
2104 2020-03-20 Alan Modra <amodra@gmail.com>
2106 * metag-dis.c (print_insn_metag): Don't ignore status from
2109 2020-03-20 Alan Modra <amodra@gmail.com>
2111 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2112 Initialize parts of buffer not written when handling a possible
2113 2-byte insn at end of section. Don't attempt decoding of such
2114 an insn by the 4-byte machinery.
2116 2020-03-20 Alan Modra <amodra@gmail.com>
2118 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2119 partially filled buffer. Prevent lookup of 4-byte insns when
2120 only VLE 2-byte insns are possible due to section size. Print
2121 ".word" rather than ".long" for 2-byte leftovers.
2123 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2126 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2128 2020-03-13 Jan Beulich <jbeulich@suse.com>
2130 * i386-dis.c (X86_64_0D): Rename to ...
2131 (X86_64_0E): ... this.
2133 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2135 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2136 * Makefile.in: Regenerated.
2138 2020-03-09 Jan Beulich <jbeulich@suse.com>
2140 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2142 * i386-tbl.h: Re-generate.
2144 2020-03-09 Jan Beulich <jbeulich@suse.com>
2146 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2147 vprot*, vpsha*, and vpshl*.
2148 * i386-tbl.h: Re-generate.
2150 2020-03-09 Jan Beulich <jbeulich@suse.com>
2152 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2153 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2154 * i386-tbl.h: Re-generate.
2156 2020-03-09 Jan Beulich <jbeulich@suse.com>
2158 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2159 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2160 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2161 * i386-tbl.h: Re-generate.
2163 2020-03-09 Jan Beulich <jbeulich@suse.com>
2165 * i386-gen.c (struct template_arg, struct template_instance,
2166 struct template_param, struct template, templates,
2167 parse_template, expand_templates): New.
2168 (process_i386_opcodes): Various local variables moved to
2169 expand_templates. Call parse_template and expand_templates.
2170 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2171 * i386-tbl.h: Re-generate.
2173 2020-03-06 Jan Beulich <jbeulich@suse.com>
2175 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2176 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2177 register and memory source templates. Replace VexW= by VexW*
2179 * i386-tbl.h: Re-generate.
2181 2020-03-06 Jan Beulich <jbeulich@suse.com>
2183 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2184 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2185 * i386-tbl.h: Re-generate.
2187 2020-03-06 Jan Beulich <jbeulich@suse.com>
2189 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2190 * i386-tbl.h: Re-generate.
2192 2020-03-06 Jan Beulich <jbeulich@suse.com>
2194 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2195 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2196 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2197 VexW0 on SSE2AVX variants.
2198 (vmovq): Drop NoRex64 from XMM/XMM variants.
2199 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2200 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2201 applicable use VexW0.
2202 * i386-tbl.h: Re-generate.
2204 2020-03-06 Jan Beulich <jbeulich@suse.com>
2206 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2207 * i386-opc.h (Rex64): Delete.
2208 (struct i386_opcode_modifier): Remove rex64 field.
2209 * i386-opc.tbl (crc32): Drop Rex64.
2210 Replace Rex64 with Size64 everywhere else.
2211 * i386-tbl.h: Re-generate.
2213 2020-03-06 Jan Beulich <jbeulich@suse.com>
2215 * i386-dis.c (OP_E_memory): Exclude recording of used address
2216 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2217 addressed memory operands for MPX insns.
2219 2020-03-06 Jan Beulich <jbeulich@suse.com>
2221 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2222 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2223 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2224 (ptwrite): Split into non-64-bit and 64-bit forms.
2225 * i386-tbl.h: Re-generate.
2227 2020-03-06 Jan Beulich <jbeulich@suse.com>
2229 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2231 * i386-tbl.h: Re-generate.
2233 2020-03-04 Jan Beulich <jbeulich@suse.com>
2235 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2236 (prefix_table): Move vmmcall here. Add vmgexit.
2237 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2238 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2239 (cpu_flags): Add CpuSEV_ES entry.
2240 * i386-opc.h (CpuSEV_ES): New.
2241 (union i386_cpu_flags): Add cpusev_es field.
2242 * i386-opc.tbl (vmgexit): New.
2243 * i386-init.h, i386-tbl.h: Re-generate.
2245 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2247 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2249 * i386-opc.h (IGNORESIZE): New.
2250 (DEFAULTSIZE): Likewise.
2251 (IgnoreSize): Removed.
2252 (DefaultSize): Likewise.
2253 (MnemonicSize): New.
2254 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2256 * i386-opc.tbl (IgnoreSize): New.
2257 (DefaultSize): Likewise.
2258 * i386-tbl.h: Regenerated.
2260 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2263 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2266 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2269 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2270 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2271 * i386-tbl.h: Regenerated.
2273 2020-02-26 Alan Modra <amodra@gmail.com>
2275 * aarch64-asm.c: Indent labels correctly.
2276 * aarch64-dis.c: Likewise.
2277 * aarch64-gen.c: Likewise.
2278 * aarch64-opc.c: Likewise.
2279 * alpha-dis.c: Likewise.
2280 * i386-dis.c: Likewise.
2281 * nds32-asm.c: Likewise.
2282 * nfp-dis.c: Likewise.
2283 * visium-dis.c: Likewise.
2285 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2287 * arc-regs.h (int_vector_base): Make it available for all ARC
2290 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2292 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2295 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2297 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2298 c.mv/c.li if rs1 is zero.
2300 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2302 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2303 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2305 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2306 * i386-opc.h (CpuABM): Removed.
2308 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2309 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2310 popcnt. Remove CpuABM from lzcnt.
2311 * i386-init.h: Regenerated.
2312 * i386-tbl.h: Likewise.
2314 2020-02-17 Jan Beulich <jbeulich@suse.com>
2316 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2317 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2318 VexW1 instead of open-coding them.
2319 * i386-tbl.h: Re-generate.
2321 2020-02-17 Jan Beulich <jbeulich@suse.com>
2323 * i386-opc.tbl (AddrPrefixOpReg): Define.
2324 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2325 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2326 templates. Drop NoRex64.
2327 * i386-tbl.h: Re-generate.
2329 2020-02-17 Jan Beulich <jbeulich@suse.com>
2332 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2333 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2334 into Intel syntax instance (with Unpsecified) and AT&T one
2336 (vcvtneps2bf16): Likewise, along with folding the two so far
2338 * i386-tbl.h: Re-generate.
2340 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2342 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2343 CPU_ANY_SSE4A_FLAGS.
2345 2020-02-17 Alan Modra <amodra@gmail.com>
2347 * i386-gen.c (cpu_flag_init): Correct last change.
2349 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2351 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2354 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2356 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2359 2020-02-14 Jan Beulich <jbeulich@suse.com>
2362 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2363 destination for Cpu64-only variant.
2364 (movzx): Fold patterns.
2365 * i386-tbl.h: Re-generate.
2367 2020-02-13 Jan Beulich <jbeulich@suse.com>
2369 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2370 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2371 CPU_ANY_SSE4_FLAGS entry.
2372 * i386-init.h: Re-generate.
2374 2020-02-12 Jan Beulich <jbeulich@suse.com>
2376 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2377 with Unspecified, making the present one AT&T syntax only.
2378 * i386-tbl.h: Re-generate.
2380 2020-02-12 Jan Beulich <jbeulich@suse.com>
2382 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2383 * i386-tbl.h: Re-generate.
2385 2020-02-12 Jan Beulich <jbeulich@suse.com>
2388 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2389 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2390 Amd64 and Intel64 templates.
2391 (call, jmp): Likewise for far indirect variants. Dro
2393 * i386-tbl.h: Re-generate.
2395 2020-02-11 Jan Beulich <jbeulich@suse.com>
2397 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2398 * i386-opc.h (ShortForm): Delete.
2399 (struct i386_opcode_modifier): Remove shortform field.
2400 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2401 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2402 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2403 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2405 * i386-tbl.h: Re-generate.
2407 2020-02-11 Jan Beulich <jbeulich@suse.com>
2409 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2410 fucompi): Drop ShortForm from operand-less templates.
2411 * i386-tbl.h: Re-generate.
2413 2020-02-11 Alan Modra <amodra@gmail.com>
2415 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2416 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2417 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2418 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2419 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2421 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2423 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2424 (cde_opcodes): Add VCX* instructions.
2426 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2427 Matthew Malcomson <matthew.malcomson@arm.com>
2429 * arm-dis.c (struct cdeopcode32): New.
2430 (CDE_OPCODE): New macro.
2431 (cde_opcodes): New disassembly table.
2432 (regnames): New option to table.
2433 (cde_coprocs): New global variable.
2434 (print_insn_cde): New
2435 (print_insn_thumb32): Use print_insn_cde.
2436 (parse_arm_disassembler_options): Parse coprocN args.
2438 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2441 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2443 * i386-opc.h (AMD64): Removed.
2444 (Intel64): Likewose.
2446 (INTEL64): Likewise.
2447 (INTEL64ONLY): Likewise.
2448 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2449 * i386-opc.tbl (Amd64): New.
2450 (Intel64): Likewise.
2451 (Intel64Only): Likewise.
2452 Replace AMD64 with Amd64. Update sysenter/sysenter with
2453 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2454 * i386-tbl.h: Regenerated.
2456 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2459 * z80-dis.c: Add support for GBZ80 opcodes.
2461 2020-02-04 Alan Modra <amodra@gmail.com>
2463 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2465 2020-02-03 Alan Modra <amodra@gmail.com>
2467 * m32c-ibld.c: Regenerate.
2469 2020-02-01 Alan Modra <amodra@gmail.com>
2471 * frv-ibld.c: Regenerate.
2473 2020-01-31 Jan Beulich <jbeulich@suse.com>
2475 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2476 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2477 (OP_E_memory): Replace xmm_mdq_mode case label by
2478 vex_scalar_w_dq_mode one.
2479 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2481 2020-01-31 Jan Beulich <jbeulich@suse.com>
2483 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2484 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2485 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2486 (intel_operand_size): Drop vex_w_dq_mode case label.
2488 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2490 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2491 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2493 2020-01-30 Alan Modra <amodra@gmail.com>
2495 * m32c-ibld.c: Regenerate.
2497 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2499 * bpf-opc.c: Regenerate.
2501 2020-01-30 Jan Beulich <jbeulich@suse.com>
2503 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2504 (dis386): Use them to replace C2/C3 table entries.
2505 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2506 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2507 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2508 * i386-tbl.h: Re-generate.
2510 2020-01-30 Jan Beulich <jbeulich@suse.com>
2512 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2514 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2516 * i386-tbl.h: Re-generate.
2518 2020-01-30 Alan Modra <amodra@gmail.com>
2520 * tic4x-dis.c (tic4x_dp): Make unsigned.
2522 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2523 Jan Beulich <jbeulich@suse.com>
2526 * i386-dis.c (MOVSXD_Fixup): New function.
2527 (movsxd_mode): New enum.
2528 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2529 (intel_operand_size): Handle movsxd_mode.
2530 (OP_E_register): Likewise.
2532 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2533 register on movsxd. Add movsxd with 16-bit destination register
2534 for AMD64 and Intel64 ISAs.
2535 * i386-tbl.h: Regenerated.
2537 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2540 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2541 * aarch64-asm-2.c: Regenerate
2542 * aarch64-dis-2.c: Likewise.
2543 * aarch64-opc-2.c: Likewise.
2545 2020-01-21 Jan Beulich <jbeulich@suse.com>
2547 * i386-opc.tbl (sysret): Drop DefaultSize.
2548 * i386-tbl.h: Re-generate.
2550 2020-01-21 Jan Beulich <jbeulich@suse.com>
2552 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2554 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2555 * i386-tbl.h: Re-generate.
2557 2020-01-20 Nick Clifton <nickc@redhat.com>
2559 * po/de.po: Updated German translation.
2560 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2561 * po/uk.po: Updated Ukranian translation.
2563 2020-01-20 Alan Modra <amodra@gmail.com>
2565 * hppa-dis.c (fput_const): Remove useless cast.
2567 2020-01-20 Alan Modra <amodra@gmail.com>
2569 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2571 2020-01-18 Nick Clifton <nickc@redhat.com>
2573 * configure: Regenerate.
2574 * po/opcodes.pot: Regenerate.
2576 2020-01-18 Nick Clifton <nickc@redhat.com>
2578 Binutils 2.34 branch created.
2580 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2582 * opintl.h: Fix spelling error (seperate).
2584 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2586 * i386-opc.tbl: Add {vex} pseudo prefix.
2587 * i386-tbl.h: Regenerated.
2589 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2592 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2593 (neon_opcodes): Likewise.
2594 (select_arm_features): Make sure we enable MVE bits when selecting
2595 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2598 2020-01-16 Jan Beulich <jbeulich@suse.com>
2600 * i386-opc.tbl: Drop stale comment from XOP section.
2602 2020-01-16 Jan Beulich <jbeulich@suse.com>
2604 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2605 (extractps): Add VexWIG to SSE2AVX forms.
2606 * i386-tbl.h: Re-generate.
2608 2020-01-16 Jan Beulich <jbeulich@suse.com>
2610 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2611 Size64 from and use VexW1 on SSE2AVX forms.
2612 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2613 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2614 * i386-tbl.h: Re-generate.
2616 2020-01-15 Alan Modra <amodra@gmail.com>
2618 * tic4x-dis.c (tic4x_version): Make unsigned long.
2619 (optab, optab_special, registernames): New file scope vars.
2620 (tic4x_print_register): Set up registernames rather than
2621 malloc'd registertable.
2622 (tic4x_disassemble): Delete optable and optable_special. Use
2623 optab and optab_special instead. Throw away old optab,
2624 optab_special and registernames when info->mach changes.
2626 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2629 * z80-dis.c (suffix): Use .db instruction to generate double
2632 2020-01-14 Alan Modra <amodra@gmail.com>
2634 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2635 values to unsigned before shifting.
2637 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2639 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2641 (print_insn_thumb16, print_insn_thumb32): Likewise.
2642 (print_insn): Initialize the insn info.
2643 * i386-dis.c (print_insn): Initialize the insn info fields, and
2646 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2648 * arc-opc.c (C_NE): Make it required.
2650 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2652 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2653 reserved register name.
2655 2020-01-13 Alan Modra <amodra@gmail.com>
2657 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2658 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2660 2020-01-13 Alan Modra <amodra@gmail.com>
2662 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2663 result of wasm_read_leb128 in a uint64_t and check that bits
2664 are not lost when copying to other locals. Use uint32_t for
2665 most locals. Use PRId64 when printing int64_t.
2667 2020-01-13 Alan Modra <amodra@gmail.com>
2669 * score-dis.c: Formatting.
2670 * score7-dis.c: Formatting.
2672 2020-01-13 Alan Modra <amodra@gmail.com>
2674 * score-dis.c (print_insn_score48): Use unsigned variables for
2675 unsigned values. Don't left shift negative values.
2676 (print_insn_score32): Likewise.
2677 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2679 2020-01-13 Alan Modra <amodra@gmail.com>
2681 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2683 2020-01-13 Alan Modra <amodra@gmail.com>
2685 * fr30-ibld.c: Regenerate.
2687 2020-01-13 Alan Modra <amodra@gmail.com>
2689 * xgate-dis.c (print_insn): Don't left shift signed value.
2690 (ripBits): Formatting, use 1u.
2692 2020-01-10 Alan Modra <amodra@gmail.com>
2694 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2695 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2697 2020-01-10 Alan Modra <amodra@gmail.com>
2699 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2700 and XRREG value earlier to avoid a shift with negative exponent.
2701 * m10200-dis.c (disassemble): Similarly.
2703 2020-01-09 Nick Clifton <nickc@redhat.com>
2706 * z80-dis.c (ld_ii_ii): Use correct cast.
2708 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2711 * z80-dis.c (ld_ii_ii): Use character constant when checking
2714 2020-01-09 Jan Beulich <jbeulich@suse.com>
2716 * i386-dis.c (SEP_Fixup): New.
2718 (dis386_twobyte): Use it for sysenter/sysexit.
2719 (enum x86_64_isa): Change amd64 enumerator to value 1.
2720 (OP_J): Compare isa64 against intel64 instead of amd64.
2721 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2723 * i386-tbl.h: Re-generate.
2725 2020-01-08 Alan Modra <amodra@gmail.com>
2727 * z8k-dis.c: Include libiberty.h
2728 (instr_data_s): Make max_fetched unsigned.
2729 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2730 Don't exceed byte_info bounds.
2731 (output_instr): Make num_bytes unsigned.
2732 (unpack_instr): Likewise for nibl_count and loop.
2733 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2735 * z8k-opc.h: Regenerate.
2737 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2739 * arc-tbl.h (llock): Use 'LLOCK' as class.
2741 (scond): Use 'SCOND' as class.
2743 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2746 2020-01-06 Alan Modra <amodra@gmail.com>
2748 * m32c-ibld.c: Regenerate.
2750 2020-01-06 Alan Modra <amodra@gmail.com>
2753 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2754 Peek at next byte to prevent recursion on repeated prefix bytes.
2755 Ensure uninitialised "mybuf" is not accessed.
2756 (print_insn_z80): Don't zero n_fetch and n_used here,..
2757 (print_insn_z80_buf): ..do it here instead.
2759 2020-01-04 Alan Modra <amodra@gmail.com>
2761 * m32r-ibld.c: Regenerate.
2763 2020-01-04 Alan Modra <amodra@gmail.com>
2765 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2767 2020-01-04 Alan Modra <amodra@gmail.com>
2769 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2771 2020-01-04 Alan Modra <amodra@gmail.com>
2773 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2775 2020-01-03 Jan Beulich <jbeulich@suse.com>
2777 * aarch64-tbl.h (aarch64_opcode_table): Use
2778 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2780 2020-01-03 Jan Beulich <jbeulich@suse.com>
2782 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2783 forms of SUDOT and USDOT.
2785 2020-01-03 Jan Beulich <jbeulich@suse.com>
2787 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2789 * opcodes/aarch64-dis-2.c: Re-generate.
2791 2020-01-03 Jan Beulich <jbeulich@suse.com>
2793 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2795 * opcodes/aarch64-dis-2.c: Re-generate.
2797 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2799 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2801 2020-01-01 Alan Modra <amodra@gmail.com>
2803 Update year range in copyright notice of all files.
2805 For older changes see ChangeLog-2019
2807 Copyright (C) 2020 Free Software Foundation, Inc.
2809 Copying and distribution of this file, with or without modification,
2810 are permitted in any medium without royalty provided the copyright
2811 notice and this notice are preserved.
2817 version-control: never
projects / thirdparty / binutils-gdb.git / blob