opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2023 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #include <limits.h>
  23 #ifndef CHAR_BIT
  24 #define CHAR_BIT 8
  25 #endif
  26
  27 /* Position of cpu flags bitfiled.  */
  28
  29 enum
  30 {
  31   /* i186 or better required */
  32   Cpu186 = 0,
  33   /* i286 or better required */
  34   Cpu286,
  35   /* i386 or better required */
  36   Cpu386,
  37   /* i486 or better required */
  38   Cpu486,
  39   /* i585 or better required */
  40   Cpu586,
  41   /* i686 or better required */
  42   Cpu686,
  43   /* CMOV Instruction support required */
  44   CpuCMOV,
  45   /* FXSR Instruction support required */
  46   CpuFXSR,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* LZCNT support required */
  88   CpuLZCNT,
  89   /* POPCNT support required */
  90   CpuPOPCNT,
  91   /* MONITOR support required */
  92   CpuMONITOR,
  93   /* SSE4.1 support required */
  94   CpuSSE4_1,
  95   /* SSE4.2 support required */
  96   CpuSSE4_2,
  97   /* AVX support required */
  98   CpuAVX,
  99   /* AVX2 support required */
 100   CpuAVX2,
 101   /* Intel AVX-512 Foundation Instructions support required */
 102   CpuAVX512F,
 103   /* Intel AVX-512 Conflict Detection Instructions support required */
 104   CpuAVX512CD,
 105   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 106      required */
 107   CpuAVX512ER,
 108   /* Intel AVX-512 Prefetch Instructions support required */
 109   CpuAVX512PF,
 110   /* Intel AVX-512 VL Instructions support required.  */
 111   CpuAVX512VL,
 112   /* Intel AVX-512 DQ Instructions support required.  */
 113   CpuAVX512DQ,
 114   /* Intel AVX-512 BW Instructions support required.  */
 115   CpuAVX512BW,
 116   /* Intel IAMCU support required */
 117   CpuIAMCU,
 118   /* Xsave/xrstor New Instructions support required */
 119   CpuXsave,
 120   /* Xsaveopt New Instructions support required */
 121   CpuXsaveopt,
 122   /* AES support required */
 123   CpuAES,
 124   /* PCLMUL support required */
 125   CpuPCLMUL,
 126   /* FMA support required */
 127   CpuFMA,
 128   /* FMA4 support required */
 129   CpuFMA4,
 130   /* XOP support required */
 131   CpuXOP,
 132   /* LWP support required */
 133   CpuLWP,
 134   /* BMI support required */
 135   CpuBMI,
 136   /* TBM support required */
 137   CpuTBM,
 138   /* MOVBE Instruction support required */
 139   CpuMovbe,
 140   /* CMPXCHG16B instruction support required.  */
 141   CpuCX16,
 142   /* LAHF/SAHF instruction support required (in 64-bit mode).  */
 143   CpuLAHF_SAHF,
 144   /* EPT Instructions required */
 145   CpuEPT,
 146   /* RDTSCP Instruction support required */
 147   CpuRdtscp,
 148   /* FSGSBASE Instructions required */
 149   CpuFSGSBase,
 150   /* RDRND Instructions required */
 151   CpuRdRnd,
 152   /* F16C Instructions required */
 153   CpuF16C,
 154   /* Intel BMI2 support required */
 155   CpuBMI2,
 156   /* HLE support required */
 157   CpuHLE,
 158   /* RTM support required */
 159   CpuRTM,
 160   /* INVPCID Instructions required */
 161   CpuINVPCID,
 162   /* VMFUNC Instruction required */
 163   CpuVMFUNC,
 164   /* Intel MPX Instructions required  */
 165   CpuMPX,
 166   /* 64bit support available, used by -march= in assembler.  */
 167   CpuLM,
 168   /* RDRSEED instruction required.  */
 169   CpuRDSEED,
 170   /* Multi-presisionn add-carry instructions are required.  */
 171   CpuADX,
 172   /* Supports prefetchw and prefetch instructions.  */
 173   CpuPRFCHW,
 174   /* SMAP instructions required.  */
 175   CpuSMAP,
 176   /* SHA instructions required.  */
 177   CpuSHA,
 178   /* SHA512 instructions required.  */
 179   CpuSHA512,
 180   /* SM3 instructions required.  */
 181   CpuSM3,
 182   /* SM4 instructions required.  */
 183   CpuSM4,
 184   /* CLFLUSHOPT instruction required */
 185   CpuClflushOpt,
 186   /* XSAVES/XRSTORS instruction required */
 187   CpuXSAVES,
 188   /* XSAVEC instruction required */
 189   CpuXSAVEC,
 190   /* PREFETCHWT1 instruction required */
 191   CpuPREFETCHWT1,
 192   /* SE1 instruction required */
 193   CpuSE1,
 194   /* CLWB instruction required */
 195   CpuCLWB,
 196   /* Intel AVX-512 IFMA Instructions support required.  */
 197   CpuAVX512IFMA,
 198   /* Intel AVX-512 VBMI Instructions support required.  */
 199   CpuAVX512VBMI,
 200   /* Intel AVX-512 4FMAPS Instructions support required.  */
 201   CpuAVX512_4FMAPS,
 202   /* Intel AVX-512 4VNNIW Instructions support required.  */
 203   CpuAVX512_4VNNIW,
 204   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 205   CpuAVX512_VPOPCNTDQ,
 206   /* Intel AVX-512 VBMI2 Instructions support required.  */
 207   CpuAVX512_VBMI2,
 208   /* Intel AVX-512 VNNI Instructions support required.  */
 209   CpuAVX512_VNNI,
 210   /* Intel AVX-512 BITALG Instructions support required.  */
 211   CpuAVX512_BITALG,
 212   /* Intel AVX-512 BF16 Instructions support required.  */
 213   CpuAVX512_BF16,
 214   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 215   CpuAVX512_VP2INTERSECT,
 216   /* TDX Instructions support required.  */
 217   CpuTDX,
 218   /* Intel AVX VNNI Instructions support required.  */
 219   CpuAVX_VNNI,
 220   /* Intel AVX-512 FP16 Instructions support required.  */
 221   CpuAVX512_FP16,
 222   /* PREFETCHI instruction required */
 223   CpuPREFETCHI,
 224   /* Intel AVX IFMA Instructions support required.  */
 225   CpuAVX_IFMA,
 226   /* Intel AVX VNNI-INT8 Instructions support required.  */
 227   CpuAVX_VNNI_INT8,
 228   /* Intel AVX VNNI-INT16 Instructions support required.  */
 229   CpuAVX_VNNI_INT16,
 230   /* Intel CMPccXADD instructions support required.  */
 231   CpuCMPCCXADD,
 232   /* Intel WRMSRNS Instructions support required */
 233   CpuWRMSRNS,
 234   /* Intel MSRLIST Instructions support required.  */
 235   CpuMSRLIST,
 236   /* Intel AVX NE CONVERT Instructions support required.  */
 237   CpuAVX_NE_CONVERT,
 238   /* Intel RAO INT Instructions support required.  */
 239   CpuRAO_INT,
 240   /* fred instruction required */
 241   CpuFRED,
 242   /* lkgs instruction required */
 243   CpuLKGS,
 244   /* mwaitx instruction required */
 245   CpuMWAITX,
 246   /* Clzero instruction required */
 247   CpuCLZERO,
 248   /* OSPKE instruction required */
 249   CpuOSPKE,
 250   /* RDPID instruction required */
 251   CpuRDPID,
 252   /* PTWRITE instruction required */
 253   CpuPTWRITE,
 254   /* CET instructions support required */
 255   CpuIBT,
 256   CpuSHSTK,
 257   /* AMX-INT8 instructions required */
 258   CpuAMX_INT8,
 259   /* AMX-BF16 instructions required */
 260   CpuAMX_BF16,
 261   /* AMX-FP16 instructions required */
 262   CpuAMX_FP16,
 263   /* AMX-COMPLEX instructions required.  */
 264   CpuAMX_COMPLEX,
 265   /* AMX-TILE instructions required */
 266   CpuAMX_TILE,
 267   /* GFNI instructions required */
 268   CpuGFNI,
 269   /* VAES instructions required */
 270   CpuVAES,
 271   /* VPCLMULQDQ instructions required */
 272   CpuVPCLMULQDQ,
 273   /* WBNOINVD instructions required */
 274   CpuWBNOINVD,
 275   /* PCONFIG instructions required */
 276   CpuPCONFIG,
 277   /* PBNDKB instructions required.  */
 278   CpuPBNDKB,
 279   /* WAITPKG instructions required */
 280   CpuWAITPKG,
 281   /* UINTR instructions required */
 282   CpuUINTR,
 283   /* CLDEMOTE instruction required */
 284   CpuCLDEMOTE,
 285   /* MOVDIRI instruction support required */
 286   CpuMOVDIRI,
 287   /* MOVDIRR64B instruction required */
 288   CpuMOVDIR64B,
 289   /* ENQCMD instruction required */
 290   CpuENQCMD,
 291   /* SERIALIZE instruction required */
 292   CpuSERIALIZE,
 293   /* RDPRU instruction required */
 294   CpuRDPRU,
 295   /* MCOMMIT instruction required */
 296   CpuMCOMMIT,
 297   /* SEV-ES instruction(s) required */
 298   CpuSEV_ES,
 299   /* TSXLDTRK instruction required */
 300   CpuTSXLDTRK,
 301   /* KL instruction support required */
 302   CpuKL,
 303   /* WideKL instruction support required */
 304   CpuWideKL,
 305   /* HRESET instruction required */
 306   CpuHRESET,
 307   /* INVLPGB instructions required */
 308   CpuINVLPGB,
 309   /* TLBSYNC instructions required */
 310   CpuTLBSYNC,
 311   /* SNP instructions required */
 312   CpuSNP,
 313   /* RMPQUERY instruction required */
 314   CpuRMPQUERY,
 315
 316   /* NOTE: These last three items need to remain last and in this order. */
 317
 318   /* 64bit support required  */
 319   Cpu64,
 320   /* Not supported in the 64bit mode  */
 321   CpuNo64,
 322   /* The last bitfield in i386_cpu_flags.  */
 323   CpuMax = CpuNo64
 324 };
 325
 326 #define CpuNumOfUints \
 327   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 328 #define CpuNumOfBits \
 329   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 330
 331 /* If you get a compiler error for zero width of the unused field,
 332    comment it out.  */
 333 #define CpuUnused       (CpuMax + 1)
 334
 335 /* We can check if an instruction is available with array instead
 336    of bitfield. */
 337 typedef union i386_cpu_flags
 338 {
 339   struct
 340     {
 341       unsigned int cpui186:1;
 342       unsigned int cpui286:1;
 343       unsigned int cpui386:1;
 344       unsigned int cpui486:1;
 345       unsigned int cpui586:1;
 346       unsigned int cpui686:1;
 347       unsigned int cpucmov:1;
 348       unsigned int cpufxsr:1;
 349       unsigned int cpuclflush:1;
 350       unsigned int cpunop:1;
 351       unsigned int cpusyscall:1;
 352       unsigned int cpu8087:1;
 353       unsigned int cpu287:1;
 354       unsigned int cpu387:1;
 355       unsigned int cpu687:1;
 356       unsigned int cpufisttp:1;
 357       unsigned int cpummx:1;
 358       unsigned int cpusse:1;
 359       unsigned int cpusse2:1;
 360       unsigned int cpua3dnow:1;
 361       unsigned int cpua3dnowa:1;
 362       unsigned int cpusse3:1;
 363       unsigned int cpupadlock:1;
 364       unsigned int cpusvme:1;
 365       unsigned int cpuvmx:1;
 366       unsigned int cpusmx:1;
 367       unsigned int cpussse3:1;
 368       unsigned int cpusse4a:1;
 369       unsigned int cpulzcnt:1;
 370       unsigned int cpupopcnt:1;
 371       unsigned int cpumonitor:1;
 372       unsigned int cpusse4_1:1;
 373       unsigned int cpusse4_2:1;
 374       unsigned int cpuavx:1;
 375       unsigned int cpuavx2:1;
 376       unsigned int cpuavx512f:1;
 377       unsigned int cpuavx512cd:1;
 378       unsigned int cpuavx512er:1;
 379       unsigned int cpuavx512pf:1;
 380       unsigned int cpuavx512vl:1;
 381       unsigned int cpuavx512dq:1;
 382       unsigned int cpuavx512bw:1;
 383       unsigned int cpuiamcu:1;
 384       unsigned int cpuxsave:1;
 385       unsigned int cpuxsaveopt:1;
 386       unsigned int cpuaes:1;
 387       unsigned int cpupclmul:1;
 388       unsigned int cpufma:1;
 389       unsigned int cpufma4:1;
 390       unsigned int cpuxop:1;
 391       unsigned int cpulwp:1;
 392       unsigned int cpubmi:1;
 393       unsigned int cputbm:1;
 394       unsigned int cpumovbe:1;
 395       unsigned int cpucx16:1;
 396       unsigned int cpulahf_sahf:1;
 397       unsigned int cpuept:1;
 398       unsigned int cpurdtscp:1;
 399       unsigned int cpufsgsbase:1;
 400       unsigned int cpurdrnd:1;
 401       unsigned int cpuf16c:1;
 402       unsigned int cpubmi2:1;
 403       unsigned int cpuhle:1;
 404       unsigned int cpurtm:1;
 405       unsigned int cpuinvpcid:1;
 406       unsigned int cpuvmfunc:1;
 407       unsigned int cpumpx:1;
 408       unsigned int cpulm:1;
 409       unsigned int cpurdseed:1;
 410       unsigned int cpuadx:1;
 411       unsigned int cpuprfchw:1;
 412       unsigned int cpusmap:1;
 413       unsigned int cpusha:1;
 414       unsigned int cpusha512:1;
 415       unsigned int cpusm3:1;
 416       unsigned int cpusm4:1;
 417       unsigned int cpuclflushopt:1;
 418       unsigned int cpuxsaves:1;
 419       unsigned int cpuxsavec:1;
 420       unsigned int cpuprefetchwt1:1;
 421       unsigned int cpuse1:1;
 422       unsigned int cpuclwb:1;
 423       unsigned int cpuavx512ifma:1;
 424       unsigned int cpuavx512vbmi:1;
 425       unsigned int cpuavx512_4fmaps:1;
 426       unsigned int cpuavx512_4vnniw:1;
 427       unsigned int cpuavx512_vpopcntdq:1;
 428       unsigned int cpuavx512_vbmi2:1;
 429       unsigned int cpuavx512_vnni:1;
 430       unsigned int cpuavx512_bitalg:1;
 431       unsigned int cpuavx512_bf16:1;
 432       unsigned int cpuavx512_vp2intersect:1;
 433       unsigned int cputdx:1;
 434       unsigned int cpuavx_vnni:1;
 435       unsigned int cpuavx512_fp16:1;
 436       unsigned int cpuprefetchi:1;
 437       unsigned int cpuavx_ifma:1;
 438       unsigned int cpuavx_vnni_int8:1;
 439       unsigned int cpuavx_vnni_int16:1;
 440       unsigned int cpucmpccxadd:1;
 441       unsigned int cpuwrmsrns:1;
 442       unsigned int cpumsrlist:1;
 443       unsigned int cpuavx_ne_convert:1;
 444       unsigned int cpurao_int:1;
 445       unsigned int cpufred:1;
 446       unsigned int cpulkgs:1;
 447       unsigned int cpumwaitx:1;
 448       unsigned int cpuclzero:1;
 449       unsigned int cpuospke:1;
 450       unsigned int cpurdpid:1;
 451       unsigned int cpuptwrite:1;
 452       unsigned int cpuibt:1;
 453       unsigned int cpushstk:1;
 454       unsigned int cpuamx_int8:1;
 455       unsigned int cpuamx_bf16:1;
 456       unsigned int cpuamx_fp16:1;
 457       unsigned int cpuamx_complex:1;
 458       unsigned int cpuamx_tile:1;
 459       unsigned int cpugfni:1;
 460       unsigned int cpuvaes:1;
 461       unsigned int cpuvpclmulqdq:1;
 462       unsigned int cpuwbnoinvd:1;
 463       unsigned int cpupconfig:1;
 464       unsigned int cpupbndkb:1;
 465       unsigned int cpuwaitpkg:1;
 466       unsigned int cpuuintr:1;
 467       unsigned int cpucldemote:1;
 468       unsigned int cpumovdiri:1;
 469       unsigned int cpumovdir64b:1;
 470       unsigned int cpuenqcmd:1;
 471       unsigned int cpuserialize:1;
 472       unsigned int cpurdpru:1;
 473       unsigned int cpumcommit:1;
 474       unsigned int cpusev_es:1;
 475       unsigned int cputsxldtrk:1;
 476       unsigned int cpukl:1;
 477       unsigned int cpuwidekl:1;
 478       unsigned int cpuhreset:1;
 479       unsigned int cpuinvlpgb:1;
 480       unsigned int cputlbsync:1;
 481       unsigned int cpusnp:1;
 482       unsigned int cpurmpquery:1;
 483       /* NOTE: These last three fields need to remain last and in this order. */
 484       unsigned int cpu64:1;
 485       unsigned int cpuno64:1;
 486 #ifdef CpuUnused
 487       unsigned int unused:(CpuNumOfBits - CpuUnused);
 488 #endif
 489     } bitfield;
 490   unsigned int array[CpuNumOfUints];
 491 } i386_cpu_flags;
 492
 493 /* Position of opcode_modifier bits.  */
 494
 495 enum
 496 {
 497   /* has direction bit. */
 498   D = 0,
 499   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 500      canonical way; the base_opcode field should hold the encoding for byte
 501      operands  */
 502   W,
 503   /* load form instruction. Must be placed before store form.  */
 504   Load,
 505   /* insn has a modrm byte. */
 506   Modrm,
 507   /* special case for jump insns; value has to be 1 */
 508 #define JUMP 1
 509   /* call and jump */
 510 #define JUMP_DWORD 2
 511   /* loop and jecxz */
 512 #define JUMP_BYTE 3
 513   /* special case for intersegment leaps/calls */
 514 #define JUMP_INTERSEGMENT 4
 515   /* absolute address for jump */
 516 #define JUMP_ABSOLUTE 5
 517   Jump,
 518   /* FP insn memory format bit, sized by 0x4 */
 519   FloatMF,
 520   /* needs size prefix if in 32-bit mode */
 521 #define SIZE16 1
 522   /* needs size prefix if in 16-bit mode */
 523 #define SIZE32 2
 524   /* needs size prefix if in 64-bit mode */
 525 #define SIZE64 3
 526   Size,
 527   /* Check that operand sizes match.  */
 528   CheckOperandSize,
 529   /* any memory size */
 530 #define ANY_SIZE 1
 531   /* fake an extra reg operand for clr, imul and special register
 532      processing for some instructions.  */
 533 #define REG_KLUDGE 2
 534   /* deprecated fp insn, gets a warning */
 535 #define UGH 3
 536   /* An implicit xmm0 as the first operand */
 537 #define IMPLICIT_1ST_XMM0 4
 538   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 539      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 540    */
 541 #define IMPLICIT_QUAD_GROUP 5
 542   /* Two source operands are swapped.  */
 543 #define SWAP_SOURCES 6
 544   /* Default mask isn't allowed.  */
 545 #define NO_DEFAULT_MASK 7
 546   /* Address prefix changes register operand */
 547 #define ADDR_PREFIX_OP_REG 8
 548   /* Instrucion requires that destination must be distinct from source
 549      registers.  */
 550 #define DISTINCT_DEST 9
 551   OperandConstraint,
 552   /* instruction ignores operand size prefix and in Intel mode ignores
 553      mnemonic size suffix check.  */
 554 #define IGNORESIZE      1
 555   /* default insn size depends on mode */
 556 #define DEFAULTSIZE     2
 557   MnemonicSize,
 558   /* b suffix on instruction illegal */
 559   No_bSuf,
 560   /* w suffix on instruction illegal */
 561   No_wSuf,
 562   /* l suffix on instruction illegal */
 563   No_lSuf,
 564   /* s suffix on instruction illegal */
 565   No_sSuf,
 566   /* q suffix on instruction illegal */
 567   No_qSuf,
 568   /* instruction needs FWAIT */
 569   FWait,
 570   /* IsString provides for a quick test for string instructions, and
 571      its actual value also indicates which of the operands (if any)
 572      requires use of the %es segment.  */
 573 #define IS_STRING_ES_OP0 2
 574 #define IS_STRING_ES_OP1 3
 575   IsString,
 576   /* RegMem is for instructions with a modrm byte where the register
 577      destination operand should be encoded in the mod and regmem fields.
 578      Normally, it will be encoded in the reg field. We add a RegMem
 579      flag to indicate that it should be encoded in the regmem field.  */
 580   RegMem,
 581   /* quick test if branch instruction is MPX supported */
 582   BNDPrefixOk,
 583 #define PrefixNone              0
 584 #define PrefixRep               1
 585 #define PrefixHLERelease        2 /* Okay with an XRELEASE (0xf3) prefix. */
 586 #define PrefixNoTrack           3
 587   /* Prefixes implying "LOCK okay" must come after Lock. All others have
 588      to come before.  */
 589 #define PrefixLock              4
 590 #define PrefixHLELock           5 /* Okay with a LOCK prefix.  */
 591 #define PrefixHLEAny            6 /* Okay with or without a LOCK prefix.  */
 592   PrefixOk,
 593   /* opcode is a prefix */
 594   IsPrefix,
 595   /* instruction has extension in 8 bit imm */
 596   ImmExt,
 597   /* instruction don't need Rex64 prefix.  */
 598   NoRex64,
 599   /* insn has VEX prefix:
 600         1: 128bit VEX prefix (or operand dependent).
 601         2: 256bit VEX prefix.
 602         3: Scalar VEX prefix.
 603    */
 604 #define VEX128          1
 605 #define VEX256          2
 606 #define VEXScalar       3
 607   Vex,
 608   /* How to encode VEX.vvvv:
 609      0: VEX.vvvv must be 1111b.
 610      1: VEX.vvvv encodes one of the register operands.
 611    */
 612   VexVVVV,
 613   /* How the VEX.W bit is used:
 614      0: Set by the REX.W bit.
 615      1: VEX.W0.  Should always be 0.
 616      2: VEX.W1.  Should always be 1.
 617      3: VEX.WIG. The VEX.W bit is ignored.
 618    */
 619 #define VEXW0   1
 620 #define VEXW1   2
 621 #define VEXWIG  3
 622   VexW,
 623   /* Opcode prefix (values chosen to be usable directly in
 624      VEX/XOP/EVEX pp fields):
 625      0: None
 626      1: Add 0x66 opcode prefix.
 627      2: Add 0xf3 opcode prefix.
 628      3: Add 0xf2 opcode prefix.
 629    */
 630 #define PREFIX_NONE     0
 631 #define PREFIX_0X66     1
 632 #define PREFIX_0XF3     2
 633 #define PREFIX_0XF2     3
 634   OpcodePrefix,
 635   /* Instruction with a mandatory SIB byte:
 636         1: 128bit vector register.
 637         2: 256bit vector register.
 638         3: 512bit vector register.
 639    */
 640 #define VECSIB128       1
 641 #define VECSIB256       2
 642 #define VECSIB512       3
 643 #define SIBMEM          4
 644   SIB,
 645
 646   /* SSE to AVX support required */
 647   SSE2AVX,
 648
 649   /* insn has EVEX prefix:
 650         1: 512bit EVEX prefix.
 651         2: 128bit EVEX prefix.
 652         3: 256bit EVEX prefix.
 653         4: Length-ignored (LIG) EVEX prefix.
 654         5: Length determined from actual operands.
 655         6: L'L = 3 (reserved, .insn only)
 656    */
 657 #define EVEX512                1
 658 #define EVEX128                2
 659 #define EVEX256                3
 660 #define EVEXLIG                4
 661 #define EVEXDYN                5
 662 #define EVEX_L3                6
 663   EVex,
 664
 665   /* AVX512 masking support */
 666   Masking,
 667
 668   /* AVX512 broadcast support.  The number of bytes to broadcast is
 669      1 << (Broadcast - 1):
 670         1: Byte broadcast.
 671         2: Word broadcast.
 672         3: Dword broadcast.
 673         4: Qword broadcast.
 674    */
 675 #define BYTE_BROADCAST  1
 676 #define WORD_BROADCAST  2
 677 #define DWORD_BROADCAST 3
 678 #define QWORD_BROADCAST 4
 679   Broadcast,
 680
 681   /* Static rounding control is supported.  */
 682   StaticRounding,
 683
 684   /* Supress All Exceptions is supported.  */
 685   SAE,
 686
 687   /* Compressed Disp8*N attribute.  */
 688 #define DISP8_SHIFT_VL 7
 689   Disp8MemShift,
 690
 691   /* Support encoding optimization.  */
 692   Optimize,
 693
 694   /* AT&T mnemonic.  */
 695   ATTMnemonic,
 696   /* AT&T syntax.  */
 697   ATTSyntax,
 698   /* Intel syntax.  */
 699   IntelSyntax,
 700   /* ISA64: Don't change the order without other code adjustments.
 701         0: Common to AMD64 and Intel64.
 702         1: AMD64.
 703         2: Intel64.
 704         3: Only in Intel64.
 705    */
 706 #define AMD64           1
 707 #define INTEL64         2
 708 #define INTEL64ONLY     3
 709   ISA64,
 710   /* The last bitfield in i386_opcode_modifier.  */
 711   Opcode_Modifier_Num
 712 };
 713
 714 typedef struct i386_opcode_modifier
 715 {
 716   unsigned int d:1;
 717   unsigned int w:1;
 718   unsigned int load:1;
 719   unsigned int modrm:1;
 720   unsigned int jump:3;
 721   unsigned int floatmf:1;
 722   unsigned int size:2;
 723   unsigned int checkoperandsize:1;
 724   unsigned int operandconstraint:4;
 725   unsigned int mnemonicsize:2;
 726   unsigned int no_bsuf:1;
 727   unsigned int no_wsuf:1;
 728   unsigned int no_lsuf:1;
 729   unsigned int no_ssuf:1;
 730   unsigned int no_qsuf:1;
 731   unsigned int fwait:1;
 732   unsigned int isstring:2;
 733   unsigned int regmem:1;
 734   unsigned int bndprefixok:1;
 735   unsigned int prefixok:3;
 736   unsigned int isprefix:1;
 737   unsigned int immext:1;
 738   unsigned int norex64:1;
 739   unsigned int vex:2;
 740   unsigned int vexvvvv:1;
 741   unsigned int vexw:2;
 742   unsigned int opcodeprefix:2;
 743   unsigned int sib:3;
 744   unsigned int sse2avx:1;
 745   unsigned int evex:3;
 746   unsigned int masking:1;
 747   unsigned int broadcast:3;
 748   unsigned int staticrounding:1;
 749   unsigned int sae:1;
 750   unsigned int disp8memshift:3;
 751   unsigned int optimize:1;
 752   unsigned int attmnemonic:1;
 753   unsigned int attsyntax:1;
 754   unsigned int intelsyntax:1;
 755   unsigned int isa64:2;
 756 } i386_opcode_modifier;
 757
 758 /* Operand classes.  */
 759
 760 #define CLASS_WIDTH 4
 761 enum operand_class
 762 {
 763   ClassNone,
 764   Reg, /* GPRs and FP regs, distinguished by operand size */
 765   SReg, /* Segment register */
 766   RegCR, /* Control register */
 767   RegDR, /* Debug register */
 768   RegTR, /* Test register */
 769   RegMMX, /* MMX register */
 770   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 771   RegMask, /* Vector Mask register */
 772   RegBND, /* Bound register */
 773 };
 774
 775 /* Special operand instances.  */
 776
 777 #define INSTANCE_WIDTH 3
 778 enum operand_instance
 779 {
 780   InstanceNone,
 781   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 782   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 783   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 784   RegB,  /* %bl / %bx / %ebx / %rbx */
 785 };
 786
 787 /* Position of operand_type bits.  */
 788
 789 enum
 790 {
 791   /* Class and Instance */
 792   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 793   /* 1 bit immediate */
 794   Imm1,
 795   /* 8 bit immediate */
 796   Imm8,
 797   /* 8 bit immediate sign extended */
 798   Imm8S,
 799   /* 16 bit immediate */
 800   Imm16,
 801   /* 32 bit immediate */
 802   Imm32,
 803   /* 32 bit immediate sign extended */
 804   Imm32S,
 805   /* 64 bit immediate */
 806   Imm64,
 807   /* 8bit/16bit/32bit displacements are used in different ways,
 808      depending on the instruction.  For jumps, they specify the
 809      size of the PC relative displacement, for instructions with
 810      memory operand, they specify the size of the offset relative
 811      to the base register, and for instructions with memory offset
 812      such as `mov 1234,%al' they specify the size of the offset
 813      relative to the segment base.  */
 814   /* 8 bit displacement */
 815   Disp8,
 816   /* 16 bit displacement */
 817   Disp16,
 818   /* 32 bit displacement (64-bit: sign-extended) */
 819   Disp32,
 820   /* 64 bit displacement */
 821   Disp64,
 822   /* Register which can be used for base or index in memory operand.  */
 823   BaseIndex,
 824   /* BYTE size. */
 825   Byte,
 826   /* WORD size. 2 byte */
 827   Word,
 828   /* DWORD size. 4 byte */
 829   Dword,
 830   /* FWORD size. 6 byte */
 831   Fword,
 832   /* QWORD size. 8 byte */
 833   Qword,
 834   /* TBYTE size. 10 byte */
 835   Tbyte,
 836   /* XMMWORD size. */
 837   Xmmword,
 838   /* YMMWORD size. */
 839   Ymmword,
 840   /* ZMMWORD size.  */
 841   Zmmword,
 842   /* TMMWORD size.  */
 843   Tmmword,
 844   /* Unspecified memory size.  */
 845   Unspecified,
 846
 847   /* The number of bits in i386_operand_type.  */
 848   OTNum
 849 };
 850
 851 #define OTNumOfUints \
 852   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 853 #define OTNumOfBits \
 854   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 855
 856 /* If you get a compiler error for zero width of the unused field,
 857    comment it out.  */
 858 #define OTUnused                OTNum
 859
 860 typedef union i386_operand_type
 861 {
 862   struct
 863     {
 864       unsigned int class:CLASS_WIDTH;
 865       unsigned int instance:INSTANCE_WIDTH;
 866       unsigned int imm1:1;
 867       unsigned int imm8:1;
 868       unsigned int imm8s:1;
 869       unsigned int imm16:1;
 870       unsigned int imm32:1;
 871       unsigned int imm32s:1;
 872       unsigned int imm64:1;
 873       unsigned int disp8:1;
 874       unsigned int disp16:1;
 875       unsigned int disp32:1;
 876       unsigned int disp64:1;
 877       unsigned int baseindex:1;
 878       unsigned int byte:1;
 879       unsigned int word:1;
 880       unsigned int dword:1;
 881       unsigned int fword:1;
 882       unsigned int qword:1;
 883       unsigned int tbyte:1;
 884       unsigned int xmmword:1;
 885       unsigned int ymmword:1;
 886       unsigned int zmmword:1;
 887       unsigned int tmmword:1;
 888       unsigned int unspecified:1;
 889 #ifdef OTUnused
 890       unsigned int unused:(OTNumOfBits - OTUnused);
 891 #endif
 892     } bitfield;
 893   unsigned int array[OTNumOfUints];
 894 } i386_operand_type;
 895
 896 typedef struct insn_template
 897 {
 898   /* instruction name sans width suffix ("mov" for movl insns) */
 899   unsigned int mnem_off;
 900
 901   /* Bitfield arrangement is such that individual fields can be easily
 902      extracted (in native builds at least) - either by at most a masking
 903      operation (base_opcode, operands), or by just a (signed) right shift
 904      (extension_opcode).  Please try to maintain this property.  */
 905
 906   /* base_opcode is the fundamental opcode byte without optional
 907      prefix(es).  */
 908   unsigned int base_opcode:16;
 909 #define Opcode_D        0x2 /* Direction bit:
 910                                set if Reg --> Regmem;
 911                                unset if Regmem --> Reg. */
 912 #define Opcode_FloatR   0x8 /* ModR/M bit to swap src/dest for float insns. */
 913 #define Opcode_FloatD   0x4 /* Direction bit for float insns. */
 914 #define Opcode_ExtD     0x1 /* Direction bit for extended opcode space insns. */
 915 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 916 /* The next value is arbitrary, as long as it's non-zero and distinct
 917    from all other values above.  */
 918 #define Opcode_VexW     0xf /* Operand order controlled by VEX.W. */
 919
 920   /* how many operands */
 921   unsigned int operands:3;
 922
 923   /* opcode space */
 924   unsigned int opcode_space:4;
 925   /* Opcode encoding space (values chosen to be usable directly in
 926      VEX/XOP mmmmm and EVEX mm fields):
 927      0: Base opcode space.
 928      1: 0F opcode prefix / space.
 929      2: 0F38 opcode prefix / space.
 930      3: 0F3A opcode prefix / space.
 931      5: EVEXMAP5 opcode prefix / space.
 932      6: EVEXMAP6 opcode prefix / space.
 933      8: XOP 08 opcode space.
 934      9: XOP 09 opcode space.
 935      A: XOP 0A opcode space.
 936    */
 937 #define SPACE_BASE      0
 938 #define SPACE_0F        1
 939 #define SPACE_0F38      2
 940 #define SPACE_0F3A      3
 941 #define SPACE_EVEXMAP5  5
 942 #define SPACE_EVEXMAP6  6
 943 #define SPACE_XOP08     8
 944 #define SPACE_XOP09     9
 945 #define SPACE_XOP0A     0xA
 946
 947 /* (Fake) base opcode value for pseudo prefixes.  */
 948 #define PSEUDO_PREFIX 0
 949
 950   /* extension_opcode is the 3 bit extension for group <n> insns.
 951      This field is also used to store the 8-bit opcode suffix for the
 952      AMD 3DNow! instructions.
 953      If this template has no extension opcode (the usual case) use None
 954      Instructions */
 955   signed int extension_opcode:9;
 956 #define None (-1)               /* If no extension_opcode is possible.  */
 957
 958 /* Pseudo prefixes.  */
 959 #define Prefix_Disp8            0       /* {disp8} */
 960 #define Prefix_Disp16           1       /* {disp16} */
 961 #define Prefix_Disp32           2       /* {disp32} */
 962 #define Prefix_Load             3       /* {load} */
 963 #define Prefix_Store            4       /* {store} */
 964 #define Prefix_VEX              5       /* {vex} */
 965 #define Prefix_VEX3             6       /* {vex3} */
 966 #define Prefix_EVEX             7       /* {evex} */
 967 #define Prefix_REX              8       /* {rex} */
 968 #define Prefix_NoOptimize       9       /* {nooptimize} */
 969
 970   /* the bits in opcode_modifier are used to generate the final opcode from
 971      the base_opcode.  These bits also are used to detect alternate forms of
 972      the same instruction */
 973   i386_opcode_modifier opcode_modifier;
 974
 975   /* cpu feature flags */
 976   i386_cpu_flags cpu_flags;
 977
 978   /* operand_types[i] describes the type of operand i.  This is made
 979      by OR'ing together all of the possible type masks.  (e.g.
 980      'operand_types[i] = Reg|Imm' specifies that operand i can be
 981      either a register or an immediate operand.  */
 982   i386_operand_type operand_types[MAX_OPERANDS];
 983 }
 984 insn_template;
 985
 986 /* these are for register name --> number & type hash lookup */
 987 typedef struct
 988 {
 989   char reg_name[8];
 990   i386_operand_type reg_type;
 991   unsigned char reg_flags;
 992 #define RegRex      0x1  /* Extended register.  */
 993 #define RegRex64    0x2  /* Extended 8 bit register.  */
 994 #define RegVRex     0x4  /* Extended vector register.  */
 995   unsigned char reg_num;
 996 #define RegIP   ((unsigned char ) ~0)
 997 /* EIZ and RIZ are fake index registers.  */
 998 #define RegIZ   (RegIP - 1)
 999 /* FLAT is a fake segment register (Intel mode).  */
1000 #define RegFlat     ((unsigned char) ~0)
1001   signed char dw2_regnum[2];
1002 #define Dw2Inval (-1)
1003 }
1004 reg_entry;