]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commitdiff
x86: replace adhoc ambiguous operand checking for CRC32
authorJan Beulich <jbeulich@suse.com>
Tue, 21 Jan 2020 07:30:05 +0000 (08:30 +0100)
committerJan Beulich <jbeulich@suse.com>
Tue, 21 Jan 2020 07:30:05 +0000 (08:30 +0100)
There's no need (anymore?) to heavily special case this - just make
generic logic consider only its first operand, and deal with the case
of an 'l' suffix not being allowed in a pattern.

13 files changed:
gas/ChangeLog
gas/config/tc-i386.c
gas/testsuite/gas/i386/inval-crc32.l
gas/testsuite/gas/i386/noreg16.d
gas/testsuite/gas/i386/noreg16.l
gas/testsuite/gas/i386/noreg16.s
gas/testsuite/gas/i386/noreg32.d
gas/testsuite/gas/i386/noreg32.l
gas/testsuite/gas/i386/noreg32.s
gas/testsuite/gas/i386/noreg64.d
gas/testsuite/gas/i386/noreg64.l
gas/testsuite/gas/i386/noreg64.s
gas/testsuite/gas/i386/x86-64-inval-crc32.l

index c5528ed6e86234fada3905f4e814f0113c984f8c..37d73faba082fea93033baf99188a578e9a33e52 100644 (file)
@@ -1,3 +1,17 @@
+2020-01-21  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (process_suffix): Merge CRC32 handling into
+       generic code path. Deal with No_lSuf being set in a template.
+       * testsuite/gas/i386/inval-crc32.l,
+       testsuite/gas/i386/x86-64-inval-crc32.l: Expect warning(s)
+       instead of error(s) when operand size is ambiguous.
+       * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
+       testsuite/gas/i386/noreg64.s: Add CRC32 tests.
+       * testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.l,
+       testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.l,
+       testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l:
+       Adjust expectations.
+
 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 
        * config/tc-i386.c (process_suffix): Drop SYSRET special case
index 0b7542f99dc0ad87811fbeeb29149e3d58c7f047..3a2a1b743536db577589e7235d453cb6fb073036 100644 (file)
@@ -6301,50 +6301,26 @@ process_suffix (void)
             Destination register type is more significant than source
             register type.  crc32 in SSE4.2 prefers source register
             type. */
-         if (i.tm.base_opcode == 0xf20f38f0
-             && i.types[0].bitfield.class == Reg)
-           {
-             if (i.types[0].bitfield.byte)
-               i.suffix = BYTE_MNEM_SUFFIX;
-             else if (i.types[0].bitfield.word)
-               i.suffix = WORD_MNEM_SUFFIX;
-             else if (i.types[0].bitfield.dword)
-               i.suffix = LONG_MNEM_SUFFIX;
-             else if (i.types[0].bitfield.qword)
-               i.suffix = QWORD_MNEM_SUFFIX;
-           }
-
-         if (!i.suffix)
-           {
-             int op;
+         unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1;
 
-             if (i.tm.base_opcode == 0xf20f38f0)
-               {
-                 /* We have to know the operand size for crc32.  */
-                 as_bad (_("ambiguous memory operand size for `%s`"),
-                         i.tm.name);
-                 return 0;
-               }
-
-             for (op = i.operands; --op >= 0;)
-               if (i.tm.operand_types[op].bitfield.instance == InstanceNone
-                   || i.tm.operand_types[op].bitfield.instance == Accum)
-                 {
-                   if (i.types[op].bitfield.class != Reg)
-                     continue;
-                   if (i.types[op].bitfield.byte)
-                     i.suffix = BYTE_MNEM_SUFFIX;
-                   else if (i.types[op].bitfield.word)
-                     i.suffix = WORD_MNEM_SUFFIX;
-                   else if (i.types[op].bitfield.dword)
-                     i.suffix = LONG_MNEM_SUFFIX;
-                   else if (i.types[op].bitfield.qword)
-                     i.suffix = QWORD_MNEM_SUFFIX;
-                   else
-                     continue;
-                   break;
-                 }
-           }
+         while (op--)
+           if (i.tm.operand_types[op].bitfield.instance == InstanceNone
+               || i.tm.operand_types[op].bitfield.instance == Accum)
+             {
+               if (i.types[op].bitfield.class != Reg)
+                 continue;
+               if (i.types[op].bitfield.byte)
+                 i.suffix = BYTE_MNEM_SUFFIX;
+               else if (i.types[op].bitfield.word)
+                 i.suffix = WORD_MNEM_SUFFIX;
+               else if (i.types[op].bitfield.dword)
+                 i.suffix = LONG_MNEM_SUFFIX;
+               else if (i.types[op].bitfield.qword)
+                 i.suffix = QWORD_MNEM_SUFFIX;
+               else
+                 continue;
+               break;
+             }
        }
       else if (i.suffix == BYTE_MNEM_SUFFIX)
        {
@@ -6484,8 +6460,10 @@ process_suffix (void)
            i.suffix = SHORT_MNEM_SUFFIX;
          else if (flag_code == CODE_16BIT)
            i.suffix = WORD_MNEM_SUFFIX;
-         else
+         else if (!i.tm.opcode_modifier.no_lsuf)
            i.suffix = LONG_MNEM_SUFFIX;
+         else
+           i.suffix = QWORD_MNEM_SUFFIX;
        }
     }
 
index 14f908d1b9fcc238c993a1ee44c9c8a0a5e7a570..5afc35c8a52b1651319de823927ce8be6e49ac7e 100644 (file)
@@ -3,7 +3,7 @@
 .*:7: Error: .*
 .*:8: Error: .*
 .*:9: Error: .*
-.*:10: Error: .*
+.*:10: Warning: .*
 .*:11: Error: .*
 .*:12: Error: .*
 .*:13: Error: .*
@@ -27,7 +27,9 @@ GAS LISTING .*
 [      ]*7[    ]+crc32w \(%esi\), %ax
 [      ]*8[    ]+crc32 \(%esi\), %al
 [      ]*9[    ]+crc32 \(%esi\), %ax
-[      ]*10[   ]+crc32 \(%esi\), %eax
+[      ]*10[   ]+\?\?\?\? F20F38F1[    ]+crc32 \(%esi\), %eax
+\*\*\*\*  Warning: .* `crc32'
+[      ]*10[   ]+06
 [      ]*11[   ]+crc32  %al, %al
 [      ]*12[   ]+crc32b  %al, %al
 [      ]*13[   ]+crc32  %ax, %ax
index fd7336fac5d9f352b5b22bb47461768ce9246944..8a6252eea628b4b6ce50a8090635d63101516003 100644 (file)
@@ -26,6 +26,7 @@ Disassembly of section .text:
  *[a-f0-9]+:   81 3f 34 12             cmpw   \$0x1234,\(%bx\)
  *[a-f0-9]+:   a7                      cmpsw  %es:\(%di\),%ds:\(%si\)
  *[a-f0-9]+:   67 a7                   cmpsw  %es:\(%edi\),%ds:\(%esi\)
+ *[a-f0-9]+:   f2 0f 38 f1 07          crc32w \(%bx\),%eax
  *[a-f0-9]+:   f2 0f 2a 07             cvtsi2sdl \(%bx\),%xmm0
  *[a-f0-9]+:   f3 0f 2a 07             cvtsi2ssl \(%bx\),%xmm0
  *[a-f0-9]+:   ff 0f                   decw   \(%bx\)
index 28614317a4fb34ab981e77621c3bade01aa40204..1b3f9bc9f07426cbe5c83f32c036d00d73a3b6d3 100644 (file)
@@ -17,6 +17,7 @@
 .*:[1-9][0-9]*: Warning: .* `cmp'
 .*:[1-9][0-9]*: Warning: .* `cmps'
 .*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `crc32'
 .*:[1-9][0-9]*: Warning: .* `dec'
 .*:[1-9][0-9]*: Warning: .* `div'
 .*:[1-9][0-9]*: Warning: .* `fadd'
index 0d64e326f089e00189052a3b14849115a2c382ee..743e5faeb6ac851c90bc7e5d73104cbb38384dac 100644 (file)
@@ -20,6 +20,7 @@ noreg:
        cmp     $0x1234, (%bx)
        cmps
        cmps    %es:(%edi), (%esi)
+       crc32   (%bx), %eax
        cvtsi2sd (%bx), %xmm0
        cvtsi2ss (%bx), %xmm0
        dec     (%bx)
index b0f8c248b1d4af67b8264609f2cb12ab5fc0e7dc..1e03f98335c83a93d46ff5ad7ca95e4eb98815bd 100644 (file)
@@ -30,6 +30,7 @@ Disassembly of section .text:
  *[a-f0-9]+:   81 38 78 56 34 12       cmpl   \$0x12345678,\(%eax\)
  *[a-f0-9]+:   a7                      cmpsl  %es:\(%edi\),%ds:\(%esi\)
  *[a-f0-9]+:   a7                      cmpsl  %es:\(%edi\),%ds:\(%esi\)
+ *[a-f0-9]+:   f2 0f 38 f1 00          crc32l \(%eax\),%eax
  *[a-f0-9]+:   f2 0f 2a 00             cvtsi2sdl \(%eax\),%xmm0
  *[a-f0-9]+:   f3 0f 2a 00             cvtsi2ssl \(%eax\),%xmm0
  *[a-f0-9]+:   ff 08                   decl   \(%eax\)
index 842774e4b707f959c7f2ab35a5961c0cd1a2625e..1fab0f4cbbe0be41a1ac50aa782da9b437f5ce04 100644 (file)
@@ -21,6 +21,7 @@
 .*:[1-9][0-9]*: Warning: .* `cmp'
 .*:[1-9][0-9]*: Warning: .* `cmps'
 .*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `crc32'
 .*:[1-9][0-9]*: Warning: .* `dec'
 .*:[1-9][0-9]*: Warning: .* `div'
 .*:[1-9][0-9]*: Warning: .* `fadd'
index 7876e963147a9f5761ba13fbf7dfabbfe3f0b429..1d1cf6d797135b59b445c49d7b1bf2ce80320a1c 100644 (file)
@@ -23,6 +23,7 @@ noreg:
        cmp     $0x12345678, (%eax)
        cmps
        cmps    %es:(%edi), (%esi)
+       crc32   (%eax), %eax
        cvtsi2sd (%eax), %xmm0
        cvtsi2ss (%eax), %xmm0
        dec     (%eax)
index d058da486fd0322b029887497d4516b64d881058..8b56ddcd9a43f06068f39bfcaac24f6f642a10ed 100644 (file)
@@ -30,6 +30,8 @@ Disassembly of section .text:
  *[a-f0-9]+:   81 38 78 56 34 12       cmpl   \$0x12345678,\(%rax\)
  *[a-f0-9]+:   a7                      cmpsl  %es:\(%rdi\),%ds:\(%rsi\)
  *[a-f0-9]+:   a7                      cmpsl  %es:\(%rdi\),%ds:\(%rsi\)
+ *[a-f0-9]+:   f2 0f 38 f1 00          crc32l \(%rax\),%eax
+ *[a-f0-9]+:   f2 48 0f 38 f1 00       crc32q \(%rax\),%rax
  *[a-f0-9]+:   f2 0f 2a 00             cvtsi2sdl \(%rax\),%xmm0
  *[a-f0-9]+:   f3 0f 2a 00             cvtsi2ssl \(%rax\),%xmm0
  *[a-f0-9]+:   ff 08                   decl   \(%rax\)
index 9ec8093d383af01d524f802e6014699a5f68837f..a4d3179e4ce5db6954b9a70c72ccf96ebc9a04cb 100644 (file)
@@ -21,6 +21,8 @@
 .*:[1-9][0-9]*: Warning: .* `cmp'
 .*:[1-9][0-9]*: Warning: .* `cmps'
 .*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `crc32'
+.*:[1-9][0-9]*: Warning: .* `crc32'
 .*:[1-9][0-9]*: Warning: .* `cvtsi2sd'
 .*:[1-9][0-9]*: Warning: .* `cvtsi2ss'
 .*:[1-9][0-9]*: Warning: .* `dec'
index 7418ccb2204dea83a2ea3a678c6646e6b4546024..119b44e7245d95e1ee6a8d49f6fdba4a640ca684 100644 (file)
@@ -23,6 +23,8 @@ noreg:
        cmp     $0x12345678, (%rax)
        cmps
        cmps    %es:(%rdi), (%rsi)
+       crc32   (%rax), %eax
+       crc32   (%rax), %rax
        cvtsi2sd (%rax), %xmm0
        cvtsi2ss (%rax), %xmm0
        dec     (%rax)
index b4a8eaabcf67176ba4f7966d6593deeb9997b4a8..e30e82f7ead744265d00027ceb498710356958f3 100644 (file)
@@ -3,8 +3,8 @@
 .*:7: Error: .*
 .*:8: Error: .*
 .*:9: Error: .*
-.*:10: Error: .*
-.*:11: Error: .*
+.*:10: Warning: .*
+.*:11: Warning: .*
 .*:12: Error: .*
 .*:13: Error: .*
 .*:14: Error: .*
@@ -38,8 +38,12 @@ GAS LISTING .*
 [      ]*7[    ]+crc32w \(%rsi\), %ax
 [      ]*8[    ]+crc32 \(%rsi\), %al
 [      ]*9[    ]+crc32 \(%rsi\), %ax
-[      ]*10[   ]+crc32 \(%rsi\), %eax
-[      ]*11[   ]+crc32 \(%rsi\), %rax
+[      ]*10[   ]+\?\?\?\? F20F38F1[    ]+crc32 \(%rsi\), %eax
+\*\*\*\*  Warning: .* `crc32'
+[      ]*10[   ]+06
+[      ]*11[   ]+\?\?\?\? F2480F38[    ]+crc32 \(%rsi\), %rax
+\*\*\*\*  Warning: .* `crc32'
+[      ]*11[   ]+F106
 [      ]*12[   ]+crc32  %al, %al
 [      ]*13[   ]+crc32b  %al, %al
 [      ]*14[   ]+crc32  %ax, %ax