]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commitdiff
gas, arm: PR26858 Fix availability of single precision vmul/vmla in arm mode
authorAndre Vieira <andre.simoesdiasvieira@arm.com>
Fri, 13 Nov 2020 08:59:48 +0000 (08:59 +0000)
committerAndre Vieira <andre.simoesdiasvieira@arm.com>
Thu, 19 Nov 2020 10:07:51 +0000 (10:07 +0000)
This patch fixes a mistake when enabling MVE instructions that disabled support
for single precision vmla and vmul for arm mode.

gas/ChangeLog:
2020-11-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>

Backport from mainline.
2020-11-12  Andre Vieira  <andre.simoesdiasvieira@arm.com>

PR 26858
*  config/tc-arm.c (asm_opcode insns): Fix vmul and vmla's ARM_VARIANT.
* testsuite/gas/arm/pr26858.s: New test.
* testsuite/gas/arm/pr26858.d: New test.

gas/config/tc-arm.c
gas/testsuite/gas/arm/pr26858.d [new file with mode: 0644]
gas/testsuite/gas/arm/pr26858.s [new file with mode: 0644]

index b6bb0debbe34dbc77af61e55d6b424427afabac2..d7849ba2fd482d91245565ca28197a9c6dd59891 100644 (file)
@@ -26002,14 +26002,14 @@ static const struct asm_opcode insns[] =
 #define ARM_VARIANT  & fpu_vfp_ext_v1
 #undef  THUMB_VARIANT
 #define THUMB_VARIANT  & arm_ext_v6t2
- mnCEF(vmla,     _vmla,    3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
- mnCEF(vmul,     _vmul,    3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
 
  mcCE(fcpyd,   eb00b40, 2, (RVD, RVD),       vfp_dp_rd_rm),
 
 #undef  ARM_VARIANT
 #define ARM_VARIANT  & fpu_vfp_ext_v1xd
 
+ mnCEF(vmla,     _vmla,    3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
+ mnCEF(vmul,     _vmul,    3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
  MNCE(vmov,   0,       1, (VMOV),            neon_mov),
  mcCE(fmrs,    e100a10, 2, (RR, RVS),        vfp_reg_from_sp),
  mcCE(fmsr,    e000a10, 2, (RVS, RR),        vfp_sp_from_reg),
diff --git a/gas/testsuite/gas/arm/pr26858.d b/gas/testsuite/gas/arm/pr26858.d
new file mode 100644 (file)
index 0000000..dbe4d71
--- /dev/null
@@ -0,0 +1,8 @@
+# name: PR26858
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+[^>]*> ee266a87        vmul.f32        s12, s13, s14
+[^>]*> ee000a81        vmla.f32        s0, s1, s2
diff --git a/gas/testsuite/gas/arm/pr26858.s b/gas/testsuite/gas/arm/pr26858.s
new file mode 100644 (file)
index 0000000..5a450e7
--- /dev/null
@@ -0,0 +1,6 @@
+.syntax unified
+.arch armv8-r
+.arm
+.fpu fpv5-sp-d16
+vmul.f32 s12, s13, s14
+vmla.f32 s0, s1, s2