+2017-12-12 Stafford Horne <shorne@gmail.com>
+ Peter Gavin <pgavin@gmail.com>
+
+ * or1k/arch.c: Generated.
+ * or1k/arch.h: Generated.
+ * or1k/cpu.c: Generated.
+ * or1k/cpu.h: Generated.
+ * or1k/cpuall.h: Generated.
+ * or1k/decode.c: Generated.
+ * or1k/decode.h: Generated.
+ * or1k/model.c: Generated.
+ * or1k/sem-switch.c: Generated.
+ * or1k/sem.c: Generated.
+
2017-12-12 Stafford Horne <shorne@gmail.com>
Peter Gavin <pgavin@gmail.com>
--- /dev/null
+/* Simulator support for or1k.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const SIM_MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_OR1K32BF
+ & or32_mach,
+#endif
+#ifdef HAVE_CPU_OR1K32BF
+ & or32nd_mach,
+#endif
+ 0
+};
+
--- /dev/null
+/* Simulator header for or1k.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef OR1K_ARCH_H
+#define OR1K_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+#define WI SI
+#define UWI USI
+#define AI USI
+
+#define IAI USI
+
+/* Enum declaration for model types. */
+typedef enum model_type {
+ MODEL_OR1200, MODEL_OR1200ND, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types. */
+typedef enum unit_type {
+ UNIT_NONE, UNIT_OR1200_U_EXEC, UNIT_OR1200ND_U_EXEC, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (1)
+
+#endif /* OR1K_ARCH_H */
--- /dev/null
+/* Misc. support for CPU family or1k32bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU or1k32bf
+#define WANT_CPU_OR1K32BF
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-pc. */
+
+USI
+or1k32bf_h_pc_get (SIM_CPU *current_cpu)
+{
+ return GET_H_PC ();
+}
+
+/* Set a value for h-pc. */
+
+void
+or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_PC (newval);
+}
+
+/* Get the value of h-fsr. */
+
+SF
+or1k32bf_h_fsr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_FSR (regno);
+}
+
+/* Set a value for h-fsr. */
+
+void
+or1k32bf_h_fsr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
+{
+ SET_H_FSR (regno, newval);
+}
+
+/* Get the value of h-spr. */
+
+USI
+or1k32bf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SPR (regno);
+}
+
+/* Set a value for h-spr. */
+
+void
+or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+ SET_H_SPR (regno, newval);
+}
+
+/* Get the value of h-gpr. */
+
+USI
+or1k32bf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GPR (regno);
+}
+
+/* Set a value for h-gpr. */
+
+void
+or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+ SET_H_GPR (regno, newval);
+}
+
+/* Get the value of h-sys-vr. */
+
+USI
+or1k32bf_h_sys_vr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_VR ();
+}
+
+/* Set a value for h-sys-vr. */
+
+void
+or1k32bf_h_sys_vr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_VR (newval);
+}
+
+/* Get the value of h-sys-upr. */
+
+USI
+or1k32bf_h_sys_upr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR ();
+}
+
+/* Set a value for h-sys-upr. */
+
+void
+or1k32bf_h_sys_upr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR (newval);
+}
+
+/* Get the value of h-sys-cpucfgr. */
+
+USI
+or1k32bf_h_sys_cpucfgr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_CPUCFGR ();
+}
+
+/* Set a value for h-sys-cpucfgr. */
+
+void
+or1k32bf_h_sys_cpucfgr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_CPUCFGR (newval);
+}
+
+/* Get the value of h-sys-dmmucfgr. */
+
+USI
+or1k32bf_h_sys_dmmucfgr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_DMMUCFGR ();
+}
+
+/* Set a value for h-sys-dmmucfgr. */
+
+void
+or1k32bf_h_sys_dmmucfgr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_DMMUCFGR (newval);
+}
+
+/* Get the value of h-sys-immucfgr. */
+
+USI
+or1k32bf_h_sys_immucfgr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_IMMUCFGR ();
+}
+
+/* Set a value for h-sys-immucfgr. */
+
+void
+or1k32bf_h_sys_immucfgr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_IMMUCFGR (newval);
+}
+
+/* Get the value of h-sys-dccfgr. */
+
+USI
+or1k32bf_h_sys_dccfgr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_DCCFGR ();
+}
+
+/* Set a value for h-sys-dccfgr. */
+
+void
+or1k32bf_h_sys_dccfgr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_DCCFGR (newval);
+}
+
+/* Get the value of h-sys-iccfgr. */
+
+USI
+or1k32bf_h_sys_iccfgr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ICCFGR ();
+}
+
+/* Set a value for h-sys-iccfgr. */
+
+void
+or1k32bf_h_sys_iccfgr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ICCFGR (newval);
+}
+
+/* Get the value of h-sys-dcfgr. */
+
+USI
+or1k32bf_h_sys_dcfgr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_DCFGR ();
+}
+
+/* Set a value for h-sys-dcfgr. */
+
+void
+or1k32bf_h_sys_dcfgr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_DCFGR (newval);
+}
+
+/* Get the value of h-sys-pccfgr. */
+
+USI
+or1k32bf_h_sys_pccfgr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_PCCFGR ();
+}
+
+/* Set a value for h-sys-pccfgr. */
+
+void
+or1k32bf_h_sys_pccfgr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_PCCFGR (newval);
+}
+
+/* Get the value of h-sys-npc. */
+
+USI
+or1k32bf_h_sys_npc_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_NPC ();
+}
+
+/* Set a value for h-sys-npc. */
+
+void
+or1k32bf_h_sys_npc_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_NPC (newval);
+}
+
+/* Get the value of h-sys-sr. */
+
+USI
+or1k32bf_h_sys_sr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR ();
+}
+
+/* Set a value for h-sys-sr. */
+
+void
+or1k32bf_h_sys_sr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR (newval);
+}
+
+/* Get the value of h-sys-ppc. */
+
+USI
+or1k32bf_h_sys_ppc_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_PPC ();
+}
+
+/* Set a value for h-sys-ppc. */
+
+void
+or1k32bf_h_sys_ppc_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_PPC (newval);
+}
+
+/* Get the value of h-sys-fpcsr. */
+
+USI
+or1k32bf_h_sys_fpcsr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR ();
+}
+
+/* Set a value for h-sys-fpcsr. */
+
+void
+or1k32bf_h_sys_fpcsr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR (newval);
+}
+
+/* Get the value of h-sys-epcr0. */
+
+USI
+or1k32bf_h_sys_epcr0_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR0 ();
+}
+
+/* Set a value for h-sys-epcr0. */
+
+void
+or1k32bf_h_sys_epcr0_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR0 (newval);
+}
+
+/* Get the value of h-sys-epcr1. */
+
+USI
+or1k32bf_h_sys_epcr1_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR1 ();
+}
+
+/* Set a value for h-sys-epcr1. */
+
+void
+or1k32bf_h_sys_epcr1_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR1 (newval);
+}
+
+/* Get the value of h-sys-epcr2. */
+
+USI
+or1k32bf_h_sys_epcr2_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR2 ();
+}
+
+/* Set a value for h-sys-epcr2. */
+
+void
+or1k32bf_h_sys_epcr2_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR2 (newval);
+}
+
+/* Get the value of h-sys-epcr3. */
+
+USI
+or1k32bf_h_sys_epcr3_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR3 ();
+}
+
+/* Set a value for h-sys-epcr3. */
+
+void
+or1k32bf_h_sys_epcr3_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR3 (newval);
+}
+
+/* Get the value of h-sys-epcr4. */
+
+USI
+or1k32bf_h_sys_epcr4_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR4 ();
+}
+
+/* Set a value for h-sys-epcr4. */
+
+void
+or1k32bf_h_sys_epcr4_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR4 (newval);
+}
+
+/* Get the value of h-sys-epcr5. */
+
+USI
+or1k32bf_h_sys_epcr5_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR5 ();
+}
+
+/* Set a value for h-sys-epcr5. */
+
+void
+or1k32bf_h_sys_epcr5_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR5 (newval);
+}
+
+/* Get the value of h-sys-epcr6. */
+
+USI
+or1k32bf_h_sys_epcr6_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR6 ();
+}
+
+/* Set a value for h-sys-epcr6. */
+
+void
+or1k32bf_h_sys_epcr6_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR6 (newval);
+}
+
+/* Get the value of h-sys-epcr7. */
+
+USI
+or1k32bf_h_sys_epcr7_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR7 ();
+}
+
+/* Set a value for h-sys-epcr7. */
+
+void
+or1k32bf_h_sys_epcr7_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR7 (newval);
+}
+
+/* Get the value of h-sys-epcr8. */
+
+USI
+or1k32bf_h_sys_epcr8_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR8 ();
+}
+
+/* Set a value for h-sys-epcr8. */
+
+void
+or1k32bf_h_sys_epcr8_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR8 (newval);
+}
+
+/* Get the value of h-sys-epcr9. */
+
+USI
+or1k32bf_h_sys_epcr9_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR9 ();
+}
+
+/* Set a value for h-sys-epcr9. */
+
+void
+or1k32bf_h_sys_epcr9_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR9 (newval);
+}
+
+/* Get the value of h-sys-epcr10. */
+
+USI
+or1k32bf_h_sys_epcr10_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR10 ();
+}
+
+/* Set a value for h-sys-epcr10. */
+
+void
+or1k32bf_h_sys_epcr10_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR10 (newval);
+}
+
+/* Get the value of h-sys-epcr11. */
+
+USI
+or1k32bf_h_sys_epcr11_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR11 ();
+}
+
+/* Set a value for h-sys-epcr11. */
+
+void
+or1k32bf_h_sys_epcr11_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR11 (newval);
+}
+
+/* Get the value of h-sys-epcr12. */
+
+USI
+or1k32bf_h_sys_epcr12_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR12 ();
+}
+
+/* Set a value for h-sys-epcr12. */
+
+void
+or1k32bf_h_sys_epcr12_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR12 (newval);
+}
+
+/* Get the value of h-sys-epcr13. */
+
+USI
+or1k32bf_h_sys_epcr13_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR13 ();
+}
+
+/* Set a value for h-sys-epcr13. */
+
+void
+or1k32bf_h_sys_epcr13_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR13 (newval);
+}
+
+/* Get the value of h-sys-epcr14. */
+
+USI
+or1k32bf_h_sys_epcr14_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR14 ();
+}
+
+/* Set a value for h-sys-epcr14. */
+
+void
+or1k32bf_h_sys_epcr14_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR14 (newval);
+}
+
+/* Get the value of h-sys-epcr15. */
+
+USI
+or1k32bf_h_sys_epcr15_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EPCR15 ();
+}
+
+/* Set a value for h-sys-epcr15. */
+
+void
+or1k32bf_h_sys_epcr15_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EPCR15 (newval);
+}
+
+/* Get the value of h-sys-eear0. */
+
+USI
+or1k32bf_h_sys_eear0_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR0 ();
+}
+
+/* Set a value for h-sys-eear0. */
+
+void
+or1k32bf_h_sys_eear0_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR0 (newval);
+}
+
+/* Get the value of h-sys-eear1. */
+
+USI
+or1k32bf_h_sys_eear1_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR1 ();
+}
+
+/* Set a value for h-sys-eear1. */
+
+void
+or1k32bf_h_sys_eear1_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR1 (newval);
+}
+
+/* Get the value of h-sys-eear2. */
+
+USI
+or1k32bf_h_sys_eear2_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR2 ();
+}
+
+/* Set a value for h-sys-eear2. */
+
+void
+or1k32bf_h_sys_eear2_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR2 (newval);
+}
+
+/* Get the value of h-sys-eear3. */
+
+USI
+or1k32bf_h_sys_eear3_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR3 ();
+}
+
+/* Set a value for h-sys-eear3. */
+
+void
+or1k32bf_h_sys_eear3_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR3 (newval);
+}
+
+/* Get the value of h-sys-eear4. */
+
+USI
+or1k32bf_h_sys_eear4_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR4 ();
+}
+
+/* Set a value for h-sys-eear4. */
+
+void
+or1k32bf_h_sys_eear4_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR4 (newval);
+}
+
+/* Get the value of h-sys-eear5. */
+
+USI
+or1k32bf_h_sys_eear5_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR5 ();
+}
+
+/* Set a value for h-sys-eear5. */
+
+void
+or1k32bf_h_sys_eear5_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR5 (newval);
+}
+
+/* Get the value of h-sys-eear6. */
+
+USI
+or1k32bf_h_sys_eear6_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR6 ();
+}
+
+/* Set a value for h-sys-eear6. */
+
+void
+or1k32bf_h_sys_eear6_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR6 (newval);
+}
+
+/* Get the value of h-sys-eear7. */
+
+USI
+or1k32bf_h_sys_eear7_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR7 ();
+}
+
+/* Set a value for h-sys-eear7. */
+
+void
+or1k32bf_h_sys_eear7_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR7 (newval);
+}
+
+/* Get the value of h-sys-eear8. */
+
+USI
+or1k32bf_h_sys_eear8_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR8 ();
+}
+
+/* Set a value for h-sys-eear8. */
+
+void
+or1k32bf_h_sys_eear8_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR8 (newval);
+}
+
+/* Get the value of h-sys-eear9. */
+
+USI
+or1k32bf_h_sys_eear9_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR9 ();
+}
+
+/* Set a value for h-sys-eear9. */
+
+void
+or1k32bf_h_sys_eear9_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR9 (newval);
+}
+
+/* Get the value of h-sys-eear10. */
+
+USI
+or1k32bf_h_sys_eear10_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR10 ();
+}
+
+/* Set a value for h-sys-eear10. */
+
+void
+or1k32bf_h_sys_eear10_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR10 (newval);
+}
+
+/* Get the value of h-sys-eear11. */
+
+USI
+or1k32bf_h_sys_eear11_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR11 ();
+}
+
+/* Set a value for h-sys-eear11. */
+
+void
+or1k32bf_h_sys_eear11_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR11 (newval);
+}
+
+/* Get the value of h-sys-eear12. */
+
+USI
+or1k32bf_h_sys_eear12_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR12 ();
+}
+
+/* Set a value for h-sys-eear12. */
+
+void
+or1k32bf_h_sys_eear12_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR12 (newval);
+}
+
+/* Get the value of h-sys-eear13. */
+
+USI
+or1k32bf_h_sys_eear13_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR13 ();
+}
+
+/* Set a value for h-sys-eear13. */
+
+void
+or1k32bf_h_sys_eear13_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR13 (newval);
+}
+
+/* Get the value of h-sys-eear14. */
+
+USI
+or1k32bf_h_sys_eear14_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR14 ();
+}
+
+/* Set a value for h-sys-eear14. */
+
+void
+or1k32bf_h_sys_eear14_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR14 (newval);
+}
+
+/* Get the value of h-sys-eear15. */
+
+USI
+or1k32bf_h_sys_eear15_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_EEAR15 ();
+}
+
+/* Set a value for h-sys-eear15. */
+
+void
+or1k32bf_h_sys_eear15_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_EEAR15 (newval);
+}
+
+/* Get the value of h-sys-esr0. */
+
+USI
+or1k32bf_h_sys_esr0_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR0 ();
+}
+
+/* Set a value for h-sys-esr0. */
+
+void
+or1k32bf_h_sys_esr0_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR0 (newval);
+}
+
+/* Get the value of h-sys-esr1. */
+
+USI
+or1k32bf_h_sys_esr1_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR1 ();
+}
+
+/* Set a value for h-sys-esr1. */
+
+void
+or1k32bf_h_sys_esr1_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR1 (newval);
+}
+
+/* Get the value of h-sys-esr2. */
+
+USI
+or1k32bf_h_sys_esr2_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR2 ();
+}
+
+/* Set a value for h-sys-esr2. */
+
+void
+or1k32bf_h_sys_esr2_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR2 (newval);
+}
+
+/* Get the value of h-sys-esr3. */
+
+USI
+or1k32bf_h_sys_esr3_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR3 ();
+}
+
+/* Set a value for h-sys-esr3. */
+
+void
+or1k32bf_h_sys_esr3_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR3 (newval);
+}
+
+/* Get the value of h-sys-esr4. */
+
+USI
+or1k32bf_h_sys_esr4_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR4 ();
+}
+
+/* Set a value for h-sys-esr4. */
+
+void
+or1k32bf_h_sys_esr4_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR4 (newval);
+}
+
+/* Get the value of h-sys-esr5. */
+
+USI
+or1k32bf_h_sys_esr5_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR5 ();
+}
+
+/* Set a value for h-sys-esr5. */
+
+void
+or1k32bf_h_sys_esr5_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR5 (newval);
+}
+
+/* Get the value of h-sys-esr6. */
+
+USI
+or1k32bf_h_sys_esr6_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR6 ();
+}
+
+/* Set a value for h-sys-esr6. */
+
+void
+or1k32bf_h_sys_esr6_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR6 (newval);
+}
+
+/* Get the value of h-sys-esr7. */
+
+USI
+or1k32bf_h_sys_esr7_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR7 ();
+}
+
+/* Set a value for h-sys-esr7. */
+
+void
+or1k32bf_h_sys_esr7_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR7 (newval);
+}
+
+/* Get the value of h-sys-esr8. */
+
+USI
+or1k32bf_h_sys_esr8_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR8 ();
+}
+
+/* Set a value for h-sys-esr8. */
+
+void
+or1k32bf_h_sys_esr8_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR8 (newval);
+}
+
+/* Get the value of h-sys-esr9. */
+
+USI
+or1k32bf_h_sys_esr9_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR9 ();
+}
+
+/* Set a value for h-sys-esr9. */
+
+void
+or1k32bf_h_sys_esr9_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR9 (newval);
+}
+
+/* Get the value of h-sys-esr10. */
+
+USI
+or1k32bf_h_sys_esr10_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR10 ();
+}
+
+/* Set a value for h-sys-esr10. */
+
+void
+or1k32bf_h_sys_esr10_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR10 (newval);
+}
+
+/* Get the value of h-sys-esr11. */
+
+USI
+or1k32bf_h_sys_esr11_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR11 ();
+}
+
+/* Set a value for h-sys-esr11. */
+
+void
+or1k32bf_h_sys_esr11_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR11 (newval);
+}
+
+/* Get the value of h-sys-esr12. */
+
+USI
+or1k32bf_h_sys_esr12_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR12 ();
+}
+
+/* Set a value for h-sys-esr12. */
+
+void
+or1k32bf_h_sys_esr12_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR12 (newval);
+}
+
+/* Get the value of h-sys-esr13. */
+
+USI
+or1k32bf_h_sys_esr13_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR13 ();
+}
+
+/* Set a value for h-sys-esr13. */
+
+void
+or1k32bf_h_sys_esr13_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR13 (newval);
+}
+
+/* Get the value of h-sys-esr14. */
+
+USI
+or1k32bf_h_sys_esr14_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR14 ();
+}
+
+/* Set a value for h-sys-esr14. */
+
+void
+or1k32bf_h_sys_esr14_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR14 (newval);
+}
+
+/* Get the value of h-sys-esr15. */
+
+USI
+or1k32bf_h_sys_esr15_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_ESR15 ();
+}
+
+/* Set a value for h-sys-esr15. */
+
+void
+or1k32bf_h_sys_esr15_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_ESR15 (newval);
+}
+
+/* Get the value of h-sys-gpr0. */
+
+USI
+or1k32bf_h_sys_gpr0_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR0 ();
+}
+
+/* Set a value for h-sys-gpr0. */
+
+void
+or1k32bf_h_sys_gpr0_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR0 (newval);
+}
+
+/* Get the value of h-sys-gpr1. */
+
+USI
+or1k32bf_h_sys_gpr1_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR1 ();
+}
+
+/* Set a value for h-sys-gpr1. */
+
+void
+or1k32bf_h_sys_gpr1_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR1 (newval);
+}
+
+/* Get the value of h-sys-gpr2. */
+
+USI
+or1k32bf_h_sys_gpr2_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR2 ();
+}
+
+/* Set a value for h-sys-gpr2. */
+
+void
+or1k32bf_h_sys_gpr2_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR2 (newval);
+}
+
+/* Get the value of h-sys-gpr3. */
+
+USI
+or1k32bf_h_sys_gpr3_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR3 ();
+}
+
+/* Set a value for h-sys-gpr3. */
+
+void
+or1k32bf_h_sys_gpr3_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR3 (newval);
+}
+
+/* Get the value of h-sys-gpr4. */
+
+USI
+or1k32bf_h_sys_gpr4_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR4 ();
+}
+
+/* Set a value for h-sys-gpr4. */
+
+void
+or1k32bf_h_sys_gpr4_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR4 (newval);
+}
+
+/* Get the value of h-sys-gpr5. */
+
+USI
+or1k32bf_h_sys_gpr5_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR5 ();
+}
+
+/* Set a value for h-sys-gpr5. */
+
+void
+or1k32bf_h_sys_gpr5_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR5 (newval);
+}
+
+/* Get the value of h-sys-gpr6. */
+
+USI
+or1k32bf_h_sys_gpr6_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR6 ();
+}
+
+/* Set a value for h-sys-gpr6. */
+
+void
+or1k32bf_h_sys_gpr6_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR6 (newval);
+}
+
+/* Get the value of h-sys-gpr7. */
+
+USI
+or1k32bf_h_sys_gpr7_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR7 ();
+}
+
+/* Set a value for h-sys-gpr7. */
+
+void
+or1k32bf_h_sys_gpr7_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR7 (newval);
+}
+
+/* Get the value of h-sys-gpr8. */
+
+USI
+or1k32bf_h_sys_gpr8_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR8 ();
+}
+
+/* Set a value for h-sys-gpr8. */
+
+void
+or1k32bf_h_sys_gpr8_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR8 (newval);
+}
+
+/* Get the value of h-sys-gpr9. */
+
+USI
+or1k32bf_h_sys_gpr9_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR9 ();
+}
+
+/* Set a value for h-sys-gpr9. */
+
+void
+or1k32bf_h_sys_gpr9_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR9 (newval);
+}
+
+/* Get the value of h-sys-gpr10. */
+
+USI
+or1k32bf_h_sys_gpr10_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR10 ();
+}
+
+/* Set a value for h-sys-gpr10. */
+
+void
+or1k32bf_h_sys_gpr10_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR10 (newval);
+}
+
+/* Get the value of h-sys-gpr11. */
+
+USI
+or1k32bf_h_sys_gpr11_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR11 ();
+}
+
+/* Set a value for h-sys-gpr11. */
+
+void
+or1k32bf_h_sys_gpr11_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR11 (newval);
+}
+
+/* Get the value of h-sys-gpr12. */
+
+USI
+or1k32bf_h_sys_gpr12_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR12 ();
+}
+
+/* Set a value for h-sys-gpr12. */
+
+void
+or1k32bf_h_sys_gpr12_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR12 (newval);
+}
+
+/* Get the value of h-sys-gpr13. */
+
+USI
+or1k32bf_h_sys_gpr13_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR13 ();
+}
+
+/* Set a value for h-sys-gpr13. */
+
+void
+or1k32bf_h_sys_gpr13_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR13 (newval);
+}
+
+/* Get the value of h-sys-gpr14. */
+
+USI
+or1k32bf_h_sys_gpr14_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR14 ();
+}
+
+/* Set a value for h-sys-gpr14. */
+
+void
+or1k32bf_h_sys_gpr14_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR14 (newval);
+}
+
+/* Get the value of h-sys-gpr15. */
+
+USI
+or1k32bf_h_sys_gpr15_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR15 ();
+}
+
+/* Set a value for h-sys-gpr15. */
+
+void
+or1k32bf_h_sys_gpr15_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR15 (newval);
+}
+
+/* Get the value of h-sys-gpr16. */
+
+USI
+or1k32bf_h_sys_gpr16_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR16 ();
+}
+
+/* Set a value for h-sys-gpr16. */
+
+void
+or1k32bf_h_sys_gpr16_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR16 (newval);
+}
+
+/* Get the value of h-sys-gpr17. */
+
+USI
+or1k32bf_h_sys_gpr17_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR17 ();
+}
+
+/* Set a value for h-sys-gpr17. */
+
+void
+or1k32bf_h_sys_gpr17_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR17 (newval);
+}
+
+/* Get the value of h-sys-gpr18. */
+
+USI
+or1k32bf_h_sys_gpr18_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR18 ();
+}
+
+/* Set a value for h-sys-gpr18. */
+
+void
+or1k32bf_h_sys_gpr18_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR18 (newval);
+}
+
+/* Get the value of h-sys-gpr19. */
+
+USI
+or1k32bf_h_sys_gpr19_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR19 ();
+}
+
+/* Set a value for h-sys-gpr19. */
+
+void
+or1k32bf_h_sys_gpr19_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR19 (newval);
+}
+
+/* Get the value of h-sys-gpr20. */
+
+USI
+or1k32bf_h_sys_gpr20_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR20 ();
+}
+
+/* Set a value for h-sys-gpr20. */
+
+void
+or1k32bf_h_sys_gpr20_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR20 (newval);
+}
+
+/* Get the value of h-sys-gpr21. */
+
+USI
+or1k32bf_h_sys_gpr21_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR21 ();
+}
+
+/* Set a value for h-sys-gpr21. */
+
+void
+or1k32bf_h_sys_gpr21_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR21 (newval);
+}
+
+/* Get the value of h-sys-gpr22. */
+
+USI
+or1k32bf_h_sys_gpr22_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR22 ();
+}
+
+/* Set a value for h-sys-gpr22. */
+
+void
+or1k32bf_h_sys_gpr22_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR22 (newval);
+}
+
+/* Get the value of h-sys-gpr23. */
+
+USI
+or1k32bf_h_sys_gpr23_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR23 ();
+}
+
+/* Set a value for h-sys-gpr23. */
+
+void
+or1k32bf_h_sys_gpr23_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR23 (newval);
+}
+
+/* Get the value of h-sys-gpr24. */
+
+USI
+or1k32bf_h_sys_gpr24_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR24 ();
+}
+
+/* Set a value for h-sys-gpr24. */
+
+void
+or1k32bf_h_sys_gpr24_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR24 (newval);
+}
+
+/* Get the value of h-sys-gpr25. */
+
+USI
+or1k32bf_h_sys_gpr25_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR25 ();
+}
+
+/* Set a value for h-sys-gpr25. */
+
+void
+or1k32bf_h_sys_gpr25_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR25 (newval);
+}
+
+/* Get the value of h-sys-gpr26. */
+
+USI
+or1k32bf_h_sys_gpr26_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR26 ();
+}
+
+/* Set a value for h-sys-gpr26. */
+
+void
+or1k32bf_h_sys_gpr26_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR26 (newval);
+}
+
+/* Get the value of h-sys-gpr27. */
+
+USI
+or1k32bf_h_sys_gpr27_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR27 ();
+}
+
+/* Set a value for h-sys-gpr27. */
+
+void
+or1k32bf_h_sys_gpr27_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR27 (newval);
+}
+
+/* Get the value of h-sys-gpr28. */
+
+USI
+or1k32bf_h_sys_gpr28_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR28 ();
+}
+
+/* Set a value for h-sys-gpr28. */
+
+void
+or1k32bf_h_sys_gpr28_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR28 (newval);
+}
+
+/* Get the value of h-sys-gpr29. */
+
+USI
+or1k32bf_h_sys_gpr29_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR29 ();
+}
+
+/* Set a value for h-sys-gpr29. */
+
+void
+or1k32bf_h_sys_gpr29_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR29 (newval);
+}
+
+/* Get the value of h-sys-gpr30. */
+
+USI
+or1k32bf_h_sys_gpr30_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR30 ();
+}
+
+/* Set a value for h-sys-gpr30. */
+
+void
+or1k32bf_h_sys_gpr30_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR30 (newval);
+}
+
+/* Get the value of h-sys-gpr31. */
+
+USI
+or1k32bf_h_sys_gpr31_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR31 ();
+}
+
+/* Set a value for h-sys-gpr31. */
+
+void
+or1k32bf_h_sys_gpr31_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR31 (newval);
+}
+
+/* Get the value of h-sys-gpr32. */
+
+USI
+or1k32bf_h_sys_gpr32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR32 ();
+}
+
+/* Set a value for h-sys-gpr32. */
+
+void
+or1k32bf_h_sys_gpr32_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR32 (newval);
+}
+
+/* Get the value of h-sys-gpr33. */
+
+USI
+or1k32bf_h_sys_gpr33_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR33 ();
+}
+
+/* Set a value for h-sys-gpr33. */
+
+void
+or1k32bf_h_sys_gpr33_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR33 (newval);
+}
+
+/* Get the value of h-sys-gpr34. */
+
+USI
+or1k32bf_h_sys_gpr34_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR34 ();
+}
+
+/* Set a value for h-sys-gpr34. */
+
+void
+or1k32bf_h_sys_gpr34_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR34 (newval);
+}
+
+/* Get the value of h-sys-gpr35. */
+
+USI
+or1k32bf_h_sys_gpr35_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR35 ();
+}
+
+/* Set a value for h-sys-gpr35. */
+
+void
+or1k32bf_h_sys_gpr35_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR35 (newval);
+}
+
+/* Get the value of h-sys-gpr36. */
+
+USI
+or1k32bf_h_sys_gpr36_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR36 ();
+}
+
+/* Set a value for h-sys-gpr36. */
+
+void
+or1k32bf_h_sys_gpr36_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR36 (newval);
+}
+
+/* Get the value of h-sys-gpr37. */
+
+USI
+or1k32bf_h_sys_gpr37_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR37 ();
+}
+
+/* Set a value for h-sys-gpr37. */
+
+void
+or1k32bf_h_sys_gpr37_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR37 (newval);
+}
+
+/* Get the value of h-sys-gpr38. */
+
+USI
+or1k32bf_h_sys_gpr38_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR38 ();
+}
+
+/* Set a value for h-sys-gpr38. */
+
+void
+or1k32bf_h_sys_gpr38_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR38 (newval);
+}
+
+/* Get the value of h-sys-gpr39. */
+
+USI
+or1k32bf_h_sys_gpr39_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR39 ();
+}
+
+/* Set a value for h-sys-gpr39. */
+
+void
+or1k32bf_h_sys_gpr39_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR39 (newval);
+}
+
+/* Get the value of h-sys-gpr40. */
+
+USI
+or1k32bf_h_sys_gpr40_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR40 ();
+}
+
+/* Set a value for h-sys-gpr40. */
+
+void
+or1k32bf_h_sys_gpr40_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR40 (newval);
+}
+
+/* Get the value of h-sys-gpr41. */
+
+USI
+or1k32bf_h_sys_gpr41_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR41 ();
+}
+
+/* Set a value for h-sys-gpr41. */
+
+void
+or1k32bf_h_sys_gpr41_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR41 (newval);
+}
+
+/* Get the value of h-sys-gpr42. */
+
+USI
+or1k32bf_h_sys_gpr42_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR42 ();
+}
+
+/* Set a value for h-sys-gpr42. */
+
+void
+or1k32bf_h_sys_gpr42_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR42 (newval);
+}
+
+/* Get the value of h-sys-gpr43. */
+
+USI
+or1k32bf_h_sys_gpr43_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR43 ();
+}
+
+/* Set a value for h-sys-gpr43. */
+
+void
+or1k32bf_h_sys_gpr43_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR43 (newval);
+}
+
+/* Get the value of h-sys-gpr44. */
+
+USI
+or1k32bf_h_sys_gpr44_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR44 ();
+}
+
+/* Set a value for h-sys-gpr44. */
+
+void
+or1k32bf_h_sys_gpr44_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR44 (newval);
+}
+
+/* Get the value of h-sys-gpr45. */
+
+USI
+or1k32bf_h_sys_gpr45_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR45 ();
+}
+
+/* Set a value for h-sys-gpr45. */
+
+void
+or1k32bf_h_sys_gpr45_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR45 (newval);
+}
+
+/* Get the value of h-sys-gpr46. */
+
+USI
+or1k32bf_h_sys_gpr46_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR46 ();
+}
+
+/* Set a value for h-sys-gpr46. */
+
+void
+or1k32bf_h_sys_gpr46_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR46 (newval);
+}
+
+/* Get the value of h-sys-gpr47. */
+
+USI
+or1k32bf_h_sys_gpr47_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR47 ();
+}
+
+/* Set a value for h-sys-gpr47. */
+
+void
+or1k32bf_h_sys_gpr47_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR47 (newval);
+}
+
+/* Get the value of h-sys-gpr48. */
+
+USI
+or1k32bf_h_sys_gpr48_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR48 ();
+}
+
+/* Set a value for h-sys-gpr48. */
+
+void
+or1k32bf_h_sys_gpr48_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR48 (newval);
+}
+
+/* Get the value of h-sys-gpr49. */
+
+USI
+or1k32bf_h_sys_gpr49_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR49 ();
+}
+
+/* Set a value for h-sys-gpr49. */
+
+void
+or1k32bf_h_sys_gpr49_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR49 (newval);
+}
+
+/* Get the value of h-sys-gpr50. */
+
+USI
+or1k32bf_h_sys_gpr50_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR50 ();
+}
+
+/* Set a value for h-sys-gpr50. */
+
+void
+or1k32bf_h_sys_gpr50_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR50 (newval);
+}
+
+/* Get the value of h-sys-gpr51. */
+
+USI
+or1k32bf_h_sys_gpr51_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR51 ();
+}
+
+/* Set a value for h-sys-gpr51. */
+
+void
+or1k32bf_h_sys_gpr51_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR51 (newval);
+}
+
+/* Get the value of h-sys-gpr52. */
+
+USI
+or1k32bf_h_sys_gpr52_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR52 ();
+}
+
+/* Set a value for h-sys-gpr52. */
+
+void
+or1k32bf_h_sys_gpr52_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR52 (newval);
+}
+
+/* Get the value of h-sys-gpr53. */
+
+USI
+or1k32bf_h_sys_gpr53_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR53 ();
+}
+
+/* Set a value for h-sys-gpr53. */
+
+void
+or1k32bf_h_sys_gpr53_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR53 (newval);
+}
+
+/* Get the value of h-sys-gpr54. */
+
+USI
+or1k32bf_h_sys_gpr54_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR54 ();
+}
+
+/* Set a value for h-sys-gpr54. */
+
+void
+or1k32bf_h_sys_gpr54_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR54 (newval);
+}
+
+/* Get the value of h-sys-gpr55. */
+
+USI
+or1k32bf_h_sys_gpr55_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR55 ();
+}
+
+/* Set a value for h-sys-gpr55. */
+
+void
+or1k32bf_h_sys_gpr55_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR55 (newval);
+}
+
+/* Get the value of h-sys-gpr56. */
+
+USI
+or1k32bf_h_sys_gpr56_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR56 ();
+}
+
+/* Set a value for h-sys-gpr56. */
+
+void
+or1k32bf_h_sys_gpr56_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR56 (newval);
+}
+
+/* Get the value of h-sys-gpr57. */
+
+USI
+or1k32bf_h_sys_gpr57_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR57 ();
+}
+
+/* Set a value for h-sys-gpr57. */
+
+void
+or1k32bf_h_sys_gpr57_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR57 (newval);
+}
+
+/* Get the value of h-sys-gpr58. */
+
+USI
+or1k32bf_h_sys_gpr58_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR58 ();
+}
+
+/* Set a value for h-sys-gpr58. */
+
+void
+or1k32bf_h_sys_gpr58_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR58 (newval);
+}
+
+/* Get the value of h-sys-gpr59. */
+
+USI
+or1k32bf_h_sys_gpr59_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR59 ();
+}
+
+/* Set a value for h-sys-gpr59. */
+
+void
+or1k32bf_h_sys_gpr59_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR59 (newval);
+}
+
+/* Get the value of h-sys-gpr60. */
+
+USI
+or1k32bf_h_sys_gpr60_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR60 ();
+}
+
+/* Set a value for h-sys-gpr60. */
+
+void
+or1k32bf_h_sys_gpr60_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR60 (newval);
+}
+
+/* Get the value of h-sys-gpr61. */
+
+USI
+or1k32bf_h_sys_gpr61_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR61 ();
+}
+
+/* Set a value for h-sys-gpr61. */
+
+void
+or1k32bf_h_sys_gpr61_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR61 (newval);
+}
+
+/* Get the value of h-sys-gpr62. */
+
+USI
+or1k32bf_h_sys_gpr62_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR62 ();
+}
+
+/* Set a value for h-sys-gpr62. */
+
+void
+or1k32bf_h_sys_gpr62_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR62 (newval);
+}
+
+/* Get the value of h-sys-gpr63. */
+
+USI
+or1k32bf_h_sys_gpr63_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR63 ();
+}
+
+/* Set a value for h-sys-gpr63. */
+
+void
+or1k32bf_h_sys_gpr63_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR63 (newval);
+}
+
+/* Get the value of h-sys-gpr64. */
+
+USI
+or1k32bf_h_sys_gpr64_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR64 ();
+}
+
+/* Set a value for h-sys-gpr64. */
+
+void
+or1k32bf_h_sys_gpr64_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR64 (newval);
+}
+
+/* Get the value of h-sys-gpr65. */
+
+USI
+or1k32bf_h_sys_gpr65_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR65 ();
+}
+
+/* Set a value for h-sys-gpr65. */
+
+void
+or1k32bf_h_sys_gpr65_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR65 (newval);
+}
+
+/* Get the value of h-sys-gpr66. */
+
+USI
+or1k32bf_h_sys_gpr66_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR66 ();
+}
+
+/* Set a value for h-sys-gpr66. */
+
+void
+or1k32bf_h_sys_gpr66_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR66 (newval);
+}
+
+/* Get the value of h-sys-gpr67. */
+
+USI
+or1k32bf_h_sys_gpr67_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR67 ();
+}
+
+/* Set a value for h-sys-gpr67. */
+
+void
+or1k32bf_h_sys_gpr67_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR67 (newval);
+}
+
+/* Get the value of h-sys-gpr68. */
+
+USI
+or1k32bf_h_sys_gpr68_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR68 ();
+}
+
+/* Set a value for h-sys-gpr68. */
+
+void
+or1k32bf_h_sys_gpr68_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR68 (newval);
+}
+
+/* Get the value of h-sys-gpr69. */
+
+USI
+or1k32bf_h_sys_gpr69_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR69 ();
+}
+
+/* Set a value for h-sys-gpr69. */
+
+void
+or1k32bf_h_sys_gpr69_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR69 (newval);
+}
+
+/* Get the value of h-sys-gpr70. */
+
+USI
+or1k32bf_h_sys_gpr70_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR70 ();
+}
+
+/* Set a value for h-sys-gpr70. */
+
+void
+or1k32bf_h_sys_gpr70_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR70 (newval);
+}
+
+/* Get the value of h-sys-gpr71. */
+
+USI
+or1k32bf_h_sys_gpr71_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR71 ();
+}
+
+/* Set a value for h-sys-gpr71. */
+
+void
+or1k32bf_h_sys_gpr71_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR71 (newval);
+}
+
+/* Get the value of h-sys-gpr72. */
+
+USI
+or1k32bf_h_sys_gpr72_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR72 ();
+}
+
+/* Set a value for h-sys-gpr72. */
+
+void
+or1k32bf_h_sys_gpr72_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR72 (newval);
+}
+
+/* Get the value of h-sys-gpr73. */
+
+USI
+or1k32bf_h_sys_gpr73_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR73 ();
+}
+
+/* Set a value for h-sys-gpr73. */
+
+void
+or1k32bf_h_sys_gpr73_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR73 (newval);
+}
+
+/* Get the value of h-sys-gpr74. */
+
+USI
+or1k32bf_h_sys_gpr74_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR74 ();
+}
+
+/* Set a value for h-sys-gpr74. */
+
+void
+or1k32bf_h_sys_gpr74_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR74 (newval);
+}
+
+/* Get the value of h-sys-gpr75. */
+
+USI
+or1k32bf_h_sys_gpr75_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR75 ();
+}
+
+/* Set a value for h-sys-gpr75. */
+
+void
+or1k32bf_h_sys_gpr75_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR75 (newval);
+}
+
+/* Get the value of h-sys-gpr76. */
+
+USI
+or1k32bf_h_sys_gpr76_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR76 ();
+}
+
+/* Set a value for h-sys-gpr76. */
+
+void
+or1k32bf_h_sys_gpr76_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR76 (newval);
+}
+
+/* Get the value of h-sys-gpr77. */
+
+USI
+or1k32bf_h_sys_gpr77_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR77 ();
+}
+
+/* Set a value for h-sys-gpr77. */
+
+void
+or1k32bf_h_sys_gpr77_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR77 (newval);
+}
+
+/* Get the value of h-sys-gpr78. */
+
+USI
+or1k32bf_h_sys_gpr78_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR78 ();
+}
+
+/* Set a value for h-sys-gpr78. */
+
+void
+or1k32bf_h_sys_gpr78_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR78 (newval);
+}
+
+/* Get the value of h-sys-gpr79. */
+
+USI
+or1k32bf_h_sys_gpr79_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR79 ();
+}
+
+/* Set a value for h-sys-gpr79. */
+
+void
+or1k32bf_h_sys_gpr79_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR79 (newval);
+}
+
+/* Get the value of h-sys-gpr80. */
+
+USI
+or1k32bf_h_sys_gpr80_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR80 ();
+}
+
+/* Set a value for h-sys-gpr80. */
+
+void
+or1k32bf_h_sys_gpr80_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR80 (newval);
+}
+
+/* Get the value of h-sys-gpr81. */
+
+USI
+or1k32bf_h_sys_gpr81_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR81 ();
+}
+
+/* Set a value for h-sys-gpr81. */
+
+void
+or1k32bf_h_sys_gpr81_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR81 (newval);
+}
+
+/* Get the value of h-sys-gpr82. */
+
+USI
+or1k32bf_h_sys_gpr82_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR82 ();
+}
+
+/* Set a value for h-sys-gpr82. */
+
+void
+or1k32bf_h_sys_gpr82_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR82 (newval);
+}
+
+/* Get the value of h-sys-gpr83. */
+
+USI
+or1k32bf_h_sys_gpr83_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR83 ();
+}
+
+/* Set a value for h-sys-gpr83. */
+
+void
+or1k32bf_h_sys_gpr83_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR83 (newval);
+}
+
+/* Get the value of h-sys-gpr84. */
+
+USI
+or1k32bf_h_sys_gpr84_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR84 ();
+}
+
+/* Set a value for h-sys-gpr84. */
+
+void
+or1k32bf_h_sys_gpr84_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR84 (newval);
+}
+
+/* Get the value of h-sys-gpr85. */
+
+USI
+or1k32bf_h_sys_gpr85_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR85 ();
+}
+
+/* Set a value for h-sys-gpr85. */
+
+void
+or1k32bf_h_sys_gpr85_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR85 (newval);
+}
+
+/* Get the value of h-sys-gpr86. */
+
+USI
+or1k32bf_h_sys_gpr86_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR86 ();
+}
+
+/* Set a value for h-sys-gpr86. */
+
+void
+or1k32bf_h_sys_gpr86_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR86 (newval);
+}
+
+/* Get the value of h-sys-gpr87. */
+
+USI
+or1k32bf_h_sys_gpr87_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR87 ();
+}
+
+/* Set a value for h-sys-gpr87. */
+
+void
+or1k32bf_h_sys_gpr87_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR87 (newval);
+}
+
+/* Get the value of h-sys-gpr88. */
+
+USI
+or1k32bf_h_sys_gpr88_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR88 ();
+}
+
+/* Set a value for h-sys-gpr88. */
+
+void
+or1k32bf_h_sys_gpr88_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR88 (newval);
+}
+
+/* Get the value of h-sys-gpr89. */
+
+USI
+or1k32bf_h_sys_gpr89_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR89 ();
+}
+
+/* Set a value for h-sys-gpr89. */
+
+void
+or1k32bf_h_sys_gpr89_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR89 (newval);
+}
+
+/* Get the value of h-sys-gpr90. */
+
+USI
+or1k32bf_h_sys_gpr90_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR90 ();
+}
+
+/* Set a value for h-sys-gpr90. */
+
+void
+or1k32bf_h_sys_gpr90_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR90 (newval);
+}
+
+/* Get the value of h-sys-gpr91. */
+
+USI
+or1k32bf_h_sys_gpr91_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR91 ();
+}
+
+/* Set a value for h-sys-gpr91. */
+
+void
+or1k32bf_h_sys_gpr91_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR91 (newval);
+}
+
+/* Get the value of h-sys-gpr92. */
+
+USI
+or1k32bf_h_sys_gpr92_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR92 ();
+}
+
+/* Set a value for h-sys-gpr92. */
+
+void
+or1k32bf_h_sys_gpr92_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR92 (newval);
+}
+
+/* Get the value of h-sys-gpr93. */
+
+USI
+or1k32bf_h_sys_gpr93_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR93 ();
+}
+
+/* Set a value for h-sys-gpr93. */
+
+void
+or1k32bf_h_sys_gpr93_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR93 (newval);
+}
+
+/* Get the value of h-sys-gpr94. */
+
+USI
+or1k32bf_h_sys_gpr94_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR94 ();
+}
+
+/* Set a value for h-sys-gpr94. */
+
+void
+or1k32bf_h_sys_gpr94_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR94 (newval);
+}
+
+/* Get the value of h-sys-gpr95. */
+
+USI
+or1k32bf_h_sys_gpr95_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR95 ();
+}
+
+/* Set a value for h-sys-gpr95. */
+
+void
+or1k32bf_h_sys_gpr95_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR95 (newval);
+}
+
+/* Get the value of h-sys-gpr96. */
+
+USI
+or1k32bf_h_sys_gpr96_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR96 ();
+}
+
+/* Set a value for h-sys-gpr96. */
+
+void
+or1k32bf_h_sys_gpr96_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR96 (newval);
+}
+
+/* Get the value of h-sys-gpr97. */
+
+USI
+or1k32bf_h_sys_gpr97_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR97 ();
+}
+
+/* Set a value for h-sys-gpr97. */
+
+void
+or1k32bf_h_sys_gpr97_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR97 (newval);
+}
+
+/* Get the value of h-sys-gpr98. */
+
+USI
+or1k32bf_h_sys_gpr98_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR98 ();
+}
+
+/* Set a value for h-sys-gpr98. */
+
+void
+or1k32bf_h_sys_gpr98_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR98 (newval);
+}
+
+/* Get the value of h-sys-gpr99. */
+
+USI
+or1k32bf_h_sys_gpr99_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR99 ();
+}
+
+/* Set a value for h-sys-gpr99. */
+
+void
+or1k32bf_h_sys_gpr99_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR99 (newval);
+}
+
+/* Get the value of h-sys-gpr100. */
+
+USI
+or1k32bf_h_sys_gpr100_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR100 ();
+}
+
+/* Set a value for h-sys-gpr100. */
+
+void
+or1k32bf_h_sys_gpr100_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR100 (newval);
+}
+
+/* Get the value of h-sys-gpr101. */
+
+USI
+or1k32bf_h_sys_gpr101_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR101 ();
+}
+
+/* Set a value for h-sys-gpr101. */
+
+void
+or1k32bf_h_sys_gpr101_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR101 (newval);
+}
+
+/* Get the value of h-sys-gpr102. */
+
+USI
+or1k32bf_h_sys_gpr102_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR102 ();
+}
+
+/* Set a value for h-sys-gpr102. */
+
+void
+or1k32bf_h_sys_gpr102_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR102 (newval);
+}
+
+/* Get the value of h-sys-gpr103. */
+
+USI
+or1k32bf_h_sys_gpr103_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR103 ();
+}
+
+/* Set a value for h-sys-gpr103. */
+
+void
+or1k32bf_h_sys_gpr103_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR103 (newval);
+}
+
+/* Get the value of h-sys-gpr104. */
+
+USI
+or1k32bf_h_sys_gpr104_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR104 ();
+}
+
+/* Set a value for h-sys-gpr104. */
+
+void
+or1k32bf_h_sys_gpr104_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR104 (newval);
+}
+
+/* Get the value of h-sys-gpr105. */
+
+USI
+or1k32bf_h_sys_gpr105_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR105 ();
+}
+
+/* Set a value for h-sys-gpr105. */
+
+void
+or1k32bf_h_sys_gpr105_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR105 (newval);
+}
+
+/* Get the value of h-sys-gpr106. */
+
+USI
+or1k32bf_h_sys_gpr106_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR106 ();
+}
+
+/* Set a value for h-sys-gpr106. */
+
+void
+or1k32bf_h_sys_gpr106_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR106 (newval);
+}
+
+/* Get the value of h-sys-gpr107. */
+
+USI
+or1k32bf_h_sys_gpr107_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR107 ();
+}
+
+/* Set a value for h-sys-gpr107. */
+
+void
+or1k32bf_h_sys_gpr107_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR107 (newval);
+}
+
+/* Get the value of h-sys-gpr108. */
+
+USI
+or1k32bf_h_sys_gpr108_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR108 ();
+}
+
+/* Set a value for h-sys-gpr108. */
+
+void
+or1k32bf_h_sys_gpr108_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR108 (newval);
+}
+
+/* Get the value of h-sys-gpr109. */
+
+USI
+or1k32bf_h_sys_gpr109_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR109 ();
+}
+
+/* Set a value for h-sys-gpr109. */
+
+void
+or1k32bf_h_sys_gpr109_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR109 (newval);
+}
+
+/* Get the value of h-sys-gpr110. */
+
+USI
+or1k32bf_h_sys_gpr110_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR110 ();
+}
+
+/* Set a value for h-sys-gpr110. */
+
+void
+or1k32bf_h_sys_gpr110_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR110 (newval);
+}
+
+/* Get the value of h-sys-gpr111. */
+
+USI
+or1k32bf_h_sys_gpr111_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR111 ();
+}
+
+/* Set a value for h-sys-gpr111. */
+
+void
+or1k32bf_h_sys_gpr111_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR111 (newval);
+}
+
+/* Get the value of h-sys-gpr112. */
+
+USI
+or1k32bf_h_sys_gpr112_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR112 ();
+}
+
+/* Set a value for h-sys-gpr112. */
+
+void
+or1k32bf_h_sys_gpr112_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR112 (newval);
+}
+
+/* Get the value of h-sys-gpr113. */
+
+USI
+or1k32bf_h_sys_gpr113_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR113 ();
+}
+
+/* Set a value for h-sys-gpr113. */
+
+void
+or1k32bf_h_sys_gpr113_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR113 (newval);
+}
+
+/* Get the value of h-sys-gpr114. */
+
+USI
+or1k32bf_h_sys_gpr114_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR114 ();
+}
+
+/* Set a value for h-sys-gpr114. */
+
+void
+or1k32bf_h_sys_gpr114_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR114 (newval);
+}
+
+/* Get the value of h-sys-gpr115. */
+
+USI
+or1k32bf_h_sys_gpr115_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR115 ();
+}
+
+/* Set a value for h-sys-gpr115. */
+
+void
+or1k32bf_h_sys_gpr115_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR115 (newval);
+}
+
+/* Get the value of h-sys-gpr116. */
+
+USI
+or1k32bf_h_sys_gpr116_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR116 ();
+}
+
+/* Set a value for h-sys-gpr116. */
+
+void
+or1k32bf_h_sys_gpr116_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR116 (newval);
+}
+
+/* Get the value of h-sys-gpr117. */
+
+USI
+or1k32bf_h_sys_gpr117_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR117 ();
+}
+
+/* Set a value for h-sys-gpr117. */
+
+void
+or1k32bf_h_sys_gpr117_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR117 (newval);
+}
+
+/* Get the value of h-sys-gpr118. */
+
+USI
+or1k32bf_h_sys_gpr118_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR118 ();
+}
+
+/* Set a value for h-sys-gpr118. */
+
+void
+or1k32bf_h_sys_gpr118_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR118 (newval);
+}
+
+/* Get the value of h-sys-gpr119. */
+
+USI
+or1k32bf_h_sys_gpr119_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR119 ();
+}
+
+/* Set a value for h-sys-gpr119. */
+
+void
+or1k32bf_h_sys_gpr119_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR119 (newval);
+}
+
+/* Get the value of h-sys-gpr120. */
+
+USI
+or1k32bf_h_sys_gpr120_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR120 ();
+}
+
+/* Set a value for h-sys-gpr120. */
+
+void
+or1k32bf_h_sys_gpr120_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR120 (newval);
+}
+
+/* Get the value of h-sys-gpr121. */
+
+USI
+or1k32bf_h_sys_gpr121_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR121 ();
+}
+
+/* Set a value for h-sys-gpr121. */
+
+void
+or1k32bf_h_sys_gpr121_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR121 (newval);
+}
+
+/* Get the value of h-sys-gpr122. */
+
+USI
+or1k32bf_h_sys_gpr122_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR122 ();
+}
+
+/* Set a value for h-sys-gpr122. */
+
+void
+or1k32bf_h_sys_gpr122_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR122 (newval);
+}
+
+/* Get the value of h-sys-gpr123. */
+
+USI
+or1k32bf_h_sys_gpr123_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR123 ();
+}
+
+/* Set a value for h-sys-gpr123. */
+
+void
+or1k32bf_h_sys_gpr123_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR123 (newval);
+}
+
+/* Get the value of h-sys-gpr124. */
+
+USI
+or1k32bf_h_sys_gpr124_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR124 ();
+}
+
+/* Set a value for h-sys-gpr124. */
+
+void
+or1k32bf_h_sys_gpr124_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR124 (newval);
+}
+
+/* Get the value of h-sys-gpr125. */
+
+USI
+or1k32bf_h_sys_gpr125_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR125 ();
+}
+
+/* Set a value for h-sys-gpr125. */
+
+void
+or1k32bf_h_sys_gpr125_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR125 (newval);
+}
+
+/* Get the value of h-sys-gpr126. */
+
+USI
+or1k32bf_h_sys_gpr126_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR126 ();
+}
+
+/* Set a value for h-sys-gpr126. */
+
+void
+or1k32bf_h_sys_gpr126_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR126 (newval);
+}
+
+/* Get the value of h-sys-gpr127. */
+
+USI
+or1k32bf_h_sys_gpr127_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR127 ();
+}
+
+/* Set a value for h-sys-gpr127. */
+
+void
+or1k32bf_h_sys_gpr127_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR127 (newval);
+}
+
+/* Get the value of h-sys-gpr128. */
+
+USI
+or1k32bf_h_sys_gpr128_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR128 ();
+}
+
+/* Set a value for h-sys-gpr128. */
+
+void
+or1k32bf_h_sys_gpr128_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR128 (newval);
+}
+
+/* Get the value of h-sys-gpr129. */
+
+USI
+or1k32bf_h_sys_gpr129_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR129 ();
+}
+
+/* Set a value for h-sys-gpr129. */
+
+void
+or1k32bf_h_sys_gpr129_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR129 (newval);
+}
+
+/* Get the value of h-sys-gpr130. */
+
+USI
+or1k32bf_h_sys_gpr130_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR130 ();
+}
+
+/* Set a value for h-sys-gpr130. */
+
+void
+or1k32bf_h_sys_gpr130_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR130 (newval);
+}
+
+/* Get the value of h-sys-gpr131. */
+
+USI
+or1k32bf_h_sys_gpr131_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR131 ();
+}
+
+/* Set a value for h-sys-gpr131. */
+
+void
+or1k32bf_h_sys_gpr131_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR131 (newval);
+}
+
+/* Get the value of h-sys-gpr132. */
+
+USI
+or1k32bf_h_sys_gpr132_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR132 ();
+}
+
+/* Set a value for h-sys-gpr132. */
+
+void
+or1k32bf_h_sys_gpr132_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR132 (newval);
+}
+
+/* Get the value of h-sys-gpr133. */
+
+USI
+or1k32bf_h_sys_gpr133_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR133 ();
+}
+
+/* Set a value for h-sys-gpr133. */
+
+void
+or1k32bf_h_sys_gpr133_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR133 (newval);
+}
+
+/* Get the value of h-sys-gpr134. */
+
+USI
+or1k32bf_h_sys_gpr134_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR134 ();
+}
+
+/* Set a value for h-sys-gpr134. */
+
+void
+or1k32bf_h_sys_gpr134_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR134 (newval);
+}
+
+/* Get the value of h-sys-gpr135. */
+
+USI
+or1k32bf_h_sys_gpr135_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR135 ();
+}
+
+/* Set a value for h-sys-gpr135. */
+
+void
+or1k32bf_h_sys_gpr135_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR135 (newval);
+}
+
+/* Get the value of h-sys-gpr136. */
+
+USI
+or1k32bf_h_sys_gpr136_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR136 ();
+}
+
+/* Set a value for h-sys-gpr136. */
+
+void
+or1k32bf_h_sys_gpr136_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR136 (newval);
+}
+
+/* Get the value of h-sys-gpr137. */
+
+USI
+or1k32bf_h_sys_gpr137_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR137 ();
+}
+
+/* Set a value for h-sys-gpr137. */
+
+void
+or1k32bf_h_sys_gpr137_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR137 (newval);
+}
+
+/* Get the value of h-sys-gpr138. */
+
+USI
+or1k32bf_h_sys_gpr138_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR138 ();
+}
+
+/* Set a value for h-sys-gpr138. */
+
+void
+or1k32bf_h_sys_gpr138_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR138 (newval);
+}
+
+/* Get the value of h-sys-gpr139. */
+
+USI
+or1k32bf_h_sys_gpr139_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR139 ();
+}
+
+/* Set a value for h-sys-gpr139. */
+
+void
+or1k32bf_h_sys_gpr139_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR139 (newval);
+}
+
+/* Get the value of h-sys-gpr140. */
+
+USI
+or1k32bf_h_sys_gpr140_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR140 ();
+}
+
+/* Set a value for h-sys-gpr140. */
+
+void
+or1k32bf_h_sys_gpr140_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR140 (newval);
+}
+
+/* Get the value of h-sys-gpr141. */
+
+USI
+or1k32bf_h_sys_gpr141_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR141 ();
+}
+
+/* Set a value for h-sys-gpr141. */
+
+void
+or1k32bf_h_sys_gpr141_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR141 (newval);
+}
+
+/* Get the value of h-sys-gpr142. */
+
+USI
+or1k32bf_h_sys_gpr142_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR142 ();
+}
+
+/* Set a value for h-sys-gpr142. */
+
+void
+or1k32bf_h_sys_gpr142_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR142 (newval);
+}
+
+/* Get the value of h-sys-gpr143. */
+
+USI
+or1k32bf_h_sys_gpr143_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR143 ();
+}
+
+/* Set a value for h-sys-gpr143. */
+
+void
+or1k32bf_h_sys_gpr143_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR143 (newval);
+}
+
+/* Get the value of h-sys-gpr144. */
+
+USI
+or1k32bf_h_sys_gpr144_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR144 ();
+}
+
+/* Set a value for h-sys-gpr144. */
+
+void
+or1k32bf_h_sys_gpr144_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR144 (newval);
+}
+
+/* Get the value of h-sys-gpr145. */
+
+USI
+or1k32bf_h_sys_gpr145_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR145 ();
+}
+
+/* Set a value for h-sys-gpr145. */
+
+void
+or1k32bf_h_sys_gpr145_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR145 (newval);
+}
+
+/* Get the value of h-sys-gpr146. */
+
+USI
+or1k32bf_h_sys_gpr146_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR146 ();
+}
+
+/* Set a value for h-sys-gpr146. */
+
+void
+or1k32bf_h_sys_gpr146_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR146 (newval);
+}
+
+/* Get the value of h-sys-gpr147. */
+
+USI
+or1k32bf_h_sys_gpr147_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR147 ();
+}
+
+/* Set a value for h-sys-gpr147. */
+
+void
+or1k32bf_h_sys_gpr147_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR147 (newval);
+}
+
+/* Get the value of h-sys-gpr148. */
+
+USI
+or1k32bf_h_sys_gpr148_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR148 ();
+}
+
+/* Set a value for h-sys-gpr148. */
+
+void
+or1k32bf_h_sys_gpr148_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR148 (newval);
+}
+
+/* Get the value of h-sys-gpr149. */
+
+USI
+or1k32bf_h_sys_gpr149_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR149 ();
+}
+
+/* Set a value for h-sys-gpr149. */
+
+void
+or1k32bf_h_sys_gpr149_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR149 (newval);
+}
+
+/* Get the value of h-sys-gpr150. */
+
+USI
+or1k32bf_h_sys_gpr150_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR150 ();
+}
+
+/* Set a value for h-sys-gpr150. */
+
+void
+or1k32bf_h_sys_gpr150_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR150 (newval);
+}
+
+/* Get the value of h-sys-gpr151. */
+
+USI
+or1k32bf_h_sys_gpr151_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR151 ();
+}
+
+/* Set a value for h-sys-gpr151. */
+
+void
+or1k32bf_h_sys_gpr151_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR151 (newval);
+}
+
+/* Get the value of h-sys-gpr152. */
+
+USI
+or1k32bf_h_sys_gpr152_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR152 ();
+}
+
+/* Set a value for h-sys-gpr152. */
+
+void
+or1k32bf_h_sys_gpr152_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR152 (newval);
+}
+
+/* Get the value of h-sys-gpr153. */
+
+USI
+or1k32bf_h_sys_gpr153_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR153 ();
+}
+
+/* Set a value for h-sys-gpr153. */
+
+void
+or1k32bf_h_sys_gpr153_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR153 (newval);
+}
+
+/* Get the value of h-sys-gpr154. */
+
+USI
+or1k32bf_h_sys_gpr154_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR154 ();
+}
+
+/* Set a value for h-sys-gpr154. */
+
+void
+or1k32bf_h_sys_gpr154_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR154 (newval);
+}
+
+/* Get the value of h-sys-gpr155. */
+
+USI
+or1k32bf_h_sys_gpr155_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR155 ();
+}
+
+/* Set a value for h-sys-gpr155. */
+
+void
+or1k32bf_h_sys_gpr155_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR155 (newval);
+}
+
+/* Get the value of h-sys-gpr156. */
+
+USI
+or1k32bf_h_sys_gpr156_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR156 ();
+}
+
+/* Set a value for h-sys-gpr156. */
+
+void
+or1k32bf_h_sys_gpr156_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR156 (newval);
+}
+
+/* Get the value of h-sys-gpr157. */
+
+USI
+or1k32bf_h_sys_gpr157_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR157 ();
+}
+
+/* Set a value for h-sys-gpr157. */
+
+void
+or1k32bf_h_sys_gpr157_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR157 (newval);
+}
+
+/* Get the value of h-sys-gpr158. */
+
+USI
+or1k32bf_h_sys_gpr158_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR158 ();
+}
+
+/* Set a value for h-sys-gpr158. */
+
+void
+or1k32bf_h_sys_gpr158_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR158 (newval);
+}
+
+/* Get the value of h-sys-gpr159. */
+
+USI
+or1k32bf_h_sys_gpr159_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR159 ();
+}
+
+/* Set a value for h-sys-gpr159. */
+
+void
+or1k32bf_h_sys_gpr159_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR159 (newval);
+}
+
+/* Get the value of h-sys-gpr160. */
+
+USI
+or1k32bf_h_sys_gpr160_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR160 ();
+}
+
+/* Set a value for h-sys-gpr160. */
+
+void
+or1k32bf_h_sys_gpr160_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR160 (newval);
+}
+
+/* Get the value of h-sys-gpr161. */
+
+USI
+or1k32bf_h_sys_gpr161_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR161 ();
+}
+
+/* Set a value for h-sys-gpr161. */
+
+void
+or1k32bf_h_sys_gpr161_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR161 (newval);
+}
+
+/* Get the value of h-sys-gpr162. */
+
+USI
+or1k32bf_h_sys_gpr162_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR162 ();
+}
+
+/* Set a value for h-sys-gpr162. */
+
+void
+or1k32bf_h_sys_gpr162_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR162 (newval);
+}
+
+/* Get the value of h-sys-gpr163. */
+
+USI
+or1k32bf_h_sys_gpr163_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR163 ();
+}
+
+/* Set a value for h-sys-gpr163. */
+
+void
+or1k32bf_h_sys_gpr163_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR163 (newval);
+}
+
+/* Get the value of h-sys-gpr164. */
+
+USI
+or1k32bf_h_sys_gpr164_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR164 ();
+}
+
+/* Set a value for h-sys-gpr164. */
+
+void
+or1k32bf_h_sys_gpr164_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR164 (newval);
+}
+
+/* Get the value of h-sys-gpr165. */
+
+USI
+or1k32bf_h_sys_gpr165_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR165 ();
+}
+
+/* Set a value for h-sys-gpr165. */
+
+void
+or1k32bf_h_sys_gpr165_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR165 (newval);
+}
+
+/* Get the value of h-sys-gpr166. */
+
+USI
+or1k32bf_h_sys_gpr166_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR166 ();
+}
+
+/* Set a value for h-sys-gpr166. */
+
+void
+or1k32bf_h_sys_gpr166_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR166 (newval);
+}
+
+/* Get the value of h-sys-gpr167. */
+
+USI
+or1k32bf_h_sys_gpr167_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR167 ();
+}
+
+/* Set a value for h-sys-gpr167. */
+
+void
+or1k32bf_h_sys_gpr167_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR167 (newval);
+}
+
+/* Get the value of h-sys-gpr168. */
+
+USI
+or1k32bf_h_sys_gpr168_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR168 ();
+}
+
+/* Set a value for h-sys-gpr168. */
+
+void
+or1k32bf_h_sys_gpr168_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR168 (newval);
+}
+
+/* Get the value of h-sys-gpr169. */
+
+USI
+or1k32bf_h_sys_gpr169_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR169 ();
+}
+
+/* Set a value for h-sys-gpr169. */
+
+void
+or1k32bf_h_sys_gpr169_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR169 (newval);
+}
+
+/* Get the value of h-sys-gpr170. */
+
+USI
+or1k32bf_h_sys_gpr170_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR170 ();
+}
+
+/* Set a value for h-sys-gpr170. */
+
+void
+or1k32bf_h_sys_gpr170_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR170 (newval);
+}
+
+/* Get the value of h-sys-gpr171. */
+
+USI
+or1k32bf_h_sys_gpr171_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR171 ();
+}
+
+/* Set a value for h-sys-gpr171. */
+
+void
+or1k32bf_h_sys_gpr171_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR171 (newval);
+}
+
+/* Get the value of h-sys-gpr172. */
+
+USI
+or1k32bf_h_sys_gpr172_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR172 ();
+}
+
+/* Set a value for h-sys-gpr172. */
+
+void
+or1k32bf_h_sys_gpr172_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR172 (newval);
+}
+
+/* Get the value of h-sys-gpr173. */
+
+USI
+or1k32bf_h_sys_gpr173_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR173 ();
+}
+
+/* Set a value for h-sys-gpr173. */
+
+void
+or1k32bf_h_sys_gpr173_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR173 (newval);
+}
+
+/* Get the value of h-sys-gpr174. */
+
+USI
+or1k32bf_h_sys_gpr174_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR174 ();
+}
+
+/* Set a value for h-sys-gpr174. */
+
+void
+or1k32bf_h_sys_gpr174_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR174 (newval);
+}
+
+/* Get the value of h-sys-gpr175. */
+
+USI
+or1k32bf_h_sys_gpr175_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR175 ();
+}
+
+/* Set a value for h-sys-gpr175. */
+
+void
+or1k32bf_h_sys_gpr175_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR175 (newval);
+}
+
+/* Get the value of h-sys-gpr176. */
+
+USI
+or1k32bf_h_sys_gpr176_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR176 ();
+}
+
+/* Set a value for h-sys-gpr176. */
+
+void
+or1k32bf_h_sys_gpr176_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR176 (newval);
+}
+
+/* Get the value of h-sys-gpr177. */
+
+USI
+or1k32bf_h_sys_gpr177_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR177 ();
+}
+
+/* Set a value for h-sys-gpr177. */
+
+void
+or1k32bf_h_sys_gpr177_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR177 (newval);
+}
+
+/* Get the value of h-sys-gpr178. */
+
+USI
+or1k32bf_h_sys_gpr178_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR178 ();
+}
+
+/* Set a value for h-sys-gpr178. */
+
+void
+or1k32bf_h_sys_gpr178_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR178 (newval);
+}
+
+/* Get the value of h-sys-gpr179. */
+
+USI
+or1k32bf_h_sys_gpr179_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR179 ();
+}
+
+/* Set a value for h-sys-gpr179. */
+
+void
+or1k32bf_h_sys_gpr179_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR179 (newval);
+}
+
+/* Get the value of h-sys-gpr180. */
+
+USI
+or1k32bf_h_sys_gpr180_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR180 ();
+}
+
+/* Set a value for h-sys-gpr180. */
+
+void
+or1k32bf_h_sys_gpr180_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR180 (newval);
+}
+
+/* Get the value of h-sys-gpr181. */
+
+USI
+or1k32bf_h_sys_gpr181_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR181 ();
+}
+
+/* Set a value for h-sys-gpr181. */
+
+void
+or1k32bf_h_sys_gpr181_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR181 (newval);
+}
+
+/* Get the value of h-sys-gpr182. */
+
+USI
+or1k32bf_h_sys_gpr182_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR182 ();
+}
+
+/* Set a value for h-sys-gpr182. */
+
+void
+or1k32bf_h_sys_gpr182_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR182 (newval);
+}
+
+/* Get the value of h-sys-gpr183. */
+
+USI
+or1k32bf_h_sys_gpr183_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR183 ();
+}
+
+/* Set a value for h-sys-gpr183. */
+
+void
+or1k32bf_h_sys_gpr183_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR183 (newval);
+}
+
+/* Get the value of h-sys-gpr184. */
+
+USI
+or1k32bf_h_sys_gpr184_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR184 ();
+}
+
+/* Set a value for h-sys-gpr184. */
+
+void
+or1k32bf_h_sys_gpr184_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR184 (newval);
+}
+
+/* Get the value of h-sys-gpr185. */
+
+USI
+or1k32bf_h_sys_gpr185_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR185 ();
+}
+
+/* Set a value for h-sys-gpr185. */
+
+void
+or1k32bf_h_sys_gpr185_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR185 (newval);
+}
+
+/* Get the value of h-sys-gpr186. */
+
+USI
+or1k32bf_h_sys_gpr186_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR186 ();
+}
+
+/* Set a value for h-sys-gpr186. */
+
+void
+or1k32bf_h_sys_gpr186_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR186 (newval);
+}
+
+/* Get the value of h-sys-gpr187. */
+
+USI
+or1k32bf_h_sys_gpr187_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR187 ();
+}
+
+/* Set a value for h-sys-gpr187. */
+
+void
+or1k32bf_h_sys_gpr187_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR187 (newval);
+}
+
+/* Get the value of h-sys-gpr188. */
+
+USI
+or1k32bf_h_sys_gpr188_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR188 ();
+}
+
+/* Set a value for h-sys-gpr188. */
+
+void
+or1k32bf_h_sys_gpr188_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR188 (newval);
+}
+
+/* Get the value of h-sys-gpr189. */
+
+USI
+or1k32bf_h_sys_gpr189_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR189 ();
+}
+
+/* Set a value for h-sys-gpr189. */
+
+void
+or1k32bf_h_sys_gpr189_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR189 (newval);
+}
+
+/* Get the value of h-sys-gpr190. */
+
+USI
+or1k32bf_h_sys_gpr190_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR190 ();
+}
+
+/* Set a value for h-sys-gpr190. */
+
+void
+or1k32bf_h_sys_gpr190_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR190 (newval);
+}
+
+/* Get the value of h-sys-gpr191. */
+
+USI
+or1k32bf_h_sys_gpr191_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR191 ();
+}
+
+/* Set a value for h-sys-gpr191. */
+
+void
+or1k32bf_h_sys_gpr191_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR191 (newval);
+}
+
+/* Get the value of h-sys-gpr192. */
+
+USI
+or1k32bf_h_sys_gpr192_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR192 ();
+}
+
+/* Set a value for h-sys-gpr192. */
+
+void
+or1k32bf_h_sys_gpr192_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR192 (newval);
+}
+
+/* Get the value of h-sys-gpr193. */
+
+USI
+or1k32bf_h_sys_gpr193_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR193 ();
+}
+
+/* Set a value for h-sys-gpr193. */
+
+void
+or1k32bf_h_sys_gpr193_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR193 (newval);
+}
+
+/* Get the value of h-sys-gpr194. */
+
+USI
+or1k32bf_h_sys_gpr194_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR194 ();
+}
+
+/* Set a value for h-sys-gpr194. */
+
+void
+or1k32bf_h_sys_gpr194_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR194 (newval);
+}
+
+/* Get the value of h-sys-gpr195. */
+
+USI
+or1k32bf_h_sys_gpr195_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR195 ();
+}
+
+/* Set a value for h-sys-gpr195. */
+
+void
+or1k32bf_h_sys_gpr195_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR195 (newval);
+}
+
+/* Get the value of h-sys-gpr196. */
+
+USI
+or1k32bf_h_sys_gpr196_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR196 ();
+}
+
+/* Set a value for h-sys-gpr196. */
+
+void
+or1k32bf_h_sys_gpr196_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR196 (newval);
+}
+
+/* Get the value of h-sys-gpr197. */
+
+USI
+or1k32bf_h_sys_gpr197_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR197 ();
+}
+
+/* Set a value for h-sys-gpr197. */
+
+void
+or1k32bf_h_sys_gpr197_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR197 (newval);
+}
+
+/* Get the value of h-sys-gpr198. */
+
+USI
+or1k32bf_h_sys_gpr198_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR198 ();
+}
+
+/* Set a value for h-sys-gpr198. */
+
+void
+or1k32bf_h_sys_gpr198_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR198 (newval);
+}
+
+/* Get the value of h-sys-gpr199. */
+
+USI
+or1k32bf_h_sys_gpr199_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR199 ();
+}
+
+/* Set a value for h-sys-gpr199. */
+
+void
+or1k32bf_h_sys_gpr199_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR199 (newval);
+}
+
+/* Get the value of h-sys-gpr200. */
+
+USI
+or1k32bf_h_sys_gpr200_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR200 ();
+}
+
+/* Set a value for h-sys-gpr200. */
+
+void
+or1k32bf_h_sys_gpr200_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR200 (newval);
+}
+
+/* Get the value of h-sys-gpr201. */
+
+USI
+or1k32bf_h_sys_gpr201_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR201 ();
+}
+
+/* Set a value for h-sys-gpr201. */
+
+void
+or1k32bf_h_sys_gpr201_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR201 (newval);
+}
+
+/* Get the value of h-sys-gpr202. */
+
+USI
+or1k32bf_h_sys_gpr202_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR202 ();
+}
+
+/* Set a value for h-sys-gpr202. */
+
+void
+or1k32bf_h_sys_gpr202_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR202 (newval);
+}
+
+/* Get the value of h-sys-gpr203. */
+
+USI
+or1k32bf_h_sys_gpr203_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR203 ();
+}
+
+/* Set a value for h-sys-gpr203. */
+
+void
+or1k32bf_h_sys_gpr203_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR203 (newval);
+}
+
+/* Get the value of h-sys-gpr204. */
+
+USI
+or1k32bf_h_sys_gpr204_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR204 ();
+}
+
+/* Set a value for h-sys-gpr204. */
+
+void
+or1k32bf_h_sys_gpr204_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR204 (newval);
+}
+
+/* Get the value of h-sys-gpr205. */
+
+USI
+or1k32bf_h_sys_gpr205_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR205 ();
+}
+
+/* Set a value for h-sys-gpr205. */
+
+void
+or1k32bf_h_sys_gpr205_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR205 (newval);
+}
+
+/* Get the value of h-sys-gpr206. */
+
+USI
+or1k32bf_h_sys_gpr206_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR206 ();
+}
+
+/* Set a value for h-sys-gpr206. */
+
+void
+or1k32bf_h_sys_gpr206_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR206 (newval);
+}
+
+/* Get the value of h-sys-gpr207. */
+
+USI
+or1k32bf_h_sys_gpr207_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR207 ();
+}
+
+/* Set a value for h-sys-gpr207. */
+
+void
+or1k32bf_h_sys_gpr207_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR207 (newval);
+}
+
+/* Get the value of h-sys-gpr208. */
+
+USI
+or1k32bf_h_sys_gpr208_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR208 ();
+}
+
+/* Set a value for h-sys-gpr208. */
+
+void
+or1k32bf_h_sys_gpr208_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR208 (newval);
+}
+
+/* Get the value of h-sys-gpr209. */
+
+USI
+or1k32bf_h_sys_gpr209_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR209 ();
+}
+
+/* Set a value for h-sys-gpr209. */
+
+void
+or1k32bf_h_sys_gpr209_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR209 (newval);
+}
+
+/* Get the value of h-sys-gpr210. */
+
+USI
+or1k32bf_h_sys_gpr210_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR210 ();
+}
+
+/* Set a value for h-sys-gpr210. */
+
+void
+or1k32bf_h_sys_gpr210_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR210 (newval);
+}
+
+/* Get the value of h-sys-gpr211. */
+
+USI
+or1k32bf_h_sys_gpr211_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR211 ();
+}
+
+/* Set a value for h-sys-gpr211. */
+
+void
+or1k32bf_h_sys_gpr211_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR211 (newval);
+}
+
+/* Get the value of h-sys-gpr212. */
+
+USI
+or1k32bf_h_sys_gpr212_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR212 ();
+}
+
+/* Set a value for h-sys-gpr212. */
+
+void
+or1k32bf_h_sys_gpr212_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR212 (newval);
+}
+
+/* Get the value of h-sys-gpr213. */
+
+USI
+or1k32bf_h_sys_gpr213_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR213 ();
+}
+
+/* Set a value for h-sys-gpr213. */
+
+void
+or1k32bf_h_sys_gpr213_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR213 (newval);
+}
+
+/* Get the value of h-sys-gpr214. */
+
+USI
+or1k32bf_h_sys_gpr214_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR214 ();
+}
+
+/* Set a value for h-sys-gpr214. */
+
+void
+or1k32bf_h_sys_gpr214_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR214 (newval);
+}
+
+/* Get the value of h-sys-gpr215. */
+
+USI
+or1k32bf_h_sys_gpr215_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR215 ();
+}
+
+/* Set a value for h-sys-gpr215. */
+
+void
+or1k32bf_h_sys_gpr215_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR215 (newval);
+}
+
+/* Get the value of h-sys-gpr216. */
+
+USI
+or1k32bf_h_sys_gpr216_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR216 ();
+}
+
+/* Set a value for h-sys-gpr216. */
+
+void
+or1k32bf_h_sys_gpr216_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR216 (newval);
+}
+
+/* Get the value of h-sys-gpr217. */
+
+USI
+or1k32bf_h_sys_gpr217_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR217 ();
+}
+
+/* Set a value for h-sys-gpr217. */
+
+void
+or1k32bf_h_sys_gpr217_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR217 (newval);
+}
+
+/* Get the value of h-sys-gpr218. */
+
+USI
+or1k32bf_h_sys_gpr218_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR218 ();
+}
+
+/* Set a value for h-sys-gpr218. */
+
+void
+or1k32bf_h_sys_gpr218_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR218 (newval);
+}
+
+/* Get the value of h-sys-gpr219. */
+
+USI
+or1k32bf_h_sys_gpr219_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR219 ();
+}
+
+/* Set a value for h-sys-gpr219. */
+
+void
+or1k32bf_h_sys_gpr219_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR219 (newval);
+}
+
+/* Get the value of h-sys-gpr220. */
+
+USI
+or1k32bf_h_sys_gpr220_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR220 ();
+}
+
+/* Set a value for h-sys-gpr220. */
+
+void
+or1k32bf_h_sys_gpr220_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR220 (newval);
+}
+
+/* Get the value of h-sys-gpr221. */
+
+USI
+or1k32bf_h_sys_gpr221_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR221 ();
+}
+
+/* Set a value for h-sys-gpr221. */
+
+void
+or1k32bf_h_sys_gpr221_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR221 (newval);
+}
+
+/* Get the value of h-sys-gpr222. */
+
+USI
+or1k32bf_h_sys_gpr222_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR222 ();
+}
+
+/* Set a value for h-sys-gpr222. */
+
+void
+or1k32bf_h_sys_gpr222_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR222 (newval);
+}
+
+/* Get the value of h-sys-gpr223. */
+
+USI
+or1k32bf_h_sys_gpr223_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR223 ();
+}
+
+/* Set a value for h-sys-gpr223. */
+
+void
+or1k32bf_h_sys_gpr223_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR223 (newval);
+}
+
+/* Get the value of h-sys-gpr224. */
+
+USI
+or1k32bf_h_sys_gpr224_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR224 ();
+}
+
+/* Set a value for h-sys-gpr224. */
+
+void
+or1k32bf_h_sys_gpr224_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR224 (newval);
+}
+
+/* Get the value of h-sys-gpr225. */
+
+USI
+or1k32bf_h_sys_gpr225_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR225 ();
+}
+
+/* Set a value for h-sys-gpr225. */
+
+void
+or1k32bf_h_sys_gpr225_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR225 (newval);
+}
+
+/* Get the value of h-sys-gpr226. */
+
+USI
+or1k32bf_h_sys_gpr226_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR226 ();
+}
+
+/* Set a value for h-sys-gpr226. */
+
+void
+or1k32bf_h_sys_gpr226_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR226 (newval);
+}
+
+/* Get the value of h-sys-gpr227. */
+
+USI
+or1k32bf_h_sys_gpr227_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR227 ();
+}
+
+/* Set a value for h-sys-gpr227. */
+
+void
+or1k32bf_h_sys_gpr227_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR227 (newval);
+}
+
+/* Get the value of h-sys-gpr228. */
+
+USI
+or1k32bf_h_sys_gpr228_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR228 ();
+}
+
+/* Set a value for h-sys-gpr228. */
+
+void
+or1k32bf_h_sys_gpr228_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR228 (newval);
+}
+
+/* Get the value of h-sys-gpr229. */
+
+USI
+or1k32bf_h_sys_gpr229_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR229 ();
+}
+
+/* Set a value for h-sys-gpr229. */
+
+void
+or1k32bf_h_sys_gpr229_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR229 (newval);
+}
+
+/* Get the value of h-sys-gpr230. */
+
+USI
+or1k32bf_h_sys_gpr230_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR230 ();
+}
+
+/* Set a value for h-sys-gpr230. */
+
+void
+or1k32bf_h_sys_gpr230_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR230 (newval);
+}
+
+/* Get the value of h-sys-gpr231. */
+
+USI
+or1k32bf_h_sys_gpr231_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR231 ();
+}
+
+/* Set a value for h-sys-gpr231. */
+
+void
+or1k32bf_h_sys_gpr231_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR231 (newval);
+}
+
+/* Get the value of h-sys-gpr232. */
+
+USI
+or1k32bf_h_sys_gpr232_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR232 ();
+}
+
+/* Set a value for h-sys-gpr232. */
+
+void
+or1k32bf_h_sys_gpr232_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR232 (newval);
+}
+
+/* Get the value of h-sys-gpr233. */
+
+USI
+or1k32bf_h_sys_gpr233_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR233 ();
+}
+
+/* Set a value for h-sys-gpr233. */
+
+void
+or1k32bf_h_sys_gpr233_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR233 (newval);
+}
+
+/* Get the value of h-sys-gpr234. */
+
+USI
+or1k32bf_h_sys_gpr234_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR234 ();
+}
+
+/* Set a value for h-sys-gpr234. */
+
+void
+or1k32bf_h_sys_gpr234_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR234 (newval);
+}
+
+/* Get the value of h-sys-gpr235. */
+
+USI
+or1k32bf_h_sys_gpr235_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR235 ();
+}
+
+/* Set a value for h-sys-gpr235. */
+
+void
+or1k32bf_h_sys_gpr235_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR235 (newval);
+}
+
+/* Get the value of h-sys-gpr236. */
+
+USI
+or1k32bf_h_sys_gpr236_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR236 ();
+}
+
+/* Set a value for h-sys-gpr236. */
+
+void
+or1k32bf_h_sys_gpr236_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR236 (newval);
+}
+
+/* Get the value of h-sys-gpr237. */
+
+USI
+or1k32bf_h_sys_gpr237_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR237 ();
+}
+
+/* Set a value for h-sys-gpr237. */
+
+void
+or1k32bf_h_sys_gpr237_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR237 (newval);
+}
+
+/* Get the value of h-sys-gpr238. */
+
+USI
+or1k32bf_h_sys_gpr238_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR238 ();
+}
+
+/* Set a value for h-sys-gpr238. */
+
+void
+or1k32bf_h_sys_gpr238_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR238 (newval);
+}
+
+/* Get the value of h-sys-gpr239. */
+
+USI
+or1k32bf_h_sys_gpr239_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR239 ();
+}
+
+/* Set a value for h-sys-gpr239. */
+
+void
+or1k32bf_h_sys_gpr239_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR239 (newval);
+}
+
+/* Get the value of h-sys-gpr240. */
+
+USI
+or1k32bf_h_sys_gpr240_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR240 ();
+}
+
+/* Set a value for h-sys-gpr240. */
+
+void
+or1k32bf_h_sys_gpr240_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR240 (newval);
+}
+
+/* Get the value of h-sys-gpr241. */
+
+USI
+or1k32bf_h_sys_gpr241_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR241 ();
+}
+
+/* Set a value for h-sys-gpr241. */
+
+void
+or1k32bf_h_sys_gpr241_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR241 (newval);
+}
+
+/* Get the value of h-sys-gpr242. */
+
+USI
+or1k32bf_h_sys_gpr242_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR242 ();
+}
+
+/* Set a value for h-sys-gpr242. */
+
+void
+or1k32bf_h_sys_gpr242_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR242 (newval);
+}
+
+/* Get the value of h-sys-gpr243. */
+
+USI
+or1k32bf_h_sys_gpr243_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR243 ();
+}
+
+/* Set a value for h-sys-gpr243. */
+
+void
+or1k32bf_h_sys_gpr243_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR243 (newval);
+}
+
+/* Get the value of h-sys-gpr244. */
+
+USI
+or1k32bf_h_sys_gpr244_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR244 ();
+}
+
+/* Set a value for h-sys-gpr244. */
+
+void
+or1k32bf_h_sys_gpr244_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR244 (newval);
+}
+
+/* Get the value of h-sys-gpr245. */
+
+USI
+or1k32bf_h_sys_gpr245_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR245 ();
+}
+
+/* Set a value for h-sys-gpr245. */
+
+void
+or1k32bf_h_sys_gpr245_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR245 (newval);
+}
+
+/* Get the value of h-sys-gpr246. */
+
+USI
+or1k32bf_h_sys_gpr246_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR246 ();
+}
+
+/* Set a value for h-sys-gpr246. */
+
+void
+or1k32bf_h_sys_gpr246_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR246 (newval);
+}
+
+/* Get the value of h-sys-gpr247. */
+
+USI
+or1k32bf_h_sys_gpr247_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR247 ();
+}
+
+/* Set a value for h-sys-gpr247. */
+
+void
+or1k32bf_h_sys_gpr247_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR247 (newval);
+}
+
+/* Get the value of h-sys-gpr248. */
+
+USI
+or1k32bf_h_sys_gpr248_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR248 ();
+}
+
+/* Set a value for h-sys-gpr248. */
+
+void
+or1k32bf_h_sys_gpr248_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR248 (newval);
+}
+
+/* Get the value of h-sys-gpr249. */
+
+USI
+or1k32bf_h_sys_gpr249_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR249 ();
+}
+
+/* Set a value for h-sys-gpr249. */
+
+void
+or1k32bf_h_sys_gpr249_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR249 (newval);
+}
+
+/* Get the value of h-sys-gpr250. */
+
+USI
+or1k32bf_h_sys_gpr250_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR250 ();
+}
+
+/* Set a value for h-sys-gpr250. */
+
+void
+or1k32bf_h_sys_gpr250_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR250 (newval);
+}
+
+/* Get the value of h-sys-gpr251. */
+
+USI
+or1k32bf_h_sys_gpr251_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR251 ();
+}
+
+/* Set a value for h-sys-gpr251. */
+
+void
+or1k32bf_h_sys_gpr251_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR251 (newval);
+}
+
+/* Get the value of h-sys-gpr252. */
+
+USI
+or1k32bf_h_sys_gpr252_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR252 ();
+}
+
+/* Set a value for h-sys-gpr252. */
+
+void
+or1k32bf_h_sys_gpr252_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR252 (newval);
+}
+
+/* Get the value of h-sys-gpr253. */
+
+USI
+or1k32bf_h_sys_gpr253_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR253 ();
+}
+
+/* Set a value for h-sys-gpr253. */
+
+void
+or1k32bf_h_sys_gpr253_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR253 (newval);
+}
+
+/* Get the value of h-sys-gpr254. */
+
+USI
+or1k32bf_h_sys_gpr254_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR254 ();
+}
+
+/* Set a value for h-sys-gpr254. */
+
+void
+or1k32bf_h_sys_gpr254_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR254 (newval);
+}
+
+/* Get the value of h-sys-gpr255. */
+
+USI
+or1k32bf_h_sys_gpr255_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR255 ();
+}
+
+/* Set a value for h-sys-gpr255. */
+
+void
+or1k32bf_h_sys_gpr255_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR255 (newval);
+}
+
+/* Get the value of h-sys-gpr256. */
+
+USI
+or1k32bf_h_sys_gpr256_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR256 ();
+}
+
+/* Set a value for h-sys-gpr256. */
+
+void
+or1k32bf_h_sys_gpr256_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR256 (newval);
+}
+
+/* Get the value of h-sys-gpr257. */
+
+USI
+or1k32bf_h_sys_gpr257_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR257 ();
+}
+
+/* Set a value for h-sys-gpr257. */
+
+void
+or1k32bf_h_sys_gpr257_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR257 (newval);
+}
+
+/* Get the value of h-sys-gpr258. */
+
+USI
+or1k32bf_h_sys_gpr258_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR258 ();
+}
+
+/* Set a value for h-sys-gpr258. */
+
+void
+or1k32bf_h_sys_gpr258_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR258 (newval);
+}
+
+/* Get the value of h-sys-gpr259. */
+
+USI
+or1k32bf_h_sys_gpr259_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR259 ();
+}
+
+/* Set a value for h-sys-gpr259. */
+
+void
+or1k32bf_h_sys_gpr259_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR259 (newval);
+}
+
+/* Get the value of h-sys-gpr260. */
+
+USI
+or1k32bf_h_sys_gpr260_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR260 ();
+}
+
+/* Set a value for h-sys-gpr260. */
+
+void
+or1k32bf_h_sys_gpr260_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR260 (newval);
+}
+
+/* Get the value of h-sys-gpr261. */
+
+USI
+or1k32bf_h_sys_gpr261_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR261 ();
+}
+
+/* Set a value for h-sys-gpr261. */
+
+void
+or1k32bf_h_sys_gpr261_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR261 (newval);
+}
+
+/* Get the value of h-sys-gpr262. */
+
+USI
+or1k32bf_h_sys_gpr262_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR262 ();
+}
+
+/* Set a value for h-sys-gpr262. */
+
+void
+or1k32bf_h_sys_gpr262_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR262 (newval);
+}
+
+/* Get the value of h-sys-gpr263. */
+
+USI
+or1k32bf_h_sys_gpr263_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR263 ();
+}
+
+/* Set a value for h-sys-gpr263. */
+
+void
+or1k32bf_h_sys_gpr263_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR263 (newval);
+}
+
+/* Get the value of h-sys-gpr264. */
+
+USI
+or1k32bf_h_sys_gpr264_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR264 ();
+}
+
+/* Set a value for h-sys-gpr264. */
+
+void
+or1k32bf_h_sys_gpr264_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR264 (newval);
+}
+
+/* Get the value of h-sys-gpr265. */
+
+USI
+or1k32bf_h_sys_gpr265_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR265 ();
+}
+
+/* Set a value for h-sys-gpr265. */
+
+void
+or1k32bf_h_sys_gpr265_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR265 (newval);
+}
+
+/* Get the value of h-sys-gpr266. */
+
+USI
+or1k32bf_h_sys_gpr266_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR266 ();
+}
+
+/* Set a value for h-sys-gpr266. */
+
+void
+or1k32bf_h_sys_gpr266_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR266 (newval);
+}
+
+/* Get the value of h-sys-gpr267. */
+
+USI
+or1k32bf_h_sys_gpr267_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR267 ();
+}
+
+/* Set a value for h-sys-gpr267. */
+
+void
+or1k32bf_h_sys_gpr267_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR267 (newval);
+}
+
+/* Get the value of h-sys-gpr268. */
+
+USI
+or1k32bf_h_sys_gpr268_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR268 ();
+}
+
+/* Set a value for h-sys-gpr268. */
+
+void
+or1k32bf_h_sys_gpr268_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR268 (newval);
+}
+
+/* Get the value of h-sys-gpr269. */
+
+USI
+or1k32bf_h_sys_gpr269_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR269 ();
+}
+
+/* Set a value for h-sys-gpr269. */
+
+void
+or1k32bf_h_sys_gpr269_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR269 (newval);
+}
+
+/* Get the value of h-sys-gpr270. */
+
+USI
+or1k32bf_h_sys_gpr270_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR270 ();
+}
+
+/* Set a value for h-sys-gpr270. */
+
+void
+or1k32bf_h_sys_gpr270_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR270 (newval);
+}
+
+/* Get the value of h-sys-gpr271. */
+
+USI
+or1k32bf_h_sys_gpr271_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR271 ();
+}
+
+/* Set a value for h-sys-gpr271. */
+
+void
+or1k32bf_h_sys_gpr271_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR271 (newval);
+}
+
+/* Get the value of h-sys-gpr272. */
+
+USI
+or1k32bf_h_sys_gpr272_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR272 ();
+}
+
+/* Set a value for h-sys-gpr272. */
+
+void
+or1k32bf_h_sys_gpr272_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR272 (newval);
+}
+
+/* Get the value of h-sys-gpr273. */
+
+USI
+or1k32bf_h_sys_gpr273_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR273 ();
+}
+
+/* Set a value for h-sys-gpr273. */
+
+void
+or1k32bf_h_sys_gpr273_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR273 (newval);
+}
+
+/* Get the value of h-sys-gpr274. */
+
+USI
+or1k32bf_h_sys_gpr274_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR274 ();
+}
+
+/* Set a value for h-sys-gpr274. */
+
+void
+or1k32bf_h_sys_gpr274_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR274 (newval);
+}
+
+/* Get the value of h-sys-gpr275. */
+
+USI
+or1k32bf_h_sys_gpr275_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR275 ();
+}
+
+/* Set a value for h-sys-gpr275. */
+
+void
+or1k32bf_h_sys_gpr275_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR275 (newval);
+}
+
+/* Get the value of h-sys-gpr276. */
+
+USI
+or1k32bf_h_sys_gpr276_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR276 ();
+}
+
+/* Set a value for h-sys-gpr276. */
+
+void
+or1k32bf_h_sys_gpr276_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR276 (newval);
+}
+
+/* Get the value of h-sys-gpr277. */
+
+USI
+or1k32bf_h_sys_gpr277_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR277 ();
+}
+
+/* Set a value for h-sys-gpr277. */
+
+void
+or1k32bf_h_sys_gpr277_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR277 (newval);
+}
+
+/* Get the value of h-sys-gpr278. */
+
+USI
+or1k32bf_h_sys_gpr278_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR278 ();
+}
+
+/* Set a value for h-sys-gpr278. */
+
+void
+or1k32bf_h_sys_gpr278_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR278 (newval);
+}
+
+/* Get the value of h-sys-gpr279. */
+
+USI
+or1k32bf_h_sys_gpr279_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR279 ();
+}
+
+/* Set a value for h-sys-gpr279. */
+
+void
+or1k32bf_h_sys_gpr279_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR279 (newval);
+}
+
+/* Get the value of h-sys-gpr280. */
+
+USI
+or1k32bf_h_sys_gpr280_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR280 ();
+}
+
+/* Set a value for h-sys-gpr280. */
+
+void
+or1k32bf_h_sys_gpr280_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR280 (newval);
+}
+
+/* Get the value of h-sys-gpr281. */
+
+USI
+or1k32bf_h_sys_gpr281_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR281 ();
+}
+
+/* Set a value for h-sys-gpr281. */
+
+void
+or1k32bf_h_sys_gpr281_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR281 (newval);
+}
+
+/* Get the value of h-sys-gpr282. */
+
+USI
+or1k32bf_h_sys_gpr282_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR282 ();
+}
+
+/* Set a value for h-sys-gpr282. */
+
+void
+or1k32bf_h_sys_gpr282_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR282 (newval);
+}
+
+/* Get the value of h-sys-gpr283. */
+
+USI
+or1k32bf_h_sys_gpr283_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR283 ();
+}
+
+/* Set a value for h-sys-gpr283. */
+
+void
+or1k32bf_h_sys_gpr283_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR283 (newval);
+}
+
+/* Get the value of h-sys-gpr284. */
+
+USI
+or1k32bf_h_sys_gpr284_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR284 ();
+}
+
+/* Set a value for h-sys-gpr284. */
+
+void
+or1k32bf_h_sys_gpr284_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR284 (newval);
+}
+
+/* Get the value of h-sys-gpr285. */
+
+USI
+or1k32bf_h_sys_gpr285_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR285 ();
+}
+
+/* Set a value for h-sys-gpr285. */
+
+void
+or1k32bf_h_sys_gpr285_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR285 (newval);
+}
+
+/* Get the value of h-sys-gpr286. */
+
+USI
+or1k32bf_h_sys_gpr286_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR286 ();
+}
+
+/* Set a value for h-sys-gpr286. */
+
+void
+or1k32bf_h_sys_gpr286_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR286 (newval);
+}
+
+/* Get the value of h-sys-gpr287. */
+
+USI
+or1k32bf_h_sys_gpr287_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR287 ();
+}
+
+/* Set a value for h-sys-gpr287. */
+
+void
+or1k32bf_h_sys_gpr287_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR287 (newval);
+}
+
+/* Get the value of h-sys-gpr288. */
+
+USI
+or1k32bf_h_sys_gpr288_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR288 ();
+}
+
+/* Set a value for h-sys-gpr288. */
+
+void
+or1k32bf_h_sys_gpr288_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR288 (newval);
+}
+
+/* Get the value of h-sys-gpr289. */
+
+USI
+or1k32bf_h_sys_gpr289_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR289 ();
+}
+
+/* Set a value for h-sys-gpr289. */
+
+void
+or1k32bf_h_sys_gpr289_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR289 (newval);
+}
+
+/* Get the value of h-sys-gpr290. */
+
+USI
+or1k32bf_h_sys_gpr290_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR290 ();
+}
+
+/* Set a value for h-sys-gpr290. */
+
+void
+or1k32bf_h_sys_gpr290_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR290 (newval);
+}
+
+/* Get the value of h-sys-gpr291. */
+
+USI
+or1k32bf_h_sys_gpr291_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR291 ();
+}
+
+/* Set a value for h-sys-gpr291. */
+
+void
+or1k32bf_h_sys_gpr291_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR291 (newval);
+}
+
+/* Get the value of h-sys-gpr292. */
+
+USI
+or1k32bf_h_sys_gpr292_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR292 ();
+}
+
+/* Set a value for h-sys-gpr292. */
+
+void
+or1k32bf_h_sys_gpr292_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR292 (newval);
+}
+
+/* Get the value of h-sys-gpr293. */
+
+USI
+or1k32bf_h_sys_gpr293_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR293 ();
+}
+
+/* Set a value for h-sys-gpr293. */
+
+void
+or1k32bf_h_sys_gpr293_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR293 (newval);
+}
+
+/* Get the value of h-sys-gpr294. */
+
+USI
+or1k32bf_h_sys_gpr294_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR294 ();
+}
+
+/* Set a value for h-sys-gpr294. */
+
+void
+or1k32bf_h_sys_gpr294_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR294 (newval);
+}
+
+/* Get the value of h-sys-gpr295. */
+
+USI
+or1k32bf_h_sys_gpr295_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR295 ();
+}
+
+/* Set a value for h-sys-gpr295. */
+
+void
+or1k32bf_h_sys_gpr295_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR295 (newval);
+}
+
+/* Get the value of h-sys-gpr296. */
+
+USI
+or1k32bf_h_sys_gpr296_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR296 ();
+}
+
+/* Set a value for h-sys-gpr296. */
+
+void
+or1k32bf_h_sys_gpr296_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR296 (newval);
+}
+
+/* Get the value of h-sys-gpr297. */
+
+USI
+or1k32bf_h_sys_gpr297_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR297 ();
+}
+
+/* Set a value for h-sys-gpr297. */
+
+void
+or1k32bf_h_sys_gpr297_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR297 (newval);
+}
+
+/* Get the value of h-sys-gpr298. */
+
+USI
+or1k32bf_h_sys_gpr298_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR298 ();
+}
+
+/* Set a value for h-sys-gpr298. */
+
+void
+or1k32bf_h_sys_gpr298_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR298 (newval);
+}
+
+/* Get the value of h-sys-gpr299. */
+
+USI
+or1k32bf_h_sys_gpr299_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR299 ();
+}
+
+/* Set a value for h-sys-gpr299. */
+
+void
+or1k32bf_h_sys_gpr299_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR299 (newval);
+}
+
+/* Get the value of h-sys-gpr300. */
+
+USI
+or1k32bf_h_sys_gpr300_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR300 ();
+}
+
+/* Set a value for h-sys-gpr300. */
+
+void
+or1k32bf_h_sys_gpr300_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR300 (newval);
+}
+
+/* Get the value of h-sys-gpr301. */
+
+USI
+or1k32bf_h_sys_gpr301_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR301 ();
+}
+
+/* Set a value for h-sys-gpr301. */
+
+void
+or1k32bf_h_sys_gpr301_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR301 (newval);
+}
+
+/* Get the value of h-sys-gpr302. */
+
+USI
+or1k32bf_h_sys_gpr302_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR302 ();
+}
+
+/* Set a value for h-sys-gpr302. */
+
+void
+or1k32bf_h_sys_gpr302_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR302 (newval);
+}
+
+/* Get the value of h-sys-gpr303. */
+
+USI
+or1k32bf_h_sys_gpr303_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR303 ();
+}
+
+/* Set a value for h-sys-gpr303. */
+
+void
+or1k32bf_h_sys_gpr303_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR303 (newval);
+}
+
+/* Get the value of h-sys-gpr304. */
+
+USI
+or1k32bf_h_sys_gpr304_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR304 ();
+}
+
+/* Set a value for h-sys-gpr304. */
+
+void
+or1k32bf_h_sys_gpr304_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR304 (newval);
+}
+
+/* Get the value of h-sys-gpr305. */
+
+USI
+or1k32bf_h_sys_gpr305_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR305 ();
+}
+
+/* Set a value for h-sys-gpr305. */
+
+void
+or1k32bf_h_sys_gpr305_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR305 (newval);
+}
+
+/* Get the value of h-sys-gpr306. */
+
+USI
+or1k32bf_h_sys_gpr306_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR306 ();
+}
+
+/* Set a value for h-sys-gpr306. */
+
+void
+or1k32bf_h_sys_gpr306_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR306 (newval);
+}
+
+/* Get the value of h-sys-gpr307. */
+
+USI
+or1k32bf_h_sys_gpr307_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR307 ();
+}
+
+/* Set a value for h-sys-gpr307. */
+
+void
+or1k32bf_h_sys_gpr307_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR307 (newval);
+}
+
+/* Get the value of h-sys-gpr308. */
+
+USI
+or1k32bf_h_sys_gpr308_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR308 ();
+}
+
+/* Set a value for h-sys-gpr308. */
+
+void
+or1k32bf_h_sys_gpr308_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR308 (newval);
+}
+
+/* Get the value of h-sys-gpr309. */
+
+USI
+or1k32bf_h_sys_gpr309_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR309 ();
+}
+
+/* Set a value for h-sys-gpr309. */
+
+void
+or1k32bf_h_sys_gpr309_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR309 (newval);
+}
+
+/* Get the value of h-sys-gpr310. */
+
+USI
+or1k32bf_h_sys_gpr310_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR310 ();
+}
+
+/* Set a value for h-sys-gpr310. */
+
+void
+or1k32bf_h_sys_gpr310_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR310 (newval);
+}
+
+/* Get the value of h-sys-gpr311. */
+
+USI
+or1k32bf_h_sys_gpr311_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR311 ();
+}
+
+/* Set a value for h-sys-gpr311. */
+
+void
+or1k32bf_h_sys_gpr311_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR311 (newval);
+}
+
+/* Get the value of h-sys-gpr312. */
+
+USI
+or1k32bf_h_sys_gpr312_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR312 ();
+}
+
+/* Set a value for h-sys-gpr312. */
+
+void
+or1k32bf_h_sys_gpr312_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR312 (newval);
+}
+
+/* Get the value of h-sys-gpr313. */
+
+USI
+or1k32bf_h_sys_gpr313_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR313 ();
+}
+
+/* Set a value for h-sys-gpr313. */
+
+void
+or1k32bf_h_sys_gpr313_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR313 (newval);
+}
+
+/* Get the value of h-sys-gpr314. */
+
+USI
+or1k32bf_h_sys_gpr314_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR314 ();
+}
+
+/* Set a value for h-sys-gpr314. */
+
+void
+or1k32bf_h_sys_gpr314_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR314 (newval);
+}
+
+/* Get the value of h-sys-gpr315. */
+
+USI
+or1k32bf_h_sys_gpr315_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR315 ();
+}
+
+/* Set a value for h-sys-gpr315. */
+
+void
+or1k32bf_h_sys_gpr315_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR315 (newval);
+}
+
+/* Get the value of h-sys-gpr316. */
+
+USI
+or1k32bf_h_sys_gpr316_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR316 ();
+}
+
+/* Set a value for h-sys-gpr316. */
+
+void
+or1k32bf_h_sys_gpr316_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR316 (newval);
+}
+
+/* Get the value of h-sys-gpr317. */
+
+USI
+or1k32bf_h_sys_gpr317_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR317 ();
+}
+
+/* Set a value for h-sys-gpr317. */
+
+void
+or1k32bf_h_sys_gpr317_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR317 (newval);
+}
+
+/* Get the value of h-sys-gpr318. */
+
+USI
+or1k32bf_h_sys_gpr318_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR318 ();
+}
+
+/* Set a value for h-sys-gpr318. */
+
+void
+or1k32bf_h_sys_gpr318_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR318 (newval);
+}
+
+/* Get the value of h-sys-gpr319. */
+
+USI
+or1k32bf_h_sys_gpr319_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR319 ();
+}
+
+/* Set a value for h-sys-gpr319. */
+
+void
+or1k32bf_h_sys_gpr319_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR319 (newval);
+}
+
+/* Get the value of h-sys-gpr320. */
+
+USI
+or1k32bf_h_sys_gpr320_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR320 ();
+}
+
+/* Set a value for h-sys-gpr320. */
+
+void
+or1k32bf_h_sys_gpr320_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR320 (newval);
+}
+
+/* Get the value of h-sys-gpr321. */
+
+USI
+or1k32bf_h_sys_gpr321_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR321 ();
+}
+
+/* Set a value for h-sys-gpr321. */
+
+void
+or1k32bf_h_sys_gpr321_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR321 (newval);
+}
+
+/* Get the value of h-sys-gpr322. */
+
+USI
+or1k32bf_h_sys_gpr322_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR322 ();
+}
+
+/* Set a value for h-sys-gpr322. */
+
+void
+or1k32bf_h_sys_gpr322_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR322 (newval);
+}
+
+/* Get the value of h-sys-gpr323. */
+
+USI
+or1k32bf_h_sys_gpr323_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR323 ();
+}
+
+/* Set a value for h-sys-gpr323. */
+
+void
+or1k32bf_h_sys_gpr323_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR323 (newval);
+}
+
+/* Get the value of h-sys-gpr324. */
+
+USI
+or1k32bf_h_sys_gpr324_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR324 ();
+}
+
+/* Set a value for h-sys-gpr324. */
+
+void
+or1k32bf_h_sys_gpr324_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR324 (newval);
+}
+
+/* Get the value of h-sys-gpr325. */
+
+USI
+or1k32bf_h_sys_gpr325_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR325 ();
+}
+
+/* Set a value for h-sys-gpr325. */
+
+void
+or1k32bf_h_sys_gpr325_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR325 (newval);
+}
+
+/* Get the value of h-sys-gpr326. */
+
+USI
+or1k32bf_h_sys_gpr326_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR326 ();
+}
+
+/* Set a value for h-sys-gpr326. */
+
+void
+or1k32bf_h_sys_gpr326_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR326 (newval);
+}
+
+/* Get the value of h-sys-gpr327. */
+
+USI
+or1k32bf_h_sys_gpr327_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR327 ();
+}
+
+/* Set a value for h-sys-gpr327. */
+
+void
+or1k32bf_h_sys_gpr327_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR327 (newval);
+}
+
+/* Get the value of h-sys-gpr328. */
+
+USI
+or1k32bf_h_sys_gpr328_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR328 ();
+}
+
+/* Set a value for h-sys-gpr328. */
+
+void
+or1k32bf_h_sys_gpr328_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR328 (newval);
+}
+
+/* Get the value of h-sys-gpr329. */
+
+USI
+or1k32bf_h_sys_gpr329_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR329 ();
+}
+
+/* Set a value for h-sys-gpr329. */
+
+void
+or1k32bf_h_sys_gpr329_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR329 (newval);
+}
+
+/* Get the value of h-sys-gpr330. */
+
+USI
+or1k32bf_h_sys_gpr330_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR330 ();
+}
+
+/* Set a value for h-sys-gpr330. */
+
+void
+or1k32bf_h_sys_gpr330_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR330 (newval);
+}
+
+/* Get the value of h-sys-gpr331. */
+
+USI
+or1k32bf_h_sys_gpr331_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR331 ();
+}
+
+/* Set a value for h-sys-gpr331. */
+
+void
+or1k32bf_h_sys_gpr331_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR331 (newval);
+}
+
+/* Get the value of h-sys-gpr332. */
+
+USI
+or1k32bf_h_sys_gpr332_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR332 ();
+}
+
+/* Set a value for h-sys-gpr332. */
+
+void
+or1k32bf_h_sys_gpr332_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR332 (newval);
+}
+
+/* Get the value of h-sys-gpr333. */
+
+USI
+or1k32bf_h_sys_gpr333_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR333 ();
+}
+
+/* Set a value for h-sys-gpr333. */
+
+void
+or1k32bf_h_sys_gpr333_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR333 (newval);
+}
+
+/* Get the value of h-sys-gpr334. */
+
+USI
+or1k32bf_h_sys_gpr334_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR334 ();
+}
+
+/* Set a value for h-sys-gpr334. */
+
+void
+or1k32bf_h_sys_gpr334_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR334 (newval);
+}
+
+/* Get the value of h-sys-gpr335. */
+
+USI
+or1k32bf_h_sys_gpr335_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR335 ();
+}
+
+/* Set a value for h-sys-gpr335. */
+
+void
+or1k32bf_h_sys_gpr335_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR335 (newval);
+}
+
+/* Get the value of h-sys-gpr336. */
+
+USI
+or1k32bf_h_sys_gpr336_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR336 ();
+}
+
+/* Set a value for h-sys-gpr336. */
+
+void
+or1k32bf_h_sys_gpr336_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR336 (newval);
+}
+
+/* Get the value of h-sys-gpr337. */
+
+USI
+or1k32bf_h_sys_gpr337_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR337 ();
+}
+
+/* Set a value for h-sys-gpr337. */
+
+void
+or1k32bf_h_sys_gpr337_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR337 (newval);
+}
+
+/* Get the value of h-sys-gpr338. */
+
+USI
+or1k32bf_h_sys_gpr338_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR338 ();
+}
+
+/* Set a value for h-sys-gpr338. */
+
+void
+or1k32bf_h_sys_gpr338_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR338 (newval);
+}
+
+/* Get the value of h-sys-gpr339. */
+
+USI
+or1k32bf_h_sys_gpr339_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR339 ();
+}
+
+/* Set a value for h-sys-gpr339. */
+
+void
+or1k32bf_h_sys_gpr339_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR339 (newval);
+}
+
+/* Get the value of h-sys-gpr340. */
+
+USI
+or1k32bf_h_sys_gpr340_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR340 ();
+}
+
+/* Set a value for h-sys-gpr340. */
+
+void
+or1k32bf_h_sys_gpr340_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR340 (newval);
+}
+
+/* Get the value of h-sys-gpr341. */
+
+USI
+or1k32bf_h_sys_gpr341_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR341 ();
+}
+
+/* Set a value for h-sys-gpr341. */
+
+void
+or1k32bf_h_sys_gpr341_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR341 (newval);
+}
+
+/* Get the value of h-sys-gpr342. */
+
+USI
+or1k32bf_h_sys_gpr342_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR342 ();
+}
+
+/* Set a value for h-sys-gpr342. */
+
+void
+or1k32bf_h_sys_gpr342_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR342 (newval);
+}
+
+/* Get the value of h-sys-gpr343. */
+
+USI
+or1k32bf_h_sys_gpr343_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR343 ();
+}
+
+/* Set a value for h-sys-gpr343. */
+
+void
+or1k32bf_h_sys_gpr343_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR343 (newval);
+}
+
+/* Get the value of h-sys-gpr344. */
+
+USI
+or1k32bf_h_sys_gpr344_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR344 ();
+}
+
+/* Set a value for h-sys-gpr344. */
+
+void
+or1k32bf_h_sys_gpr344_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR344 (newval);
+}
+
+/* Get the value of h-sys-gpr345. */
+
+USI
+or1k32bf_h_sys_gpr345_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR345 ();
+}
+
+/* Set a value for h-sys-gpr345. */
+
+void
+or1k32bf_h_sys_gpr345_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR345 (newval);
+}
+
+/* Get the value of h-sys-gpr346. */
+
+USI
+or1k32bf_h_sys_gpr346_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR346 ();
+}
+
+/* Set a value for h-sys-gpr346. */
+
+void
+or1k32bf_h_sys_gpr346_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR346 (newval);
+}
+
+/* Get the value of h-sys-gpr347. */
+
+USI
+or1k32bf_h_sys_gpr347_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR347 ();
+}
+
+/* Set a value for h-sys-gpr347. */
+
+void
+or1k32bf_h_sys_gpr347_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR347 (newval);
+}
+
+/* Get the value of h-sys-gpr348. */
+
+USI
+or1k32bf_h_sys_gpr348_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR348 ();
+}
+
+/* Set a value for h-sys-gpr348. */
+
+void
+or1k32bf_h_sys_gpr348_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR348 (newval);
+}
+
+/* Get the value of h-sys-gpr349. */
+
+USI
+or1k32bf_h_sys_gpr349_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR349 ();
+}
+
+/* Set a value for h-sys-gpr349. */
+
+void
+or1k32bf_h_sys_gpr349_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR349 (newval);
+}
+
+/* Get the value of h-sys-gpr350. */
+
+USI
+or1k32bf_h_sys_gpr350_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR350 ();
+}
+
+/* Set a value for h-sys-gpr350. */
+
+void
+or1k32bf_h_sys_gpr350_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR350 (newval);
+}
+
+/* Get the value of h-sys-gpr351. */
+
+USI
+or1k32bf_h_sys_gpr351_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR351 ();
+}
+
+/* Set a value for h-sys-gpr351. */
+
+void
+or1k32bf_h_sys_gpr351_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR351 (newval);
+}
+
+/* Get the value of h-sys-gpr352. */
+
+USI
+or1k32bf_h_sys_gpr352_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR352 ();
+}
+
+/* Set a value for h-sys-gpr352. */
+
+void
+or1k32bf_h_sys_gpr352_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR352 (newval);
+}
+
+/* Get the value of h-sys-gpr353. */
+
+USI
+or1k32bf_h_sys_gpr353_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR353 ();
+}
+
+/* Set a value for h-sys-gpr353. */
+
+void
+or1k32bf_h_sys_gpr353_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR353 (newval);
+}
+
+/* Get the value of h-sys-gpr354. */
+
+USI
+or1k32bf_h_sys_gpr354_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR354 ();
+}
+
+/* Set a value for h-sys-gpr354. */
+
+void
+or1k32bf_h_sys_gpr354_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR354 (newval);
+}
+
+/* Get the value of h-sys-gpr355. */
+
+USI
+or1k32bf_h_sys_gpr355_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR355 ();
+}
+
+/* Set a value for h-sys-gpr355. */
+
+void
+or1k32bf_h_sys_gpr355_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR355 (newval);
+}
+
+/* Get the value of h-sys-gpr356. */
+
+USI
+or1k32bf_h_sys_gpr356_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR356 ();
+}
+
+/* Set a value for h-sys-gpr356. */
+
+void
+or1k32bf_h_sys_gpr356_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR356 (newval);
+}
+
+/* Get the value of h-sys-gpr357. */
+
+USI
+or1k32bf_h_sys_gpr357_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR357 ();
+}
+
+/* Set a value for h-sys-gpr357. */
+
+void
+or1k32bf_h_sys_gpr357_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR357 (newval);
+}
+
+/* Get the value of h-sys-gpr358. */
+
+USI
+or1k32bf_h_sys_gpr358_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR358 ();
+}
+
+/* Set a value for h-sys-gpr358. */
+
+void
+or1k32bf_h_sys_gpr358_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR358 (newval);
+}
+
+/* Get the value of h-sys-gpr359. */
+
+USI
+or1k32bf_h_sys_gpr359_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR359 ();
+}
+
+/* Set a value for h-sys-gpr359. */
+
+void
+or1k32bf_h_sys_gpr359_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR359 (newval);
+}
+
+/* Get the value of h-sys-gpr360. */
+
+USI
+or1k32bf_h_sys_gpr360_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR360 ();
+}
+
+/* Set a value for h-sys-gpr360. */
+
+void
+or1k32bf_h_sys_gpr360_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR360 (newval);
+}
+
+/* Get the value of h-sys-gpr361. */
+
+USI
+or1k32bf_h_sys_gpr361_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR361 ();
+}
+
+/* Set a value for h-sys-gpr361. */
+
+void
+or1k32bf_h_sys_gpr361_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR361 (newval);
+}
+
+/* Get the value of h-sys-gpr362. */
+
+USI
+or1k32bf_h_sys_gpr362_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR362 ();
+}
+
+/* Set a value for h-sys-gpr362. */
+
+void
+or1k32bf_h_sys_gpr362_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR362 (newval);
+}
+
+/* Get the value of h-sys-gpr363. */
+
+USI
+or1k32bf_h_sys_gpr363_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR363 ();
+}
+
+/* Set a value for h-sys-gpr363. */
+
+void
+or1k32bf_h_sys_gpr363_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR363 (newval);
+}
+
+/* Get the value of h-sys-gpr364. */
+
+USI
+or1k32bf_h_sys_gpr364_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR364 ();
+}
+
+/* Set a value for h-sys-gpr364. */
+
+void
+or1k32bf_h_sys_gpr364_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR364 (newval);
+}
+
+/* Get the value of h-sys-gpr365. */
+
+USI
+or1k32bf_h_sys_gpr365_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR365 ();
+}
+
+/* Set a value for h-sys-gpr365. */
+
+void
+or1k32bf_h_sys_gpr365_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR365 (newval);
+}
+
+/* Get the value of h-sys-gpr366. */
+
+USI
+or1k32bf_h_sys_gpr366_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR366 ();
+}
+
+/* Set a value for h-sys-gpr366. */
+
+void
+or1k32bf_h_sys_gpr366_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR366 (newval);
+}
+
+/* Get the value of h-sys-gpr367. */
+
+USI
+or1k32bf_h_sys_gpr367_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR367 ();
+}
+
+/* Set a value for h-sys-gpr367. */
+
+void
+or1k32bf_h_sys_gpr367_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR367 (newval);
+}
+
+/* Get the value of h-sys-gpr368. */
+
+USI
+or1k32bf_h_sys_gpr368_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR368 ();
+}
+
+/* Set a value for h-sys-gpr368. */
+
+void
+or1k32bf_h_sys_gpr368_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR368 (newval);
+}
+
+/* Get the value of h-sys-gpr369. */
+
+USI
+or1k32bf_h_sys_gpr369_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR369 ();
+}
+
+/* Set a value for h-sys-gpr369. */
+
+void
+or1k32bf_h_sys_gpr369_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR369 (newval);
+}
+
+/* Get the value of h-sys-gpr370. */
+
+USI
+or1k32bf_h_sys_gpr370_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR370 ();
+}
+
+/* Set a value for h-sys-gpr370. */
+
+void
+or1k32bf_h_sys_gpr370_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR370 (newval);
+}
+
+/* Get the value of h-sys-gpr371. */
+
+USI
+or1k32bf_h_sys_gpr371_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR371 ();
+}
+
+/* Set a value for h-sys-gpr371. */
+
+void
+or1k32bf_h_sys_gpr371_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR371 (newval);
+}
+
+/* Get the value of h-sys-gpr372. */
+
+USI
+or1k32bf_h_sys_gpr372_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR372 ();
+}
+
+/* Set a value for h-sys-gpr372. */
+
+void
+or1k32bf_h_sys_gpr372_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR372 (newval);
+}
+
+/* Get the value of h-sys-gpr373. */
+
+USI
+or1k32bf_h_sys_gpr373_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR373 ();
+}
+
+/* Set a value for h-sys-gpr373. */
+
+void
+or1k32bf_h_sys_gpr373_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR373 (newval);
+}
+
+/* Get the value of h-sys-gpr374. */
+
+USI
+or1k32bf_h_sys_gpr374_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR374 ();
+}
+
+/* Set a value for h-sys-gpr374. */
+
+void
+or1k32bf_h_sys_gpr374_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR374 (newval);
+}
+
+/* Get the value of h-sys-gpr375. */
+
+USI
+or1k32bf_h_sys_gpr375_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR375 ();
+}
+
+/* Set a value for h-sys-gpr375. */
+
+void
+or1k32bf_h_sys_gpr375_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR375 (newval);
+}
+
+/* Get the value of h-sys-gpr376. */
+
+USI
+or1k32bf_h_sys_gpr376_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR376 ();
+}
+
+/* Set a value for h-sys-gpr376. */
+
+void
+or1k32bf_h_sys_gpr376_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR376 (newval);
+}
+
+/* Get the value of h-sys-gpr377. */
+
+USI
+or1k32bf_h_sys_gpr377_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR377 ();
+}
+
+/* Set a value for h-sys-gpr377. */
+
+void
+or1k32bf_h_sys_gpr377_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR377 (newval);
+}
+
+/* Get the value of h-sys-gpr378. */
+
+USI
+or1k32bf_h_sys_gpr378_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR378 ();
+}
+
+/* Set a value for h-sys-gpr378. */
+
+void
+or1k32bf_h_sys_gpr378_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR378 (newval);
+}
+
+/* Get the value of h-sys-gpr379. */
+
+USI
+or1k32bf_h_sys_gpr379_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR379 ();
+}
+
+/* Set a value for h-sys-gpr379. */
+
+void
+or1k32bf_h_sys_gpr379_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR379 (newval);
+}
+
+/* Get the value of h-sys-gpr380. */
+
+USI
+or1k32bf_h_sys_gpr380_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR380 ();
+}
+
+/* Set a value for h-sys-gpr380. */
+
+void
+or1k32bf_h_sys_gpr380_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR380 (newval);
+}
+
+/* Get the value of h-sys-gpr381. */
+
+USI
+or1k32bf_h_sys_gpr381_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR381 ();
+}
+
+/* Set a value for h-sys-gpr381. */
+
+void
+or1k32bf_h_sys_gpr381_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR381 (newval);
+}
+
+/* Get the value of h-sys-gpr382. */
+
+USI
+or1k32bf_h_sys_gpr382_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR382 ();
+}
+
+/* Set a value for h-sys-gpr382. */
+
+void
+or1k32bf_h_sys_gpr382_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR382 (newval);
+}
+
+/* Get the value of h-sys-gpr383. */
+
+USI
+or1k32bf_h_sys_gpr383_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR383 ();
+}
+
+/* Set a value for h-sys-gpr383. */
+
+void
+or1k32bf_h_sys_gpr383_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR383 (newval);
+}
+
+/* Get the value of h-sys-gpr384. */
+
+USI
+or1k32bf_h_sys_gpr384_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR384 ();
+}
+
+/* Set a value for h-sys-gpr384. */
+
+void
+or1k32bf_h_sys_gpr384_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR384 (newval);
+}
+
+/* Get the value of h-sys-gpr385. */
+
+USI
+or1k32bf_h_sys_gpr385_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR385 ();
+}
+
+/* Set a value for h-sys-gpr385. */
+
+void
+or1k32bf_h_sys_gpr385_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR385 (newval);
+}
+
+/* Get the value of h-sys-gpr386. */
+
+USI
+or1k32bf_h_sys_gpr386_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR386 ();
+}
+
+/* Set a value for h-sys-gpr386. */
+
+void
+or1k32bf_h_sys_gpr386_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR386 (newval);
+}
+
+/* Get the value of h-sys-gpr387. */
+
+USI
+or1k32bf_h_sys_gpr387_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR387 ();
+}
+
+/* Set a value for h-sys-gpr387. */
+
+void
+or1k32bf_h_sys_gpr387_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR387 (newval);
+}
+
+/* Get the value of h-sys-gpr388. */
+
+USI
+or1k32bf_h_sys_gpr388_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR388 ();
+}
+
+/* Set a value for h-sys-gpr388. */
+
+void
+or1k32bf_h_sys_gpr388_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR388 (newval);
+}
+
+/* Get the value of h-sys-gpr389. */
+
+USI
+or1k32bf_h_sys_gpr389_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR389 ();
+}
+
+/* Set a value for h-sys-gpr389. */
+
+void
+or1k32bf_h_sys_gpr389_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR389 (newval);
+}
+
+/* Get the value of h-sys-gpr390. */
+
+USI
+or1k32bf_h_sys_gpr390_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR390 ();
+}
+
+/* Set a value for h-sys-gpr390. */
+
+void
+or1k32bf_h_sys_gpr390_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR390 (newval);
+}
+
+/* Get the value of h-sys-gpr391. */
+
+USI
+or1k32bf_h_sys_gpr391_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR391 ();
+}
+
+/* Set a value for h-sys-gpr391. */
+
+void
+or1k32bf_h_sys_gpr391_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR391 (newval);
+}
+
+/* Get the value of h-sys-gpr392. */
+
+USI
+or1k32bf_h_sys_gpr392_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR392 ();
+}
+
+/* Set a value for h-sys-gpr392. */
+
+void
+or1k32bf_h_sys_gpr392_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR392 (newval);
+}
+
+/* Get the value of h-sys-gpr393. */
+
+USI
+or1k32bf_h_sys_gpr393_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR393 ();
+}
+
+/* Set a value for h-sys-gpr393. */
+
+void
+or1k32bf_h_sys_gpr393_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR393 (newval);
+}
+
+/* Get the value of h-sys-gpr394. */
+
+USI
+or1k32bf_h_sys_gpr394_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR394 ();
+}
+
+/* Set a value for h-sys-gpr394. */
+
+void
+or1k32bf_h_sys_gpr394_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR394 (newval);
+}
+
+/* Get the value of h-sys-gpr395. */
+
+USI
+or1k32bf_h_sys_gpr395_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR395 ();
+}
+
+/* Set a value for h-sys-gpr395. */
+
+void
+or1k32bf_h_sys_gpr395_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR395 (newval);
+}
+
+/* Get the value of h-sys-gpr396. */
+
+USI
+or1k32bf_h_sys_gpr396_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR396 ();
+}
+
+/* Set a value for h-sys-gpr396. */
+
+void
+or1k32bf_h_sys_gpr396_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR396 (newval);
+}
+
+/* Get the value of h-sys-gpr397. */
+
+USI
+or1k32bf_h_sys_gpr397_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR397 ();
+}
+
+/* Set a value for h-sys-gpr397. */
+
+void
+or1k32bf_h_sys_gpr397_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR397 (newval);
+}
+
+/* Get the value of h-sys-gpr398. */
+
+USI
+or1k32bf_h_sys_gpr398_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR398 ();
+}
+
+/* Set a value for h-sys-gpr398. */
+
+void
+or1k32bf_h_sys_gpr398_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR398 (newval);
+}
+
+/* Get the value of h-sys-gpr399. */
+
+USI
+or1k32bf_h_sys_gpr399_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR399 ();
+}
+
+/* Set a value for h-sys-gpr399. */
+
+void
+or1k32bf_h_sys_gpr399_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR399 (newval);
+}
+
+/* Get the value of h-sys-gpr400. */
+
+USI
+or1k32bf_h_sys_gpr400_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR400 ();
+}
+
+/* Set a value for h-sys-gpr400. */
+
+void
+or1k32bf_h_sys_gpr400_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR400 (newval);
+}
+
+/* Get the value of h-sys-gpr401. */
+
+USI
+or1k32bf_h_sys_gpr401_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR401 ();
+}
+
+/* Set a value for h-sys-gpr401. */
+
+void
+or1k32bf_h_sys_gpr401_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR401 (newval);
+}
+
+/* Get the value of h-sys-gpr402. */
+
+USI
+or1k32bf_h_sys_gpr402_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR402 ();
+}
+
+/* Set a value for h-sys-gpr402. */
+
+void
+or1k32bf_h_sys_gpr402_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR402 (newval);
+}
+
+/* Get the value of h-sys-gpr403. */
+
+USI
+or1k32bf_h_sys_gpr403_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR403 ();
+}
+
+/* Set a value for h-sys-gpr403. */
+
+void
+or1k32bf_h_sys_gpr403_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR403 (newval);
+}
+
+/* Get the value of h-sys-gpr404. */
+
+USI
+or1k32bf_h_sys_gpr404_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR404 ();
+}
+
+/* Set a value for h-sys-gpr404. */
+
+void
+or1k32bf_h_sys_gpr404_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR404 (newval);
+}
+
+/* Get the value of h-sys-gpr405. */
+
+USI
+or1k32bf_h_sys_gpr405_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR405 ();
+}
+
+/* Set a value for h-sys-gpr405. */
+
+void
+or1k32bf_h_sys_gpr405_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR405 (newval);
+}
+
+/* Get the value of h-sys-gpr406. */
+
+USI
+or1k32bf_h_sys_gpr406_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR406 ();
+}
+
+/* Set a value for h-sys-gpr406. */
+
+void
+or1k32bf_h_sys_gpr406_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR406 (newval);
+}
+
+/* Get the value of h-sys-gpr407. */
+
+USI
+or1k32bf_h_sys_gpr407_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR407 ();
+}
+
+/* Set a value for h-sys-gpr407. */
+
+void
+or1k32bf_h_sys_gpr407_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR407 (newval);
+}
+
+/* Get the value of h-sys-gpr408. */
+
+USI
+or1k32bf_h_sys_gpr408_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR408 ();
+}
+
+/* Set a value for h-sys-gpr408. */
+
+void
+or1k32bf_h_sys_gpr408_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR408 (newval);
+}
+
+/* Get the value of h-sys-gpr409. */
+
+USI
+or1k32bf_h_sys_gpr409_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR409 ();
+}
+
+/* Set a value for h-sys-gpr409. */
+
+void
+or1k32bf_h_sys_gpr409_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR409 (newval);
+}
+
+/* Get the value of h-sys-gpr410. */
+
+USI
+or1k32bf_h_sys_gpr410_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR410 ();
+}
+
+/* Set a value for h-sys-gpr410. */
+
+void
+or1k32bf_h_sys_gpr410_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR410 (newval);
+}
+
+/* Get the value of h-sys-gpr411. */
+
+USI
+or1k32bf_h_sys_gpr411_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR411 ();
+}
+
+/* Set a value for h-sys-gpr411. */
+
+void
+or1k32bf_h_sys_gpr411_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR411 (newval);
+}
+
+/* Get the value of h-sys-gpr412. */
+
+USI
+or1k32bf_h_sys_gpr412_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR412 ();
+}
+
+/* Set a value for h-sys-gpr412. */
+
+void
+or1k32bf_h_sys_gpr412_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR412 (newval);
+}
+
+/* Get the value of h-sys-gpr413. */
+
+USI
+or1k32bf_h_sys_gpr413_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR413 ();
+}
+
+/* Set a value for h-sys-gpr413. */
+
+void
+or1k32bf_h_sys_gpr413_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR413 (newval);
+}
+
+/* Get the value of h-sys-gpr414. */
+
+USI
+or1k32bf_h_sys_gpr414_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR414 ();
+}
+
+/* Set a value for h-sys-gpr414. */
+
+void
+or1k32bf_h_sys_gpr414_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR414 (newval);
+}
+
+/* Get the value of h-sys-gpr415. */
+
+USI
+or1k32bf_h_sys_gpr415_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR415 ();
+}
+
+/* Set a value for h-sys-gpr415. */
+
+void
+or1k32bf_h_sys_gpr415_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR415 (newval);
+}
+
+/* Get the value of h-sys-gpr416. */
+
+USI
+or1k32bf_h_sys_gpr416_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR416 ();
+}
+
+/* Set a value for h-sys-gpr416. */
+
+void
+or1k32bf_h_sys_gpr416_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR416 (newval);
+}
+
+/* Get the value of h-sys-gpr417. */
+
+USI
+or1k32bf_h_sys_gpr417_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR417 ();
+}
+
+/* Set a value for h-sys-gpr417. */
+
+void
+or1k32bf_h_sys_gpr417_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR417 (newval);
+}
+
+/* Get the value of h-sys-gpr418. */
+
+USI
+or1k32bf_h_sys_gpr418_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR418 ();
+}
+
+/* Set a value for h-sys-gpr418. */
+
+void
+or1k32bf_h_sys_gpr418_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR418 (newval);
+}
+
+/* Get the value of h-sys-gpr419. */
+
+USI
+or1k32bf_h_sys_gpr419_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR419 ();
+}
+
+/* Set a value for h-sys-gpr419. */
+
+void
+or1k32bf_h_sys_gpr419_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR419 (newval);
+}
+
+/* Get the value of h-sys-gpr420. */
+
+USI
+or1k32bf_h_sys_gpr420_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR420 ();
+}
+
+/* Set a value for h-sys-gpr420. */
+
+void
+or1k32bf_h_sys_gpr420_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR420 (newval);
+}
+
+/* Get the value of h-sys-gpr421. */
+
+USI
+or1k32bf_h_sys_gpr421_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR421 ();
+}
+
+/* Set a value for h-sys-gpr421. */
+
+void
+or1k32bf_h_sys_gpr421_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR421 (newval);
+}
+
+/* Get the value of h-sys-gpr422. */
+
+USI
+or1k32bf_h_sys_gpr422_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR422 ();
+}
+
+/* Set a value for h-sys-gpr422. */
+
+void
+or1k32bf_h_sys_gpr422_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR422 (newval);
+}
+
+/* Get the value of h-sys-gpr423. */
+
+USI
+or1k32bf_h_sys_gpr423_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR423 ();
+}
+
+/* Set a value for h-sys-gpr423. */
+
+void
+or1k32bf_h_sys_gpr423_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR423 (newval);
+}
+
+/* Get the value of h-sys-gpr424. */
+
+USI
+or1k32bf_h_sys_gpr424_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR424 ();
+}
+
+/* Set a value for h-sys-gpr424. */
+
+void
+or1k32bf_h_sys_gpr424_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR424 (newval);
+}
+
+/* Get the value of h-sys-gpr425. */
+
+USI
+or1k32bf_h_sys_gpr425_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR425 ();
+}
+
+/* Set a value for h-sys-gpr425. */
+
+void
+or1k32bf_h_sys_gpr425_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR425 (newval);
+}
+
+/* Get the value of h-sys-gpr426. */
+
+USI
+or1k32bf_h_sys_gpr426_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR426 ();
+}
+
+/* Set a value for h-sys-gpr426. */
+
+void
+or1k32bf_h_sys_gpr426_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR426 (newval);
+}
+
+/* Get the value of h-sys-gpr427. */
+
+USI
+or1k32bf_h_sys_gpr427_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR427 ();
+}
+
+/* Set a value for h-sys-gpr427. */
+
+void
+or1k32bf_h_sys_gpr427_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR427 (newval);
+}
+
+/* Get the value of h-sys-gpr428. */
+
+USI
+or1k32bf_h_sys_gpr428_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR428 ();
+}
+
+/* Set a value for h-sys-gpr428. */
+
+void
+or1k32bf_h_sys_gpr428_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR428 (newval);
+}
+
+/* Get the value of h-sys-gpr429. */
+
+USI
+or1k32bf_h_sys_gpr429_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR429 ();
+}
+
+/* Set a value for h-sys-gpr429. */
+
+void
+or1k32bf_h_sys_gpr429_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR429 (newval);
+}
+
+/* Get the value of h-sys-gpr430. */
+
+USI
+or1k32bf_h_sys_gpr430_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR430 ();
+}
+
+/* Set a value for h-sys-gpr430. */
+
+void
+or1k32bf_h_sys_gpr430_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR430 (newval);
+}
+
+/* Get the value of h-sys-gpr431. */
+
+USI
+or1k32bf_h_sys_gpr431_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR431 ();
+}
+
+/* Set a value for h-sys-gpr431. */
+
+void
+or1k32bf_h_sys_gpr431_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR431 (newval);
+}
+
+/* Get the value of h-sys-gpr432. */
+
+USI
+or1k32bf_h_sys_gpr432_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR432 ();
+}
+
+/* Set a value for h-sys-gpr432. */
+
+void
+or1k32bf_h_sys_gpr432_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR432 (newval);
+}
+
+/* Get the value of h-sys-gpr433. */
+
+USI
+or1k32bf_h_sys_gpr433_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR433 ();
+}
+
+/* Set a value for h-sys-gpr433. */
+
+void
+or1k32bf_h_sys_gpr433_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR433 (newval);
+}
+
+/* Get the value of h-sys-gpr434. */
+
+USI
+or1k32bf_h_sys_gpr434_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR434 ();
+}
+
+/* Set a value for h-sys-gpr434. */
+
+void
+or1k32bf_h_sys_gpr434_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR434 (newval);
+}
+
+/* Get the value of h-sys-gpr435. */
+
+USI
+or1k32bf_h_sys_gpr435_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR435 ();
+}
+
+/* Set a value for h-sys-gpr435. */
+
+void
+or1k32bf_h_sys_gpr435_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR435 (newval);
+}
+
+/* Get the value of h-sys-gpr436. */
+
+USI
+or1k32bf_h_sys_gpr436_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR436 ();
+}
+
+/* Set a value for h-sys-gpr436. */
+
+void
+or1k32bf_h_sys_gpr436_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR436 (newval);
+}
+
+/* Get the value of h-sys-gpr437. */
+
+USI
+or1k32bf_h_sys_gpr437_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR437 ();
+}
+
+/* Set a value for h-sys-gpr437. */
+
+void
+or1k32bf_h_sys_gpr437_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR437 (newval);
+}
+
+/* Get the value of h-sys-gpr438. */
+
+USI
+or1k32bf_h_sys_gpr438_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR438 ();
+}
+
+/* Set a value for h-sys-gpr438. */
+
+void
+or1k32bf_h_sys_gpr438_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR438 (newval);
+}
+
+/* Get the value of h-sys-gpr439. */
+
+USI
+or1k32bf_h_sys_gpr439_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR439 ();
+}
+
+/* Set a value for h-sys-gpr439. */
+
+void
+or1k32bf_h_sys_gpr439_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR439 (newval);
+}
+
+/* Get the value of h-sys-gpr440. */
+
+USI
+or1k32bf_h_sys_gpr440_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR440 ();
+}
+
+/* Set a value for h-sys-gpr440. */
+
+void
+or1k32bf_h_sys_gpr440_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR440 (newval);
+}
+
+/* Get the value of h-sys-gpr441. */
+
+USI
+or1k32bf_h_sys_gpr441_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR441 ();
+}
+
+/* Set a value for h-sys-gpr441. */
+
+void
+or1k32bf_h_sys_gpr441_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR441 (newval);
+}
+
+/* Get the value of h-sys-gpr442. */
+
+USI
+or1k32bf_h_sys_gpr442_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR442 ();
+}
+
+/* Set a value for h-sys-gpr442. */
+
+void
+or1k32bf_h_sys_gpr442_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR442 (newval);
+}
+
+/* Get the value of h-sys-gpr443. */
+
+USI
+or1k32bf_h_sys_gpr443_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR443 ();
+}
+
+/* Set a value for h-sys-gpr443. */
+
+void
+or1k32bf_h_sys_gpr443_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR443 (newval);
+}
+
+/* Get the value of h-sys-gpr444. */
+
+USI
+or1k32bf_h_sys_gpr444_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR444 ();
+}
+
+/* Set a value for h-sys-gpr444. */
+
+void
+or1k32bf_h_sys_gpr444_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR444 (newval);
+}
+
+/* Get the value of h-sys-gpr445. */
+
+USI
+or1k32bf_h_sys_gpr445_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR445 ();
+}
+
+/* Set a value for h-sys-gpr445. */
+
+void
+or1k32bf_h_sys_gpr445_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR445 (newval);
+}
+
+/* Get the value of h-sys-gpr446. */
+
+USI
+or1k32bf_h_sys_gpr446_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR446 ();
+}
+
+/* Set a value for h-sys-gpr446. */
+
+void
+or1k32bf_h_sys_gpr446_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR446 (newval);
+}
+
+/* Get the value of h-sys-gpr447. */
+
+USI
+or1k32bf_h_sys_gpr447_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR447 ();
+}
+
+/* Set a value for h-sys-gpr447. */
+
+void
+or1k32bf_h_sys_gpr447_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR447 (newval);
+}
+
+/* Get the value of h-sys-gpr448. */
+
+USI
+or1k32bf_h_sys_gpr448_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR448 ();
+}
+
+/* Set a value for h-sys-gpr448. */
+
+void
+or1k32bf_h_sys_gpr448_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR448 (newval);
+}
+
+/* Get the value of h-sys-gpr449. */
+
+USI
+or1k32bf_h_sys_gpr449_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR449 ();
+}
+
+/* Set a value for h-sys-gpr449. */
+
+void
+or1k32bf_h_sys_gpr449_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR449 (newval);
+}
+
+/* Get the value of h-sys-gpr450. */
+
+USI
+or1k32bf_h_sys_gpr450_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR450 ();
+}
+
+/* Set a value for h-sys-gpr450. */
+
+void
+or1k32bf_h_sys_gpr450_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR450 (newval);
+}
+
+/* Get the value of h-sys-gpr451. */
+
+USI
+or1k32bf_h_sys_gpr451_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR451 ();
+}
+
+/* Set a value for h-sys-gpr451. */
+
+void
+or1k32bf_h_sys_gpr451_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR451 (newval);
+}
+
+/* Get the value of h-sys-gpr452. */
+
+USI
+or1k32bf_h_sys_gpr452_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR452 ();
+}
+
+/* Set a value for h-sys-gpr452. */
+
+void
+or1k32bf_h_sys_gpr452_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR452 (newval);
+}
+
+/* Get the value of h-sys-gpr453. */
+
+USI
+or1k32bf_h_sys_gpr453_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR453 ();
+}
+
+/* Set a value for h-sys-gpr453. */
+
+void
+or1k32bf_h_sys_gpr453_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR453 (newval);
+}
+
+/* Get the value of h-sys-gpr454. */
+
+USI
+or1k32bf_h_sys_gpr454_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR454 ();
+}
+
+/* Set a value for h-sys-gpr454. */
+
+void
+or1k32bf_h_sys_gpr454_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR454 (newval);
+}
+
+/* Get the value of h-sys-gpr455. */
+
+USI
+or1k32bf_h_sys_gpr455_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR455 ();
+}
+
+/* Set a value for h-sys-gpr455. */
+
+void
+or1k32bf_h_sys_gpr455_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR455 (newval);
+}
+
+/* Get the value of h-sys-gpr456. */
+
+USI
+or1k32bf_h_sys_gpr456_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR456 ();
+}
+
+/* Set a value for h-sys-gpr456. */
+
+void
+or1k32bf_h_sys_gpr456_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR456 (newval);
+}
+
+/* Get the value of h-sys-gpr457. */
+
+USI
+or1k32bf_h_sys_gpr457_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR457 ();
+}
+
+/* Set a value for h-sys-gpr457. */
+
+void
+or1k32bf_h_sys_gpr457_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR457 (newval);
+}
+
+/* Get the value of h-sys-gpr458. */
+
+USI
+or1k32bf_h_sys_gpr458_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR458 ();
+}
+
+/* Set a value for h-sys-gpr458. */
+
+void
+or1k32bf_h_sys_gpr458_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR458 (newval);
+}
+
+/* Get the value of h-sys-gpr459. */
+
+USI
+or1k32bf_h_sys_gpr459_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR459 ();
+}
+
+/* Set a value for h-sys-gpr459. */
+
+void
+or1k32bf_h_sys_gpr459_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR459 (newval);
+}
+
+/* Get the value of h-sys-gpr460. */
+
+USI
+or1k32bf_h_sys_gpr460_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR460 ();
+}
+
+/* Set a value for h-sys-gpr460. */
+
+void
+or1k32bf_h_sys_gpr460_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR460 (newval);
+}
+
+/* Get the value of h-sys-gpr461. */
+
+USI
+or1k32bf_h_sys_gpr461_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR461 ();
+}
+
+/* Set a value for h-sys-gpr461. */
+
+void
+or1k32bf_h_sys_gpr461_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR461 (newval);
+}
+
+/* Get the value of h-sys-gpr462. */
+
+USI
+or1k32bf_h_sys_gpr462_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR462 ();
+}
+
+/* Set a value for h-sys-gpr462. */
+
+void
+or1k32bf_h_sys_gpr462_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR462 (newval);
+}
+
+/* Get the value of h-sys-gpr463. */
+
+USI
+or1k32bf_h_sys_gpr463_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR463 ();
+}
+
+/* Set a value for h-sys-gpr463. */
+
+void
+or1k32bf_h_sys_gpr463_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR463 (newval);
+}
+
+/* Get the value of h-sys-gpr464. */
+
+USI
+or1k32bf_h_sys_gpr464_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR464 ();
+}
+
+/* Set a value for h-sys-gpr464. */
+
+void
+or1k32bf_h_sys_gpr464_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR464 (newval);
+}
+
+/* Get the value of h-sys-gpr465. */
+
+USI
+or1k32bf_h_sys_gpr465_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR465 ();
+}
+
+/* Set a value for h-sys-gpr465. */
+
+void
+or1k32bf_h_sys_gpr465_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR465 (newval);
+}
+
+/* Get the value of h-sys-gpr466. */
+
+USI
+or1k32bf_h_sys_gpr466_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR466 ();
+}
+
+/* Set a value for h-sys-gpr466. */
+
+void
+or1k32bf_h_sys_gpr466_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR466 (newval);
+}
+
+/* Get the value of h-sys-gpr467. */
+
+USI
+or1k32bf_h_sys_gpr467_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR467 ();
+}
+
+/* Set a value for h-sys-gpr467. */
+
+void
+or1k32bf_h_sys_gpr467_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR467 (newval);
+}
+
+/* Get the value of h-sys-gpr468. */
+
+USI
+or1k32bf_h_sys_gpr468_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR468 ();
+}
+
+/* Set a value for h-sys-gpr468. */
+
+void
+or1k32bf_h_sys_gpr468_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR468 (newval);
+}
+
+/* Get the value of h-sys-gpr469. */
+
+USI
+or1k32bf_h_sys_gpr469_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR469 ();
+}
+
+/* Set a value for h-sys-gpr469. */
+
+void
+or1k32bf_h_sys_gpr469_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR469 (newval);
+}
+
+/* Get the value of h-sys-gpr470. */
+
+USI
+or1k32bf_h_sys_gpr470_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR470 ();
+}
+
+/* Set a value for h-sys-gpr470. */
+
+void
+or1k32bf_h_sys_gpr470_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR470 (newval);
+}
+
+/* Get the value of h-sys-gpr471. */
+
+USI
+or1k32bf_h_sys_gpr471_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR471 ();
+}
+
+/* Set a value for h-sys-gpr471. */
+
+void
+or1k32bf_h_sys_gpr471_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR471 (newval);
+}
+
+/* Get the value of h-sys-gpr472. */
+
+USI
+or1k32bf_h_sys_gpr472_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR472 ();
+}
+
+/* Set a value for h-sys-gpr472. */
+
+void
+or1k32bf_h_sys_gpr472_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR472 (newval);
+}
+
+/* Get the value of h-sys-gpr473. */
+
+USI
+or1k32bf_h_sys_gpr473_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR473 ();
+}
+
+/* Set a value for h-sys-gpr473. */
+
+void
+or1k32bf_h_sys_gpr473_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR473 (newval);
+}
+
+/* Get the value of h-sys-gpr474. */
+
+USI
+or1k32bf_h_sys_gpr474_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR474 ();
+}
+
+/* Set a value for h-sys-gpr474. */
+
+void
+or1k32bf_h_sys_gpr474_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR474 (newval);
+}
+
+/* Get the value of h-sys-gpr475. */
+
+USI
+or1k32bf_h_sys_gpr475_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR475 ();
+}
+
+/* Set a value for h-sys-gpr475. */
+
+void
+or1k32bf_h_sys_gpr475_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR475 (newval);
+}
+
+/* Get the value of h-sys-gpr476. */
+
+USI
+or1k32bf_h_sys_gpr476_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR476 ();
+}
+
+/* Set a value for h-sys-gpr476. */
+
+void
+or1k32bf_h_sys_gpr476_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR476 (newval);
+}
+
+/* Get the value of h-sys-gpr477. */
+
+USI
+or1k32bf_h_sys_gpr477_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR477 ();
+}
+
+/* Set a value for h-sys-gpr477. */
+
+void
+or1k32bf_h_sys_gpr477_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR477 (newval);
+}
+
+/* Get the value of h-sys-gpr478. */
+
+USI
+or1k32bf_h_sys_gpr478_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR478 ();
+}
+
+/* Set a value for h-sys-gpr478. */
+
+void
+or1k32bf_h_sys_gpr478_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR478 (newval);
+}
+
+/* Get the value of h-sys-gpr479. */
+
+USI
+or1k32bf_h_sys_gpr479_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR479 ();
+}
+
+/* Set a value for h-sys-gpr479. */
+
+void
+or1k32bf_h_sys_gpr479_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR479 (newval);
+}
+
+/* Get the value of h-sys-gpr480. */
+
+USI
+or1k32bf_h_sys_gpr480_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR480 ();
+}
+
+/* Set a value for h-sys-gpr480. */
+
+void
+or1k32bf_h_sys_gpr480_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR480 (newval);
+}
+
+/* Get the value of h-sys-gpr481. */
+
+USI
+or1k32bf_h_sys_gpr481_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR481 ();
+}
+
+/* Set a value for h-sys-gpr481. */
+
+void
+or1k32bf_h_sys_gpr481_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR481 (newval);
+}
+
+/* Get the value of h-sys-gpr482. */
+
+USI
+or1k32bf_h_sys_gpr482_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR482 ();
+}
+
+/* Set a value for h-sys-gpr482. */
+
+void
+or1k32bf_h_sys_gpr482_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR482 (newval);
+}
+
+/* Get the value of h-sys-gpr483. */
+
+USI
+or1k32bf_h_sys_gpr483_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR483 ();
+}
+
+/* Set a value for h-sys-gpr483. */
+
+void
+or1k32bf_h_sys_gpr483_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR483 (newval);
+}
+
+/* Get the value of h-sys-gpr484. */
+
+USI
+or1k32bf_h_sys_gpr484_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR484 ();
+}
+
+/* Set a value for h-sys-gpr484. */
+
+void
+or1k32bf_h_sys_gpr484_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR484 (newval);
+}
+
+/* Get the value of h-sys-gpr485. */
+
+USI
+or1k32bf_h_sys_gpr485_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR485 ();
+}
+
+/* Set a value for h-sys-gpr485. */
+
+void
+or1k32bf_h_sys_gpr485_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR485 (newval);
+}
+
+/* Get the value of h-sys-gpr486. */
+
+USI
+or1k32bf_h_sys_gpr486_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR486 ();
+}
+
+/* Set a value for h-sys-gpr486. */
+
+void
+or1k32bf_h_sys_gpr486_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR486 (newval);
+}
+
+/* Get the value of h-sys-gpr487. */
+
+USI
+or1k32bf_h_sys_gpr487_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR487 ();
+}
+
+/* Set a value for h-sys-gpr487. */
+
+void
+or1k32bf_h_sys_gpr487_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR487 (newval);
+}
+
+/* Get the value of h-sys-gpr488. */
+
+USI
+or1k32bf_h_sys_gpr488_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR488 ();
+}
+
+/* Set a value for h-sys-gpr488. */
+
+void
+or1k32bf_h_sys_gpr488_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR488 (newval);
+}
+
+/* Get the value of h-sys-gpr489. */
+
+USI
+or1k32bf_h_sys_gpr489_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR489 ();
+}
+
+/* Set a value for h-sys-gpr489. */
+
+void
+or1k32bf_h_sys_gpr489_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR489 (newval);
+}
+
+/* Get the value of h-sys-gpr490. */
+
+USI
+or1k32bf_h_sys_gpr490_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR490 ();
+}
+
+/* Set a value for h-sys-gpr490. */
+
+void
+or1k32bf_h_sys_gpr490_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR490 (newval);
+}
+
+/* Get the value of h-sys-gpr491. */
+
+USI
+or1k32bf_h_sys_gpr491_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR491 ();
+}
+
+/* Set a value for h-sys-gpr491. */
+
+void
+or1k32bf_h_sys_gpr491_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR491 (newval);
+}
+
+/* Get the value of h-sys-gpr492. */
+
+USI
+or1k32bf_h_sys_gpr492_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR492 ();
+}
+
+/* Set a value for h-sys-gpr492. */
+
+void
+or1k32bf_h_sys_gpr492_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR492 (newval);
+}
+
+/* Get the value of h-sys-gpr493. */
+
+USI
+or1k32bf_h_sys_gpr493_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR493 ();
+}
+
+/* Set a value for h-sys-gpr493. */
+
+void
+or1k32bf_h_sys_gpr493_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR493 (newval);
+}
+
+/* Get the value of h-sys-gpr494. */
+
+USI
+or1k32bf_h_sys_gpr494_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR494 ();
+}
+
+/* Set a value for h-sys-gpr494. */
+
+void
+or1k32bf_h_sys_gpr494_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR494 (newval);
+}
+
+/* Get the value of h-sys-gpr495. */
+
+USI
+or1k32bf_h_sys_gpr495_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR495 ();
+}
+
+/* Set a value for h-sys-gpr495. */
+
+void
+or1k32bf_h_sys_gpr495_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR495 (newval);
+}
+
+/* Get the value of h-sys-gpr496. */
+
+USI
+or1k32bf_h_sys_gpr496_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR496 ();
+}
+
+/* Set a value for h-sys-gpr496. */
+
+void
+or1k32bf_h_sys_gpr496_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR496 (newval);
+}
+
+/* Get the value of h-sys-gpr497. */
+
+USI
+or1k32bf_h_sys_gpr497_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR497 ();
+}
+
+/* Set a value for h-sys-gpr497. */
+
+void
+or1k32bf_h_sys_gpr497_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR497 (newval);
+}
+
+/* Get the value of h-sys-gpr498. */
+
+USI
+or1k32bf_h_sys_gpr498_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR498 ();
+}
+
+/* Set a value for h-sys-gpr498. */
+
+void
+or1k32bf_h_sys_gpr498_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR498 (newval);
+}
+
+/* Get the value of h-sys-gpr499. */
+
+USI
+or1k32bf_h_sys_gpr499_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR499 ();
+}
+
+/* Set a value for h-sys-gpr499. */
+
+void
+or1k32bf_h_sys_gpr499_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR499 (newval);
+}
+
+/* Get the value of h-sys-gpr500. */
+
+USI
+or1k32bf_h_sys_gpr500_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR500 ();
+}
+
+/* Set a value for h-sys-gpr500. */
+
+void
+or1k32bf_h_sys_gpr500_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR500 (newval);
+}
+
+/* Get the value of h-sys-gpr501. */
+
+USI
+or1k32bf_h_sys_gpr501_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR501 ();
+}
+
+/* Set a value for h-sys-gpr501. */
+
+void
+or1k32bf_h_sys_gpr501_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR501 (newval);
+}
+
+/* Get the value of h-sys-gpr502. */
+
+USI
+or1k32bf_h_sys_gpr502_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR502 ();
+}
+
+/* Set a value for h-sys-gpr502. */
+
+void
+or1k32bf_h_sys_gpr502_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR502 (newval);
+}
+
+/* Get the value of h-sys-gpr503. */
+
+USI
+or1k32bf_h_sys_gpr503_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR503 ();
+}
+
+/* Set a value for h-sys-gpr503. */
+
+void
+or1k32bf_h_sys_gpr503_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR503 (newval);
+}
+
+/* Get the value of h-sys-gpr504. */
+
+USI
+or1k32bf_h_sys_gpr504_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR504 ();
+}
+
+/* Set a value for h-sys-gpr504. */
+
+void
+or1k32bf_h_sys_gpr504_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR504 (newval);
+}
+
+/* Get the value of h-sys-gpr505. */
+
+USI
+or1k32bf_h_sys_gpr505_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR505 ();
+}
+
+/* Set a value for h-sys-gpr505. */
+
+void
+or1k32bf_h_sys_gpr505_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR505 (newval);
+}
+
+/* Get the value of h-sys-gpr506. */
+
+USI
+or1k32bf_h_sys_gpr506_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR506 ();
+}
+
+/* Set a value for h-sys-gpr506. */
+
+void
+or1k32bf_h_sys_gpr506_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR506 (newval);
+}
+
+/* Get the value of h-sys-gpr507. */
+
+USI
+or1k32bf_h_sys_gpr507_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR507 ();
+}
+
+/* Set a value for h-sys-gpr507. */
+
+void
+or1k32bf_h_sys_gpr507_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR507 (newval);
+}
+
+/* Get the value of h-sys-gpr508. */
+
+USI
+or1k32bf_h_sys_gpr508_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR508 ();
+}
+
+/* Set a value for h-sys-gpr508. */
+
+void
+or1k32bf_h_sys_gpr508_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR508 (newval);
+}
+
+/* Get the value of h-sys-gpr509. */
+
+USI
+or1k32bf_h_sys_gpr509_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR509 ();
+}
+
+/* Set a value for h-sys-gpr509. */
+
+void
+or1k32bf_h_sys_gpr509_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR509 (newval);
+}
+
+/* Get the value of h-sys-gpr510. */
+
+USI
+or1k32bf_h_sys_gpr510_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR510 ();
+}
+
+/* Set a value for h-sys-gpr510. */
+
+void
+or1k32bf_h_sys_gpr510_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR510 (newval);
+}
+
+/* Get the value of h-sys-gpr511. */
+
+USI
+or1k32bf_h_sys_gpr511_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_GPR511 ();
+}
+
+/* Set a value for h-sys-gpr511. */
+
+void
+or1k32bf_h_sys_gpr511_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_GPR511 (newval);
+}
+
+/* Get the value of h-mac-maclo. */
+
+USI
+or1k32bf_h_mac_maclo_get (SIM_CPU *current_cpu)
+{
+ return GET_H_MAC_MACLO ();
+}
+
+/* Set a value for h-mac-maclo. */
+
+void
+or1k32bf_h_mac_maclo_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_MAC_MACLO (newval);
+}
+
+/* Get the value of h-mac-machi. */
+
+USI
+or1k32bf_h_mac_machi_get (SIM_CPU *current_cpu)
+{
+ return GET_H_MAC_MACHI ();
+}
+
+/* Set a value for h-mac-machi. */
+
+void
+or1k32bf_h_mac_machi_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_MAC_MACHI (newval);
+}
+
+/* Get the value of h-tick-ttmr. */
+
+USI
+or1k32bf_h_tick_ttmr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_TICK_TTMR ();
+}
+
+/* Set a value for h-tick-ttmr. */
+
+void
+or1k32bf_h_tick_ttmr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_TICK_TTMR (newval);
+}
+
+/* Get the value of h-sys-vr-rev. */
+
+USI
+or1k32bf_h_sys_vr_rev_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_VR_REV ();
+}
+
+/* Set a value for h-sys-vr-rev. */
+
+void
+or1k32bf_h_sys_vr_rev_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_VR_REV (newval);
+}
+
+/* Get the value of h-sys-vr-cfg. */
+
+USI
+or1k32bf_h_sys_vr_cfg_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_VR_CFG ();
+}
+
+/* Set a value for h-sys-vr-cfg. */
+
+void
+or1k32bf_h_sys_vr_cfg_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_VR_CFG (newval);
+}
+
+/* Get the value of h-sys-vr-ver. */
+
+USI
+or1k32bf_h_sys_vr_ver_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_VR_VER ();
+}
+
+/* Set a value for h-sys-vr-ver. */
+
+void
+or1k32bf_h_sys_vr_ver_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_VR_VER (newval);
+}
+
+/* Get the value of h-sys-upr-up. */
+
+USI
+or1k32bf_h_sys_upr_up_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_UP ();
+}
+
+/* Set a value for h-sys-upr-up. */
+
+void
+or1k32bf_h_sys_upr_up_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_UP (newval);
+}
+
+/* Get the value of h-sys-upr-dcp. */
+
+USI
+or1k32bf_h_sys_upr_dcp_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_DCP ();
+}
+
+/* Set a value for h-sys-upr-dcp. */
+
+void
+or1k32bf_h_sys_upr_dcp_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_DCP (newval);
+}
+
+/* Get the value of h-sys-upr-icp. */
+
+USI
+or1k32bf_h_sys_upr_icp_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_ICP ();
+}
+
+/* Set a value for h-sys-upr-icp. */
+
+void
+or1k32bf_h_sys_upr_icp_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_ICP (newval);
+}
+
+/* Get the value of h-sys-upr-dmp. */
+
+USI
+or1k32bf_h_sys_upr_dmp_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_DMP ();
+}
+
+/* Set a value for h-sys-upr-dmp. */
+
+void
+or1k32bf_h_sys_upr_dmp_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_DMP (newval);
+}
+
+/* Get the value of h-sys-upr-mp. */
+
+USI
+or1k32bf_h_sys_upr_mp_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_MP ();
+}
+
+/* Set a value for h-sys-upr-mp. */
+
+void
+or1k32bf_h_sys_upr_mp_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_MP (newval);
+}
+
+/* Get the value of h-sys-upr-imp. */
+
+USI
+or1k32bf_h_sys_upr_imp_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_IMP ();
+}
+
+/* Set a value for h-sys-upr-imp. */
+
+void
+or1k32bf_h_sys_upr_imp_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_IMP (newval);
+}
+
+/* Get the value of h-sys-upr-dup. */
+
+USI
+or1k32bf_h_sys_upr_dup_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_DUP ();
+}
+
+/* Set a value for h-sys-upr-dup. */
+
+void
+or1k32bf_h_sys_upr_dup_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_DUP (newval);
+}
+
+/* Get the value of h-sys-upr-pcup. */
+
+USI
+or1k32bf_h_sys_upr_pcup_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_PCUP ();
+}
+
+/* Set a value for h-sys-upr-pcup. */
+
+void
+or1k32bf_h_sys_upr_pcup_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_PCUP (newval);
+}
+
+/* Get the value of h-sys-upr-picp. */
+
+USI
+or1k32bf_h_sys_upr_picp_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_PICP ();
+}
+
+/* Set a value for h-sys-upr-picp. */
+
+void
+or1k32bf_h_sys_upr_picp_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_PICP (newval);
+}
+
+/* Get the value of h-sys-upr-pmp. */
+
+USI
+or1k32bf_h_sys_upr_pmp_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_PMP ();
+}
+
+/* Set a value for h-sys-upr-pmp. */
+
+void
+or1k32bf_h_sys_upr_pmp_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_PMP (newval);
+}
+
+/* Get the value of h-sys-upr-ttp. */
+
+USI
+or1k32bf_h_sys_upr_ttp_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_TTP ();
+}
+
+/* Set a value for h-sys-upr-ttp. */
+
+void
+or1k32bf_h_sys_upr_ttp_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_TTP (newval);
+}
+
+/* Get the value of h-sys-upr-cup. */
+
+USI
+or1k32bf_h_sys_upr_cup_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_UPR_CUP ();
+}
+
+/* Set a value for h-sys-upr-cup. */
+
+void
+or1k32bf_h_sys_upr_cup_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_UPR_CUP (newval);
+}
+
+/* Get the value of h-sys-cpucfgr-nsgr. */
+
+USI
+or1k32bf_h_sys_cpucfgr_nsgr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_CPUCFGR_NSGR ();
+}
+
+/* Set a value for h-sys-cpucfgr-nsgr. */
+
+void
+or1k32bf_h_sys_cpucfgr_nsgr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_CPUCFGR_NSGR (newval);
+}
+
+/* Get the value of h-sys-cpucfgr-cgf. */
+
+USI
+or1k32bf_h_sys_cpucfgr_cgf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_CPUCFGR_CGF ();
+}
+
+/* Set a value for h-sys-cpucfgr-cgf. */
+
+void
+or1k32bf_h_sys_cpucfgr_cgf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_CPUCFGR_CGF (newval);
+}
+
+/* Get the value of h-sys-cpucfgr-ob32s. */
+
+USI
+or1k32bf_h_sys_cpucfgr_ob32s_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_CPUCFGR_OB32S ();
+}
+
+/* Set a value for h-sys-cpucfgr-ob32s. */
+
+void
+or1k32bf_h_sys_cpucfgr_ob32s_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_CPUCFGR_OB32S (newval);
+}
+
+/* Get the value of h-sys-cpucfgr-ob64s. */
+
+USI
+or1k32bf_h_sys_cpucfgr_ob64s_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_CPUCFGR_OB64S ();
+}
+
+/* Set a value for h-sys-cpucfgr-ob64s. */
+
+void
+or1k32bf_h_sys_cpucfgr_ob64s_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_CPUCFGR_OB64S (newval);
+}
+
+/* Get the value of h-sys-cpucfgr-of32s. */
+
+USI
+or1k32bf_h_sys_cpucfgr_of32s_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_CPUCFGR_OF32S ();
+}
+
+/* Set a value for h-sys-cpucfgr-of32s. */
+
+void
+or1k32bf_h_sys_cpucfgr_of32s_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_CPUCFGR_OF32S (newval);
+}
+
+/* Get the value of h-sys-cpucfgr-of64s. */
+
+USI
+or1k32bf_h_sys_cpucfgr_of64s_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_CPUCFGR_OF64S ();
+}
+
+/* Set a value for h-sys-cpucfgr-of64s. */
+
+void
+or1k32bf_h_sys_cpucfgr_of64s_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_CPUCFGR_OF64S (newval);
+}
+
+/* Get the value of h-sys-cpucfgr-ov64s. */
+
+USI
+or1k32bf_h_sys_cpucfgr_ov64s_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_CPUCFGR_OV64S ();
+}
+
+/* Set a value for h-sys-cpucfgr-ov64s. */
+
+void
+or1k32bf_h_sys_cpucfgr_ov64s_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_CPUCFGR_OV64S (newval);
+}
+
+/* Get the value of h-sys-cpucfgr-nd. */
+
+USI
+or1k32bf_h_sys_cpucfgr_nd_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_CPUCFGR_ND ();
+}
+
+/* Set a value for h-sys-cpucfgr-nd. */
+
+void
+or1k32bf_h_sys_cpucfgr_nd_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_CPUCFGR_ND (newval);
+}
+
+/* Get the value of h-sys-sr-sm. */
+
+USI
+or1k32bf_h_sys_sr_sm_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_SM ();
+}
+
+/* Set a value for h-sys-sr-sm. */
+
+void
+or1k32bf_h_sys_sr_sm_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_SM (newval);
+}
+
+/* Get the value of h-sys-sr-tee. */
+
+USI
+or1k32bf_h_sys_sr_tee_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_TEE ();
+}
+
+/* Set a value for h-sys-sr-tee. */
+
+void
+or1k32bf_h_sys_sr_tee_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_TEE (newval);
+}
+
+/* Get the value of h-sys-sr-iee. */
+
+USI
+or1k32bf_h_sys_sr_iee_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_IEE ();
+}
+
+/* Set a value for h-sys-sr-iee. */
+
+void
+or1k32bf_h_sys_sr_iee_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_IEE (newval);
+}
+
+/* Get the value of h-sys-sr-dce. */
+
+USI
+or1k32bf_h_sys_sr_dce_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_DCE ();
+}
+
+/* Set a value for h-sys-sr-dce. */
+
+void
+or1k32bf_h_sys_sr_dce_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_DCE (newval);
+}
+
+/* Get the value of h-sys-sr-ice. */
+
+USI
+or1k32bf_h_sys_sr_ice_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_ICE ();
+}
+
+/* Set a value for h-sys-sr-ice. */
+
+void
+or1k32bf_h_sys_sr_ice_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_ICE (newval);
+}
+
+/* Get the value of h-sys-sr-dme. */
+
+USI
+or1k32bf_h_sys_sr_dme_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_DME ();
+}
+
+/* Set a value for h-sys-sr-dme. */
+
+void
+or1k32bf_h_sys_sr_dme_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_DME (newval);
+}
+
+/* Get the value of h-sys-sr-ime. */
+
+USI
+or1k32bf_h_sys_sr_ime_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_IME ();
+}
+
+/* Set a value for h-sys-sr-ime. */
+
+void
+or1k32bf_h_sys_sr_ime_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_IME (newval);
+}
+
+/* Get the value of h-sys-sr-lee. */
+
+USI
+or1k32bf_h_sys_sr_lee_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_LEE ();
+}
+
+/* Set a value for h-sys-sr-lee. */
+
+void
+or1k32bf_h_sys_sr_lee_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_LEE (newval);
+}
+
+/* Get the value of h-sys-sr-ce. */
+
+USI
+or1k32bf_h_sys_sr_ce_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_CE ();
+}
+
+/* Set a value for h-sys-sr-ce. */
+
+void
+or1k32bf_h_sys_sr_ce_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_CE (newval);
+}
+
+/* Get the value of h-sys-sr-f. */
+
+USI
+or1k32bf_h_sys_sr_f_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_F ();
+}
+
+/* Set a value for h-sys-sr-f. */
+
+void
+or1k32bf_h_sys_sr_f_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_F (newval);
+}
+
+/* Get the value of h-sys-sr-cy. */
+
+USI
+or1k32bf_h_sys_sr_cy_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_CY ();
+}
+
+/* Set a value for h-sys-sr-cy. */
+
+void
+or1k32bf_h_sys_sr_cy_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_CY (newval);
+}
+
+/* Get the value of h-sys-sr-ov. */
+
+USI
+or1k32bf_h_sys_sr_ov_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_OV ();
+}
+
+/* Set a value for h-sys-sr-ov. */
+
+void
+or1k32bf_h_sys_sr_ov_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_OV (newval);
+}
+
+/* Get the value of h-sys-sr-ove. */
+
+USI
+or1k32bf_h_sys_sr_ove_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_OVE ();
+}
+
+/* Set a value for h-sys-sr-ove. */
+
+void
+or1k32bf_h_sys_sr_ove_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_OVE (newval);
+}
+
+/* Get the value of h-sys-sr-dsx. */
+
+USI
+or1k32bf_h_sys_sr_dsx_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_DSX ();
+}
+
+/* Set a value for h-sys-sr-dsx. */
+
+void
+or1k32bf_h_sys_sr_dsx_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_DSX (newval);
+}
+
+/* Get the value of h-sys-sr-eph. */
+
+USI
+or1k32bf_h_sys_sr_eph_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_EPH ();
+}
+
+/* Set a value for h-sys-sr-eph. */
+
+void
+or1k32bf_h_sys_sr_eph_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_EPH (newval);
+}
+
+/* Get the value of h-sys-sr-fo. */
+
+USI
+or1k32bf_h_sys_sr_fo_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_FO ();
+}
+
+/* Set a value for h-sys-sr-fo. */
+
+void
+or1k32bf_h_sys_sr_fo_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_FO (newval);
+}
+
+/* Get the value of h-sys-sr-sumra. */
+
+USI
+or1k32bf_h_sys_sr_sumra_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_SUMRA ();
+}
+
+/* Set a value for h-sys-sr-sumra. */
+
+void
+or1k32bf_h_sys_sr_sumra_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_SUMRA (newval);
+}
+
+/* Get the value of h-sys-sr-cid. */
+
+USI
+or1k32bf_h_sys_sr_cid_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_SR_CID ();
+}
+
+/* Set a value for h-sys-sr-cid. */
+
+void
+or1k32bf_h_sys_sr_cid_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_SR_CID (newval);
+}
+
+/* Get the value of h-sys-fpcsr-fpee. */
+
+USI
+or1k32bf_h_sys_fpcsr_fpee_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_FPEE ();
+}
+
+/* Set a value for h-sys-fpcsr-fpee. */
+
+void
+or1k32bf_h_sys_fpcsr_fpee_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_FPEE (newval);
+}
+
+/* Get the value of h-sys-fpcsr-rm. */
+
+USI
+or1k32bf_h_sys_fpcsr_rm_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_RM ();
+}
+
+/* Set a value for h-sys-fpcsr-rm. */
+
+void
+or1k32bf_h_sys_fpcsr_rm_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_RM (newval);
+}
+
+/* Get the value of h-sys-fpcsr-ovf. */
+
+USI
+or1k32bf_h_sys_fpcsr_ovf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_OVF ();
+}
+
+/* Set a value for h-sys-fpcsr-ovf. */
+
+void
+or1k32bf_h_sys_fpcsr_ovf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_OVF (newval);
+}
+
+/* Get the value of h-sys-fpcsr-unf. */
+
+USI
+or1k32bf_h_sys_fpcsr_unf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_UNF ();
+}
+
+/* Set a value for h-sys-fpcsr-unf. */
+
+void
+or1k32bf_h_sys_fpcsr_unf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_UNF (newval);
+}
+
+/* Get the value of h-sys-fpcsr-snf. */
+
+USI
+or1k32bf_h_sys_fpcsr_snf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_SNF ();
+}
+
+/* Set a value for h-sys-fpcsr-snf. */
+
+void
+or1k32bf_h_sys_fpcsr_snf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_SNF (newval);
+}
+
+/* Get the value of h-sys-fpcsr-qnf. */
+
+USI
+or1k32bf_h_sys_fpcsr_qnf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_QNF ();
+}
+
+/* Set a value for h-sys-fpcsr-qnf. */
+
+void
+or1k32bf_h_sys_fpcsr_qnf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_QNF (newval);
+}
+
+/* Get the value of h-sys-fpcsr-zf. */
+
+USI
+or1k32bf_h_sys_fpcsr_zf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_ZF ();
+}
+
+/* Set a value for h-sys-fpcsr-zf. */
+
+void
+or1k32bf_h_sys_fpcsr_zf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_ZF (newval);
+}
+
+/* Get the value of h-sys-fpcsr-ixf. */
+
+USI
+or1k32bf_h_sys_fpcsr_ixf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_IXF ();
+}
+
+/* Set a value for h-sys-fpcsr-ixf. */
+
+void
+or1k32bf_h_sys_fpcsr_ixf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_IXF (newval);
+}
+
+/* Get the value of h-sys-fpcsr-ivf. */
+
+USI
+or1k32bf_h_sys_fpcsr_ivf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_IVF ();
+}
+
+/* Set a value for h-sys-fpcsr-ivf. */
+
+void
+or1k32bf_h_sys_fpcsr_ivf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_IVF (newval);
+}
+
+/* Get the value of h-sys-fpcsr-inf. */
+
+USI
+or1k32bf_h_sys_fpcsr_inf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_INF ();
+}
+
+/* Set a value for h-sys-fpcsr-inf. */
+
+void
+or1k32bf_h_sys_fpcsr_inf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_INF (newval);
+}
+
+/* Get the value of h-sys-fpcsr-dzf. */
+
+USI
+or1k32bf_h_sys_fpcsr_dzf_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SYS_FPCSR_DZF ();
+}
+
+/* Set a value for h-sys-fpcsr-dzf. */
+
+void
+or1k32bf_h_sys_fpcsr_dzf_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_SYS_FPCSR_DZF (newval);
+}
+
+/* Get the value of h-atomic-reserve. */
+
+BI
+or1k32bf_h_atomic_reserve_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_atomic_reserve);
+}
+
+/* Set a value for h-atomic-reserve. */
+
+void
+or1k32bf_h_atomic_reserve_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_atomic_reserve) = newval;
+}
+
+/* Get the value of h-atomic-address. */
+
+SI
+or1k32bf_h_atomic_address_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_atomic_address);
+}
+
+/* Set a value for h-atomic-address. */
+
+void
+or1k32bf_h_atomic_address_set (SIM_CPU *current_cpu, SI newval)
+{
+ CPU (h_atomic_address) = newval;
+}
+
+/* Record trace results for INSN. */
+
+void
+or1k32bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+ int *indices, TRACE_RECORD *tr)
+{
+}
--- /dev/null
+/* CPU family header for or1k32bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef CPU_OR1K32BF_H
+#define CPU_OR1K32BF_H
+
+/* Maximum number of instructions that are fetched at a time.
+ This is for LIW type instructions sets (e.g. m32r). */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel. */
+#define MAX_PARALLEL_INSNS 1
+
+/* The size of an "int" needed to hold an instruction word.
+ This is usually 32 bits, but some architectures needs 64 bits. */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
+/* CPU state information. */
+typedef struct {
+ /* Hardware elements. */
+ struct {
+ /* program counter */
+ USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) \
+do { \
+{\
+SET_H_SYS_PPC (CPU (h_pc));\
+CPU (h_pc) = (x);\
+}\
+;} while (0)
+ /* general registers */
+ USI h_gpr[32];
+#define GET_H_GPR(index) GET_H_SPR (((index) + (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))))
+#define SET_H_GPR(index, x) \
+do { \
+SET_H_SPR ((((index)) + (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))), (x));\
+;} while (0)
+ /* atomic reserve flag */
+ BI h_atomic_reserve;
+#define GET_H_ATOMIC_RESERVE() CPU (h_atomic_reserve)
+#define SET_H_ATOMIC_RESERVE(x) (CPU (h_atomic_reserve) = (x))
+ /* atomic reserve address */
+ SI h_atomic_address;
+#define GET_H_ATOMIC_ADDRESS() CPU (h_atomic_address)
+#define SET_H_ATOMIC_ADDRESS(x) (CPU (h_atomic_address) = (x))
+ } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} OR1K32BF_CPU_DATA;
+
+/* Virtual regs. */
+
+#define GET_H_FSR(index) SUBWORDSISF (TRUNCSISI (GET_H_GPR (index)))
+#define SET_H_FSR(index, x) \
+do { \
+SET_H_GPR ((index), ZEXTSISI (SUBWORDSFSI ((x))));\
+;} while (0)
+#define GET_H_SPR(index) or1k32bf_h_spr_get_raw (current_cpu, index)
+#define SET_H_SPR(index, x) \
+do { \
+or1k32bf_h_spr_set_raw (current_cpu, (index), (x));\
+;} while (0)
+#define GET_H_SYS_VR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR))
+#define SET_H_SYS_VR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), (x));\
+;} while (0)
+#define GET_H_SYS_UPR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR))
+#define SET_H_SYS_UPR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), (x));\
+;} while (0)
+#define GET_H_SYS_CPUCFGR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR))
+#define SET_H_SYS_CPUCFGR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), (x));\
+;} while (0)
+#define GET_H_SYS_DMMUCFGR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_DMMUCFGR))
+#define SET_H_SYS_DMMUCFGR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_DMMUCFGR), (x));\
+;} while (0)
+#define GET_H_SYS_IMMUCFGR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_IMMUCFGR))
+#define SET_H_SYS_IMMUCFGR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_IMMUCFGR), (x));\
+;} while (0)
+#define GET_H_SYS_DCCFGR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_DCCFGR))
+#define SET_H_SYS_DCCFGR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_DCCFGR), (x));\
+;} while (0)
+#define GET_H_SYS_ICCFGR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ICCFGR))
+#define SET_H_SYS_ICCFGR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ICCFGR), (x));\
+;} while (0)
+#define GET_H_SYS_DCFGR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_DCFGR))
+#define SET_H_SYS_DCFGR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_DCFGR), (x));\
+;} while (0)
+#define GET_H_SYS_PCCFGR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_PCCFGR))
+#define SET_H_SYS_PCCFGR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_PCCFGR), (x));\
+;} while (0)
+#define GET_H_SYS_NPC() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_NPC))
+#define SET_H_SYS_NPC(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_NPC), (x));\
+;} while (0)
+#define GET_H_SYS_SR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR))
+#define SET_H_SYS_SR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), (x));\
+;} while (0)
+#define GET_H_SYS_PPC() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_PPC))
+#define SET_H_SYS_PPC(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_PPC), (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR))
+#define SET_H_SYS_FPCSR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR0() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR0))
+#define SET_H_SYS_EPCR0(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR0), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR1() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR1))
+#define SET_H_SYS_EPCR1(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR1), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR2() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR2))
+#define SET_H_SYS_EPCR2(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR2), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR3() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR3))
+#define SET_H_SYS_EPCR3(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR3), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR4() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR4))
+#define SET_H_SYS_EPCR4(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR4), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR5() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR5))
+#define SET_H_SYS_EPCR5(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR5), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR6() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR6))
+#define SET_H_SYS_EPCR6(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR6), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR7() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR7))
+#define SET_H_SYS_EPCR7(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR7), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR8() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR8))
+#define SET_H_SYS_EPCR8(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR8), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR9() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR9))
+#define SET_H_SYS_EPCR9(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR9), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR10() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR10))
+#define SET_H_SYS_EPCR10(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR10), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR11() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR11))
+#define SET_H_SYS_EPCR11(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR11), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR12() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR12))
+#define SET_H_SYS_EPCR12(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR12), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR13() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR13))
+#define SET_H_SYS_EPCR13(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR13), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR14() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR14))
+#define SET_H_SYS_EPCR14(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR14), (x));\
+;} while (0)
+#define GET_H_SYS_EPCR15() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR15))
+#define SET_H_SYS_EPCR15(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EPCR15), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR0() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR0))
+#define SET_H_SYS_EEAR0(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR0), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR1() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR1))
+#define SET_H_SYS_EEAR1(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR1), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR2() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR2))
+#define SET_H_SYS_EEAR2(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR2), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR3() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR3))
+#define SET_H_SYS_EEAR3(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR3), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR4() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR4))
+#define SET_H_SYS_EEAR4(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR4), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR5() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR5))
+#define SET_H_SYS_EEAR5(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR5), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR6() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR6))
+#define SET_H_SYS_EEAR6(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR6), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR7() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR7))
+#define SET_H_SYS_EEAR7(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR7), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR8() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR8))
+#define SET_H_SYS_EEAR8(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR8), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR9() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR9))
+#define SET_H_SYS_EEAR9(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR9), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR10() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR10))
+#define SET_H_SYS_EEAR10(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR10), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR11() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR11))
+#define SET_H_SYS_EEAR11(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR11), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR12() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR12))
+#define SET_H_SYS_EEAR12(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR12), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR13() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR13))
+#define SET_H_SYS_EEAR13(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR13), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR14() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR14))
+#define SET_H_SYS_EEAR14(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR14), (x));\
+;} while (0)
+#define GET_H_SYS_EEAR15() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR15))
+#define SET_H_SYS_EEAR15(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_EEAR15), (x));\
+;} while (0)
+#define GET_H_SYS_ESR0() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR0))
+#define SET_H_SYS_ESR0(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR0), (x));\
+;} while (0)
+#define GET_H_SYS_ESR1() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR1))
+#define SET_H_SYS_ESR1(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR1), (x));\
+;} while (0)
+#define GET_H_SYS_ESR2() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR2))
+#define SET_H_SYS_ESR2(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR2), (x));\
+;} while (0)
+#define GET_H_SYS_ESR3() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR3))
+#define SET_H_SYS_ESR3(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR3), (x));\
+;} while (0)
+#define GET_H_SYS_ESR4() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR4))
+#define SET_H_SYS_ESR4(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR4), (x));\
+;} while (0)
+#define GET_H_SYS_ESR5() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR5))
+#define SET_H_SYS_ESR5(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR5), (x));\
+;} while (0)
+#define GET_H_SYS_ESR6() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR6))
+#define SET_H_SYS_ESR6(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR6), (x));\
+;} while (0)
+#define GET_H_SYS_ESR7() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR7))
+#define SET_H_SYS_ESR7(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR7), (x));\
+;} while (0)
+#define GET_H_SYS_ESR8() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR8))
+#define SET_H_SYS_ESR8(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR8), (x));\
+;} while (0)
+#define GET_H_SYS_ESR9() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR9))
+#define SET_H_SYS_ESR9(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR9), (x));\
+;} while (0)
+#define GET_H_SYS_ESR10() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR10))
+#define SET_H_SYS_ESR10(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR10), (x));\
+;} while (0)
+#define GET_H_SYS_ESR11() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR11))
+#define SET_H_SYS_ESR11(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR11), (x));\
+;} while (0)
+#define GET_H_SYS_ESR12() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR12))
+#define SET_H_SYS_ESR12(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR12), (x));\
+;} while (0)
+#define GET_H_SYS_ESR13() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR13))
+#define SET_H_SYS_ESR13(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR13), (x));\
+;} while (0)
+#define GET_H_SYS_ESR14() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR14))
+#define SET_H_SYS_ESR14(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR14), (x));\
+;} while (0)
+#define GET_H_SYS_ESR15() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR15))
+#define SET_H_SYS_ESR15(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_ESR15), (x));\
+;} while (0)
+#define GET_H_SYS_GPR0() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))
+#define SET_H_SYS_GPR0(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0), (x));\
+;} while (0)
+#define GET_H_SYS_GPR1() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR1))
+#define SET_H_SYS_GPR1(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR1), (x));\
+;} while (0)
+#define GET_H_SYS_GPR2() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR2))
+#define SET_H_SYS_GPR2(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR2), (x));\
+;} while (0)
+#define GET_H_SYS_GPR3() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR3))
+#define SET_H_SYS_GPR3(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR3), (x));\
+;} while (0)
+#define GET_H_SYS_GPR4() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR4))
+#define SET_H_SYS_GPR4(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR4), (x));\
+;} while (0)
+#define GET_H_SYS_GPR5() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR5))
+#define SET_H_SYS_GPR5(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR5), (x));\
+;} while (0)
+#define GET_H_SYS_GPR6() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR6))
+#define SET_H_SYS_GPR6(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR6), (x));\
+;} while (0)
+#define GET_H_SYS_GPR7() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR7))
+#define SET_H_SYS_GPR7(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR7), (x));\
+;} while (0)
+#define GET_H_SYS_GPR8() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR8))
+#define SET_H_SYS_GPR8(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR8), (x));\
+;} while (0)
+#define GET_H_SYS_GPR9() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR9))
+#define SET_H_SYS_GPR9(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR9), (x));\
+;} while (0)
+#define GET_H_SYS_GPR10() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR10))
+#define SET_H_SYS_GPR10(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR10), (x));\
+;} while (0)
+#define GET_H_SYS_GPR11() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR11))
+#define SET_H_SYS_GPR11(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR11), (x));\
+;} while (0)
+#define GET_H_SYS_GPR12() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR12))
+#define SET_H_SYS_GPR12(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR12), (x));\
+;} while (0)
+#define GET_H_SYS_GPR13() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR13))
+#define SET_H_SYS_GPR13(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR13), (x));\
+;} while (0)
+#define GET_H_SYS_GPR14() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR14))
+#define SET_H_SYS_GPR14(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR14), (x));\
+;} while (0)
+#define GET_H_SYS_GPR15() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR15))
+#define SET_H_SYS_GPR15(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR15), (x));\
+;} while (0)
+#define GET_H_SYS_GPR16() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR16))
+#define SET_H_SYS_GPR16(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR16), (x));\
+;} while (0)
+#define GET_H_SYS_GPR17() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR17))
+#define SET_H_SYS_GPR17(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR17), (x));\
+;} while (0)
+#define GET_H_SYS_GPR18() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR18))
+#define SET_H_SYS_GPR18(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR18), (x));\
+;} while (0)
+#define GET_H_SYS_GPR19() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR19))
+#define SET_H_SYS_GPR19(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR19), (x));\
+;} while (0)
+#define GET_H_SYS_GPR20() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR20))
+#define SET_H_SYS_GPR20(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR20), (x));\
+;} while (0)
+#define GET_H_SYS_GPR21() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR21))
+#define SET_H_SYS_GPR21(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR21), (x));\
+;} while (0)
+#define GET_H_SYS_GPR22() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR22))
+#define SET_H_SYS_GPR22(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR22), (x));\
+;} while (0)
+#define GET_H_SYS_GPR23() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR23))
+#define SET_H_SYS_GPR23(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR23), (x));\
+;} while (0)
+#define GET_H_SYS_GPR24() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR24))
+#define SET_H_SYS_GPR24(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR24), (x));\
+;} while (0)
+#define GET_H_SYS_GPR25() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR25))
+#define SET_H_SYS_GPR25(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR25), (x));\
+;} while (0)
+#define GET_H_SYS_GPR26() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR26))
+#define SET_H_SYS_GPR26(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR26), (x));\
+;} while (0)
+#define GET_H_SYS_GPR27() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR27))
+#define SET_H_SYS_GPR27(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR27), (x));\
+;} while (0)
+#define GET_H_SYS_GPR28() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR28))
+#define SET_H_SYS_GPR28(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR28), (x));\
+;} while (0)
+#define GET_H_SYS_GPR29() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR29))
+#define SET_H_SYS_GPR29(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR29), (x));\
+;} while (0)
+#define GET_H_SYS_GPR30() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR30))
+#define SET_H_SYS_GPR30(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR30), (x));\
+;} while (0)
+#define GET_H_SYS_GPR31() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR31))
+#define SET_H_SYS_GPR31(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR31), (x));\
+;} while (0)
+#define GET_H_SYS_GPR32() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR32))
+#define SET_H_SYS_GPR32(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR32), (x));\
+;} while (0)
+#define GET_H_SYS_GPR33() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR33))
+#define SET_H_SYS_GPR33(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR33), (x));\
+;} while (0)
+#define GET_H_SYS_GPR34() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR34))
+#define SET_H_SYS_GPR34(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR34), (x));\
+;} while (0)
+#define GET_H_SYS_GPR35() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR35))
+#define SET_H_SYS_GPR35(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR35), (x));\
+;} while (0)
+#define GET_H_SYS_GPR36() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR36))
+#define SET_H_SYS_GPR36(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR36), (x));\
+;} while (0)
+#define GET_H_SYS_GPR37() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR37))
+#define SET_H_SYS_GPR37(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR37), (x));\
+;} while (0)
+#define GET_H_SYS_GPR38() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR38))
+#define SET_H_SYS_GPR38(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR38), (x));\
+;} while (0)
+#define GET_H_SYS_GPR39() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR39))
+#define SET_H_SYS_GPR39(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR39), (x));\
+;} while (0)
+#define GET_H_SYS_GPR40() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR40))
+#define SET_H_SYS_GPR40(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR40), (x));\
+;} while (0)
+#define GET_H_SYS_GPR41() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR41))
+#define SET_H_SYS_GPR41(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR41), (x));\
+;} while (0)
+#define GET_H_SYS_GPR42() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR42))
+#define SET_H_SYS_GPR42(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR42), (x));\
+;} while (0)
+#define GET_H_SYS_GPR43() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR43))
+#define SET_H_SYS_GPR43(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR43), (x));\
+;} while (0)
+#define GET_H_SYS_GPR44() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR44))
+#define SET_H_SYS_GPR44(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR44), (x));\
+;} while (0)
+#define GET_H_SYS_GPR45() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR45))
+#define SET_H_SYS_GPR45(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR45), (x));\
+;} while (0)
+#define GET_H_SYS_GPR46() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR46))
+#define SET_H_SYS_GPR46(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR46), (x));\
+;} while (0)
+#define GET_H_SYS_GPR47() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR47))
+#define SET_H_SYS_GPR47(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR47), (x));\
+;} while (0)
+#define GET_H_SYS_GPR48() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR48))
+#define SET_H_SYS_GPR48(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR48), (x));\
+;} while (0)
+#define GET_H_SYS_GPR49() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR49))
+#define SET_H_SYS_GPR49(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR49), (x));\
+;} while (0)
+#define GET_H_SYS_GPR50() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR50))
+#define SET_H_SYS_GPR50(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR50), (x));\
+;} while (0)
+#define GET_H_SYS_GPR51() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR51))
+#define SET_H_SYS_GPR51(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR51), (x));\
+;} while (0)
+#define GET_H_SYS_GPR52() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR52))
+#define SET_H_SYS_GPR52(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR52), (x));\
+;} while (0)
+#define GET_H_SYS_GPR53() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR53))
+#define SET_H_SYS_GPR53(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR53), (x));\
+;} while (0)
+#define GET_H_SYS_GPR54() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR54))
+#define SET_H_SYS_GPR54(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR54), (x));\
+;} while (0)
+#define GET_H_SYS_GPR55() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR55))
+#define SET_H_SYS_GPR55(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR55), (x));\
+;} while (0)
+#define GET_H_SYS_GPR56() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR56))
+#define SET_H_SYS_GPR56(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR56), (x));\
+;} while (0)
+#define GET_H_SYS_GPR57() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR57))
+#define SET_H_SYS_GPR57(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR57), (x));\
+;} while (0)
+#define GET_H_SYS_GPR58() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR58))
+#define SET_H_SYS_GPR58(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR58), (x));\
+;} while (0)
+#define GET_H_SYS_GPR59() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR59))
+#define SET_H_SYS_GPR59(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR59), (x));\
+;} while (0)
+#define GET_H_SYS_GPR60() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR60))
+#define SET_H_SYS_GPR60(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR60), (x));\
+;} while (0)
+#define GET_H_SYS_GPR61() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR61))
+#define SET_H_SYS_GPR61(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR61), (x));\
+;} while (0)
+#define GET_H_SYS_GPR62() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR62))
+#define SET_H_SYS_GPR62(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR62), (x));\
+;} while (0)
+#define GET_H_SYS_GPR63() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR63))
+#define SET_H_SYS_GPR63(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR63), (x));\
+;} while (0)
+#define GET_H_SYS_GPR64() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR64))
+#define SET_H_SYS_GPR64(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR64), (x));\
+;} while (0)
+#define GET_H_SYS_GPR65() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR65))
+#define SET_H_SYS_GPR65(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR65), (x));\
+;} while (0)
+#define GET_H_SYS_GPR66() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR66))
+#define SET_H_SYS_GPR66(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR66), (x));\
+;} while (0)
+#define GET_H_SYS_GPR67() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR67))
+#define SET_H_SYS_GPR67(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR67), (x));\
+;} while (0)
+#define GET_H_SYS_GPR68() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR68))
+#define SET_H_SYS_GPR68(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR68), (x));\
+;} while (0)
+#define GET_H_SYS_GPR69() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR69))
+#define SET_H_SYS_GPR69(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR69), (x));\
+;} while (0)
+#define GET_H_SYS_GPR70() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR70))
+#define SET_H_SYS_GPR70(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR70), (x));\
+;} while (0)
+#define GET_H_SYS_GPR71() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR71))
+#define SET_H_SYS_GPR71(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR71), (x));\
+;} while (0)
+#define GET_H_SYS_GPR72() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR72))
+#define SET_H_SYS_GPR72(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR72), (x));\
+;} while (0)
+#define GET_H_SYS_GPR73() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR73))
+#define SET_H_SYS_GPR73(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR73), (x));\
+;} while (0)
+#define GET_H_SYS_GPR74() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR74))
+#define SET_H_SYS_GPR74(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR74), (x));\
+;} while (0)
+#define GET_H_SYS_GPR75() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR75))
+#define SET_H_SYS_GPR75(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR75), (x));\
+;} while (0)
+#define GET_H_SYS_GPR76() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR76))
+#define SET_H_SYS_GPR76(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR76), (x));\
+;} while (0)
+#define GET_H_SYS_GPR77() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR77))
+#define SET_H_SYS_GPR77(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR77), (x));\
+;} while (0)
+#define GET_H_SYS_GPR78() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR78))
+#define SET_H_SYS_GPR78(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR78), (x));\
+;} while (0)
+#define GET_H_SYS_GPR79() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR79))
+#define SET_H_SYS_GPR79(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR79), (x));\
+;} while (0)
+#define GET_H_SYS_GPR80() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR80))
+#define SET_H_SYS_GPR80(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR80), (x));\
+;} while (0)
+#define GET_H_SYS_GPR81() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR81))
+#define SET_H_SYS_GPR81(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR81), (x));\
+;} while (0)
+#define GET_H_SYS_GPR82() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR82))
+#define SET_H_SYS_GPR82(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR82), (x));\
+;} while (0)
+#define GET_H_SYS_GPR83() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR83))
+#define SET_H_SYS_GPR83(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR83), (x));\
+;} while (0)
+#define GET_H_SYS_GPR84() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR84))
+#define SET_H_SYS_GPR84(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR84), (x));\
+;} while (0)
+#define GET_H_SYS_GPR85() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR85))
+#define SET_H_SYS_GPR85(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR85), (x));\
+;} while (0)
+#define GET_H_SYS_GPR86() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR86))
+#define SET_H_SYS_GPR86(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR86), (x));\
+;} while (0)
+#define GET_H_SYS_GPR87() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR87))
+#define SET_H_SYS_GPR87(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR87), (x));\
+;} while (0)
+#define GET_H_SYS_GPR88() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR88))
+#define SET_H_SYS_GPR88(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR88), (x));\
+;} while (0)
+#define GET_H_SYS_GPR89() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR89))
+#define SET_H_SYS_GPR89(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR89), (x));\
+;} while (0)
+#define GET_H_SYS_GPR90() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR90))
+#define SET_H_SYS_GPR90(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR90), (x));\
+;} while (0)
+#define GET_H_SYS_GPR91() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR91))
+#define SET_H_SYS_GPR91(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR91), (x));\
+;} while (0)
+#define GET_H_SYS_GPR92() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR92))
+#define SET_H_SYS_GPR92(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR92), (x));\
+;} while (0)
+#define GET_H_SYS_GPR93() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR93))
+#define SET_H_SYS_GPR93(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR93), (x));\
+;} while (0)
+#define GET_H_SYS_GPR94() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR94))
+#define SET_H_SYS_GPR94(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR94), (x));\
+;} while (0)
+#define GET_H_SYS_GPR95() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR95))
+#define SET_H_SYS_GPR95(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR95), (x));\
+;} while (0)
+#define GET_H_SYS_GPR96() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR96))
+#define SET_H_SYS_GPR96(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR96), (x));\
+;} while (0)
+#define GET_H_SYS_GPR97() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR97))
+#define SET_H_SYS_GPR97(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR97), (x));\
+;} while (0)
+#define GET_H_SYS_GPR98() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR98))
+#define SET_H_SYS_GPR98(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR98), (x));\
+;} while (0)
+#define GET_H_SYS_GPR99() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR99))
+#define SET_H_SYS_GPR99(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR99), (x));\
+;} while (0)
+#define GET_H_SYS_GPR100() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR100))
+#define SET_H_SYS_GPR100(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR100), (x));\
+;} while (0)
+#define GET_H_SYS_GPR101() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR101))
+#define SET_H_SYS_GPR101(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR101), (x));\
+;} while (0)
+#define GET_H_SYS_GPR102() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR102))
+#define SET_H_SYS_GPR102(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR102), (x));\
+;} while (0)
+#define GET_H_SYS_GPR103() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR103))
+#define SET_H_SYS_GPR103(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR103), (x));\
+;} while (0)
+#define GET_H_SYS_GPR104() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR104))
+#define SET_H_SYS_GPR104(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR104), (x));\
+;} while (0)
+#define GET_H_SYS_GPR105() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR105))
+#define SET_H_SYS_GPR105(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR105), (x));\
+;} while (0)
+#define GET_H_SYS_GPR106() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR106))
+#define SET_H_SYS_GPR106(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR106), (x));\
+;} while (0)
+#define GET_H_SYS_GPR107() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR107))
+#define SET_H_SYS_GPR107(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR107), (x));\
+;} while (0)
+#define GET_H_SYS_GPR108() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR108))
+#define SET_H_SYS_GPR108(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR108), (x));\
+;} while (0)
+#define GET_H_SYS_GPR109() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR109))
+#define SET_H_SYS_GPR109(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR109), (x));\
+;} while (0)
+#define GET_H_SYS_GPR110() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR110))
+#define SET_H_SYS_GPR110(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR110), (x));\
+;} while (0)
+#define GET_H_SYS_GPR111() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR111))
+#define SET_H_SYS_GPR111(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR111), (x));\
+;} while (0)
+#define GET_H_SYS_GPR112() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR112))
+#define SET_H_SYS_GPR112(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR112), (x));\
+;} while (0)
+#define GET_H_SYS_GPR113() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR113))
+#define SET_H_SYS_GPR113(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR113), (x));\
+;} while (0)
+#define GET_H_SYS_GPR114() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR114))
+#define SET_H_SYS_GPR114(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR114), (x));\
+;} while (0)
+#define GET_H_SYS_GPR115() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR115))
+#define SET_H_SYS_GPR115(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR115), (x));\
+;} while (0)
+#define GET_H_SYS_GPR116() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR116))
+#define SET_H_SYS_GPR116(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR116), (x));\
+;} while (0)
+#define GET_H_SYS_GPR117() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR117))
+#define SET_H_SYS_GPR117(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR117), (x));\
+;} while (0)
+#define GET_H_SYS_GPR118() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR118))
+#define SET_H_SYS_GPR118(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR118), (x));\
+;} while (0)
+#define GET_H_SYS_GPR119() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR119))
+#define SET_H_SYS_GPR119(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR119), (x));\
+;} while (0)
+#define GET_H_SYS_GPR120() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR120))
+#define SET_H_SYS_GPR120(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR120), (x));\
+;} while (0)
+#define GET_H_SYS_GPR121() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR121))
+#define SET_H_SYS_GPR121(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR121), (x));\
+;} while (0)
+#define GET_H_SYS_GPR122() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR122))
+#define SET_H_SYS_GPR122(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR122), (x));\
+;} while (0)
+#define GET_H_SYS_GPR123() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR123))
+#define SET_H_SYS_GPR123(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR123), (x));\
+;} while (0)
+#define GET_H_SYS_GPR124() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR124))
+#define SET_H_SYS_GPR124(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR124), (x));\
+;} while (0)
+#define GET_H_SYS_GPR125() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR125))
+#define SET_H_SYS_GPR125(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR125), (x));\
+;} while (0)
+#define GET_H_SYS_GPR126() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR126))
+#define SET_H_SYS_GPR126(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR126), (x));\
+;} while (0)
+#define GET_H_SYS_GPR127() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR127))
+#define SET_H_SYS_GPR127(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR127), (x));\
+;} while (0)
+#define GET_H_SYS_GPR128() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR128))
+#define SET_H_SYS_GPR128(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR128), (x));\
+;} while (0)
+#define GET_H_SYS_GPR129() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR129))
+#define SET_H_SYS_GPR129(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR129), (x));\
+;} while (0)
+#define GET_H_SYS_GPR130() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR130))
+#define SET_H_SYS_GPR130(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR130), (x));\
+;} while (0)
+#define GET_H_SYS_GPR131() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR131))
+#define SET_H_SYS_GPR131(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR131), (x));\
+;} while (0)
+#define GET_H_SYS_GPR132() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR132))
+#define SET_H_SYS_GPR132(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR132), (x));\
+;} while (0)
+#define GET_H_SYS_GPR133() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR133))
+#define SET_H_SYS_GPR133(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR133), (x));\
+;} while (0)
+#define GET_H_SYS_GPR134() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR134))
+#define SET_H_SYS_GPR134(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR134), (x));\
+;} while (0)
+#define GET_H_SYS_GPR135() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR135))
+#define SET_H_SYS_GPR135(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR135), (x));\
+;} while (0)
+#define GET_H_SYS_GPR136() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR136))
+#define SET_H_SYS_GPR136(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR136), (x));\
+;} while (0)
+#define GET_H_SYS_GPR137() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR137))
+#define SET_H_SYS_GPR137(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR137), (x));\
+;} while (0)
+#define GET_H_SYS_GPR138() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR138))
+#define SET_H_SYS_GPR138(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR138), (x));\
+;} while (0)
+#define GET_H_SYS_GPR139() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR139))
+#define SET_H_SYS_GPR139(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR139), (x));\
+;} while (0)
+#define GET_H_SYS_GPR140() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR140))
+#define SET_H_SYS_GPR140(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR140), (x));\
+;} while (0)
+#define GET_H_SYS_GPR141() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR141))
+#define SET_H_SYS_GPR141(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR141), (x));\
+;} while (0)
+#define GET_H_SYS_GPR142() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR142))
+#define SET_H_SYS_GPR142(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR142), (x));\
+;} while (0)
+#define GET_H_SYS_GPR143() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR143))
+#define SET_H_SYS_GPR143(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR143), (x));\
+;} while (0)
+#define GET_H_SYS_GPR144() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR144))
+#define SET_H_SYS_GPR144(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR144), (x));\
+;} while (0)
+#define GET_H_SYS_GPR145() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR145))
+#define SET_H_SYS_GPR145(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR145), (x));\
+;} while (0)
+#define GET_H_SYS_GPR146() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR146))
+#define SET_H_SYS_GPR146(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR146), (x));\
+;} while (0)
+#define GET_H_SYS_GPR147() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR147))
+#define SET_H_SYS_GPR147(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR147), (x));\
+;} while (0)
+#define GET_H_SYS_GPR148() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR148))
+#define SET_H_SYS_GPR148(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR148), (x));\
+;} while (0)
+#define GET_H_SYS_GPR149() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR149))
+#define SET_H_SYS_GPR149(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR149), (x));\
+;} while (0)
+#define GET_H_SYS_GPR150() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR150))
+#define SET_H_SYS_GPR150(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR150), (x));\
+;} while (0)
+#define GET_H_SYS_GPR151() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR151))
+#define SET_H_SYS_GPR151(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR151), (x));\
+;} while (0)
+#define GET_H_SYS_GPR152() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR152))
+#define SET_H_SYS_GPR152(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR152), (x));\
+;} while (0)
+#define GET_H_SYS_GPR153() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR153))
+#define SET_H_SYS_GPR153(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR153), (x));\
+;} while (0)
+#define GET_H_SYS_GPR154() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR154))
+#define SET_H_SYS_GPR154(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR154), (x));\
+;} while (0)
+#define GET_H_SYS_GPR155() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR155))
+#define SET_H_SYS_GPR155(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR155), (x));\
+;} while (0)
+#define GET_H_SYS_GPR156() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR156))
+#define SET_H_SYS_GPR156(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR156), (x));\
+;} while (0)
+#define GET_H_SYS_GPR157() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR157))
+#define SET_H_SYS_GPR157(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR157), (x));\
+;} while (0)
+#define GET_H_SYS_GPR158() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR158))
+#define SET_H_SYS_GPR158(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR158), (x));\
+;} while (0)
+#define GET_H_SYS_GPR159() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR159))
+#define SET_H_SYS_GPR159(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR159), (x));\
+;} while (0)
+#define GET_H_SYS_GPR160() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR160))
+#define SET_H_SYS_GPR160(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR160), (x));\
+;} while (0)
+#define GET_H_SYS_GPR161() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR161))
+#define SET_H_SYS_GPR161(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR161), (x));\
+;} while (0)
+#define GET_H_SYS_GPR162() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR162))
+#define SET_H_SYS_GPR162(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR162), (x));\
+;} while (0)
+#define GET_H_SYS_GPR163() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR163))
+#define SET_H_SYS_GPR163(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR163), (x));\
+;} while (0)
+#define GET_H_SYS_GPR164() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR164))
+#define SET_H_SYS_GPR164(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR164), (x));\
+;} while (0)
+#define GET_H_SYS_GPR165() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR165))
+#define SET_H_SYS_GPR165(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR165), (x));\
+;} while (0)
+#define GET_H_SYS_GPR166() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR166))
+#define SET_H_SYS_GPR166(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR166), (x));\
+;} while (0)
+#define GET_H_SYS_GPR167() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR167))
+#define SET_H_SYS_GPR167(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR167), (x));\
+;} while (0)
+#define GET_H_SYS_GPR168() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR168))
+#define SET_H_SYS_GPR168(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR168), (x));\
+;} while (0)
+#define GET_H_SYS_GPR169() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR169))
+#define SET_H_SYS_GPR169(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR169), (x));\
+;} while (0)
+#define GET_H_SYS_GPR170() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR170))
+#define SET_H_SYS_GPR170(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR170), (x));\
+;} while (0)
+#define GET_H_SYS_GPR171() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR171))
+#define SET_H_SYS_GPR171(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR171), (x));\
+;} while (0)
+#define GET_H_SYS_GPR172() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR172))
+#define SET_H_SYS_GPR172(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR172), (x));\
+;} while (0)
+#define GET_H_SYS_GPR173() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR173))
+#define SET_H_SYS_GPR173(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR173), (x));\
+;} while (0)
+#define GET_H_SYS_GPR174() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR174))
+#define SET_H_SYS_GPR174(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR174), (x));\
+;} while (0)
+#define GET_H_SYS_GPR175() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR175))
+#define SET_H_SYS_GPR175(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR175), (x));\
+;} while (0)
+#define GET_H_SYS_GPR176() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR176))
+#define SET_H_SYS_GPR176(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR176), (x));\
+;} while (0)
+#define GET_H_SYS_GPR177() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR177))
+#define SET_H_SYS_GPR177(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR177), (x));\
+;} while (0)
+#define GET_H_SYS_GPR178() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR178))
+#define SET_H_SYS_GPR178(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR178), (x));\
+;} while (0)
+#define GET_H_SYS_GPR179() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR179))
+#define SET_H_SYS_GPR179(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR179), (x));\
+;} while (0)
+#define GET_H_SYS_GPR180() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR180))
+#define SET_H_SYS_GPR180(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR180), (x));\
+;} while (0)
+#define GET_H_SYS_GPR181() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR181))
+#define SET_H_SYS_GPR181(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR181), (x));\
+;} while (0)
+#define GET_H_SYS_GPR182() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR182))
+#define SET_H_SYS_GPR182(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR182), (x));\
+;} while (0)
+#define GET_H_SYS_GPR183() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR183))
+#define SET_H_SYS_GPR183(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR183), (x));\
+;} while (0)
+#define GET_H_SYS_GPR184() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR184))
+#define SET_H_SYS_GPR184(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR184), (x));\
+;} while (0)
+#define GET_H_SYS_GPR185() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR185))
+#define SET_H_SYS_GPR185(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR185), (x));\
+;} while (0)
+#define GET_H_SYS_GPR186() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR186))
+#define SET_H_SYS_GPR186(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR186), (x));\
+;} while (0)
+#define GET_H_SYS_GPR187() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR187))
+#define SET_H_SYS_GPR187(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR187), (x));\
+;} while (0)
+#define GET_H_SYS_GPR188() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR188))
+#define SET_H_SYS_GPR188(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR188), (x));\
+;} while (0)
+#define GET_H_SYS_GPR189() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR189))
+#define SET_H_SYS_GPR189(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR189), (x));\
+;} while (0)
+#define GET_H_SYS_GPR190() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR190))
+#define SET_H_SYS_GPR190(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR190), (x));\
+;} while (0)
+#define GET_H_SYS_GPR191() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR191))
+#define SET_H_SYS_GPR191(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR191), (x));\
+;} while (0)
+#define GET_H_SYS_GPR192() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR192))
+#define SET_H_SYS_GPR192(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR192), (x));\
+;} while (0)
+#define GET_H_SYS_GPR193() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR193))
+#define SET_H_SYS_GPR193(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR193), (x));\
+;} while (0)
+#define GET_H_SYS_GPR194() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR194))
+#define SET_H_SYS_GPR194(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR194), (x));\
+;} while (0)
+#define GET_H_SYS_GPR195() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR195))
+#define SET_H_SYS_GPR195(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR195), (x));\
+;} while (0)
+#define GET_H_SYS_GPR196() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR196))
+#define SET_H_SYS_GPR196(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR196), (x));\
+;} while (0)
+#define GET_H_SYS_GPR197() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR197))
+#define SET_H_SYS_GPR197(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR197), (x));\
+;} while (0)
+#define GET_H_SYS_GPR198() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR198))
+#define SET_H_SYS_GPR198(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR198), (x));\
+;} while (0)
+#define GET_H_SYS_GPR199() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR199))
+#define SET_H_SYS_GPR199(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR199), (x));\
+;} while (0)
+#define GET_H_SYS_GPR200() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR200))
+#define SET_H_SYS_GPR200(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR200), (x));\
+;} while (0)
+#define GET_H_SYS_GPR201() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR201))
+#define SET_H_SYS_GPR201(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR201), (x));\
+;} while (0)
+#define GET_H_SYS_GPR202() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR202))
+#define SET_H_SYS_GPR202(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR202), (x));\
+;} while (0)
+#define GET_H_SYS_GPR203() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR203))
+#define SET_H_SYS_GPR203(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR203), (x));\
+;} while (0)
+#define GET_H_SYS_GPR204() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR204))
+#define SET_H_SYS_GPR204(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR204), (x));\
+;} while (0)
+#define GET_H_SYS_GPR205() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR205))
+#define SET_H_SYS_GPR205(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR205), (x));\
+;} while (0)
+#define GET_H_SYS_GPR206() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR206))
+#define SET_H_SYS_GPR206(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR206), (x));\
+;} while (0)
+#define GET_H_SYS_GPR207() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR207))
+#define SET_H_SYS_GPR207(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR207), (x));\
+;} while (0)
+#define GET_H_SYS_GPR208() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR208))
+#define SET_H_SYS_GPR208(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR208), (x));\
+;} while (0)
+#define GET_H_SYS_GPR209() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR209))
+#define SET_H_SYS_GPR209(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR209), (x));\
+;} while (0)
+#define GET_H_SYS_GPR210() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR210))
+#define SET_H_SYS_GPR210(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR210), (x));\
+;} while (0)
+#define GET_H_SYS_GPR211() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR211))
+#define SET_H_SYS_GPR211(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR211), (x));\
+;} while (0)
+#define GET_H_SYS_GPR212() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR212))
+#define SET_H_SYS_GPR212(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR212), (x));\
+;} while (0)
+#define GET_H_SYS_GPR213() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR213))
+#define SET_H_SYS_GPR213(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR213), (x));\
+;} while (0)
+#define GET_H_SYS_GPR214() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR214))
+#define SET_H_SYS_GPR214(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR214), (x));\
+;} while (0)
+#define GET_H_SYS_GPR215() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR215))
+#define SET_H_SYS_GPR215(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR215), (x));\
+;} while (0)
+#define GET_H_SYS_GPR216() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR216))
+#define SET_H_SYS_GPR216(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR216), (x));\
+;} while (0)
+#define GET_H_SYS_GPR217() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR217))
+#define SET_H_SYS_GPR217(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR217), (x));\
+;} while (0)
+#define GET_H_SYS_GPR218() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR218))
+#define SET_H_SYS_GPR218(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR218), (x));\
+;} while (0)
+#define GET_H_SYS_GPR219() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR219))
+#define SET_H_SYS_GPR219(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR219), (x));\
+;} while (0)
+#define GET_H_SYS_GPR220() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR220))
+#define SET_H_SYS_GPR220(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR220), (x));\
+;} while (0)
+#define GET_H_SYS_GPR221() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR221))
+#define SET_H_SYS_GPR221(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR221), (x));\
+;} while (0)
+#define GET_H_SYS_GPR222() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR222))
+#define SET_H_SYS_GPR222(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR222), (x));\
+;} while (0)
+#define GET_H_SYS_GPR223() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR223))
+#define SET_H_SYS_GPR223(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR223), (x));\
+;} while (0)
+#define GET_H_SYS_GPR224() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR224))
+#define SET_H_SYS_GPR224(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR224), (x));\
+;} while (0)
+#define GET_H_SYS_GPR225() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR225))
+#define SET_H_SYS_GPR225(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR225), (x));\
+;} while (0)
+#define GET_H_SYS_GPR226() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR226))
+#define SET_H_SYS_GPR226(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR226), (x));\
+;} while (0)
+#define GET_H_SYS_GPR227() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR227))
+#define SET_H_SYS_GPR227(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR227), (x));\
+;} while (0)
+#define GET_H_SYS_GPR228() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR228))
+#define SET_H_SYS_GPR228(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR228), (x));\
+;} while (0)
+#define GET_H_SYS_GPR229() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR229))
+#define SET_H_SYS_GPR229(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR229), (x));\
+;} while (0)
+#define GET_H_SYS_GPR230() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR230))
+#define SET_H_SYS_GPR230(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR230), (x));\
+;} while (0)
+#define GET_H_SYS_GPR231() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR231))
+#define SET_H_SYS_GPR231(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR231), (x));\
+;} while (0)
+#define GET_H_SYS_GPR232() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR232))
+#define SET_H_SYS_GPR232(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR232), (x));\
+;} while (0)
+#define GET_H_SYS_GPR233() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR233))
+#define SET_H_SYS_GPR233(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR233), (x));\
+;} while (0)
+#define GET_H_SYS_GPR234() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR234))
+#define SET_H_SYS_GPR234(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR234), (x));\
+;} while (0)
+#define GET_H_SYS_GPR235() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR235))
+#define SET_H_SYS_GPR235(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR235), (x));\
+;} while (0)
+#define GET_H_SYS_GPR236() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR236))
+#define SET_H_SYS_GPR236(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR236), (x));\
+;} while (0)
+#define GET_H_SYS_GPR237() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR237))
+#define SET_H_SYS_GPR237(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR237), (x));\
+;} while (0)
+#define GET_H_SYS_GPR238() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR238))
+#define SET_H_SYS_GPR238(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR238), (x));\
+;} while (0)
+#define GET_H_SYS_GPR239() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR239))
+#define SET_H_SYS_GPR239(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR239), (x));\
+;} while (0)
+#define GET_H_SYS_GPR240() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR240))
+#define SET_H_SYS_GPR240(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR240), (x));\
+;} while (0)
+#define GET_H_SYS_GPR241() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR241))
+#define SET_H_SYS_GPR241(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR241), (x));\
+;} while (0)
+#define GET_H_SYS_GPR242() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR242))
+#define SET_H_SYS_GPR242(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR242), (x));\
+;} while (0)
+#define GET_H_SYS_GPR243() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR243))
+#define SET_H_SYS_GPR243(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR243), (x));\
+;} while (0)
+#define GET_H_SYS_GPR244() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR244))
+#define SET_H_SYS_GPR244(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR244), (x));\
+;} while (0)
+#define GET_H_SYS_GPR245() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR245))
+#define SET_H_SYS_GPR245(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR245), (x));\
+;} while (0)
+#define GET_H_SYS_GPR246() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR246))
+#define SET_H_SYS_GPR246(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR246), (x));\
+;} while (0)
+#define GET_H_SYS_GPR247() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR247))
+#define SET_H_SYS_GPR247(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR247), (x));\
+;} while (0)
+#define GET_H_SYS_GPR248() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR248))
+#define SET_H_SYS_GPR248(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR248), (x));\
+;} while (0)
+#define GET_H_SYS_GPR249() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR249))
+#define SET_H_SYS_GPR249(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR249), (x));\
+;} while (0)
+#define GET_H_SYS_GPR250() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR250))
+#define SET_H_SYS_GPR250(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR250), (x));\
+;} while (0)
+#define GET_H_SYS_GPR251() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR251))
+#define SET_H_SYS_GPR251(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR251), (x));\
+;} while (0)
+#define GET_H_SYS_GPR252() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR252))
+#define SET_H_SYS_GPR252(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR252), (x));\
+;} while (0)
+#define GET_H_SYS_GPR253() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR253))
+#define SET_H_SYS_GPR253(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR253), (x));\
+;} while (0)
+#define GET_H_SYS_GPR254() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR254))
+#define SET_H_SYS_GPR254(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR254), (x));\
+;} while (0)
+#define GET_H_SYS_GPR255() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR255))
+#define SET_H_SYS_GPR255(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR255), (x));\
+;} while (0)
+#define GET_H_SYS_GPR256() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR256))
+#define SET_H_SYS_GPR256(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR256), (x));\
+;} while (0)
+#define GET_H_SYS_GPR257() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR257))
+#define SET_H_SYS_GPR257(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR257), (x));\
+;} while (0)
+#define GET_H_SYS_GPR258() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR258))
+#define SET_H_SYS_GPR258(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR258), (x));\
+;} while (0)
+#define GET_H_SYS_GPR259() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR259))
+#define SET_H_SYS_GPR259(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR259), (x));\
+;} while (0)
+#define GET_H_SYS_GPR260() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR260))
+#define SET_H_SYS_GPR260(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR260), (x));\
+;} while (0)
+#define GET_H_SYS_GPR261() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR261))
+#define SET_H_SYS_GPR261(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR261), (x));\
+;} while (0)
+#define GET_H_SYS_GPR262() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR262))
+#define SET_H_SYS_GPR262(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR262), (x));\
+;} while (0)
+#define GET_H_SYS_GPR263() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR263))
+#define SET_H_SYS_GPR263(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR263), (x));\
+;} while (0)
+#define GET_H_SYS_GPR264() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR264))
+#define SET_H_SYS_GPR264(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR264), (x));\
+;} while (0)
+#define GET_H_SYS_GPR265() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR265))
+#define SET_H_SYS_GPR265(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR265), (x));\
+;} while (0)
+#define GET_H_SYS_GPR266() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR266))
+#define SET_H_SYS_GPR266(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR266), (x));\
+;} while (0)
+#define GET_H_SYS_GPR267() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR267))
+#define SET_H_SYS_GPR267(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR267), (x));\
+;} while (0)
+#define GET_H_SYS_GPR268() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR268))
+#define SET_H_SYS_GPR268(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR268), (x));\
+;} while (0)
+#define GET_H_SYS_GPR269() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR269))
+#define SET_H_SYS_GPR269(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR269), (x));\
+;} while (0)
+#define GET_H_SYS_GPR270() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR270))
+#define SET_H_SYS_GPR270(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR270), (x));\
+;} while (0)
+#define GET_H_SYS_GPR271() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR271))
+#define SET_H_SYS_GPR271(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR271), (x));\
+;} while (0)
+#define GET_H_SYS_GPR272() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR272))
+#define SET_H_SYS_GPR272(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR272), (x));\
+;} while (0)
+#define GET_H_SYS_GPR273() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR273))
+#define SET_H_SYS_GPR273(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR273), (x));\
+;} while (0)
+#define GET_H_SYS_GPR274() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR274))
+#define SET_H_SYS_GPR274(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR274), (x));\
+;} while (0)
+#define GET_H_SYS_GPR275() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR275))
+#define SET_H_SYS_GPR275(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR275), (x));\
+;} while (0)
+#define GET_H_SYS_GPR276() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR276))
+#define SET_H_SYS_GPR276(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR276), (x));\
+;} while (0)
+#define GET_H_SYS_GPR277() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR277))
+#define SET_H_SYS_GPR277(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR277), (x));\
+;} while (0)
+#define GET_H_SYS_GPR278() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR278))
+#define SET_H_SYS_GPR278(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR278), (x));\
+;} while (0)
+#define GET_H_SYS_GPR279() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR279))
+#define SET_H_SYS_GPR279(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR279), (x));\
+;} while (0)
+#define GET_H_SYS_GPR280() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR280))
+#define SET_H_SYS_GPR280(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR280), (x));\
+;} while (0)
+#define GET_H_SYS_GPR281() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR281))
+#define SET_H_SYS_GPR281(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR281), (x));\
+;} while (0)
+#define GET_H_SYS_GPR282() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR282))
+#define SET_H_SYS_GPR282(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR282), (x));\
+;} while (0)
+#define GET_H_SYS_GPR283() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR283))
+#define SET_H_SYS_GPR283(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR283), (x));\
+;} while (0)
+#define GET_H_SYS_GPR284() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR284))
+#define SET_H_SYS_GPR284(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR284), (x));\
+;} while (0)
+#define GET_H_SYS_GPR285() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR285))
+#define SET_H_SYS_GPR285(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR285), (x));\
+;} while (0)
+#define GET_H_SYS_GPR286() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR286))
+#define SET_H_SYS_GPR286(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR286), (x));\
+;} while (0)
+#define GET_H_SYS_GPR287() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR287))
+#define SET_H_SYS_GPR287(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR287), (x));\
+;} while (0)
+#define GET_H_SYS_GPR288() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR288))
+#define SET_H_SYS_GPR288(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR288), (x));\
+;} while (0)
+#define GET_H_SYS_GPR289() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR289))
+#define SET_H_SYS_GPR289(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR289), (x));\
+;} while (0)
+#define GET_H_SYS_GPR290() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR290))
+#define SET_H_SYS_GPR290(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR290), (x));\
+;} while (0)
+#define GET_H_SYS_GPR291() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR291))
+#define SET_H_SYS_GPR291(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR291), (x));\
+;} while (0)
+#define GET_H_SYS_GPR292() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR292))
+#define SET_H_SYS_GPR292(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR292), (x));\
+;} while (0)
+#define GET_H_SYS_GPR293() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR293))
+#define SET_H_SYS_GPR293(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR293), (x));\
+;} while (0)
+#define GET_H_SYS_GPR294() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR294))
+#define SET_H_SYS_GPR294(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR294), (x));\
+;} while (0)
+#define GET_H_SYS_GPR295() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR295))
+#define SET_H_SYS_GPR295(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR295), (x));\
+;} while (0)
+#define GET_H_SYS_GPR296() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR296))
+#define SET_H_SYS_GPR296(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR296), (x));\
+;} while (0)
+#define GET_H_SYS_GPR297() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR297))
+#define SET_H_SYS_GPR297(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR297), (x));\
+;} while (0)
+#define GET_H_SYS_GPR298() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR298))
+#define SET_H_SYS_GPR298(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR298), (x));\
+;} while (0)
+#define GET_H_SYS_GPR299() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR299))
+#define SET_H_SYS_GPR299(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR299), (x));\
+;} while (0)
+#define GET_H_SYS_GPR300() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR300))
+#define SET_H_SYS_GPR300(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR300), (x));\
+;} while (0)
+#define GET_H_SYS_GPR301() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR301))
+#define SET_H_SYS_GPR301(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR301), (x));\
+;} while (0)
+#define GET_H_SYS_GPR302() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR302))
+#define SET_H_SYS_GPR302(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR302), (x));\
+;} while (0)
+#define GET_H_SYS_GPR303() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR303))
+#define SET_H_SYS_GPR303(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR303), (x));\
+;} while (0)
+#define GET_H_SYS_GPR304() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR304))
+#define SET_H_SYS_GPR304(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR304), (x));\
+;} while (0)
+#define GET_H_SYS_GPR305() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR305))
+#define SET_H_SYS_GPR305(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR305), (x));\
+;} while (0)
+#define GET_H_SYS_GPR306() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR306))
+#define SET_H_SYS_GPR306(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR306), (x));\
+;} while (0)
+#define GET_H_SYS_GPR307() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR307))
+#define SET_H_SYS_GPR307(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR307), (x));\
+;} while (0)
+#define GET_H_SYS_GPR308() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR308))
+#define SET_H_SYS_GPR308(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR308), (x));\
+;} while (0)
+#define GET_H_SYS_GPR309() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR309))
+#define SET_H_SYS_GPR309(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR309), (x));\
+;} while (0)
+#define GET_H_SYS_GPR310() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR310))
+#define SET_H_SYS_GPR310(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR310), (x));\
+;} while (0)
+#define GET_H_SYS_GPR311() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR311))
+#define SET_H_SYS_GPR311(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR311), (x));\
+;} while (0)
+#define GET_H_SYS_GPR312() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR312))
+#define SET_H_SYS_GPR312(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR312), (x));\
+;} while (0)
+#define GET_H_SYS_GPR313() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR313))
+#define SET_H_SYS_GPR313(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR313), (x));\
+;} while (0)
+#define GET_H_SYS_GPR314() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR314))
+#define SET_H_SYS_GPR314(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR314), (x));\
+;} while (0)
+#define GET_H_SYS_GPR315() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR315))
+#define SET_H_SYS_GPR315(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR315), (x));\
+;} while (0)
+#define GET_H_SYS_GPR316() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR316))
+#define SET_H_SYS_GPR316(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR316), (x));\
+;} while (0)
+#define GET_H_SYS_GPR317() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR317))
+#define SET_H_SYS_GPR317(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR317), (x));\
+;} while (0)
+#define GET_H_SYS_GPR318() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR318))
+#define SET_H_SYS_GPR318(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR318), (x));\
+;} while (0)
+#define GET_H_SYS_GPR319() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR319))
+#define SET_H_SYS_GPR319(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR319), (x));\
+;} while (0)
+#define GET_H_SYS_GPR320() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR320))
+#define SET_H_SYS_GPR320(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR320), (x));\
+;} while (0)
+#define GET_H_SYS_GPR321() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR321))
+#define SET_H_SYS_GPR321(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR321), (x));\
+;} while (0)
+#define GET_H_SYS_GPR322() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR322))
+#define SET_H_SYS_GPR322(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR322), (x));\
+;} while (0)
+#define GET_H_SYS_GPR323() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR323))
+#define SET_H_SYS_GPR323(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR323), (x));\
+;} while (0)
+#define GET_H_SYS_GPR324() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR324))
+#define SET_H_SYS_GPR324(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR324), (x));\
+;} while (0)
+#define GET_H_SYS_GPR325() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR325))
+#define SET_H_SYS_GPR325(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR325), (x));\
+;} while (0)
+#define GET_H_SYS_GPR326() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR326))
+#define SET_H_SYS_GPR326(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR326), (x));\
+;} while (0)
+#define GET_H_SYS_GPR327() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR327))
+#define SET_H_SYS_GPR327(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR327), (x));\
+;} while (0)
+#define GET_H_SYS_GPR328() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR328))
+#define SET_H_SYS_GPR328(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR328), (x));\
+;} while (0)
+#define GET_H_SYS_GPR329() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR329))
+#define SET_H_SYS_GPR329(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR329), (x));\
+;} while (0)
+#define GET_H_SYS_GPR330() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR330))
+#define SET_H_SYS_GPR330(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR330), (x));\
+;} while (0)
+#define GET_H_SYS_GPR331() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR331))
+#define SET_H_SYS_GPR331(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR331), (x));\
+;} while (0)
+#define GET_H_SYS_GPR332() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR332))
+#define SET_H_SYS_GPR332(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR332), (x));\
+;} while (0)
+#define GET_H_SYS_GPR333() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR333))
+#define SET_H_SYS_GPR333(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR333), (x));\
+;} while (0)
+#define GET_H_SYS_GPR334() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR334))
+#define SET_H_SYS_GPR334(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR334), (x));\
+;} while (0)
+#define GET_H_SYS_GPR335() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR335))
+#define SET_H_SYS_GPR335(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR335), (x));\
+;} while (0)
+#define GET_H_SYS_GPR336() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR336))
+#define SET_H_SYS_GPR336(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR336), (x));\
+;} while (0)
+#define GET_H_SYS_GPR337() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR337))
+#define SET_H_SYS_GPR337(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR337), (x));\
+;} while (0)
+#define GET_H_SYS_GPR338() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR338))
+#define SET_H_SYS_GPR338(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR338), (x));\
+;} while (0)
+#define GET_H_SYS_GPR339() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR339))
+#define SET_H_SYS_GPR339(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR339), (x));\
+;} while (0)
+#define GET_H_SYS_GPR340() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR340))
+#define SET_H_SYS_GPR340(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR340), (x));\
+;} while (0)
+#define GET_H_SYS_GPR341() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR341))
+#define SET_H_SYS_GPR341(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR341), (x));\
+;} while (0)
+#define GET_H_SYS_GPR342() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR342))
+#define SET_H_SYS_GPR342(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR342), (x));\
+;} while (0)
+#define GET_H_SYS_GPR343() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR343))
+#define SET_H_SYS_GPR343(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR343), (x));\
+;} while (0)
+#define GET_H_SYS_GPR344() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR344))
+#define SET_H_SYS_GPR344(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR344), (x));\
+;} while (0)
+#define GET_H_SYS_GPR345() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR345))
+#define SET_H_SYS_GPR345(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR345), (x));\
+;} while (0)
+#define GET_H_SYS_GPR346() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR346))
+#define SET_H_SYS_GPR346(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR346), (x));\
+;} while (0)
+#define GET_H_SYS_GPR347() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR347))
+#define SET_H_SYS_GPR347(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR347), (x));\
+;} while (0)
+#define GET_H_SYS_GPR348() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR348))
+#define SET_H_SYS_GPR348(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR348), (x));\
+;} while (0)
+#define GET_H_SYS_GPR349() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR349))
+#define SET_H_SYS_GPR349(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR349), (x));\
+;} while (0)
+#define GET_H_SYS_GPR350() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR350))
+#define SET_H_SYS_GPR350(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR350), (x));\
+;} while (0)
+#define GET_H_SYS_GPR351() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR351))
+#define SET_H_SYS_GPR351(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR351), (x));\
+;} while (0)
+#define GET_H_SYS_GPR352() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR352))
+#define SET_H_SYS_GPR352(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR352), (x));\
+;} while (0)
+#define GET_H_SYS_GPR353() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR353))
+#define SET_H_SYS_GPR353(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR353), (x));\
+;} while (0)
+#define GET_H_SYS_GPR354() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR354))
+#define SET_H_SYS_GPR354(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR354), (x));\
+;} while (0)
+#define GET_H_SYS_GPR355() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR355))
+#define SET_H_SYS_GPR355(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR355), (x));\
+;} while (0)
+#define GET_H_SYS_GPR356() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR356))
+#define SET_H_SYS_GPR356(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR356), (x));\
+;} while (0)
+#define GET_H_SYS_GPR357() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR357))
+#define SET_H_SYS_GPR357(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR357), (x));\
+;} while (0)
+#define GET_H_SYS_GPR358() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR358))
+#define SET_H_SYS_GPR358(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR358), (x));\
+;} while (0)
+#define GET_H_SYS_GPR359() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR359))
+#define SET_H_SYS_GPR359(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR359), (x));\
+;} while (0)
+#define GET_H_SYS_GPR360() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR360))
+#define SET_H_SYS_GPR360(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR360), (x));\
+;} while (0)
+#define GET_H_SYS_GPR361() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR361))
+#define SET_H_SYS_GPR361(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR361), (x));\
+;} while (0)
+#define GET_H_SYS_GPR362() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR362))
+#define SET_H_SYS_GPR362(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR362), (x));\
+;} while (0)
+#define GET_H_SYS_GPR363() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR363))
+#define SET_H_SYS_GPR363(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR363), (x));\
+;} while (0)
+#define GET_H_SYS_GPR364() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR364))
+#define SET_H_SYS_GPR364(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR364), (x));\
+;} while (0)
+#define GET_H_SYS_GPR365() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR365))
+#define SET_H_SYS_GPR365(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR365), (x));\
+;} while (0)
+#define GET_H_SYS_GPR366() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR366))
+#define SET_H_SYS_GPR366(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR366), (x));\
+;} while (0)
+#define GET_H_SYS_GPR367() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR367))
+#define SET_H_SYS_GPR367(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR367), (x));\
+;} while (0)
+#define GET_H_SYS_GPR368() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR368))
+#define SET_H_SYS_GPR368(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR368), (x));\
+;} while (0)
+#define GET_H_SYS_GPR369() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR369))
+#define SET_H_SYS_GPR369(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR369), (x));\
+;} while (0)
+#define GET_H_SYS_GPR370() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR370))
+#define SET_H_SYS_GPR370(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR370), (x));\
+;} while (0)
+#define GET_H_SYS_GPR371() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR371))
+#define SET_H_SYS_GPR371(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR371), (x));\
+;} while (0)
+#define GET_H_SYS_GPR372() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR372))
+#define SET_H_SYS_GPR372(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR372), (x));\
+;} while (0)
+#define GET_H_SYS_GPR373() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR373))
+#define SET_H_SYS_GPR373(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR373), (x));\
+;} while (0)
+#define GET_H_SYS_GPR374() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR374))
+#define SET_H_SYS_GPR374(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR374), (x));\
+;} while (0)
+#define GET_H_SYS_GPR375() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR375))
+#define SET_H_SYS_GPR375(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR375), (x));\
+;} while (0)
+#define GET_H_SYS_GPR376() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR376))
+#define SET_H_SYS_GPR376(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR376), (x));\
+;} while (0)
+#define GET_H_SYS_GPR377() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR377))
+#define SET_H_SYS_GPR377(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR377), (x));\
+;} while (0)
+#define GET_H_SYS_GPR378() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR378))
+#define SET_H_SYS_GPR378(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR378), (x));\
+;} while (0)
+#define GET_H_SYS_GPR379() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR379))
+#define SET_H_SYS_GPR379(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR379), (x));\
+;} while (0)
+#define GET_H_SYS_GPR380() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR380))
+#define SET_H_SYS_GPR380(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR380), (x));\
+;} while (0)
+#define GET_H_SYS_GPR381() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR381))
+#define SET_H_SYS_GPR381(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR381), (x));\
+;} while (0)
+#define GET_H_SYS_GPR382() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR382))
+#define SET_H_SYS_GPR382(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR382), (x));\
+;} while (0)
+#define GET_H_SYS_GPR383() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR383))
+#define SET_H_SYS_GPR383(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR383), (x));\
+;} while (0)
+#define GET_H_SYS_GPR384() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR384))
+#define SET_H_SYS_GPR384(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR384), (x));\
+;} while (0)
+#define GET_H_SYS_GPR385() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR385))
+#define SET_H_SYS_GPR385(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR385), (x));\
+;} while (0)
+#define GET_H_SYS_GPR386() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR386))
+#define SET_H_SYS_GPR386(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR386), (x));\
+;} while (0)
+#define GET_H_SYS_GPR387() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR387))
+#define SET_H_SYS_GPR387(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR387), (x));\
+;} while (0)
+#define GET_H_SYS_GPR388() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR388))
+#define SET_H_SYS_GPR388(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR388), (x));\
+;} while (0)
+#define GET_H_SYS_GPR389() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR389))
+#define SET_H_SYS_GPR389(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR389), (x));\
+;} while (0)
+#define GET_H_SYS_GPR390() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR390))
+#define SET_H_SYS_GPR390(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR390), (x));\
+;} while (0)
+#define GET_H_SYS_GPR391() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR391))
+#define SET_H_SYS_GPR391(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR391), (x));\
+;} while (0)
+#define GET_H_SYS_GPR392() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR392))
+#define SET_H_SYS_GPR392(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR392), (x));\
+;} while (0)
+#define GET_H_SYS_GPR393() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR393))
+#define SET_H_SYS_GPR393(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR393), (x));\
+;} while (0)
+#define GET_H_SYS_GPR394() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR394))
+#define SET_H_SYS_GPR394(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR394), (x));\
+;} while (0)
+#define GET_H_SYS_GPR395() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR395))
+#define SET_H_SYS_GPR395(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR395), (x));\
+;} while (0)
+#define GET_H_SYS_GPR396() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR396))
+#define SET_H_SYS_GPR396(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR396), (x));\
+;} while (0)
+#define GET_H_SYS_GPR397() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR397))
+#define SET_H_SYS_GPR397(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR397), (x));\
+;} while (0)
+#define GET_H_SYS_GPR398() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR398))
+#define SET_H_SYS_GPR398(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR398), (x));\
+;} while (0)
+#define GET_H_SYS_GPR399() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR399))
+#define SET_H_SYS_GPR399(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR399), (x));\
+;} while (0)
+#define GET_H_SYS_GPR400() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR400))
+#define SET_H_SYS_GPR400(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR400), (x));\
+;} while (0)
+#define GET_H_SYS_GPR401() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR401))
+#define SET_H_SYS_GPR401(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR401), (x));\
+;} while (0)
+#define GET_H_SYS_GPR402() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR402))
+#define SET_H_SYS_GPR402(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR402), (x));\
+;} while (0)
+#define GET_H_SYS_GPR403() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR403))
+#define SET_H_SYS_GPR403(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR403), (x));\
+;} while (0)
+#define GET_H_SYS_GPR404() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR404))
+#define SET_H_SYS_GPR404(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR404), (x));\
+;} while (0)
+#define GET_H_SYS_GPR405() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR405))
+#define SET_H_SYS_GPR405(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR405), (x));\
+;} while (0)
+#define GET_H_SYS_GPR406() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR406))
+#define SET_H_SYS_GPR406(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR406), (x));\
+;} while (0)
+#define GET_H_SYS_GPR407() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR407))
+#define SET_H_SYS_GPR407(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR407), (x));\
+;} while (0)
+#define GET_H_SYS_GPR408() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR408))
+#define SET_H_SYS_GPR408(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR408), (x));\
+;} while (0)
+#define GET_H_SYS_GPR409() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR409))
+#define SET_H_SYS_GPR409(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR409), (x));\
+;} while (0)
+#define GET_H_SYS_GPR410() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR410))
+#define SET_H_SYS_GPR410(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR410), (x));\
+;} while (0)
+#define GET_H_SYS_GPR411() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR411))
+#define SET_H_SYS_GPR411(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR411), (x));\
+;} while (0)
+#define GET_H_SYS_GPR412() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR412))
+#define SET_H_SYS_GPR412(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR412), (x));\
+;} while (0)
+#define GET_H_SYS_GPR413() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR413))
+#define SET_H_SYS_GPR413(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR413), (x));\
+;} while (0)
+#define GET_H_SYS_GPR414() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR414))
+#define SET_H_SYS_GPR414(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR414), (x));\
+;} while (0)
+#define GET_H_SYS_GPR415() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR415))
+#define SET_H_SYS_GPR415(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR415), (x));\
+;} while (0)
+#define GET_H_SYS_GPR416() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR416))
+#define SET_H_SYS_GPR416(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR416), (x));\
+;} while (0)
+#define GET_H_SYS_GPR417() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR417))
+#define SET_H_SYS_GPR417(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR417), (x));\
+;} while (0)
+#define GET_H_SYS_GPR418() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR418))
+#define SET_H_SYS_GPR418(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR418), (x));\
+;} while (0)
+#define GET_H_SYS_GPR419() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR419))
+#define SET_H_SYS_GPR419(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR419), (x));\
+;} while (0)
+#define GET_H_SYS_GPR420() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR420))
+#define SET_H_SYS_GPR420(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR420), (x));\
+;} while (0)
+#define GET_H_SYS_GPR421() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR421))
+#define SET_H_SYS_GPR421(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR421), (x));\
+;} while (0)
+#define GET_H_SYS_GPR422() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR422))
+#define SET_H_SYS_GPR422(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR422), (x));\
+;} while (0)
+#define GET_H_SYS_GPR423() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR423))
+#define SET_H_SYS_GPR423(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR423), (x));\
+;} while (0)
+#define GET_H_SYS_GPR424() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR424))
+#define SET_H_SYS_GPR424(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR424), (x));\
+;} while (0)
+#define GET_H_SYS_GPR425() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR425))
+#define SET_H_SYS_GPR425(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR425), (x));\
+;} while (0)
+#define GET_H_SYS_GPR426() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR426))
+#define SET_H_SYS_GPR426(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR426), (x));\
+;} while (0)
+#define GET_H_SYS_GPR427() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR427))
+#define SET_H_SYS_GPR427(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR427), (x));\
+;} while (0)
+#define GET_H_SYS_GPR428() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR428))
+#define SET_H_SYS_GPR428(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR428), (x));\
+;} while (0)
+#define GET_H_SYS_GPR429() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR429))
+#define SET_H_SYS_GPR429(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR429), (x));\
+;} while (0)
+#define GET_H_SYS_GPR430() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR430))
+#define SET_H_SYS_GPR430(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR430), (x));\
+;} while (0)
+#define GET_H_SYS_GPR431() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR431))
+#define SET_H_SYS_GPR431(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR431), (x));\
+;} while (0)
+#define GET_H_SYS_GPR432() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR432))
+#define SET_H_SYS_GPR432(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR432), (x));\
+;} while (0)
+#define GET_H_SYS_GPR433() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR433))
+#define SET_H_SYS_GPR433(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR433), (x));\
+;} while (0)
+#define GET_H_SYS_GPR434() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR434))
+#define SET_H_SYS_GPR434(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR434), (x));\
+;} while (0)
+#define GET_H_SYS_GPR435() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR435))
+#define SET_H_SYS_GPR435(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR435), (x));\
+;} while (0)
+#define GET_H_SYS_GPR436() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR436))
+#define SET_H_SYS_GPR436(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR436), (x));\
+;} while (0)
+#define GET_H_SYS_GPR437() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR437))
+#define SET_H_SYS_GPR437(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR437), (x));\
+;} while (0)
+#define GET_H_SYS_GPR438() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR438))
+#define SET_H_SYS_GPR438(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR438), (x));\
+;} while (0)
+#define GET_H_SYS_GPR439() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR439))
+#define SET_H_SYS_GPR439(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR439), (x));\
+;} while (0)
+#define GET_H_SYS_GPR440() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR440))
+#define SET_H_SYS_GPR440(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR440), (x));\
+;} while (0)
+#define GET_H_SYS_GPR441() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR441))
+#define SET_H_SYS_GPR441(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR441), (x));\
+;} while (0)
+#define GET_H_SYS_GPR442() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR442))
+#define SET_H_SYS_GPR442(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR442), (x));\
+;} while (0)
+#define GET_H_SYS_GPR443() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR443))
+#define SET_H_SYS_GPR443(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR443), (x));\
+;} while (0)
+#define GET_H_SYS_GPR444() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR444))
+#define SET_H_SYS_GPR444(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR444), (x));\
+;} while (0)
+#define GET_H_SYS_GPR445() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR445))
+#define SET_H_SYS_GPR445(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR445), (x));\
+;} while (0)
+#define GET_H_SYS_GPR446() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR446))
+#define SET_H_SYS_GPR446(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR446), (x));\
+;} while (0)
+#define GET_H_SYS_GPR447() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR447))
+#define SET_H_SYS_GPR447(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR447), (x));\
+;} while (0)
+#define GET_H_SYS_GPR448() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR448))
+#define SET_H_SYS_GPR448(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR448), (x));\
+;} while (0)
+#define GET_H_SYS_GPR449() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR449))
+#define SET_H_SYS_GPR449(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR449), (x));\
+;} while (0)
+#define GET_H_SYS_GPR450() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR450))
+#define SET_H_SYS_GPR450(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR450), (x));\
+;} while (0)
+#define GET_H_SYS_GPR451() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR451))
+#define SET_H_SYS_GPR451(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR451), (x));\
+;} while (0)
+#define GET_H_SYS_GPR452() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR452))
+#define SET_H_SYS_GPR452(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR452), (x));\
+;} while (0)
+#define GET_H_SYS_GPR453() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR453))
+#define SET_H_SYS_GPR453(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR453), (x));\
+;} while (0)
+#define GET_H_SYS_GPR454() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR454))
+#define SET_H_SYS_GPR454(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR454), (x));\
+;} while (0)
+#define GET_H_SYS_GPR455() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR455))
+#define SET_H_SYS_GPR455(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR455), (x));\
+;} while (0)
+#define GET_H_SYS_GPR456() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR456))
+#define SET_H_SYS_GPR456(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR456), (x));\
+;} while (0)
+#define GET_H_SYS_GPR457() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR457))
+#define SET_H_SYS_GPR457(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR457), (x));\
+;} while (0)
+#define GET_H_SYS_GPR458() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR458))
+#define SET_H_SYS_GPR458(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR458), (x));\
+;} while (0)
+#define GET_H_SYS_GPR459() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR459))
+#define SET_H_SYS_GPR459(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR459), (x));\
+;} while (0)
+#define GET_H_SYS_GPR460() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR460))
+#define SET_H_SYS_GPR460(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR460), (x));\
+;} while (0)
+#define GET_H_SYS_GPR461() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR461))
+#define SET_H_SYS_GPR461(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR461), (x));\
+;} while (0)
+#define GET_H_SYS_GPR462() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR462))
+#define SET_H_SYS_GPR462(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR462), (x));\
+;} while (0)
+#define GET_H_SYS_GPR463() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR463))
+#define SET_H_SYS_GPR463(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR463), (x));\
+;} while (0)
+#define GET_H_SYS_GPR464() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR464))
+#define SET_H_SYS_GPR464(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR464), (x));\
+;} while (0)
+#define GET_H_SYS_GPR465() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR465))
+#define SET_H_SYS_GPR465(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR465), (x));\
+;} while (0)
+#define GET_H_SYS_GPR466() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR466))
+#define SET_H_SYS_GPR466(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR466), (x));\
+;} while (0)
+#define GET_H_SYS_GPR467() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR467))
+#define SET_H_SYS_GPR467(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR467), (x));\
+;} while (0)
+#define GET_H_SYS_GPR468() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR468))
+#define SET_H_SYS_GPR468(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR468), (x));\
+;} while (0)
+#define GET_H_SYS_GPR469() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR469))
+#define SET_H_SYS_GPR469(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR469), (x));\
+;} while (0)
+#define GET_H_SYS_GPR470() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR470))
+#define SET_H_SYS_GPR470(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR470), (x));\
+;} while (0)
+#define GET_H_SYS_GPR471() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR471))
+#define SET_H_SYS_GPR471(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR471), (x));\
+;} while (0)
+#define GET_H_SYS_GPR472() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR472))
+#define SET_H_SYS_GPR472(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR472), (x));\
+;} while (0)
+#define GET_H_SYS_GPR473() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR473))
+#define SET_H_SYS_GPR473(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR473), (x));\
+;} while (0)
+#define GET_H_SYS_GPR474() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR474))
+#define SET_H_SYS_GPR474(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR474), (x));\
+;} while (0)
+#define GET_H_SYS_GPR475() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR475))
+#define SET_H_SYS_GPR475(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR475), (x));\
+;} while (0)
+#define GET_H_SYS_GPR476() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR476))
+#define SET_H_SYS_GPR476(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR476), (x));\
+;} while (0)
+#define GET_H_SYS_GPR477() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR477))
+#define SET_H_SYS_GPR477(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR477), (x));\
+;} while (0)
+#define GET_H_SYS_GPR478() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR478))
+#define SET_H_SYS_GPR478(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR478), (x));\
+;} while (0)
+#define GET_H_SYS_GPR479() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR479))
+#define SET_H_SYS_GPR479(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR479), (x));\
+;} while (0)
+#define GET_H_SYS_GPR480() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR480))
+#define SET_H_SYS_GPR480(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR480), (x));\
+;} while (0)
+#define GET_H_SYS_GPR481() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR481))
+#define SET_H_SYS_GPR481(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR481), (x));\
+;} while (0)
+#define GET_H_SYS_GPR482() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR482))
+#define SET_H_SYS_GPR482(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR482), (x));\
+;} while (0)
+#define GET_H_SYS_GPR483() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR483))
+#define SET_H_SYS_GPR483(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR483), (x));\
+;} while (0)
+#define GET_H_SYS_GPR484() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR484))
+#define SET_H_SYS_GPR484(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR484), (x));\
+;} while (0)
+#define GET_H_SYS_GPR485() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR485))
+#define SET_H_SYS_GPR485(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR485), (x));\
+;} while (0)
+#define GET_H_SYS_GPR486() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR486))
+#define SET_H_SYS_GPR486(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR486), (x));\
+;} while (0)
+#define GET_H_SYS_GPR487() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR487))
+#define SET_H_SYS_GPR487(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR487), (x));\
+;} while (0)
+#define GET_H_SYS_GPR488() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR488))
+#define SET_H_SYS_GPR488(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR488), (x));\
+;} while (0)
+#define GET_H_SYS_GPR489() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR489))
+#define SET_H_SYS_GPR489(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR489), (x));\
+;} while (0)
+#define GET_H_SYS_GPR490() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR490))
+#define SET_H_SYS_GPR490(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR490), (x));\
+;} while (0)
+#define GET_H_SYS_GPR491() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR491))
+#define SET_H_SYS_GPR491(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR491), (x));\
+;} while (0)
+#define GET_H_SYS_GPR492() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR492))
+#define SET_H_SYS_GPR492(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR492), (x));\
+;} while (0)
+#define GET_H_SYS_GPR493() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR493))
+#define SET_H_SYS_GPR493(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR493), (x));\
+;} while (0)
+#define GET_H_SYS_GPR494() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR494))
+#define SET_H_SYS_GPR494(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR494), (x));\
+;} while (0)
+#define GET_H_SYS_GPR495() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR495))
+#define SET_H_SYS_GPR495(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR495), (x));\
+;} while (0)
+#define GET_H_SYS_GPR496() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR496))
+#define SET_H_SYS_GPR496(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR496), (x));\
+;} while (0)
+#define GET_H_SYS_GPR497() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR497))
+#define SET_H_SYS_GPR497(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR497), (x));\
+;} while (0)
+#define GET_H_SYS_GPR498() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR498))
+#define SET_H_SYS_GPR498(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR498), (x));\
+;} while (0)
+#define GET_H_SYS_GPR499() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR499))
+#define SET_H_SYS_GPR499(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR499), (x));\
+;} while (0)
+#define GET_H_SYS_GPR500() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR500))
+#define SET_H_SYS_GPR500(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR500), (x));\
+;} while (0)
+#define GET_H_SYS_GPR501() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR501))
+#define SET_H_SYS_GPR501(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR501), (x));\
+;} while (0)
+#define GET_H_SYS_GPR502() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR502))
+#define SET_H_SYS_GPR502(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR502), (x));\
+;} while (0)
+#define GET_H_SYS_GPR503() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR503))
+#define SET_H_SYS_GPR503(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR503), (x));\
+;} while (0)
+#define GET_H_SYS_GPR504() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR504))
+#define SET_H_SYS_GPR504(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR504), (x));\
+;} while (0)
+#define GET_H_SYS_GPR505() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR505))
+#define SET_H_SYS_GPR505(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR505), (x));\
+;} while (0)
+#define GET_H_SYS_GPR506() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR506))
+#define SET_H_SYS_GPR506(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR506), (x));\
+;} while (0)
+#define GET_H_SYS_GPR507() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR507))
+#define SET_H_SYS_GPR507(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR507), (x));\
+;} while (0)
+#define GET_H_SYS_GPR508() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR508))
+#define SET_H_SYS_GPR508(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR508), (x));\
+;} while (0)
+#define GET_H_SYS_GPR509() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR509))
+#define SET_H_SYS_GPR509(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR509), (x));\
+;} while (0)
+#define GET_H_SYS_GPR510() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR510))
+#define SET_H_SYS_GPR510(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR510), (x));\
+;} while (0)
+#define GET_H_SYS_GPR511() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR511))
+#define SET_H_SYS_GPR511(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR511), (x));\
+;} while (0)
+#define GET_H_MAC_MACLO() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACLO))
+#define SET_H_MAC_MACLO(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACLO), (x));\
+;} while (0)
+#define GET_H_MAC_MACHI() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACHI))
+#define SET_H_MAC_MACHI(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACHI), (x));\
+;} while (0)
+#define GET_H_TICK_TTMR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR))
+#define SET_H_TICK_TTMR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR), (x));\
+;} while (0)
+#define GET_H_SYS_VR_REV() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 5, 0)
+#define SET_H_SYS_VR_REV(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 5, 0, (x));\
+;} while (0)
+#define GET_H_SYS_VR_CFG() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 23, 16)
+#define SET_H_SYS_VR_CFG(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 23, 16, (x));\
+;} while (0)
+#define GET_H_SYS_VR_VER() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 31, 24)
+#define SET_H_SYS_VR_VER(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 31, 24, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_UP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 0, 0)
+#define SET_H_SYS_UPR_UP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 0, 0, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_DCP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 1, 1)
+#define SET_H_SYS_UPR_DCP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 1, 1, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_ICP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 2, 2)
+#define SET_H_SYS_UPR_ICP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 2, 2, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_DMP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 3, 3)
+#define SET_H_SYS_UPR_DMP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 3, 3, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_MP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 4, 4)
+#define SET_H_SYS_UPR_MP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 4, 4, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_IMP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 5, 5)
+#define SET_H_SYS_UPR_IMP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 5, 5, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_DUP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 6, 6)
+#define SET_H_SYS_UPR_DUP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 6, 6, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_PCUP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 7, 7)
+#define SET_H_SYS_UPR_PCUP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 7, 7, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_PICP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 8, 8)
+#define SET_H_SYS_UPR_PICP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 8, 8, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_PMP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 9, 9)
+#define SET_H_SYS_UPR_PMP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 9, 9, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_TTP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 10, 10)
+#define SET_H_SYS_UPR_TTP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 10, 10, (x));\
+;} while (0)
+#define GET_H_SYS_UPR_CUP() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 31, 24)
+#define SET_H_SYS_UPR_CUP(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_UPR), 31, 24, (x));\
+;} while (0)
+#define GET_H_SYS_CPUCFGR_NSGR() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 3, 0)
+#define SET_H_SYS_CPUCFGR_NSGR(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 3, 0, (x));\
+;} while (0)
+#define GET_H_SYS_CPUCFGR_CGF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 4, 4)
+#define SET_H_SYS_CPUCFGR_CGF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 4, 4, (x));\
+;} while (0)
+#define GET_H_SYS_CPUCFGR_OB32S() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 5, 5)
+#define SET_H_SYS_CPUCFGR_OB32S(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 5, 5, (x));\
+;} while (0)
+#define GET_H_SYS_CPUCFGR_OB64S() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 6, 6)
+#define SET_H_SYS_CPUCFGR_OB64S(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 6, 6, (x));\
+;} while (0)
+#define GET_H_SYS_CPUCFGR_OF32S() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 7, 7)
+#define SET_H_SYS_CPUCFGR_OF32S(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 7, 7, (x));\
+;} while (0)
+#define GET_H_SYS_CPUCFGR_OF64S() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 8, 8)
+#define SET_H_SYS_CPUCFGR_OF64S(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 8, 8, (x));\
+;} while (0)
+#define GET_H_SYS_CPUCFGR_OV64S() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 9, 9)
+#define SET_H_SYS_CPUCFGR_OV64S(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 9, 9, (x));\
+;} while (0)
+#define GET_H_SYS_CPUCFGR_ND() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 10, 10)
+#define SET_H_SYS_CPUCFGR_ND(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_CPUCFGR), 10, 10, (x));\
+;} while (0)
+#define GET_H_SYS_SR_SM() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 0, 0)
+#define SET_H_SYS_SR_SM(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 0, 0, (x));\
+;} while (0)
+#define GET_H_SYS_SR_TEE() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 1, 1)
+#define SET_H_SYS_SR_TEE(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 1, 1, (x));\
+;} while (0)
+#define GET_H_SYS_SR_IEE() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 2, 2)
+#define SET_H_SYS_SR_IEE(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 2, 2, (x));\
+;} while (0)
+#define GET_H_SYS_SR_DCE() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 3, 3)
+#define SET_H_SYS_SR_DCE(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 3, 3, (x));\
+;} while (0)
+#define GET_H_SYS_SR_ICE() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 4, 4)
+#define SET_H_SYS_SR_ICE(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 4, 4, (x));\
+;} while (0)
+#define GET_H_SYS_SR_DME() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 5, 5)
+#define SET_H_SYS_SR_DME(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 5, 5, (x));\
+;} while (0)
+#define GET_H_SYS_SR_IME() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 6, 6)
+#define SET_H_SYS_SR_IME(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 6, 6, (x));\
+;} while (0)
+#define GET_H_SYS_SR_LEE() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 7, 7)
+#define SET_H_SYS_SR_LEE(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 7, 7, (x));\
+;} while (0)
+#define GET_H_SYS_SR_CE() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 8, 8)
+#define SET_H_SYS_SR_CE(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 8, 8, (x));\
+;} while (0)
+#define GET_H_SYS_SR_F() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 9, 9)
+#define SET_H_SYS_SR_F(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 9, 9, (x));\
+;} while (0)
+#define GET_H_SYS_SR_CY() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 10, 10)
+#define SET_H_SYS_SR_CY(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 10, 10, (x));\
+;} while (0)
+#define GET_H_SYS_SR_OV() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 11, 11)
+#define SET_H_SYS_SR_OV(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 11, 11, (x));\
+;} while (0)
+#define GET_H_SYS_SR_OVE() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 12, 12)
+#define SET_H_SYS_SR_OVE(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 12, 12, (x));\
+;} while (0)
+#define GET_H_SYS_SR_DSX() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 13, 13)
+#define SET_H_SYS_SR_DSX(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 13, 13, (x));\
+;} while (0)
+#define GET_H_SYS_SR_EPH() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 14, 14)
+#define SET_H_SYS_SR_EPH(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 14, 14, (x));\
+;} while (0)
+#define GET_H_SYS_SR_FO() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 15, 15)
+#define SET_H_SYS_SR_FO(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 15, 15, (x));\
+;} while (0)
+#define GET_H_SYS_SR_SUMRA() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 16, 16)
+#define SET_H_SYS_SR_SUMRA(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 16, 16, (x));\
+;} while (0)
+#define GET_H_SYS_SR_CID() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 31, 28)
+#define SET_H_SYS_SR_CID(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_SR), 31, 28, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_FPEE() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 0, 0)
+#define SET_H_SYS_FPCSR_FPEE(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 0, 0, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_RM() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 2, 1)
+#define SET_H_SYS_FPCSR_RM(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 2, 1, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_OVF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 3, 3)
+#define SET_H_SYS_FPCSR_OVF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 3, 3, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_UNF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 4, 4)
+#define SET_H_SYS_FPCSR_UNF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 4, 4, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_SNF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 5, 5)
+#define SET_H_SYS_FPCSR_SNF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 5, 5, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_QNF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 6, 6)
+#define SET_H_SYS_FPCSR_QNF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 6, 6, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_ZF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 7, 7)
+#define SET_H_SYS_FPCSR_ZF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 7, 7, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_IXF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 8, 8)
+#define SET_H_SYS_FPCSR_IXF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 8, 8, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_IVF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 9, 9)
+#define SET_H_SYS_FPCSR_IVF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 9, 9, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_INF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 10, 10)
+#define SET_H_SYS_FPCSR_INF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 10, 10, (x));\
+;} while (0)
+#define GET_H_SYS_FPCSR_DZF() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 11, 11)
+#define SET_H_SYS_FPCSR_DZF(x) \
+do { \
+or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_FPCSR), 11, 11, (x));\
+;} while (0)
+
+/* Cover fns for register access. */
+USI or1k32bf_h_pc_get (SIM_CPU *);
+void or1k32bf_h_pc_set (SIM_CPU *, USI);
+SF or1k32bf_h_fsr_get (SIM_CPU *, UINT);
+void or1k32bf_h_fsr_set (SIM_CPU *, UINT, SF);
+USI or1k32bf_h_spr_get (SIM_CPU *, UINT);
+void or1k32bf_h_spr_set (SIM_CPU *, UINT, USI);
+USI or1k32bf_h_gpr_get (SIM_CPU *, UINT);
+void or1k32bf_h_gpr_set (SIM_CPU *, UINT, USI);
+USI or1k32bf_h_sys_vr_get (SIM_CPU *);
+void or1k32bf_h_sys_vr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_cpucfgr_get (SIM_CPU *);
+void or1k32bf_h_sys_cpucfgr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_dmmucfgr_get (SIM_CPU *);
+void or1k32bf_h_sys_dmmucfgr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_immucfgr_get (SIM_CPU *);
+void or1k32bf_h_sys_immucfgr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_dccfgr_get (SIM_CPU *);
+void or1k32bf_h_sys_dccfgr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_iccfgr_get (SIM_CPU *);
+void or1k32bf_h_sys_iccfgr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_dcfgr_get (SIM_CPU *);
+void or1k32bf_h_sys_dcfgr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_pccfgr_get (SIM_CPU *);
+void or1k32bf_h_sys_pccfgr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_npc_get (SIM_CPU *);
+void or1k32bf_h_sys_npc_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_ppc_get (SIM_CPU *);
+void or1k32bf_h_sys_ppc_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr0_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr0_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr1_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr1_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr2_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr2_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr3_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr3_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr4_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr4_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr5_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr5_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr6_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr6_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr7_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr7_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr8_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr8_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr9_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr9_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr10_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr10_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr11_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr11_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr12_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr12_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr13_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr13_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr14_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr14_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_epcr15_get (SIM_CPU *);
+void or1k32bf_h_sys_epcr15_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear0_get (SIM_CPU *);
+void or1k32bf_h_sys_eear0_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear1_get (SIM_CPU *);
+void or1k32bf_h_sys_eear1_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear2_get (SIM_CPU *);
+void or1k32bf_h_sys_eear2_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear3_get (SIM_CPU *);
+void or1k32bf_h_sys_eear3_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear4_get (SIM_CPU *);
+void or1k32bf_h_sys_eear4_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear5_get (SIM_CPU *);
+void or1k32bf_h_sys_eear5_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear6_get (SIM_CPU *);
+void or1k32bf_h_sys_eear6_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear7_get (SIM_CPU *);
+void or1k32bf_h_sys_eear7_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear8_get (SIM_CPU *);
+void or1k32bf_h_sys_eear8_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear9_get (SIM_CPU *);
+void or1k32bf_h_sys_eear9_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear10_get (SIM_CPU *);
+void or1k32bf_h_sys_eear10_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear11_get (SIM_CPU *);
+void or1k32bf_h_sys_eear11_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear12_get (SIM_CPU *);
+void or1k32bf_h_sys_eear12_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear13_get (SIM_CPU *);
+void or1k32bf_h_sys_eear13_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear14_get (SIM_CPU *);
+void or1k32bf_h_sys_eear14_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_eear15_get (SIM_CPU *);
+void or1k32bf_h_sys_eear15_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr0_get (SIM_CPU *);
+void or1k32bf_h_sys_esr0_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr1_get (SIM_CPU *);
+void or1k32bf_h_sys_esr1_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr2_get (SIM_CPU *);
+void or1k32bf_h_sys_esr2_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr3_get (SIM_CPU *);
+void or1k32bf_h_sys_esr3_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr4_get (SIM_CPU *);
+void or1k32bf_h_sys_esr4_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr5_get (SIM_CPU *);
+void or1k32bf_h_sys_esr5_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr6_get (SIM_CPU *);
+void or1k32bf_h_sys_esr6_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr7_get (SIM_CPU *);
+void or1k32bf_h_sys_esr7_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr8_get (SIM_CPU *);
+void or1k32bf_h_sys_esr8_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr9_get (SIM_CPU *);
+void or1k32bf_h_sys_esr9_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr10_get (SIM_CPU *);
+void or1k32bf_h_sys_esr10_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr11_get (SIM_CPU *);
+void or1k32bf_h_sys_esr11_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr12_get (SIM_CPU *);
+void or1k32bf_h_sys_esr12_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr13_get (SIM_CPU *);
+void or1k32bf_h_sys_esr13_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr14_get (SIM_CPU *);
+void or1k32bf_h_sys_esr14_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_esr15_get (SIM_CPU *);
+void or1k32bf_h_sys_esr15_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr0_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr0_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr1_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr1_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr2_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr2_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr3_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr3_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr4_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr4_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr5_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr5_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr6_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr6_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr7_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr7_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr8_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr8_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr9_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr9_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr10_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr10_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr11_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr11_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr12_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr12_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr13_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr13_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr14_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr14_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr15_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr15_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr16_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr16_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr17_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr17_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr18_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr18_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr19_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr19_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr20_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr20_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr21_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr21_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr22_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr22_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr23_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr23_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr24_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr24_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr25_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr25_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr26_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr26_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr27_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr27_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr28_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr28_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr29_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr29_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr30_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr30_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr31_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr31_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr32_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr32_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr33_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr33_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr34_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr34_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr35_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr35_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr36_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr36_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr37_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr37_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr38_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr38_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr39_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr39_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr40_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr40_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr41_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr41_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr42_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr42_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr43_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr43_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr44_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr44_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr45_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr45_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr46_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr46_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr47_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr47_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr48_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr48_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr49_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr49_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr50_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr50_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr51_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr51_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr52_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr52_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr53_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr53_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr54_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr54_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr55_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr55_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr56_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr56_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr57_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr57_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr58_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr58_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr59_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr59_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr60_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr60_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr61_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr61_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr62_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr62_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr63_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr63_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr64_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr64_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr65_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr65_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr66_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr66_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr67_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr67_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr68_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr68_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr69_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr69_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr70_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr70_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr71_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr71_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr72_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr72_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr73_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr73_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr74_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr74_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr75_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr75_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr76_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr76_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr77_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr77_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr78_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr78_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr79_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr79_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr80_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr80_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr81_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr81_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr82_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr82_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr83_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr83_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr84_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr84_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr85_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr85_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr86_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr86_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr87_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr87_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr88_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr88_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr89_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr89_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr90_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr90_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr91_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr91_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr92_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr92_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr93_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr93_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr94_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr94_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr95_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr95_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr96_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr96_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr97_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr97_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr98_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr98_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr99_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr99_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr100_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr100_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr101_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr101_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr102_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr102_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr103_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr103_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr104_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr104_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr105_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr105_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr106_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr106_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr107_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr107_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr108_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr108_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr109_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr109_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr110_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr110_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr111_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr111_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr112_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr112_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr113_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr113_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr114_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr114_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr115_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr115_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr116_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr116_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr117_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr117_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr118_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr118_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr119_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr119_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr120_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr120_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr121_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr121_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr122_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr122_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr123_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr123_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr124_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr124_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr125_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr125_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr126_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr126_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr127_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr127_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr128_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr128_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr129_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr129_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr130_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr130_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr131_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr131_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr132_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr132_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr133_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr133_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr134_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr134_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr135_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr135_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr136_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr136_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr137_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr137_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr138_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr138_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr139_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr139_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr140_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr140_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr141_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr141_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr142_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr142_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr143_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr143_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr144_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr144_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr145_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr145_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr146_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr146_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr147_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr147_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr148_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr148_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr149_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr149_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr150_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr150_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr151_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr151_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr152_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr152_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr153_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr153_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr154_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr154_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr155_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr155_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr156_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr156_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr157_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr157_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr158_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr158_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr159_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr159_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr160_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr160_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr161_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr161_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr162_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr162_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr163_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr163_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr164_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr164_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr165_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr165_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr166_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr166_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr167_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr167_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr168_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr168_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr169_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr169_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr170_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr170_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr171_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr171_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr172_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr172_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr173_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr173_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr174_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr174_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr175_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr175_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr176_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr176_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr177_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr177_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr178_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr178_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr179_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr179_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr180_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr180_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr181_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr181_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr182_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr182_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr183_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr183_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr184_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr184_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr185_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr185_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr186_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr186_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr187_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr187_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr188_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr188_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr189_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr189_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr190_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr190_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr191_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr191_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr192_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr192_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr193_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr193_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr194_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr194_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr195_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr195_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr196_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr196_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr197_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr197_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr198_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr198_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr199_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr199_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr200_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr200_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr201_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr201_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr202_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr202_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr203_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr203_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr204_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr204_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr205_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr205_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr206_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr206_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr207_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr207_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr208_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr208_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr209_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr209_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr210_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr210_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr211_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr211_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr212_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr212_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr213_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr213_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr214_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr214_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr215_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr215_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr216_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr216_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr217_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr217_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr218_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr218_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr219_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr219_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr220_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr220_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr221_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr221_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr222_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr222_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr223_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr223_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr224_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr224_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr225_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr225_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr226_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr226_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr227_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr227_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr228_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr228_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr229_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr229_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr230_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr230_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr231_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr231_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr232_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr232_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr233_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr233_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr234_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr234_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr235_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr235_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr236_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr236_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr237_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr237_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr238_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr238_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr239_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr239_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr240_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr240_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr241_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr241_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr242_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr242_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr243_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr243_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr244_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr244_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr245_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr245_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr246_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr246_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr247_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr247_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr248_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr248_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr249_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr249_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr250_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr250_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr251_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr251_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr252_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr252_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr253_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr253_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr254_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr254_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr255_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr255_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr256_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr256_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr257_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr257_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr258_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr258_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr259_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr259_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr260_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr260_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr261_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr261_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr262_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr262_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr263_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr263_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr264_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr264_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr265_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr265_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr266_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr266_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr267_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr267_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr268_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr268_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr269_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr269_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr270_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr270_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr271_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr271_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr272_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr272_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr273_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr273_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr274_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr274_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr275_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr275_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr276_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr276_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr277_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr277_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr278_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr278_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr279_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr279_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr280_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr280_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr281_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr281_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr282_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr282_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr283_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr283_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr284_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr284_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr285_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr285_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr286_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr286_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr287_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr287_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr288_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr288_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr289_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr289_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr290_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr290_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr291_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr291_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr292_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr292_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr293_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr293_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr294_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr294_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr295_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr295_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr296_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr296_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr297_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr297_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr298_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr298_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr299_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr299_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr300_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr300_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr301_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr301_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr302_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr302_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr303_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr303_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr304_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr304_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr305_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr305_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr306_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr306_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr307_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr307_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr308_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr308_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr309_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr309_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr310_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr310_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr311_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr311_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr312_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr312_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr313_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr313_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr314_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr314_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr315_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr315_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr316_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr316_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr317_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr317_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr318_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr318_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr319_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr319_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr320_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr320_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr321_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr321_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr322_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr322_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr323_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr323_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr324_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr324_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr325_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr325_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr326_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr326_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr327_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr327_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr328_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr328_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr329_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr329_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr330_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr330_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr331_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr331_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr332_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr332_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr333_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr333_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr334_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr334_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr335_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr335_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr336_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr336_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr337_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr337_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr338_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr338_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr339_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr339_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr340_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr340_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr341_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr341_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr342_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr342_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr343_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr343_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr344_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr344_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr345_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr345_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr346_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr346_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr347_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr347_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr348_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr348_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr349_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr349_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr350_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr350_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr351_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr351_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr352_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr352_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr353_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr353_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr354_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr354_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr355_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr355_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr356_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr356_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr357_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr357_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr358_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr358_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr359_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr359_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr360_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr360_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr361_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr361_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr362_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr362_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr363_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr363_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr364_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr364_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr365_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr365_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr366_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr366_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr367_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr367_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr368_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr368_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr369_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr369_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr370_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr370_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr371_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr371_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr372_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr372_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr373_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr373_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr374_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr374_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr375_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr375_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr376_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr376_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr377_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr377_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr378_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr378_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr379_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr379_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr380_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr380_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr381_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr381_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr382_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr382_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr383_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr383_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr384_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr384_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr385_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr385_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr386_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr386_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr387_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr387_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr388_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr388_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr389_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr389_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr390_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr390_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr391_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr391_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr392_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr392_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr393_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr393_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr394_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr394_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr395_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr395_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr396_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr396_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr397_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr397_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr398_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr398_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr399_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr399_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr400_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr400_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr401_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr401_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr402_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr402_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr403_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr403_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr404_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr404_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr405_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr405_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr406_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr406_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr407_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr407_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr408_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr408_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr409_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr409_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr410_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr410_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr411_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr411_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr412_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr412_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr413_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr413_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr414_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr414_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr415_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr415_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr416_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr416_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr417_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr417_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr418_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr418_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr419_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr419_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr420_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr420_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr421_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr421_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr422_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr422_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr423_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr423_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr424_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr424_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr425_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr425_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr426_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr426_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr427_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr427_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr428_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr428_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr429_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr429_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr430_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr430_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr431_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr431_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr432_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr432_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr433_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr433_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr434_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr434_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr435_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr435_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr436_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr436_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr437_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr437_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr438_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr438_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr439_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr439_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr440_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr440_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr441_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr441_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr442_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr442_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr443_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr443_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr444_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr444_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr445_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr445_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr446_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr446_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr447_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr447_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr448_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr448_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr449_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr449_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr450_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr450_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr451_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr451_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr452_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr452_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr453_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr453_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr454_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr454_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr455_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr455_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr456_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr456_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr457_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr457_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr458_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr458_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr459_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr459_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr460_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr460_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr461_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr461_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr462_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr462_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr463_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr463_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr464_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr464_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr465_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr465_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr466_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr466_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr467_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr467_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr468_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr468_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr469_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr469_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr470_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr470_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr471_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr471_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr472_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr472_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr473_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr473_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr474_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr474_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr475_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr475_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr476_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr476_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr477_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr477_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr478_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr478_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr479_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr479_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr480_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr480_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr481_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr481_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr482_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr482_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr483_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr483_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr484_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr484_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr485_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr485_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr486_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr486_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr487_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr487_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr488_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr488_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr489_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr489_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr490_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr490_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr491_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr491_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr492_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr492_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr493_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr493_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr494_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr494_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr495_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr495_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr496_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr496_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr497_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr497_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr498_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr498_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr499_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr499_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr500_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr500_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr501_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr501_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr502_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr502_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr503_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr503_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr504_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr504_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr505_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr505_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr506_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr506_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr507_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr507_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr508_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr508_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr509_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr509_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr510_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr510_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_gpr511_get (SIM_CPU *);
+void or1k32bf_h_sys_gpr511_set (SIM_CPU *, USI);
+USI or1k32bf_h_mac_maclo_get (SIM_CPU *);
+void or1k32bf_h_mac_maclo_set (SIM_CPU *, USI);
+USI or1k32bf_h_mac_machi_get (SIM_CPU *);
+void or1k32bf_h_mac_machi_set (SIM_CPU *, USI);
+USI or1k32bf_h_tick_ttmr_get (SIM_CPU *);
+void or1k32bf_h_tick_ttmr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_vr_rev_get (SIM_CPU *);
+void or1k32bf_h_sys_vr_rev_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_vr_cfg_get (SIM_CPU *);
+void or1k32bf_h_sys_vr_cfg_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_vr_ver_get (SIM_CPU *);
+void or1k32bf_h_sys_vr_ver_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_up_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_up_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_dcp_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_dcp_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_icp_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_icp_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_dmp_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_dmp_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_mp_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_mp_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_imp_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_imp_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_dup_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_dup_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_pcup_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_pcup_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_picp_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_picp_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_pmp_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_pmp_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_ttp_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_ttp_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_upr_cup_get (SIM_CPU *);
+void or1k32bf_h_sys_upr_cup_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_cpucfgr_nsgr_get (SIM_CPU *);
+void or1k32bf_h_sys_cpucfgr_nsgr_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_cpucfgr_cgf_get (SIM_CPU *);
+void or1k32bf_h_sys_cpucfgr_cgf_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_cpucfgr_ob32s_get (SIM_CPU *);
+void or1k32bf_h_sys_cpucfgr_ob32s_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_cpucfgr_ob64s_get (SIM_CPU *);
+void or1k32bf_h_sys_cpucfgr_ob64s_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_cpucfgr_of32s_get (SIM_CPU *);
+void or1k32bf_h_sys_cpucfgr_of32s_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_cpucfgr_of64s_get (SIM_CPU *);
+void or1k32bf_h_sys_cpucfgr_of64s_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_cpucfgr_ov64s_get (SIM_CPU *);
+void or1k32bf_h_sys_cpucfgr_ov64s_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_cpucfgr_nd_get (SIM_CPU *);
+void or1k32bf_h_sys_cpucfgr_nd_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_sm_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_sm_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_tee_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_tee_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_iee_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_iee_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_dce_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_dce_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_ice_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_ice_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_dme_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_dme_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_ime_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_ime_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_lee_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_lee_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_ce_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_ce_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_f_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_f_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_cy_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_cy_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_ov_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_ov_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_ove_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_ove_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_dsx_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_dsx_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_eph_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_eph_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_fo_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_fo_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_sumra_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_sumra_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_sr_cid_get (SIM_CPU *);
+void or1k32bf_h_sys_sr_cid_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_fpee_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_fpee_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_rm_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_rm_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_ovf_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_ovf_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_unf_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_unf_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_snf_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_snf_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_qnf_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_qnf_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_zf_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_zf_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_ixf_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_ixf_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_ivf_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_ivf_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_inf_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_inf_set (SIM_CPU *, USI);
+USI or1k32bf_h_sys_fpcsr_dzf_get (SIM_CPU *);
+void or1k32bf_h_sys_fpcsr_dzf_set (SIM_CPU *, USI);
+BI or1k32bf_h_atomic_reserve_get (SIM_CPU *);
+void or1k32bf_h_atomic_reserve_set (SIM_CPU *, BI);
+SI or1k32bf_h_atomic_address_get (SIM_CPU *);
+void or1k32bf_h_atomic_address_set (SIM_CPU *, SI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN or1k32bf_fetch_register;
+extern CPUREG_STORE_FN or1k32bf_store_register;
+
+typedef struct {
+ int empty;
+} MODEL_OR1200_DATA;
+
+typedef struct {
+ int empty;
+} MODEL_OR1200ND_DATA;
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } sfmt_empty;
+ struct { /* */
+ IADDR i_disp26;
+ } sfmt_l_j;
+ struct { /* */
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_uimm6;
+ } sfmt_l_slli;
+ struct { /* */
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+ } sfmt_l_sll;
+ struct { /* */
+ INT f_simm16_split;
+ UINT f_r2;
+ UINT f_r3;
+ } sfmt_l_sw;
+ struct { /* */
+ INT f_simm16;
+ UINT f_r1;
+ UINT f_r2;
+ } sfmt_l_lwz;
+ struct { /* */
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_uimm16_split;
+ } sfmt_l_mtspr;
+ struct { /* */
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_uimm16;
+ } sfmt_l_mfspr;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_L_J_VARS \
+ UINT f_opcode; \
+ USI f_disp26; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_J_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc)); \
+
+#define EXTRACT_IFMT_L_JR_VARS \
+ UINT f_opcode; \
+ UINT f_resv_25_10; \
+ UINT f_r3; \
+ UINT f_resv_10_11; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_JR_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_resv_25_10 = EXTRACT_LSB0_UINT (insn, 32, 25, 10); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
+
+#define EXTRACT_IFMT_L_TRAP_VARS \
+ UINT f_opcode; \
+ UINT f_op_25_5; \
+ UINT f_resv_20_5; \
+ UINT f_uimm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_TRAP_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_resv_20_5 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_L_MSYNC_VARS \
+ UINT f_opcode; \
+ UINT f_op_25_5; \
+ UINT f_resv_20_21; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_MSYNC_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_resv_20_21 = EXTRACT_LSB0_UINT (insn, 32, 20, 21); \
+
+#define EXTRACT_IFMT_L_RFE_VARS \
+ UINT f_opcode; \
+ UINT f_resv_25_26; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_RFE_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_resv_25_26 = EXTRACT_LSB0_UINT (insn, 32, 25, 26); \
+
+#define EXTRACT_IFMT_L_NOP_IMM_VARS \
+ UINT f_opcode; \
+ UINT f_op_25_2; \
+ UINT f_resv_23_8; \
+ UINT f_uimm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_NOP_IMM_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_op_25_2 = EXTRACT_LSB0_UINT (insn, 32, 25, 2); \
+ f_resv_23_8 = EXTRACT_LSB0_UINT (insn, 32, 23, 8); \
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_L_MOVHI_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_resv_20_4; \
+ UINT f_op_16_1; \
+ UINT f_uimm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_MOVHI_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_resv_20_4 = EXTRACT_LSB0_UINT (insn, 32, 20, 4); \
+ f_op_16_1 = EXTRACT_LSB0_UINT (insn, 32, 16, 1); \
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_L_MACRC_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_resv_20_4; \
+ UINT f_op_16_1; \
+ UINT f_uimm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_MACRC_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_resv_20_4 = EXTRACT_LSB0_UINT (insn, 32, 20, 4); \
+ f_op_16_1 = EXTRACT_LSB0_UINT (insn, 32, 16, 1); \
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_L_MFSPR_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_uimm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_MFSPR_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_L_MTSPR_VARS \
+ UINT f_opcode; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_imm16_25_5; \
+ UINT f_imm16_10_11; \
+ UINT f_uimm16_split; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_MTSPR_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
+ f_uimm16_split = ((UHI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
+
+#define EXTRACT_IFMT_L_LWZ_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_LWZ_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_L_SW_VARS \
+ UINT f_opcode; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_imm16_25_5; \
+ UINT f_imm16_10_11; \
+ INT f_simm16_split; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_SW_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
+ f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
+
+#define EXTRACT_IFMT_L_SWA_VARS \
+ UINT f_opcode; \
+ UINT f_r2; \
+ UINT f_r3; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_SWA_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_L_SLL_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_2; \
+ UINT f_resv_5_2; \
+ UINT f_op_3_4; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_SLL_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_2 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+ f_resv_5_2 = EXTRACT_LSB0_UINT (insn, 32, 5, 2); \
+ f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_L_SLLI_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_resv_15_8; \
+ UINT f_op_7_2; \
+ UINT f_uimm6; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_SLLI_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_resv_15_8 = EXTRACT_LSB0_UINT (insn, 32, 15, 8); \
+ f_op_7_2 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
+ f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_L_AND_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_7; \
+ UINT f_op_3_4; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_AND_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_7 = EXTRACT_LSB0_UINT (insn, 32, 10, 7); \
+ f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_L_EXTHS_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_resv_15_6; \
+ UINT f_op_9_4; \
+ UINT f_resv_5_2; \
+ UINT f_op_3_4; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_EXTHS_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_resv_15_6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_op_9_4 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
+ f_resv_5_2 = EXTRACT_LSB0_UINT (insn, 32, 5, 2); \
+ f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_L_CMOV_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_1; \
+ UINT f_op_9_2; \
+ UINT f_resv_7_4; \
+ UINT f_op_3_4; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_CMOV_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_1 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
+ f_op_9_2 = EXTRACT_LSB0_UINT (insn, 32, 9, 2); \
+ f_resv_7_4 = EXTRACT_LSB0_UINT (insn, 32, 7, 4); \
+ f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_L_SFGTS_VARS \
+ UINT f_opcode; \
+ UINT f_op_25_5; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_11; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_SFGTS_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
+
+#define EXTRACT_IFMT_L_SFGTSI_VARS \
+ UINT f_opcode; \
+ UINT f_op_25_5; \
+ UINT f_r2; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_SFGTSI_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_L_MAC_VARS \
+ UINT f_opcode; \
+ UINT f_op_25_5; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_7; \
+ UINT f_op_3_4; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_MAC_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_7 = EXTRACT_LSB0_UINT (insn, 32, 10, 7); \
+ f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_L_MACI_VARS \
+ UINT f_opcode; \
+ UINT f_resv_25_5; \
+ UINT f_r2; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_MACI_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_LF_ADD_S_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_ADD_S_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
+#define EXTRACT_IFMT_LF_ITOF_S_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_ITOF_S_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
+#define EXTRACT_IFMT_LF_FTOI_S_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_FTOI_S_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
+#define EXTRACT_IFMT_LF_EQ_S_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_EQ_S_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
+#define EXTRACT_IFMT_LF_CUST1_S_VARS \
+ UINT f_opcode; \
+ UINT f_resv_25_5; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_CUST1_S_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_OR1K32BF_H */
--- /dev/null
+/* Simulator CPU header for or1k.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef OR1K_CPUALL_H
+#define OR1K_CPUALL_H
+
+/* Include files for each cpu family. */
+
+#ifdef WANT_CPU_OR1K32BF
+#include "eng.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+extern const SIM_MACH or32_mach;
+extern const SIM_MACH or32nd_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+#endif
+
+#endif /* OR1K_CPUALL_H */
--- /dev/null
+/* Simulator instruction decoder for or1k32bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU or1k32bf
+#define WANT_CPU_OR1K32BF
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC or1k32bf_insn_data[OR1K32BF_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem or1k32bf_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, OR1K32BF_INSN_X_INVALID, OR1K32BF_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, OR1K32BF_INSN_X_AFTER, OR1K32BF_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, OR1K32BF_INSN_X_BEFORE, OR1K32BF_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, OR1K32BF_INSN_X_CTI_CHAIN, OR1K32BF_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, OR1K32BF_INSN_X_CHAIN, OR1K32BF_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, OR1K32BF_INSN_X_BEGIN, OR1K32BF_SFMT_EMPTY },
+ { OR1K_INSN_L_J, OR1K32BF_INSN_L_J, OR1K32BF_SFMT_L_J },
+ { OR1K_INSN_L_JAL, OR1K32BF_INSN_L_JAL, OR1K32BF_SFMT_L_JAL },
+ { OR1K_INSN_L_JR, OR1K32BF_INSN_L_JR, OR1K32BF_SFMT_L_JR },
+ { OR1K_INSN_L_JALR, OR1K32BF_INSN_L_JALR, OR1K32BF_SFMT_L_JALR },
+ { OR1K_INSN_L_BNF, OR1K32BF_INSN_L_BNF, OR1K32BF_SFMT_L_BNF },
+ { OR1K_INSN_L_BF, OR1K32BF_INSN_L_BF, OR1K32BF_SFMT_L_BNF },
+ { OR1K_INSN_L_TRAP, OR1K32BF_INSN_L_TRAP, OR1K32BF_SFMT_L_TRAP },
+ { OR1K_INSN_L_SYS, OR1K32BF_INSN_L_SYS, OR1K32BF_SFMT_L_TRAP },
+ { OR1K_INSN_L_MSYNC, OR1K32BF_INSN_L_MSYNC, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_PSYNC, OR1K32BF_INSN_L_PSYNC, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CSYNC, OR1K32BF_INSN_L_CSYNC, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_RFE, OR1K32BF_INSN_L_RFE, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_NOP_IMM, OR1K32BF_INSN_L_NOP_IMM, OR1K32BF_SFMT_L_NOP_IMM },
+ { OR1K_INSN_L_MOVHI, OR1K32BF_INSN_L_MOVHI, OR1K32BF_SFMT_L_MOVHI },
+ { OR1K_INSN_L_MACRC, OR1K32BF_INSN_L_MACRC, OR1K32BF_SFMT_L_MACRC },
+ { OR1K_INSN_L_MFSPR, OR1K32BF_INSN_L_MFSPR, OR1K32BF_SFMT_L_MFSPR },
+ { OR1K_INSN_L_MTSPR, OR1K32BF_INSN_L_MTSPR, OR1K32BF_SFMT_L_MTSPR },
+ { OR1K_INSN_L_LWZ, OR1K32BF_INSN_L_LWZ, OR1K32BF_SFMT_L_LWZ },
+ { OR1K_INSN_L_LWS, OR1K32BF_INSN_L_LWS, OR1K32BF_SFMT_L_LWS },
+ { OR1K_INSN_L_LWA, OR1K32BF_INSN_L_LWA, OR1K32BF_SFMT_L_LWA },
+ { OR1K_INSN_L_LBZ, OR1K32BF_INSN_L_LBZ, OR1K32BF_SFMT_L_LBZ },
+ { OR1K_INSN_L_LBS, OR1K32BF_INSN_L_LBS, OR1K32BF_SFMT_L_LBS },
+ { OR1K_INSN_L_LHZ, OR1K32BF_INSN_L_LHZ, OR1K32BF_SFMT_L_LHZ },
+ { OR1K_INSN_L_LHS, OR1K32BF_INSN_L_LHS, OR1K32BF_SFMT_L_LHS },
+ { OR1K_INSN_L_SW, OR1K32BF_INSN_L_SW, OR1K32BF_SFMT_L_SW },
+ { OR1K_INSN_L_SB, OR1K32BF_INSN_L_SB, OR1K32BF_SFMT_L_SB },
+ { OR1K_INSN_L_SH, OR1K32BF_INSN_L_SH, OR1K32BF_SFMT_L_SH },
+ { OR1K_INSN_L_SWA, OR1K32BF_INSN_L_SWA, OR1K32BF_SFMT_L_SWA },
+ { OR1K_INSN_L_SLL, OR1K32BF_INSN_L_SLL, OR1K32BF_SFMT_L_SLL },
+ { OR1K_INSN_L_SLLI, OR1K32BF_INSN_L_SLLI, OR1K32BF_SFMT_L_SLLI },
+ { OR1K_INSN_L_SRL, OR1K32BF_INSN_L_SRL, OR1K32BF_SFMT_L_SLL },
+ { OR1K_INSN_L_SRLI, OR1K32BF_INSN_L_SRLI, OR1K32BF_SFMT_L_SLLI },
+ { OR1K_INSN_L_SRA, OR1K32BF_INSN_L_SRA, OR1K32BF_SFMT_L_SLL },
+ { OR1K_INSN_L_SRAI, OR1K32BF_INSN_L_SRAI, OR1K32BF_SFMT_L_SLLI },
+ { OR1K_INSN_L_ROR, OR1K32BF_INSN_L_ROR, OR1K32BF_SFMT_L_SLL },
+ { OR1K_INSN_L_RORI, OR1K32BF_INSN_L_RORI, OR1K32BF_SFMT_L_SLLI },
+ { OR1K_INSN_L_AND, OR1K32BF_INSN_L_AND, OR1K32BF_SFMT_L_AND },
+ { OR1K_INSN_L_OR, OR1K32BF_INSN_L_OR, OR1K32BF_SFMT_L_AND },
+ { OR1K_INSN_L_XOR, OR1K32BF_INSN_L_XOR, OR1K32BF_SFMT_L_AND },
+ { OR1K_INSN_L_ADD, OR1K32BF_INSN_L_ADD, OR1K32BF_SFMT_L_ADD },
+ { OR1K_INSN_L_SUB, OR1K32BF_INSN_L_SUB, OR1K32BF_SFMT_L_ADD },
+ { OR1K_INSN_L_ADDC, OR1K32BF_INSN_L_ADDC, OR1K32BF_SFMT_L_ADDC },
+ { OR1K_INSN_L_MUL, OR1K32BF_INSN_L_MUL, OR1K32BF_SFMT_L_ADD },
+ { OR1K_INSN_L_MULU, OR1K32BF_INSN_L_MULU, OR1K32BF_SFMT_L_ADD },
+ { OR1K_INSN_L_DIV, OR1K32BF_INSN_L_DIV, OR1K32BF_SFMT_L_DIV },
+ { OR1K_INSN_L_DIVU, OR1K32BF_INSN_L_DIVU, OR1K32BF_SFMT_L_DIV },
+ { OR1K_INSN_L_FF1, OR1K32BF_INSN_L_FF1, OR1K32BF_SFMT_L_FF1 },
+ { OR1K_INSN_L_FL1, OR1K32BF_INSN_L_FL1, OR1K32BF_SFMT_L_FF1 },
+ { OR1K_INSN_L_ANDI, OR1K32BF_INSN_L_ANDI, OR1K32BF_SFMT_L_MFSPR },
+ { OR1K_INSN_L_ORI, OR1K32BF_INSN_L_ORI, OR1K32BF_SFMT_L_MFSPR },
+ { OR1K_INSN_L_XORI, OR1K32BF_INSN_L_XORI, OR1K32BF_SFMT_L_XORI },
+ { OR1K_INSN_L_ADDI, OR1K32BF_INSN_L_ADDI, OR1K32BF_SFMT_L_ADDI },
+ { OR1K_INSN_L_ADDIC, OR1K32BF_INSN_L_ADDIC, OR1K32BF_SFMT_L_ADDIC },
+ { OR1K_INSN_L_MULI, OR1K32BF_INSN_L_MULI, OR1K32BF_SFMT_L_ADDI },
+ { OR1K_INSN_L_EXTHS, OR1K32BF_INSN_L_EXTHS, OR1K32BF_SFMT_L_EXTHS },
+ { OR1K_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTBS, OR1K32BF_SFMT_L_EXTHS },
+ { OR1K_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_SFMT_L_EXTHS },
+ { OR1K_INSN_L_EXTBZ, OR1K32BF_INSN_L_EXTBZ, OR1K32BF_SFMT_L_EXTHS },
+ { OR1K_INSN_L_EXTWS, OR1K32BF_INSN_L_EXTWS, OR1K32BF_SFMT_L_EXTHS },
+ { OR1K_INSN_L_EXTWZ, OR1K32BF_INSN_L_EXTWZ, OR1K32BF_SFMT_L_EXTHS },
+ { OR1K_INSN_L_CMOV, OR1K32BF_INSN_L_CMOV, OR1K32BF_SFMT_L_CMOV },
+ { OR1K_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGTS, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFGTSI, OR1K32BF_INSN_L_SFGTSI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTU, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFGES, OR1K32BF_INSN_L_SFGES, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFGESI, OR1K32BF_INSN_L_SFGESI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEU, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLTS, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFLTSI, OR1K32BF_INSN_L_SFLTSI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTU, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLES, OR1K32BF_INSN_L_SFLES, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFLESI, OR1K32BF_INSN_L_SFLESI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEU, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQ, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFEQI, OR1K32BF_INSN_L_SFEQI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFNE, OR1K32BF_INSN_L_SFNE, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFNEI, OR1K32BF_INSN_L_SFNEI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_MAC, OR1K32BF_INSN_L_MAC, OR1K32BF_SFMT_L_MAC },
+ { OR1K_INSN_L_MSB, OR1K32BF_INSN_L_MSB, OR1K32BF_SFMT_L_MAC },
+ { OR1K_INSN_L_MACI, OR1K32BF_INSN_L_MACI, OR1K32BF_SFMT_L_MACI },
+ { OR1K_INSN_L_CUST1, OR1K32BF_INSN_L_CUST1, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST2, OR1K32BF_INSN_L_CUST2, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST3, OR1K32BF_INSN_L_CUST3, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST4, OR1K32BF_INSN_L_CUST4, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST5, OR1K32BF_INSN_L_CUST5, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST6, OR1K32BF_INSN_L_CUST6, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST7, OR1K32BF_INSN_L_CUST7, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST8, OR1K32BF_INSN_L_CUST8, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_LF_ADD_S, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_MUL_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_DIV_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_REM_S, OR1K32BF_INSN_LF_REM_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_SFMT_LF_ITOF_S },
+ { OR1K_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_SFMT_LF_FTOI_S },
+ { OR1K_INSN_LF_EQ_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_NE_S, OR1K32BF_INSN_LF_NE_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_GE_S, OR1K32BF_INSN_LF_GE_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_GT_S, OR1K32BF_INSN_LF_GT_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_LT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_LE_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_MADD_S, OR1K32BF_INSN_LF_MADD_S, OR1K32BF_SFMT_LF_MADD_S },
+ { OR1K_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_SFMT_L_MSYNC },
+};
+
+static const struct insn_sem or1k32bf_insn_sem_invalid =
+{
+ VIRTUAL_INSN_X_INVALID, OR1K32BF_INSN_X_INVALID, OR1K32BF_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+or1k32bf_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = OR1K32BF_INSN__MAX;
+ IDESC *table = or1k32bf_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & or1k32bf_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = or1k32bf_insn_sem, tend = t + sizeof (or1k32bf_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ OR1K32BF_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_WORD insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 21) & (63 << 5)) | ((insn >> 2) & (1 << 4)) | ((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 : /* fall through */
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 : /* fall through */
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 : itype = OR1K32BF_INSN_L_J; goto extract_sfmt_l_j;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 : /* fall through */
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 : itype = OR1K32BF_INSN_L_JAL; goto extract_sfmt_l_jal;
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 : itype = OR1K32BF_INSN_L_BNF; goto extract_sfmt_l_bnf;
+ case 128 : /* fall through */
+ case 129 : /* fall through */
+ case 130 : /* fall through */
+ case 131 : /* fall through */
+ case 132 : /* fall through */
+ case 133 : /* fall through */
+ case 134 : /* fall through */
+ case 135 : /* fall through */
+ case 136 : /* fall through */
+ case 137 : /* fall through */
+ case 138 : /* fall through */
+ case 139 : /* fall through */
+ case 140 : /* fall through */
+ case 141 : /* fall through */
+ case 142 : /* fall through */
+ case 143 : /* fall through */
+ case 144 : /* fall through */
+ case 145 : /* fall through */
+ case 146 : /* fall through */
+ case 147 : /* fall through */
+ case 148 : /* fall through */
+ case 149 : /* fall through */
+ case 150 : /* fall through */
+ case 151 : /* fall through */
+ case 152 : /* fall through */
+ case 153 : /* fall through */
+ case 154 : /* fall through */
+ case 155 : /* fall through */
+ case 156 : /* fall through */
+ case 157 : /* fall through */
+ case 158 : /* fall through */
+ case 159 : itype = OR1K32BF_INSN_L_BF; goto extract_sfmt_l_bnf;
+ case 160 : /* fall through */
+ case 161 : /* fall through */
+ case 162 : /* fall through */
+ case 163 : /* fall through */
+ case 164 : /* fall through */
+ case 165 : /* fall through */
+ case 166 : /* fall through */
+ case 167 : /* fall through */
+ case 168 : /* fall through */
+ case 169 : /* fall through */
+ case 170 : /* fall through */
+ case 171 : /* fall through */
+ case 172 : /* fall through */
+ case 173 : /* fall through */
+ case 174 : /* fall through */
+ case 175 : /* fall through */
+ case 176 : /* fall through */
+ case 177 : /* fall through */
+ case 178 : /* fall through */
+ case 179 : /* fall through */
+ case 180 : /* fall through */
+ case 181 : /* fall through */
+ case 182 : /* fall through */
+ case 183 : /* fall through */
+ case 184 : /* fall through */
+ case 185 : /* fall through */
+ case 186 : /* fall through */
+ case 187 : /* fall through */
+ case 188 : /* fall through */
+ case 189 : /* fall through */
+ case 190 : /* fall through */
+ case 191 :
+ if ((entire_insn & 0xffff0000) == 0x15000000)
+ { itype = OR1K32BF_INSN_L_NOP_IMM; goto extract_sfmt_l_nop_imm; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 192 :
+ {
+ unsigned int val = (((insn >> 16) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc1f0000) == 0x18000000)
+ { itype = OR1K32BF_INSN_L_MOVHI; goto extract_sfmt_l_movhi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xfc1fffff) == 0x18010000)
+ { itype = OR1K32BF_INSN_L_MACRC; goto extract_sfmt_l_macrc; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 193 : /* fall through */
+ case 194 : /* fall through */
+ case 195 : /* fall through */
+ case 196 : /* fall through */
+ case 197 : /* fall through */
+ case 198 : /* fall through */
+ case 199 : /* fall through */
+ case 200 : /* fall through */
+ case 201 : /* fall through */
+ case 202 : /* fall through */
+ case 203 : /* fall through */
+ case 204 : /* fall through */
+ case 205 : /* fall through */
+ case 206 : /* fall through */
+ case 207 : /* fall through */
+ case 208 : /* fall through */
+ case 209 : /* fall through */
+ case 210 : /* fall through */
+ case 211 : /* fall through */
+ case 212 : /* fall through */
+ case 213 : /* fall through */
+ case 214 : /* fall through */
+ case 215 : /* fall through */
+ case 216 : /* fall through */
+ case 217 : /* fall through */
+ case 218 : /* fall through */
+ case 219 : /* fall through */
+ case 220 : /* fall through */
+ case 221 : /* fall through */
+ case 222 : /* fall through */
+ case 223 :
+ if ((entire_insn & 0xfc1f0000) == 0x18000000)
+ { itype = OR1K32BF_INSN_L_MOVHI; goto extract_sfmt_l_movhi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 256 :
+ {
+ unsigned int val = (((insn >> 23) & (7 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffff0000) == 0x20000000)
+ { itype = OR1K32BF_INSN_L_SYS; goto extract_sfmt_l_trap; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffff0000) == 0x21000000)
+ { itype = OR1K32BF_INSN_L_TRAP; goto extract_sfmt_l_trap; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffffffff) == 0x22000000)
+ { itype = OR1K32BF_INSN_L_MSYNC; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffffffff) == 0x22800000)
+ { itype = OR1K32BF_INSN_L_PSYNC; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xffffffff) == 0x23000000)
+ { itype = OR1K32BF_INSN_L_CSYNC; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 257 : /* fall through */
+ case 258 : /* fall through */
+ case 259 : /* fall through */
+ case 260 : /* fall through */
+ case 261 : /* fall through */
+ case 262 : /* fall through */
+ case 263 : /* fall through */
+ case 264 : /* fall through */
+ case 265 : /* fall through */
+ case 266 : /* fall through */
+ case 267 : /* fall through */
+ case 268 : /* fall through */
+ case 269 : /* fall through */
+ case 270 : /* fall through */
+ case 271 : /* fall through */
+ case 272 : /* fall through */
+ case 273 : /* fall through */
+ case 274 : /* fall through */
+ case 275 : /* fall through */
+ case 276 : /* fall through */
+ case 277 : /* fall through */
+ case 278 : /* fall through */
+ case 279 : /* fall through */
+ case 280 : /* fall through */
+ case 281 : /* fall through */
+ case 282 : /* fall through */
+ case 283 : /* fall through */
+ case 284 : /* fall through */
+ case 285 : /* fall through */
+ case 286 : /* fall through */
+ case 287 :
+ {
+ unsigned int val = (((insn >> 24) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffff0000) == 0x20000000)
+ { itype = OR1K32BF_INSN_L_SYS; goto extract_sfmt_l_trap; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffff0000) == 0x21000000)
+ { itype = OR1K32BF_INSN_L_TRAP; goto extract_sfmt_l_trap; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 288 :
+ if ((entire_insn & 0xffffffff) == 0x24000000)
+ { itype = OR1K32BF_INSN_L_RFE; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 544 :
+ if ((entire_insn & 0xffff07ff) == 0x44000000)
+ { itype = OR1K32BF_INSN_L_JR; goto extract_sfmt_l_jr; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 576 :
+ if ((entire_insn & 0xffff07ff) == 0x48000000)
+ { itype = OR1K32BF_INSN_L_JALR; goto extract_sfmt_l_jalr; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 608 : /* fall through */
+ case 609 : /* fall through */
+ case 610 : /* fall through */
+ case 611 : /* fall through */
+ case 612 : /* fall through */
+ case 613 : /* fall through */
+ case 614 : /* fall through */
+ case 615 : /* fall through */
+ case 616 : /* fall through */
+ case 617 : /* fall through */
+ case 618 : /* fall through */
+ case 619 : /* fall through */
+ case 620 : /* fall through */
+ case 621 : /* fall through */
+ case 622 : /* fall through */
+ case 623 : /* fall through */
+ case 624 : /* fall through */
+ case 625 : /* fall through */
+ case 626 : /* fall through */
+ case 627 : /* fall through */
+ case 628 : /* fall through */
+ case 629 : /* fall through */
+ case 630 : /* fall through */
+ case 631 : /* fall through */
+ case 632 : /* fall through */
+ case 633 : /* fall through */
+ case 634 : /* fall through */
+ case 635 : /* fall through */
+ case 636 : /* fall through */
+ case 637 : /* fall through */
+ case 638 : /* fall through */
+ case 639 :
+ if ((entire_insn & 0xffe00000) == 0x4c000000)
+ { itype = OR1K32BF_INSN_L_MACI; goto extract_sfmt_l_maci; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 864 : /* fall through */
+ case 865 : /* fall through */
+ case 866 : /* fall through */
+ case 867 : /* fall through */
+ case 868 : /* fall through */
+ case 869 : /* fall through */
+ case 870 : /* fall through */
+ case 871 : /* fall through */
+ case 872 : /* fall through */
+ case 873 : /* fall through */
+ case 874 : /* fall through */
+ case 875 : /* fall through */
+ case 876 : /* fall through */
+ case 877 : /* fall through */
+ case 878 : /* fall through */
+ case 879 : /* fall through */
+ case 880 : /* fall through */
+ case 881 : /* fall through */
+ case 882 : /* fall through */
+ case 883 : /* fall through */
+ case 884 : /* fall through */
+ case 885 : /* fall through */
+ case 886 : /* fall through */
+ case 887 : /* fall through */
+ case 888 : /* fall through */
+ case 889 : /* fall through */
+ case 890 : /* fall through */
+ case 891 : /* fall through */
+ case 892 : /* fall through */
+ case 893 : /* fall through */
+ case 894 : /* fall through */
+ case 895 : itype = OR1K32BF_INSN_L_LWA; goto extract_sfmt_l_lwa;
+ case 896 :
+ if ((entire_insn & 0xffffffff) == 0x70000000)
+ { itype = OR1K32BF_INSN_L_CUST1; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 928 :
+ if ((entire_insn & 0xffffffff) == 0x74000000)
+ { itype = OR1K32BF_INSN_L_CUST2; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 960 :
+ if ((entire_insn & 0xffffffff) == 0x78000000)
+ { itype = OR1K32BF_INSN_L_CUST3; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 992 :
+ if ((entire_insn & 0xffffffff) == 0x7c000000)
+ { itype = OR1K32BF_INSN_L_CUST4; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1056 : /* fall through */
+ case 1057 : /* fall through */
+ case 1058 : /* fall through */
+ case 1059 : /* fall through */
+ case 1060 : /* fall through */
+ case 1061 : /* fall through */
+ case 1062 : /* fall through */
+ case 1063 : /* fall through */
+ case 1064 : /* fall through */
+ case 1065 : /* fall through */
+ case 1066 : /* fall through */
+ case 1067 : /* fall through */
+ case 1068 : /* fall through */
+ case 1069 : /* fall through */
+ case 1070 : /* fall through */
+ case 1071 : /* fall through */
+ case 1072 : /* fall through */
+ case 1073 : /* fall through */
+ case 1074 : /* fall through */
+ case 1075 : /* fall through */
+ case 1076 : /* fall through */
+ case 1077 : /* fall through */
+ case 1078 : /* fall through */
+ case 1079 : /* fall through */
+ case 1080 : /* fall through */
+ case 1081 : /* fall through */
+ case 1082 : /* fall through */
+ case 1083 : /* fall through */
+ case 1084 : /* fall through */
+ case 1085 : /* fall through */
+ case 1086 : /* fall through */
+ case 1087 : itype = OR1K32BF_INSN_L_LWZ; goto extract_sfmt_l_lwz;
+ case 1088 : /* fall through */
+ case 1089 : /* fall through */
+ case 1090 : /* fall through */
+ case 1091 : /* fall through */
+ case 1092 : /* fall through */
+ case 1093 : /* fall through */
+ case 1094 : /* fall through */
+ case 1095 : /* fall through */
+ case 1096 : /* fall through */
+ case 1097 : /* fall through */
+ case 1098 : /* fall through */
+ case 1099 : /* fall through */
+ case 1100 : /* fall through */
+ case 1101 : /* fall through */
+ case 1102 : /* fall through */
+ case 1103 : /* fall through */
+ case 1104 : /* fall through */
+ case 1105 : /* fall through */
+ case 1106 : /* fall through */
+ case 1107 : /* fall through */
+ case 1108 : /* fall through */
+ case 1109 : /* fall through */
+ case 1110 : /* fall through */
+ case 1111 : /* fall through */
+ case 1112 : /* fall through */
+ case 1113 : /* fall through */
+ case 1114 : /* fall through */
+ case 1115 : /* fall through */
+ case 1116 : /* fall through */
+ case 1117 : /* fall through */
+ case 1118 : /* fall through */
+ case 1119 : itype = OR1K32BF_INSN_L_LWS; goto extract_sfmt_l_lws;
+ case 1120 : /* fall through */
+ case 1121 : /* fall through */
+ case 1122 : /* fall through */
+ case 1123 : /* fall through */
+ case 1124 : /* fall through */
+ case 1125 : /* fall through */
+ case 1126 : /* fall through */
+ case 1127 : /* fall through */
+ case 1128 : /* fall through */
+ case 1129 : /* fall through */
+ case 1130 : /* fall through */
+ case 1131 : /* fall through */
+ case 1132 : /* fall through */
+ case 1133 : /* fall through */
+ case 1134 : /* fall through */
+ case 1135 : /* fall through */
+ case 1136 : /* fall through */
+ case 1137 : /* fall through */
+ case 1138 : /* fall through */
+ case 1139 : /* fall through */
+ case 1140 : /* fall through */
+ case 1141 : /* fall through */
+ case 1142 : /* fall through */
+ case 1143 : /* fall through */
+ case 1144 : /* fall through */
+ case 1145 : /* fall through */
+ case 1146 : /* fall through */
+ case 1147 : /* fall through */
+ case 1148 : /* fall through */
+ case 1149 : /* fall through */
+ case 1150 : /* fall through */
+ case 1151 : itype = OR1K32BF_INSN_L_LBZ; goto extract_sfmt_l_lbz;
+ case 1152 : /* fall through */
+ case 1153 : /* fall through */
+ case 1154 : /* fall through */
+ case 1155 : /* fall through */
+ case 1156 : /* fall through */
+ case 1157 : /* fall through */
+ case 1158 : /* fall through */
+ case 1159 : /* fall through */
+ case 1160 : /* fall through */
+ case 1161 : /* fall through */
+ case 1162 : /* fall through */
+ case 1163 : /* fall through */
+ case 1164 : /* fall through */
+ case 1165 : /* fall through */
+ case 1166 : /* fall through */
+ case 1167 : /* fall through */
+ case 1168 : /* fall through */
+ case 1169 : /* fall through */
+ case 1170 : /* fall through */
+ case 1171 : /* fall through */
+ case 1172 : /* fall through */
+ case 1173 : /* fall through */
+ case 1174 : /* fall through */
+ case 1175 : /* fall through */
+ case 1176 : /* fall through */
+ case 1177 : /* fall through */
+ case 1178 : /* fall through */
+ case 1179 : /* fall through */
+ case 1180 : /* fall through */
+ case 1181 : /* fall through */
+ case 1182 : /* fall through */
+ case 1183 : itype = OR1K32BF_INSN_L_LBS; goto extract_sfmt_l_lbs;
+ case 1184 : /* fall through */
+ case 1185 : /* fall through */
+ case 1186 : /* fall through */
+ case 1187 : /* fall through */
+ case 1188 : /* fall through */
+ case 1189 : /* fall through */
+ case 1190 : /* fall through */
+ case 1191 : /* fall through */
+ case 1192 : /* fall through */
+ case 1193 : /* fall through */
+ case 1194 : /* fall through */
+ case 1195 : /* fall through */
+ case 1196 : /* fall through */
+ case 1197 : /* fall through */
+ case 1198 : /* fall through */
+ case 1199 : /* fall through */
+ case 1200 : /* fall through */
+ case 1201 : /* fall through */
+ case 1202 : /* fall through */
+ case 1203 : /* fall through */
+ case 1204 : /* fall through */
+ case 1205 : /* fall through */
+ case 1206 : /* fall through */
+ case 1207 : /* fall through */
+ case 1208 : /* fall through */
+ case 1209 : /* fall through */
+ case 1210 : /* fall through */
+ case 1211 : /* fall through */
+ case 1212 : /* fall through */
+ case 1213 : /* fall through */
+ case 1214 : /* fall through */
+ case 1215 : itype = OR1K32BF_INSN_L_LHZ; goto extract_sfmt_l_lhz;
+ case 1216 : /* fall through */
+ case 1217 : /* fall through */
+ case 1218 : /* fall through */
+ case 1219 : /* fall through */
+ case 1220 : /* fall through */
+ case 1221 : /* fall through */
+ case 1222 : /* fall through */
+ case 1223 : /* fall through */
+ case 1224 : /* fall through */
+ case 1225 : /* fall through */
+ case 1226 : /* fall through */
+ case 1227 : /* fall through */
+ case 1228 : /* fall through */
+ case 1229 : /* fall through */
+ case 1230 : /* fall through */
+ case 1231 : /* fall through */
+ case 1232 : /* fall through */
+ case 1233 : /* fall through */
+ case 1234 : /* fall through */
+ case 1235 : /* fall through */
+ case 1236 : /* fall through */
+ case 1237 : /* fall through */
+ case 1238 : /* fall through */
+ case 1239 : /* fall through */
+ case 1240 : /* fall through */
+ case 1241 : /* fall through */
+ case 1242 : /* fall through */
+ case 1243 : /* fall through */
+ case 1244 : /* fall through */
+ case 1245 : /* fall through */
+ case 1246 : /* fall through */
+ case 1247 : itype = OR1K32BF_INSN_L_LHS; goto extract_sfmt_l_lhs;
+ case 1248 : /* fall through */
+ case 1249 : /* fall through */
+ case 1250 : /* fall through */
+ case 1251 : /* fall through */
+ case 1252 : /* fall through */
+ case 1253 : /* fall through */
+ case 1254 : /* fall through */
+ case 1255 : /* fall through */
+ case 1256 : /* fall through */
+ case 1257 : /* fall through */
+ case 1258 : /* fall through */
+ case 1259 : /* fall through */
+ case 1260 : /* fall through */
+ case 1261 : /* fall through */
+ case 1262 : /* fall through */
+ case 1263 : /* fall through */
+ case 1264 : /* fall through */
+ case 1265 : /* fall through */
+ case 1266 : /* fall through */
+ case 1267 : /* fall through */
+ case 1268 : /* fall through */
+ case 1269 : /* fall through */
+ case 1270 : /* fall through */
+ case 1271 : /* fall through */
+ case 1272 : /* fall through */
+ case 1273 : /* fall through */
+ case 1274 : /* fall through */
+ case 1275 : /* fall through */
+ case 1276 : /* fall through */
+ case 1277 : /* fall through */
+ case 1278 : /* fall through */
+ case 1279 : itype = OR1K32BF_INSN_L_ADDI; goto extract_sfmt_l_addi;
+ case 1280 : /* fall through */
+ case 1281 : /* fall through */
+ case 1282 : /* fall through */
+ case 1283 : /* fall through */
+ case 1284 : /* fall through */
+ case 1285 : /* fall through */
+ case 1286 : /* fall through */
+ case 1287 : /* fall through */
+ case 1288 : /* fall through */
+ case 1289 : /* fall through */
+ case 1290 : /* fall through */
+ case 1291 : /* fall through */
+ case 1292 : /* fall through */
+ case 1293 : /* fall through */
+ case 1294 : /* fall through */
+ case 1295 : /* fall through */
+ case 1296 : /* fall through */
+ case 1297 : /* fall through */
+ case 1298 : /* fall through */
+ case 1299 : /* fall through */
+ case 1300 : /* fall through */
+ case 1301 : /* fall through */
+ case 1302 : /* fall through */
+ case 1303 : /* fall through */
+ case 1304 : /* fall through */
+ case 1305 : /* fall through */
+ case 1306 : /* fall through */
+ case 1307 : /* fall through */
+ case 1308 : /* fall through */
+ case 1309 : /* fall through */
+ case 1310 : /* fall through */
+ case 1311 : itype = OR1K32BF_INSN_L_ADDIC; goto extract_sfmt_l_addic;
+ case 1312 : /* fall through */
+ case 1313 : /* fall through */
+ case 1314 : /* fall through */
+ case 1315 : /* fall through */
+ case 1316 : /* fall through */
+ case 1317 : /* fall through */
+ case 1318 : /* fall through */
+ case 1319 : /* fall through */
+ case 1320 : /* fall through */
+ case 1321 : /* fall through */
+ case 1322 : /* fall through */
+ case 1323 : /* fall through */
+ case 1324 : /* fall through */
+ case 1325 : /* fall through */
+ case 1326 : /* fall through */
+ case 1327 : /* fall through */
+ case 1328 : /* fall through */
+ case 1329 : /* fall through */
+ case 1330 : /* fall through */
+ case 1331 : /* fall through */
+ case 1332 : /* fall through */
+ case 1333 : /* fall through */
+ case 1334 : /* fall through */
+ case 1335 : /* fall through */
+ case 1336 : /* fall through */
+ case 1337 : /* fall through */
+ case 1338 : /* fall through */
+ case 1339 : /* fall through */
+ case 1340 : /* fall through */
+ case 1341 : /* fall through */
+ case 1342 : /* fall through */
+ case 1343 : itype = OR1K32BF_INSN_L_ANDI; goto extract_sfmt_l_mfspr;
+ case 1344 : /* fall through */
+ case 1345 : /* fall through */
+ case 1346 : /* fall through */
+ case 1347 : /* fall through */
+ case 1348 : /* fall through */
+ case 1349 : /* fall through */
+ case 1350 : /* fall through */
+ case 1351 : /* fall through */
+ case 1352 : /* fall through */
+ case 1353 : /* fall through */
+ case 1354 : /* fall through */
+ case 1355 : /* fall through */
+ case 1356 : /* fall through */
+ case 1357 : /* fall through */
+ case 1358 : /* fall through */
+ case 1359 : /* fall through */
+ case 1360 : /* fall through */
+ case 1361 : /* fall through */
+ case 1362 : /* fall through */
+ case 1363 : /* fall through */
+ case 1364 : /* fall through */
+ case 1365 : /* fall through */
+ case 1366 : /* fall through */
+ case 1367 : /* fall through */
+ case 1368 : /* fall through */
+ case 1369 : /* fall through */
+ case 1370 : /* fall through */
+ case 1371 : /* fall through */
+ case 1372 : /* fall through */
+ case 1373 : /* fall through */
+ case 1374 : /* fall through */
+ case 1375 : itype = OR1K32BF_INSN_L_ORI; goto extract_sfmt_l_mfspr;
+ case 1376 : /* fall through */
+ case 1377 : /* fall through */
+ case 1378 : /* fall through */
+ case 1379 : /* fall through */
+ case 1380 : /* fall through */
+ case 1381 : /* fall through */
+ case 1382 : /* fall through */
+ case 1383 : /* fall through */
+ case 1384 : /* fall through */
+ case 1385 : /* fall through */
+ case 1386 : /* fall through */
+ case 1387 : /* fall through */
+ case 1388 : /* fall through */
+ case 1389 : /* fall through */
+ case 1390 : /* fall through */
+ case 1391 : /* fall through */
+ case 1392 : /* fall through */
+ case 1393 : /* fall through */
+ case 1394 : /* fall through */
+ case 1395 : /* fall through */
+ case 1396 : /* fall through */
+ case 1397 : /* fall through */
+ case 1398 : /* fall through */
+ case 1399 : /* fall through */
+ case 1400 : /* fall through */
+ case 1401 : /* fall through */
+ case 1402 : /* fall through */
+ case 1403 : /* fall through */
+ case 1404 : /* fall through */
+ case 1405 : /* fall through */
+ case 1406 : /* fall through */
+ case 1407 : itype = OR1K32BF_INSN_L_XORI; goto extract_sfmt_l_xori;
+ case 1408 : /* fall through */
+ case 1409 : /* fall through */
+ case 1410 : /* fall through */
+ case 1411 : /* fall through */
+ case 1412 : /* fall through */
+ case 1413 : /* fall through */
+ case 1414 : /* fall through */
+ case 1415 : /* fall through */
+ case 1416 : /* fall through */
+ case 1417 : /* fall through */
+ case 1418 : /* fall through */
+ case 1419 : /* fall through */
+ case 1420 : /* fall through */
+ case 1421 : /* fall through */
+ case 1422 : /* fall through */
+ case 1423 : /* fall through */
+ case 1424 : /* fall through */
+ case 1425 : /* fall through */
+ case 1426 : /* fall through */
+ case 1427 : /* fall through */
+ case 1428 : /* fall through */
+ case 1429 : /* fall through */
+ case 1430 : /* fall through */
+ case 1431 : /* fall through */
+ case 1432 : /* fall through */
+ case 1433 : /* fall through */
+ case 1434 : /* fall through */
+ case 1435 : /* fall through */
+ case 1436 : /* fall through */
+ case 1437 : /* fall through */
+ case 1438 : /* fall through */
+ case 1439 : itype = OR1K32BF_INSN_L_MULI; goto extract_sfmt_l_addi;
+ case 1440 : /* fall through */
+ case 1441 : /* fall through */
+ case 1442 : /* fall through */
+ case 1443 : /* fall through */
+ case 1444 : /* fall through */
+ case 1445 : /* fall through */
+ case 1446 : /* fall through */
+ case 1447 : /* fall through */
+ case 1448 : /* fall through */
+ case 1449 : /* fall through */
+ case 1450 : /* fall through */
+ case 1451 : /* fall through */
+ case 1452 : /* fall through */
+ case 1453 : /* fall through */
+ case 1454 : /* fall through */
+ case 1455 : /* fall through */
+ case 1456 : /* fall through */
+ case 1457 : /* fall through */
+ case 1458 : /* fall through */
+ case 1459 : /* fall through */
+ case 1460 : /* fall through */
+ case 1461 : /* fall through */
+ case 1462 : /* fall through */
+ case 1463 : /* fall through */
+ case 1464 : /* fall through */
+ case 1465 : /* fall through */
+ case 1466 : /* fall through */
+ case 1467 : /* fall through */
+ case 1468 : /* fall through */
+ case 1469 : /* fall through */
+ case 1470 : /* fall through */
+ case 1471 : itype = OR1K32BF_INSN_L_MFSPR; goto extract_sfmt_l_mfspr;
+ case 1472 : /* fall through */
+ case 1473 : /* fall through */
+ case 1474 : /* fall through */
+ case 1475 : /* fall through */
+ case 1476 : /* fall through */
+ case 1477 : /* fall through */
+ case 1478 : /* fall through */
+ case 1479 : /* fall through */
+ case 1480 : /* fall through */
+ case 1481 : /* fall through */
+ case 1482 : /* fall through */
+ case 1483 : /* fall through */
+ case 1484 : /* fall through */
+ case 1485 : /* fall through */
+ case 1486 : /* fall through */
+ case 1487 :
+ {
+ unsigned int val = (((insn >> 7) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc00ffc0) == 0xb8000000)
+ { itype = OR1K32BF_INSN_L_SLLI; goto extract_sfmt_l_slli; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xfc00ffc0) == 0xb8000080)
+ { itype = OR1K32BF_INSN_L_SRAI; goto extract_sfmt_l_slli; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1488 : /* fall through */
+ case 1489 : /* fall through */
+ case 1490 : /* fall through */
+ case 1491 : /* fall through */
+ case 1492 : /* fall through */
+ case 1493 : /* fall through */
+ case 1494 : /* fall through */
+ case 1495 : /* fall through */
+ case 1496 : /* fall through */
+ case 1497 : /* fall through */
+ case 1498 : /* fall through */
+ case 1499 : /* fall through */
+ case 1500 : /* fall through */
+ case 1501 : /* fall through */
+ case 1502 : /* fall through */
+ case 1503 :
+ {
+ unsigned int val = (((insn >> 7) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc00ffc0) == 0xb8000040)
+ { itype = OR1K32BF_INSN_L_SRLI; goto extract_sfmt_l_slli; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xfc00ffc0) == 0xb80000c0)
+ { itype = OR1K32BF_INSN_L_RORI; goto extract_sfmt_l_slli; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1504 : /* fall through */
+ case 1505 : /* fall through */
+ case 1506 : /* fall through */
+ case 1507 : /* fall through */
+ case 1508 : /* fall through */
+ case 1509 : /* fall through */
+ case 1510 : /* fall through */
+ case 1511 : /* fall through */
+ case 1512 : /* fall through */
+ case 1513 : /* fall through */
+ case 1514 : /* fall through */
+ case 1515 : /* fall through */
+ case 1516 : /* fall through */
+ case 1517 : /* fall through */
+ case 1518 : /* fall through */
+ case 1519 : /* fall through */
+ case 1520 : /* fall through */
+ case 1521 : /* fall through */
+ case 1522 : /* fall through */
+ case 1523 : /* fall through */
+ case 1524 : /* fall through */
+ case 1525 : /* fall through */
+ case 1526 : /* fall through */
+ case 1527 : /* fall through */
+ case 1528 : /* fall through */
+ case 1529 : /* fall through */
+ case 1530 : /* fall through */
+ case 1531 : /* fall through */
+ case 1532 : /* fall through */
+ case 1533 : /* fall through */
+ case 1534 : /* fall through */
+ case 1535 :
+ {
+ unsigned int val = (((insn >> 21) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe00000) == 0xbc000000)
+ { itype = OR1K32BF_INSN_L_SFEQI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe00000) == 0xbc200000)
+ { itype = OR1K32BF_INSN_L_SFNEI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffe00000) == 0xbc400000)
+ { itype = OR1K32BF_INSN_L_SFGTUI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xffe00000) == 0xbc600000)
+ { itype = OR1K32BF_INSN_L_SFGEUI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe00000) == 0xbc800000)
+ { itype = OR1K32BF_INSN_L_SFLTUI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe00000) == 0xbca00000)
+ { itype = OR1K32BF_INSN_L_SFLEUI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xffe00000) == 0xbd400000)
+ { itype = OR1K32BF_INSN_L_SFGTSI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xffe00000) == 0xbd600000)
+ { itype = OR1K32BF_INSN_L_SFGESI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xffe00000) == 0xbd800000)
+ { itype = OR1K32BF_INSN_L_SFLTSI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xffe00000) == 0xbda00000)
+ { itype = OR1K32BF_INSN_L_SFLESI; goto extract_sfmt_l_sfgtsi; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1536 : /* fall through */
+ case 1537 : /* fall through */
+ case 1538 : /* fall through */
+ case 1539 : /* fall through */
+ case 1540 : /* fall through */
+ case 1541 : /* fall through */
+ case 1542 : /* fall through */
+ case 1543 : /* fall through */
+ case 1544 : /* fall through */
+ case 1545 : /* fall through */
+ case 1546 : /* fall through */
+ case 1547 : /* fall through */
+ case 1548 : /* fall through */
+ case 1549 : /* fall through */
+ case 1550 : /* fall through */
+ case 1551 : /* fall through */
+ case 1552 : /* fall through */
+ case 1553 : /* fall through */
+ case 1554 : /* fall through */
+ case 1555 : /* fall through */
+ case 1556 : /* fall through */
+ case 1557 : /* fall through */
+ case 1558 : /* fall through */
+ case 1559 : /* fall through */
+ case 1560 : /* fall through */
+ case 1561 : /* fall through */
+ case 1562 : /* fall through */
+ case 1563 : /* fall through */
+ case 1564 : /* fall through */
+ case 1565 : /* fall through */
+ case 1566 : /* fall through */
+ case 1567 : itype = OR1K32BF_INSN_L_MTSPR; goto extract_sfmt_l_mtspr;
+ case 1569 :
+ if ((entire_insn & 0xffe007ff) == 0xc4000001)
+ { itype = OR1K32BF_INSN_L_MAC; goto extract_sfmt_l_mac; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1570 :
+ if ((entire_insn & 0xffe007ff) == 0xc4000002)
+ { itype = OR1K32BF_INSN_L_MSB; goto extract_sfmt_l_mac; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1600 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000000)
+ { itype = OR1K32BF_INSN_LF_ADD_S; goto extract_sfmt_lf_add_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1601 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000001)
+ { itype = OR1K32BF_INSN_LF_SUB_S; goto extract_sfmt_lf_add_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1602 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000002)
+ { itype = OR1K32BF_INSN_LF_MUL_S; goto extract_sfmt_lf_add_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1603 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000003)
+ { itype = OR1K32BF_INSN_LF_DIV_S; goto extract_sfmt_lf_add_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1604 :
+ if ((entire_insn & 0xfc00ffff) == 0xc8000004)
+ { itype = OR1K32BF_INSN_LF_ITOF_S; goto extract_sfmt_lf_itof_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1605 :
+ if ((entire_insn & 0xfc00ffff) == 0xc8000005)
+ { itype = OR1K32BF_INSN_LF_FTOI_S; goto extract_sfmt_lf_ftoi_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1606 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000006)
+ { itype = OR1K32BF_INSN_LF_REM_S; goto extract_sfmt_lf_add_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1607 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000007)
+ { itype = OR1K32BF_INSN_LF_MADD_S; goto extract_sfmt_lf_madd_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1608 :
+ if ((entire_insn & 0xffe007ff) == 0xc8000008)
+ { itype = OR1K32BF_INSN_LF_EQ_S; goto extract_sfmt_lf_eq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1609 :
+ if ((entire_insn & 0xffe007ff) == 0xc8000009)
+ { itype = OR1K32BF_INSN_LF_NE_S; goto extract_sfmt_lf_eq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1610 :
+ if ((entire_insn & 0xffe007ff) == 0xc800000a)
+ { itype = OR1K32BF_INSN_LF_GT_S; goto extract_sfmt_lf_eq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1611 :
+ if ((entire_insn & 0xffe007ff) == 0xc800000b)
+ { itype = OR1K32BF_INSN_LF_GE_S; goto extract_sfmt_lf_eq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1612 :
+ if ((entire_insn & 0xffe007ff) == 0xc800000c)
+ { itype = OR1K32BF_INSN_LF_LT_S; goto extract_sfmt_lf_eq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1613 :
+ if ((entire_insn & 0xffe007ff) == 0xc800000d)
+ { itype = OR1K32BF_INSN_LF_LE_S; goto extract_sfmt_lf_eq_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1616 :
+ if ((entire_insn & 0xffe007ff) == 0xc80000d0)
+ { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1632 : /* fall through */
+ case 1633 : /* fall through */
+ case 1634 : /* fall through */
+ case 1635 : /* fall through */
+ case 1636 : /* fall through */
+ case 1637 : /* fall through */
+ case 1638 : /* fall through */
+ case 1639 : /* fall through */
+ case 1640 : /* fall through */
+ case 1641 : /* fall through */
+ case 1642 : /* fall through */
+ case 1643 : /* fall through */
+ case 1644 : /* fall through */
+ case 1645 : /* fall through */
+ case 1646 : /* fall through */
+ case 1647 : /* fall through */
+ case 1648 : /* fall through */
+ case 1649 : /* fall through */
+ case 1650 : /* fall through */
+ case 1651 : /* fall through */
+ case 1652 : /* fall through */
+ case 1653 : /* fall through */
+ case 1654 : /* fall through */
+ case 1655 : /* fall through */
+ case 1656 : /* fall through */
+ case 1657 : /* fall through */
+ case 1658 : /* fall through */
+ case 1659 : /* fall through */
+ case 1660 : /* fall through */
+ case 1661 : /* fall through */
+ case 1662 : /* fall through */
+ case 1663 : itype = OR1K32BF_INSN_L_SWA; goto extract_sfmt_l_swa;
+ case 1696 : /* fall through */
+ case 1697 : /* fall through */
+ case 1698 : /* fall through */
+ case 1699 : /* fall through */
+ case 1700 : /* fall through */
+ case 1701 : /* fall through */
+ case 1702 : /* fall through */
+ case 1703 : /* fall through */
+ case 1704 : /* fall through */
+ case 1705 : /* fall through */
+ case 1706 : /* fall through */
+ case 1707 : /* fall through */
+ case 1708 : /* fall through */
+ case 1709 : /* fall through */
+ case 1710 : /* fall through */
+ case 1711 : /* fall through */
+ case 1712 : /* fall through */
+ case 1713 : /* fall through */
+ case 1714 : /* fall through */
+ case 1715 : /* fall through */
+ case 1716 : /* fall through */
+ case 1717 : /* fall through */
+ case 1718 : /* fall through */
+ case 1719 : /* fall through */
+ case 1720 : /* fall through */
+ case 1721 : /* fall through */
+ case 1722 : /* fall through */
+ case 1723 : /* fall through */
+ case 1724 : /* fall through */
+ case 1725 : /* fall through */
+ case 1726 : /* fall through */
+ case 1727 : itype = OR1K32BF_INSN_L_SW; goto extract_sfmt_l_sw;
+ case 1728 : /* fall through */
+ case 1729 : /* fall through */
+ case 1730 : /* fall through */
+ case 1731 : /* fall through */
+ case 1732 : /* fall through */
+ case 1733 : /* fall through */
+ case 1734 : /* fall through */
+ case 1735 : /* fall through */
+ case 1736 : /* fall through */
+ case 1737 : /* fall through */
+ case 1738 : /* fall through */
+ case 1739 : /* fall through */
+ case 1740 : /* fall through */
+ case 1741 : /* fall through */
+ case 1742 : /* fall through */
+ case 1743 : /* fall through */
+ case 1744 : /* fall through */
+ case 1745 : /* fall through */
+ case 1746 : /* fall through */
+ case 1747 : /* fall through */
+ case 1748 : /* fall through */
+ case 1749 : /* fall through */
+ case 1750 : /* fall through */
+ case 1751 : /* fall through */
+ case 1752 : /* fall through */
+ case 1753 : /* fall through */
+ case 1754 : /* fall through */
+ case 1755 : /* fall through */
+ case 1756 : /* fall through */
+ case 1757 : /* fall through */
+ case 1758 : /* fall through */
+ case 1759 : itype = OR1K32BF_INSN_L_SB; goto extract_sfmt_l_sb;
+ case 1760 : /* fall through */
+ case 1761 : /* fall through */
+ case 1762 : /* fall through */
+ case 1763 : /* fall through */
+ case 1764 : /* fall through */
+ case 1765 : /* fall through */
+ case 1766 : /* fall through */
+ case 1767 : /* fall through */
+ case 1768 : /* fall through */
+ case 1769 : /* fall through */
+ case 1770 : /* fall through */
+ case 1771 : /* fall through */
+ case 1772 : /* fall through */
+ case 1773 : /* fall through */
+ case 1774 : /* fall through */
+ case 1775 : /* fall through */
+ case 1776 : /* fall through */
+ case 1777 : /* fall through */
+ case 1778 : /* fall through */
+ case 1779 : /* fall through */
+ case 1780 : /* fall through */
+ case 1781 : /* fall through */
+ case 1782 : /* fall through */
+ case 1783 : /* fall through */
+ case 1784 : /* fall through */
+ case 1785 : /* fall through */
+ case 1786 : /* fall through */
+ case 1787 : /* fall through */
+ case 1788 : /* fall through */
+ case 1789 : /* fall through */
+ case 1790 : /* fall through */
+ case 1791 : itype = OR1K32BF_INSN_L_SH; goto extract_sfmt_l_sh;
+ case 1792 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000000)
+ { itype = OR1K32BF_INSN_L_ADD; goto extract_sfmt_l_add; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1793 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000001)
+ { itype = OR1K32BF_INSN_L_ADDC; goto extract_sfmt_l_addc; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1794 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000002)
+ { itype = OR1K32BF_INSN_L_SUB; goto extract_sfmt_l_add; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1795 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000003)
+ { itype = OR1K32BF_INSN_L_AND; goto extract_sfmt_l_and; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1796 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000004)
+ { itype = OR1K32BF_INSN_L_OR; goto extract_sfmt_l_and; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1797 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000005)
+ { itype = OR1K32BF_INSN_L_XOR; goto extract_sfmt_l_and; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1798 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000306)
+ { itype = OR1K32BF_INSN_L_MUL; goto extract_sfmt_l_add; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1800 :
+ {
+ unsigned int val = (((insn >> 7) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000008)
+ { itype = OR1K32BF_INSN_L_SLL; goto extract_sfmt_l_sll; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000088)
+ { itype = OR1K32BF_INSN_L_SRA; goto extract_sfmt_l_sll; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1801 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000309)
+ { itype = OR1K32BF_INSN_L_DIV; goto extract_sfmt_l_div; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1802 :
+ if ((entire_insn & 0xfc0007ff) == 0xe000030a)
+ { itype = OR1K32BF_INSN_L_DIVU; goto extract_sfmt_l_div; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1803 :
+ if ((entire_insn & 0xfc0007ff) == 0xe000030b)
+ { itype = OR1K32BF_INSN_L_MULU; goto extract_sfmt_l_add; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1804 :
+ {
+ unsigned int val = (((insn >> 7) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc00ffff) == 0xe000000c)
+ { itype = OR1K32BF_INSN_L_EXTHS; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xfc00ffff) == 0xe000008c)
+ { itype = OR1K32BF_INSN_L_EXTHZ; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1805 :
+ if ((entire_insn & 0xfc00ffff) == 0xe000000d)
+ { itype = OR1K32BF_INSN_L_EXTWS; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1806 :
+ if ((entire_insn & 0xfc0007ff) == 0xe000000e)
+ { itype = OR1K32BF_INSN_L_CMOV; goto extract_sfmt_l_cmov; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1807 :
+ {
+ unsigned int val = (((insn >> 8) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc0007ff) == 0xe000000f)
+ { itype = OR1K32BF_INSN_L_FF1; goto extract_sfmt_l_ff1; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xfc0007ff) == 0xe000010f)
+ { itype = OR1K32BF_INSN_L_FL1; goto extract_sfmt_l_ff1; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1816 :
+ {
+ unsigned int val = (((insn >> 7) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000048)
+ { itype = OR1K32BF_INSN_L_SRL; goto extract_sfmt_l_sll; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xfc0007ff) == 0xe00000c8)
+ { itype = OR1K32BF_INSN_L_ROR; goto extract_sfmt_l_sll; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1820 :
+ {
+ unsigned int val = (((insn >> 7) & (1 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc00ffff) == 0xe000004c)
+ { itype = OR1K32BF_INSN_L_EXTBS; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xfc00ffff) == 0xe00000cc)
+ { itype = OR1K32BF_INSN_L_EXTBZ; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1821 :
+ if ((entire_insn & 0xfc00ffff) == 0xe000004d)
+ { itype = OR1K32BF_INSN_L_EXTWZ; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1824 :
+ {
+ unsigned int val = (((insn >> 21) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffe007ff) == 0xe4000000)
+ { itype = OR1K32BF_INSN_L_SFEQ; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
+ if ((entire_insn & 0xffe007ff) == 0xe4200000)
+ { itype = OR1K32BF_INSN_L_SFNE; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffe007ff) == 0xe4400000)
+ { itype = OR1K32BF_INSN_L_SFGTU; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xffe007ff) == 0xe4600000)
+ { itype = OR1K32BF_INSN_L_SFGEU; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffe007ff) == 0xe4800000)
+ { itype = OR1K32BF_INSN_L_SFLTU; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffe007ff) == 0xe4a00000)
+ { itype = OR1K32BF_INSN_L_SFLEU; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 10 :
+ if ((entire_insn & 0xffe007ff) == 0xe5400000)
+ { itype = OR1K32BF_INSN_L_SFGTS; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 11 :
+ if ((entire_insn & 0xffe007ff) == 0xe5600000)
+ { itype = OR1K32BF_INSN_L_SFGES; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 12 :
+ if ((entire_insn & 0xffe007ff) == 0xe5800000)
+ { itype = OR1K32BF_INSN_L_SFLTS; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 13 :
+ if ((entire_insn & 0xffe007ff) == 0xe5a00000)
+ { itype = OR1K32BF_INSN_L_SFLES; goto extract_sfmt_l_sfgts; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1920 :
+ if ((entire_insn & 0xffffffff) == 0xf0000000)
+ { itype = OR1K32BF_INSN_L_CUST5; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1952 :
+ if ((entire_insn & 0xffffffff) == 0xf4000000)
+ { itype = OR1K32BF_INSN_L_CUST6; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1984 :
+ if ((entire_insn & 0xffffffff) == 0xf8000000)
+ { itype = OR1K32BF_INSN_L_CUST7; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2016 :
+ if ((entire_insn & 0xffffffff) == 0xfc000000)
+ { itype = OR1K32BF_INSN_L_CUST8; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_j:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ USI f_disp26;
+
+ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp26) = f_disp26;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_j", "disp26 0x%x", 'x', f_disp26, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_jal:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ USI f_disp26;
+
+ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp26) = f_disp26;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_jal", "disp26 0x%x", 'x', f_disp26, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_jr:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r3;
+
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r3) = f_r3;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_jr", "f_r3 0x%x", 'x', f_r3, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_jalr:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r3;
+
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r3) = f_r3;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_jalr", "f_r3 0x%x", 'x', f_r3, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_bnf:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ USI f_disp26;
+
+ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp26) = f_disp26;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_bnf", "disp26 0x%x", 'x', f_disp26, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_trap:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_trap", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_msync:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_msync", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_nop_imm:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ UINT f_uimm16;
+
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_uimm16) = f_uimm16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_nop_imm", "f_uimm16 0x%x", 'x', f_uimm16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_movhi:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ UINT f_r1;
+ UINT f_uimm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_uimm16) = f_uimm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_movhi", "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_macrc:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ UINT f_r1;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_macrc", "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_mfspr:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_uimm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_uimm16) = f_uimm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_mfspr", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_mtspr:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_mtspr.f
+ UINT f_imm16_25_5;
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_imm16_10_11;
+ UINT f_uimm16_split;
+
+ f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
+ f_uimm16_split = ((UHI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_uimm16_split) = f_uimm16_split;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_mtspr", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_uimm16_split 0x%x", 'x', f_uimm16_split, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_lwz:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_lwz", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_lws:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_lws", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_lwa:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_lwa", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_lbz:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_lbz", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_lbs:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_lbs", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_lhz:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_lhz", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_lhs:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_lhs", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_sw:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ UINT f_imm16_25_5;
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_imm16_10_11;
+ INT f_simm16_split;
+
+ f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
+ f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_simm16_split) = f_simm16_split;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sw", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_simm16_split 0x%x", 'x', f_simm16_split, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_sb:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ UINT f_imm16_25_5;
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_imm16_10_11;
+ INT f_simm16_split;
+
+ f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
+ f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_simm16_split) = f_simm16_split;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sb", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_simm16_split 0x%x", 'x', f_simm16_split, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_sh:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ UINT f_imm16_25_5;
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_imm16_10_11;
+ INT f_simm16_split;
+
+ f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
+ f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_simm16_split) = f_simm16_split;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sh", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_simm16_split 0x%x", 'x', f_simm16_split, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_swa:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ UINT f_imm16_25_5;
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_imm16_10_11;
+ INT f_simm16_split;
+
+ f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
+ f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_simm16_split) = f_simm16_split;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_swa", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_simm16_split 0x%x", 'x', f_simm16_split, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_sll:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sll", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_slli:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_uimm6;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_uimm6) = f_uimm6;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_slli", "f_r2 0x%x", 'x', f_r2, "f_uimm6 0x%x", 'x', f_uimm6, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_and:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_and", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_add:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_add", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_addc:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_addc", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_div:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_div", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_ff1:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_ff1", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_xori:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_xori", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_addi:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_addi", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_addic:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_addic", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_exths:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_exths", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_cmov:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_cmov", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_sfgts:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sfgts", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_sfgtsi:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sfgtsi", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_mac:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_mac", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_l_maci:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_maci", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_add_s:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_add_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_itof_s:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_itof_s", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_ftoi_s:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_ftoi_s", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_eq_s:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_eq_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_madd_s:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_madd_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+}
--- /dev/null
+/* Decode header for or1k32bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef OR1K32BF_DECODE_H
+#define OR1K32BF_DECODE_H
+
+extern const IDESC *or1k32bf_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_WORD, CGEN_INSN_WORD,
+ ARGBUF *);
+extern void or1k32bf_init_idesc_table (SIM_CPU *);
+extern void or1k32bf_sem_init_idesc_table (SIM_CPU *);
+extern void or1k32bf_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family or1k32bf. */
+typedef enum or1k32bf_insn_type {
+ OR1K32BF_INSN_X_INVALID, OR1K32BF_INSN_X_AFTER, OR1K32BF_INSN_X_BEFORE, OR1K32BF_INSN_X_CTI_CHAIN
+ , OR1K32BF_INSN_X_CHAIN, OR1K32BF_INSN_X_BEGIN, OR1K32BF_INSN_L_J, OR1K32BF_INSN_L_JAL
+ , OR1K32BF_INSN_L_JR, OR1K32BF_INSN_L_JALR, OR1K32BF_INSN_L_BNF, OR1K32BF_INSN_L_BF
+ , OR1K32BF_INSN_L_TRAP, OR1K32BF_INSN_L_SYS, OR1K32BF_INSN_L_MSYNC, OR1K32BF_INSN_L_PSYNC
+ , OR1K32BF_INSN_L_CSYNC, OR1K32BF_INSN_L_RFE, OR1K32BF_INSN_L_NOP_IMM, OR1K32BF_INSN_L_MOVHI
+ , OR1K32BF_INSN_L_MACRC, OR1K32BF_INSN_L_MFSPR, OR1K32BF_INSN_L_MTSPR, OR1K32BF_INSN_L_LWZ
+ , OR1K32BF_INSN_L_LWS, OR1K32BF_INSN_L_LWA, OR1K32BF_INSN_L_LBZ, OR1K32BF_INSN_L_LBS
+ , OR1K32BF_INSN_L_LHZ, OR1K32BF_INSN_L_LHS, OR1K32BF_INSN_L_SW, OR1K32BF_INSN_L_SB
+ , OR1K32BF_INSN_L_SH, OR1K32BF_INSN_L_SWA, OR1K32BF_INSN_L_SLL, OR1K32BF_INSN_L_SLLI
+ , OR1K32BF_INSN_L_SRL, OR1K32BF_INSN_L_SRLI, OR1K32BF_INSN_L_SRA, OR1K32BF_INSN_L_SRAI
+ , OR1K32BF_INSN_L_ROR, OR1K32BF_INSN_L_RORI, OR1K32BF_INSN_L_AND, OR1K32BF_INSN_L_OR
+ , OR1K32BF_INSN_L_XOR, OR1K32BF_INSN_L_ADD, OR1K32BF_INSN_L_SUB, OR1K32BF_INSN_L_ADDC
+ , OR1K32BF_INSN_L_MUL, OR1K32BF_INSN_L_MULU, OR1K32BF_INSN_L_DIV, OR1K32BF_INSN_L_DIVU
+ , OR1K32BF_INSN_L_FF1, OR1K32BF_INSN_L_FL1, OR1K32BF_INSN_L_ANDI, OR1K32BF_INSN_L_ORI
+ , OR1K32BF_INSN_L_XORI, OR1K32BF_INSN_L_ADDI, OR1K32BF_INSN_L_ADDIC, OR1K32BF_INSN_L_MULI
+ , OR1K32BF_INSN_L_EXTHS, OR1K32BF_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTBZ
+ , OR1K32BF_INSN_L_EXTWS, OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTS
+ , OR1K32BF_INSN_L_SFGTSI, OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGES
+ , OR1K32BF_INSN_L_SFGESI, OR1K32BF_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFLTS
+ , OR1K32BF_INSN_L_SFLTSI, OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLES
+ , OR1K32BF_INSN_L_SFLESI, OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFEQ
+ , OR1K32BF_INSN_L_SFEQI, OR1K32BF_INSN_L_SFNE, OR1K32BF_INSN_L_SFNEI, OR1K32BF_INSN_L_MAC
+ , OR1K32BF_INSN_L_MSB, OR1K32BF_INSN_L_MACI, OR1K32BF_INSN_L_CUST1, OR1K32BF_INSN_L_CUST2
+ , OR1K32BF_INSN_L_CUST3, OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5, OR1K32BF_INSN_L_CUST6
+ , OR1K32BF_INSN_L_CUST7, OR1K32BF_INSN_L_CUST8, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_INSN_LF_SUB_S
+ , OR1K32BF_INSN_LF_MUL_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_REM_S, OR1K32BF_INSN_LF_ITOF_S
+ , OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_NE_S, OR1K32BF_INSN_LF_GE_S
+ , OR1K32BF_INSN_LF_GT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_INSN_LF_MADD_S
+ , OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_INSN__MAX
+} OR1K32BF_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family or1k32bf. */
+typedef enum or1k32bf_sfmt_type {
+ OR1K32BF_SFMT_EMPTY, OR1K32BF_SFMT_L_J, OR1K32BF_SFMT_L_JAL, OR1K32BF_SFMT_L_JR
+ , OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP, OR1K32BF_SFMT_L_MSYNC
+ , OR1K32BF_SFMT_L_NOP_IMM, OR1K32BF_SFMT_L_MOVHI, OR1K32BF_SFMT_L_MACRC, OR1K32BF_SFMT_L_MFSPR
+ , OR1K32BF_SFMT_L_MTSPR, OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS, OR1K32BF_SFMT_L_LWA
+ , OR1K32BF_SFMT_L_LBZ, OR1K32BF_SFMT_L_LBS, OR1K32BF_SFMT_L_LHZ, OR1K32BF_SFMT_L_LHS
+ , OR1K32BF_SFMT_L_SW, OR1K32BF_SFMT_L_SB, OR1K32BF_SFMT_L_SH, OR1K32BF_SFMT_L_SWA
+ , OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI, OR1K32BF_SFMT_L_AND, OR1K32BF_SFMT_L_ADD
+ , OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_DIV, OR1K32BF_SFMT_L_FF1, OR1K32BF_SFMT_L_XORI
+ , OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC, OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV
+ , OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI, OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI
+ , OR1K32BF_SFMT_LF_ADD_S, OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S
+ , OR1K32BF_SFMT_LF_MADD_S
+} OR1K32BF_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int or1k32bf_model_or1200_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int or1k32bf_model_or1200nd_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void or1k32bf_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void or1k32bf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* OR1K32BF_DECODE_H */
--- /dev/null
+/* Simulator model support for or1k32bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU or1k32bf
+#define WANT_CPU_OR1K32BF
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+ mechanism. After all, this is information for profiling. */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn. */
+
+static int
+model_or1200_l_j (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_jal (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_jr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_jalr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_bnf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_bf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_trap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sys (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_msync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_psync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_csync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_rfe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_nop_imm (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_movhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_macrc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_mfspr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_mtspr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mtspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_lwz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_lws (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_lwa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_lbz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_lbs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_lhz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_lhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_swa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_ror (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_rori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_addc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_mul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_mulu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_div (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_divu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_ff1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_fl1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_andi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_ori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_xori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_addic (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_muli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_exths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_extbs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_exthz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_extbz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_extws (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_extwz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_cmov (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sflesi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfeqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_sfnei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_mac (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_msb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_maci (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_cust1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_cust2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_cust3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_cust4 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_cust5 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_cust6 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_cust7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_cust8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_j (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_jal (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_jr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_jalr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_bnf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_bf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_trap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sys (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_msync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_psync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_csync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_rfe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_nop_imm (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_movhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_macrc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_mfspr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_mtspr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mtspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lwz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lws (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lwa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lbz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lbs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lhz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_lhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_swa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_ror (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_rori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_addc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_mul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_mulu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_div (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_divu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_ff1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_fl1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_andi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_ori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_xori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_addic (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_muli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_exths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_extbs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_exthz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_extbz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_extws (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_extwz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_cmov (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sflesi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfeqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_sfnei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_mac (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_msb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_maci (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_cust1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_cust2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_cust3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_cust4 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_cust5 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_cust6 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_cust7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_cust8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+ entries with it. */
+
+/* Model timing data for `or1200'. */
+
+static const INSN_TIMING or1200_timing[] = {
+ { OR1K32BF_INSN_X_INVALID, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_AFTER, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_BEFORE, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_CHAIN, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_BEGIN, 0, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_J, model_or1200_l_j, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_JAL, model_or1200_l_jal, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_JR, model_or1200_l_jr, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_JALR, model_or1200_l_jalr, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_BNF, model_or1200_l_bnf, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_BF, model_or1200_l_bf, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_TRAP, model_or1200_l_trap, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SYS, model_or1200_l_sys, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MSYNC, model_or1200_l_msync, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_PSYNC, model_or1200_l_psync, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CSYNC, model_or1200_l_csync, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_RFE, model_or1200_l_rfe, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_NOP_IMM, model_or1200_l_nop_imm, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MOVHI, model_or1200_l_movhi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MACRC, model_or1200_l_macrc, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MFSPR, model_or1200_l_mfspr, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MTSPR, model_or1200_l_mtspr, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LWZ, model_or1200_l_lwz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LWS, model_or1200_l_lws, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LWA, model_or1200_l_lwa, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LBZ, model_or1200_l_lbz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LBS, model_or1200_l_lbs, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LHZ, model_or1200_l_lhz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LHS, model_or1200_l_lhs, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SW, model_or1200_l_sw, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SB, model_or1200_l_sb, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SH, model_or1200_l_sh, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SWA, model_or1200_l_swa, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SLL, model_or1200_l_sll, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SLLI, model_or1200_l_slli, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SRL, model_or1200_l_srl, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SRLI, model_or1200_l_srli, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SRA, model_or1200_l_sra, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SRAI, model_or1200_l_srai, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ROR, model_or1200_l_ror, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_RORI, model_or1200_l_rori, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_AND, model_or1200_l_and, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_OR, model_or1200_l_or, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_XOR, model_or1200_l_xor, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ADD, model_or1200_l_add, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SUB, model_or1200_l_sub, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ADDC, model_or1200_l_addc, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MUL, model_or1200_l_mul, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MULU, model_or1200_l_mulu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_DIV, model_or1200_l_div, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_DIVU, model_or1200_l_divu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_FF1, model_or1200_l_ff1, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_FL1, model_or1200_l_fl1, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ANDI, model_or1200_l_andi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ORI, model_or1200_l_ori, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_XORI, model_or1200_l_xori, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ADDI, model_or1200_l_addi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ADDIC, model_or1200_l_addic, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MULI, model_or1200_l_muli, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTHS, model_or1200_l_exths, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTBS, model_or1200_l_extbs, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTHZ, model_or1200_l_exthz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTBZ, model_or1200_l_extbz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTWS, model_or1200_l_extws, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTWZ, model_or1200_l_extwz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CMOV, model_or1200_l_cmov, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTS, model_or1200_l_sfgts, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTSI, model_or1200_l_sfgtsi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTU, model_or1200_l_sfgtu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTUI, model_or1200_l_sfgtui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGES, model_or1200_l_sfges, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGESI, model_or1200_l_sfgesi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGEU, model_or1200_l_sfgeu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGEUI, model_or1200_l_sfgeui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTS, model_or1200_l_sflts, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTSI, model_or1200_l_sfltsi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTU, model_or1200_l_sfltu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTUI, model_or1200_l_sfltui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLES, model_or1200_l_sfles, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLESI, model_or1200_l_sflesi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLEU, model_or1200_l_sfleu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLEUI, model_or1200_l_sfleui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFEQ, model_or1200_l_sfeq, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFEQI, model_or1200_l_sfeqi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFNE, model_or1200_l_sfne, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFNEI, model_or1200_l_sfnei, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MAC, model_or1200_l_mac, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MSB, model_or1200_l_msb, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MACI, model_or1200_l_maci, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST1, model_or1200_l_cust1, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST2, model_or1200_l_cust2, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST3, model_or1200_l_cust3, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST4, model_or1200_l_cust4, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST5, model_or1200_l_cust5, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST6, model_or1200_l_cust6, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST7, model_or1200_l_cust7, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST8, model_or1200_l_cust8, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ADD_S, model_or1200_lf_add_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SUB_S, model_or1200_lf_sub_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MUL_S, model_or1200_lf_mul_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_DIV_S, model_or1200_lf_div_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_REM_S, model_or1200_lf_rem_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ITOF_S, model_or1200_lf_itof_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_FTOI_S, model_or1200_lf_ftoi_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_EQ_S, model_or1200_lf_eq_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_NE_S, model_or1200_lf_ne_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_GE_S, model_or1200_lf_ge_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_GT_S, model_or1200_lf_gt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_LT_S, model_or1200_lf_lt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_LE_S, model_or1200_lf_le_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MADD_S, model_or1200_lf_madd_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_CUST1_S, model_or1200_lf_cust1_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+};
+
+/* Model timing data for `or1200nd'. */
+
+static const INSN_TIMING or1200nd_timing[] = {
+ { OR1K32BF_INSN_X_INVALID, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_AFTER, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_BEFORE, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_CHAIN, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_X_BEGIN, 0, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_J, model_or1200nd_l_j, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_JAL, model_or1200nd_l_jal, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_JR, model_or1200nd_l_jr, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_JALR, model_or1200nd_l_jalr, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_BNF, model_or1200nd_l_bnf, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_BF, model_or1200nd_l_bf, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_TRAP, model_or1200nd_l_trap, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SYS, model_or1200nd_l_sys, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MSYNC, model_or1200nd_l_msync, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_PSYNC, model_or1200nd_l_psync, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CSYNC, model_or1200nd_l_csync, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_RFE, model_or1200nd_l_rfe, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_NOP_IMM, model_or1200nd_l_nop_imm, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MOVHI, model_or1200nd_l_movhi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MACRC, model_or1200nd_l_macrc, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MFSPR, model_or1200nd_l_mfspr, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MTSPR, model_or1200nd_l_mtspr, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LWZ, model_or1200nd_l_lwz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LWS, model_or1200nd_l_lws, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LWA, model_or1200nd_l_lwa, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LBZ, model_or1200nd_l_lbz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LBS, model_or1200nd_l_lbs, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LHZ, model_or1200nd_l_lhz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LHS, model_or1200nd_l_lhs, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SW, model_or1200nd_l_sw, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SB, model_or1200nd_l_sb, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SH, model_or1200nd_l_sh, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SWA, model_or1200nd_l_swa, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SLL, model_or1200nd_l_sll, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SLLI, model_or1200nd_l_slli, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SRL, model_or1200nd_l_srl, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SRLI, model_or1200nd_l_srli, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SRA, model_or1200nd_l_sra, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SRAI, model_or1200nd_l_srai, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ROR, model_or1200nd_l_ror, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_RORI, model_or1200nd_l_rori, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_AND, model_or1200nd_l_and, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_OR, model_or1200nd_l_or, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_XOR, model_or1200nd_l_xor, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ADD, model_or1200nd_l_add, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SUB, model_or1200nd_l_sub, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ADDC, model_or1200nd_l_addc, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MUL, model_or1200nd_l_mul, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MULU, model_or1200nd_l_mulu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_DIV, model_or1200nd_l_div, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_DIVU, model_or1200nd_l_divu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_FF1, model_or1200nd_l_ff1, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_FL1, model_or1200nd_l_fl1, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ANDI, model_or1200nd_l_andi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ORI, model_or1200nd_l_ori, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_XORI, model_or1200nd_l_xori, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ADDI, model_or1200nd_l_addi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_ADDIC, model_or1200nd_l_addic, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MULI, model_or1200nd_l_muli, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTHS, model_or1200nd_l_exths, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTBS, model_or1200nd_l_extbs, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTHZ, model_or1200nd_l_exthz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTBZ, model_or1200nd_l_extbz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTWS, model_or1200nd_l_extws, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_EXTWZ, model_or1200nd_l_extwz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CMOV, model_or1200nd_l_cmov, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTS, model_or1200nd_l_sfgts, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTSI, model_or1200nd_l_sfgtsi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTU, model_or1200nd_l_sfgtu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTUI, model_or1200nd_l_sfgtui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGES, model_or1200nd_l_sfges, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGESI, model_or1200nd_l_sfgesi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGEU, model_or1200nd_l_sfgeu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGEUI, model_or1200nd_l_sfgeui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTS, model_or1200nd_l_sflts, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTSI, model_or1200nd_l_sfltsi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTU, model_or1200nd_l_sfltu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTUI, model_or1200nd_l_sfltui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLES, model_or1200nd_l_sfles, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLESI, model_or1200nd_l_sflesi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLEU, model_or1200nd_l_sfleu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLEUI, model_or1200nd_l_sfleui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFEQ, model_or1200nd_l_sfeq, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFEQI, model_or1200nd_l_sfeqi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFNE, model_or1200nd_l_sfne, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFNEI, model_or1200nd_l_sfnei, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MAC, model_or1200nd_l_mac, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MSB, model_or1200nd_l_msb, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MACI, model_or1200nd_l_maci, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST1, model_or1200nd_l_cust1, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST2, model_or1200nd_l_cust2, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST3, model_or1200nd_l_cust3, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST4, model_or1200nd_l_cust4, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST5, model_or1200nd_l_cust5, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST6, model_or1200nd_l_cust6, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST7, model_or1200nd_l_cust7, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CUST8, model_or1200nd_l_cust8, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ADD_S, model_or1200nd_lf_add_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SUB_S, model_or1200nd_lf_sub_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MUL_S, model_or1200nd_lf_mul_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_DIV_S, model_or1200nd_lf_div_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_REM_S, model_or1200nd_lf_rem_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ITOF_S, model_or1200nd_lf_itof_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_FTOI_S, model_or1200nd_lf_ftoi_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_EQ_S, model_or1200nd_lf_eq_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_NE_S, model_or1200nd_lf_ne_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_GE_S, model_or1200nd_lf_ge_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_GT_S, model_or1200nd_lf_gt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_LT_S, model_or1200nd_lf_lt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_LE_S, model_or1200nd_lf_le_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MADD_S, model_or1200nd_lf_madd_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_CUST1_S, model_or1200nd_lf_cust1_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+or1200_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_OR1200_DATA));
+}
+
+static void
+or1200nd_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_OR1200ND_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const SIM_MODEL or32_models[] =
+{
+ { "or1200", & or32_mach, MODEL_OR1200, TIMING_DATA (& or1200_timing[0]), or1200_model_init },
+ { 0 }
+};
+
+static const SIM_MODEL or32nd_models[] =
+{
+ { "or1200nd", & or32nd_mach, MODEL_OR1200ND, TIMING_DATA (& or1200nd_timing[0]), or1200nd_model_init },
+ { 0 }
+};
+
+/* The properties of this cpu's implementation. */
+
+static const SIM_MACH_IMP_PROPERTIES or1k32bf_imp_properties =
+{
+ sizeof (SIM_CPU),
+#if WITH_SCACHE
+ sizeof (SCACHE)
+#else
+ 0
+#endif
+};
+
+
+static void
+or1k32bf_prepare_run (SIM_CPU *cpu)
+{
+ if (CPU_IDESC (cpu) == NULL)
+ or1k32bf_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+or1k32bf_get_idata (SIM_CPU *cpu, int inum)
+{
+ return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+or32_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = or1k32bf_fetch_register;
+ CPU_REG_STORE (cpu) = or1k32bf_store_register;
+ CPU_PC_FETCH (cpu) = or1k32bf_h_pc_get;
+ CPU_PC_STORE (cpu) = or1k32bf_h_pc_set;
+ CPU_GET_IDATA (cpu) = or1k32bf_get_idata;
+ CPU_MAX_INSNS (cpu) = OR1K32BF_INSN__MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = or1k32bf_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = or1k32bf_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = or1k32bf_engine_run_full;
+#endif
+}
+
+const SIM_MACH or32_mach =
+{
+ "or32", "or1k", MACH_OR32,
+ 32, 32, & or32_models[0], & or1k32bf_imp_properties,
+ or32_init_cpu,
+ or1k32bf_prepare_run
+};
+
+static void
+or32nd_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = or1k32bf_fetch_register;
+ CPU_REG_STORE (cpu) = or1k32bf_store_register;
+ CPU_PC_FETCH (cpu) = or1k32bf_h_pc_get;
+ CPU_PC_STORE (cpu) = or1k32bf_h_pc_set;
+ CPU_GET_IDATA (cpu) = or1k32bf_get_idata;
+ CPU_MAX_INSNS (cpu) = OR1K32BF_INSN__MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = or1k32bf_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = or1k32bf_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = or1k32bf_engine_run_full;
+#endif
+}
+
+const SIM_MACH or32nd_mach =
+{
+ "or32nd", "or1knd", MACH_OR32ND,
+ 32, 32, & or32nd_models[0], & or1k32bf_imp_properties,
+ or32nd_init_cpu,
+ or1k32bf_prepare_run
+};
+
--- /dev/null
+/* Simulator instruction semantics for or1k32bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { OR1K32BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { OR1K32BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { OR1K32BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { OR1K32BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { OR1K32BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { OR1K32BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { OR1K32BF_INSN_L_J, && case_sem_INSN_L_J },
+ { OR1K32BF_INSN_L_JAL, && case_sem_INSN_L_JAL },
+ { OR1K32BF_INSN_L_JR, && case_sem_INSN_L_JR },
+ { OR1K32BF_INSN_L_JALR, && case_sem_INSN_L_JALR },
+ { OR1K32BF_INSN_L_BNF, && case_sem_INSN_L_BNF },
+ { OR1K32BF_INSN_L_BF, && case_sem_INSN_L_BF },
+ { OR1K32BF_INSN_L_TRAP, && case_sem_INSN_L_TRAP },
+ { OR1K32BF_INSN_L_SYS, && case_sem_INSN_L_SYS },
+ { OR1K32BF_INSN_L_MSYNC, && case_sem_INSN_L_MSYNC },
+ { OR1K32BF_INSN_L_PSYNC, && case_sem_INSN_L_PSYNC },
+ { OR1K32BF_INSN_L_CSYNC, && case_sem_INSN_L_CSYNC },
+ { OR1K32BF_INSN_L_RFE, && case_sem_INSN_L_RFE },
+ { OR1K32BF_INSN_L_NOP_IMM, && case_sem_INSN_L_NOP_IMM },
+ { OR1K32BF_INSN_L_MOVHI, && case_sem_INSN_L_MOVHI },
+ { OR1K32BF_INSN_L_MACRC, && case_sem_INSN_L_MACRC },
+ { OR1K32BF_INSN_L_MFSPR, && case_sem_INSN_L_MFSPR },
+ { OR1K32BF_INSN_L_MTSPR, && case_sem_INSN_L_MTSPR },
+ { OR1K32BF_INSN_L_LWZ, && case_sem_INSN_L_LWZ },
+ { OR1K32BF_INSN_L_LWS, && case_sem_INSN_L_LWS },
+ { OR1K32BF_INSN_L_LWA, && case_sem_INSN_L_LWA },
+ { OR1K32BF_INSN_L_LBZ, && case_sem_INSN_L_LBZ },
+ { OR1K32BF_INSN_L_LBS, && case_sem_INSN_L_LBS },
+ { OR1K32BF_INSN_L_LHZ, && case_sem_INSN_L_LHZ },
+ { OR1K32BF_INSN_L_LHS, && case_sem_INSN_L_LHS },
+ { OR1K32BF_INSN_L_SW, && case_sem_INSN_L_SW },
+ { OR1K32BF_INSN_L_SB, && case_sem_INSN_L_SB },
+ { OR1K32BF_INSN_L_SH, && case_sem_INSN_L_SH },
+ { OR1K32BF_INSN_L_SWA, && case_sem_INSN_L_SWA },
+ { OR1K32BF_INSN_L_SLL, && case_sem_INSN_L_SLL },
+ { OR1K32BF_INSN_L_SLLI, && case_sem_INSN_L_SLLI },
+ { OR1K32BF_INSN_L_SRL, && case_sem_INSN_L_SRL },
+ { OR1K32BF_INSN_L_SRLI, && case_sem_INSN_L_SRLI },
+ { OR1K32BF_INSN_L_SRA, && case_sem_INSN_L_SRA },
+ { OR1K32BF_INSN_L_SRAI, && case_sem_INSN_L_SRAI },
+ { OR1K32BF_INSN_L_ROR, && case_sem_INSN_L_ROR },
+ { OR1K32BF_INSN_L_RORI, && case_sem_INSN_L_RORI },
+ { OR1K32BF_INSN_L_AND, && case_sem_INSN_L_AND },
+ { OR1K32BF_INSN_L_OR, && case_sem_INSN_L_OR },
+ { OR1K32BF_INSN_L_XOR, && case_sem_INSN_L_XOR },
+ { OR1K32BF_INSN_L_ADD, && case_sem_INSN_L_ADD },
+ { OR1K32BF_INSN_L_SUB, && case_sem_INSN_L_SUB },
+ { OR1K32BF_INSN_L_ADDC, && case_sem_INSN_L_ADDC },
+ { OR1K32BF_INSN_L_MUL, && case_sem_INSN_L_MUL },
+ { OR1K32BF_INSN_L_MULU, && case_sem_INSN_L_MULU },
+ { OR1K32BF_INSN_L_DIV, && case_sem_INSN_L_DIV },
+ { OR1K32BF_INSN_L_DIVU, && case_sem_INSN_L_DIVU },
+ { OR1K32BF_INSN_L_FF1, && case_sem_INSN_L_FF1 },
+ { OR1K32BF_INSN_L_FL1, && case_sem_INSN_L_FL1 },
+ { OR1K32BF_INSN_L_ANDI, && case_sem_INSN_L_ANDI },
+ { OR1K32BF_INSN_L_ORI, && case_sem_INSN_L_ORI },
+ { OR1K32BF_INSN_L_XORI, && case_sem_INSN_L_XORI },
+ { OR1K32BF_INSN_L_ADDI, && case_sem_INSN_L_ADDI },
+ { OR1K32BF_INSN_L_ADDIC, && case_sem_INSN_L_ADDIC },
+ { OR1K32BF_INSN_L_MULI, && case_sem_INSN_L_MULI },
+ { OR1K32BF_INSN_L_EXTHS, && case_sem_INSN_L_EXTHS },
+ { OR1K32BF_INSN_L_EXTBS, && case_sem_INSN_L_EXTBS },
+ { OR1K32BF_INSN_L_EXTHZ, && case_sem_INSN_L_EXTHZ },
+ { OR1K32BF_INSN_L_EXTBZ, && case_sem_INSN_L_EXTBZ },
+ { OR1K32BF_INSN_L_EXTWS, && case_sem_INSN_L_EXTWS },
+ { OR1K32BF_INSN_L_EXTWZ, && case_sem_INSN_L_EXTWZ },
+ { OR1K32BF_INSN_L_CMOV, && case_sem_INSN_L_CMOV },
+ { OR1K32BF_INSN_L_SFGTS, && case_sem_INSN_L_SFGTS },
+ { OR1K32BF_INSN_L_SFGTSI, && case_sem_INSN_L_SFGTSI },
+ { OR1K32BF_INSN_L_SFGTU, && case_sem_INSN_L_SFGTU },
+ { OR1K32BF_INSN_L_SFGTUI, && case_sem_INSN_L_SFGTUI },
+ { OR1K32BF_INSN_L_SFGES, && case_sem_INSN_L_SFGES },
+ { OR1K32BF_INSN_L_SFGESI, && case_sem_INSN_L_SFGESI },
+ { OR1K32BF_INSN_L_SFGEU, && case_sem_INSN_L_SFGEU },
+ { OR1K32BF_INSN_L_SFGEUI, && case_sem_INSN_L_SFGEUI },
+ { OR1K32BF_INSN_L_SFLTS, && case_sem_INSN_L_SFLTS },
+ { OR1K32BF_INSN_L_SFLTSI, && case_sem_INSN_L_SFLTSI },
+ { OR1K32BF_INSN_L_SFLTU, && case_sem_INSN_L_SFLTU },
+ { OR1K32BF_INSN_L_SFLTUI, && case_sem_INSN_L_SFLTUI },
+ { OR1K32BF_INSN_L_SFLES, && case_sem_INSN_L_SFLES },
+ { OR1K32BF_INSN_L_SFLESI, && case_sem_INSN_L_SFLESI },
+ { OR1K32BF_INSN_L_SFLEU, && case_sem_INSN_L_SFLEU },
+ { OR1K32BF_INSN_L_SFLEUI, && case_sem_INSN_L_SFLEUI },
+ { OR1K32BF_INSN_L_SFEQ, && case_sem_INSN_L_SFEQ },
+ { OR1K32BF_INSN_L_SFEQI, && case_sem_INSN_L_SFEQI },
+ { OR1K32BF_INSN_L_SFNE, && case_sem_INSN_L_SFNE },
+ { OR1K32BF_INSN_L_SFNEI, && case_sem_INSN_L_SFNEI },
+ { OR1K32BF_INSN_L_MAC, && case_sem_INSN_L_MAC },
+ { OR1K32BF_INSN_L_MSB, && case_sem_INSN_L_MSB },
+ { OR1K32BF_INSN_L_MACI, && case_sem_INSN_L_MACI },
+ { OR1K32BF_INSN_L_CUST1, && case_sem_INSN_L_CUST1 },
+ { OR1K32BF_INSN_L_CUST2, && case_sem_INSN_L_CUST2 },
+ { OR1K32BF_INSN_L_CUST3, && case_sem_INSN_L_CUST3 },
+ { OR1K32BF_INSN_L_CUST4, && case_sem_INSN_L_CUST4 },
+ { OR1K32BF_INSN_L_CUST5, && case_sem_INSN_L_CUST5 },
+ { OR1K32BF_INSN_L_CUST6, && case_sem_INSN_L_CUST6 },
+ { OR1K32BF_INSN_L_CUST7, && case_sem_INSN_L_CUST7 },
+ { OR1K32BF_INSN_L_CUST8, && case_sem_INSN_L_CUST8 },
+ { OR1K32BF_INSN_LF_ADD_S, && case_sem_INSN_LF_ADD_S },
+ { OR1K32BF_INSN_LF_SUB_S, && case_sem_INSN_LF_SUB_S },
+ { OR1K32BF_INSN_LF_MUL_S, && case_sem_INSN_LF_MUL_S },
+ { OR1K32BF_INSN_LF_DIV_S, && case_sem_INSN_LF_DIV_S },
+ { OR1K32BF_INSN_LF_REM_S, && case_sem_INSN_LF_REM_S },
+ { OR1K32BF_INSN_LF_ITOF_S, && case_sem_INSN_LF_ITOF_S },
+ { OR1K32BF_INSN_LF_FTOI_S, && case_sem_INSN_LF_FTOI_S },
+ { OR1K32BF_INSN_LF_EQ_S, && case_sem_INSN_LF_EQ_S },
+ { OR1K32BF_INSN_LF_NE_S, && case_sem_INSN_LF_NE_S },
+ { OR1K32BF_INSN_LF_GE_S, && case_sem_INSN_LF_GE_S },
+ { OR1K32BF_INSN_LF_GT_S, && case_sem_INSN_LF_GT_S },
+ { OR1K32BF_INSN_LF_LT_S, && case_sem_INSN_LF_LT_S },
+ { OR1K32BF_INSN_LF_LE_S, && case_sem_INSN_LF_LE_S },
+ { OR1K32BF_INSN_LF_MADD_S, && case_sem_INSN_LF_MADD_S },
+ { OR1K32BF_INSN_LF_CUST1_S, && case_sem_INSN_LF_CUST1_S },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+ or1k32bf_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+ or1k32bf_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+#ifdef DEFINE_SWITCH
+ vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+ vpc = or1k32bf_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = or1k32bf_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = or1k32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = or1k32bf_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_J) : /* l.j ${disp26} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ USI opval = FLD (i_disp26);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_JAL) : /* l.jal ${disp26} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
+ SET_H_GPR (((UINT) 9), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+{
+{
+ {
+ USI opval = FLD (i_disp26);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_JR) : /* l.jr $rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ USI opval = GET_H_GPR (FLD (f_r3));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_JALR) : /* l.jalr $rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
+ SET_H_GPR (((UINT) 9), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+{
+{
+ {
+ USI opval = GET_H_GPR (FLD (f_r3));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_BNF) : /* l.bnf ${disp26} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (NOTSI (GET_H_SYS_SR_F ())) {
+{
+ {
+ USI opval = FLD (i_disp26);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+} else {
+if (GET_H_SYS_CPUCFGR_ND ()) {
+{
+ {
+ USI opval = ADDSI (pc, 4);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_BF) : /* l.bf ${disp26} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (GET_H_SYS_SR_F ()) {
+{
+ {
+ USI opval = FLD (i_disp26);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+} else {
+if (GET_H_SYS_CPUCFGR_ND ()) {
+{
+ {
+ USI opval = ADDSI (pc, 4);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_TRAP) : /* l.trap ${uimm16} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_exception (current_cpu, pc, EXCEPT_TRAP);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SYS) : /* l.sys ${uimm16} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MSYNC) : /* l.msync */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_PSYNC) : /* l.psync */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CSYNC) : /* l.csync */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_RFE) : /* l.rfe */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_rfe (current_cpu);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_NOP_IMM) : /* l.nop ${uimm16} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MOVHI) : /* l.movhi $rD,$uimm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16);
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MACRC) : /* l.macrc $rD */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = GET_H_MAC_MACLO ();
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+ {
+ USI opval = 0;
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+ {
+ USI opval = 0;
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MFSPR) : /* l.mfspr $rD,$rA,${uimm16} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MTSPR) : /* l.mtspr $rA,$rB,${uimm16-split} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_mtspr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_LWZ) : /* l.lwz $rD,${simm16}($rA) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_LWS) : /* l.lws $rD,${simm16}($rA) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_LWA) : /* l.lwa $rD,${simm16}($rA) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+ {
+ SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4);
+ CPU (h_atomic_address) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_LBZ) : /* l.lbz $rD,${simm16}($rA) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_LBS) : /* l.lbs $rD,${simm16}($rA) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_LHZ) : /* l.lhz $rD,${simm16}($rA) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_LHS) : /* l.lhs $rD,${simm16}($rA) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SW) : /* l.sw ${simm16-split}($rA),$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
+ {
+ USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SB) : /* l.sb ${simm16-split}($rA),$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1);
+ {
+ UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SH) : /* l.sh ${simm16-split}($rA),$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2);
+ {
+ UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUHI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SWA) : /* l.swa ${simm16-split}($rA),$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ BI tmp_flag;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
+ {
+ USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+if (GET_H_SYS_SR_F ()) {
+ {
+ USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SLL) : /* l.sll $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SLLI) : /* l.slli $rD,$rA,${uimm6} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SRL) : /* l.srl $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SRLI) : /* l.srli $rD,$rA,${uimm6} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SRA) : /* l.sra $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SRASI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SRAI) : /* l.srai $rD,$rA,${uimm6} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SRASI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_ROR) : /* l.ror $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = RORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_RORI) : /* l.rori $rD,$rA,${uimm6} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = RORSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_AND) : /* l.and $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_OR) : /* l.or $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_XOR) : /* l.xor $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = XORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_ADD) : /* l.add $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SUB) : /* l.sub $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = SUBCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = SUBSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_ADDC) : /* l.addc $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ BI tmp_tmp_sys_sr_cy;
+ tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
+ {
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MUL) : /* l.mul $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MULU) : /* l.mulu $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_DIV) : /* l.div $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
+{
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_CY (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ written |= (1 << 5);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ SET_H_SYS_SR_CY (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_DIVU) : /* l.divu $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
+{
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_CY (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ written |= (1 << 5);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ SET_H_SYS_SR_CY (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_FF1) : /* l.ff1 $rD,$rA */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = or1k32bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_FL1) : /* l.fl1 $rD,$rA */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = or1k32bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_ANDI) : /* l.andi $rD,$rA,$uimm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_ORI) : /* l.ori $rD,$rA,$uimm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_XORI) : /* l.xori $rD,$rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = XORSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_ADDI) : /* l.addi $rD,$rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_ADDIC) : /* l.addic $rD,$rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ BI tmp_tmp_sys_sr_cy;
+ tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
+ {
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ SI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MULI) : /* l.muli $rD,$rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ USI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_EXTHS) : /* l.exths $rD,$rA */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_EXTBS) : /* l.extbs $rD,$rA */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_EXTHZ) : /* l.exthz $rD,$rA */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_EXTBZ) : /* l.extbz $rD,$rA */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_EXTWS) : /* l.extws $rD,$rA */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_EXTWZ) : /* l.extwz $rD,$rA */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CMOV) : /* l.cmov $rD,$rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_SYS_SR_F ()) {
+ {
+ USI opval = GET_H_GPR (FLD (f_r2));
+ SET_H_GPR (FLD (f_r1), opval);
+ written |= (1 << 3);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+} else {
+ {
+ USI opval = GET_H_GPR (FLD (f_r3));
+ SET_H_GPR (FLD (f_r1), opval);
+ written |= (1 << 3);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFGTS) : /* l.sfgts $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFGTSI) : /* l.sfgtsi $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFGTU) : /* l.sfgtu $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFGTUI) : /* l.sfgtui $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFGES) : /* l.sfges $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFGESI) : /* l.sfgesi $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFGEU) : /* l.sfgeu $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFGEUI) : /* l.sfgeui $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFLTS) : /* l.sflts $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFLTSI) : /* l.sfltsi $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFLTU) : /* l.sfltu $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFLTUI) : /* l.sfltui $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFLES) : /* l.sfles $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFLESI) : /* l.sflesi $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFLEU) : /* l.sfleu $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFLEUI) : /* l.sfleui $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFEQ) : /* l.sfeq $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EQSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFEQI) : /* l.sfeqi $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EQSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFNE) : /* l.sfne $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = NESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SFNEI) : /* l.sfnei $rA,$simm16 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = NESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MAC) : /* l.mac $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_prod;
+ DI tmp_result;
+ tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MSB) : /* l.msb $rA,$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_prod;
+ DI tmp_result;
+ tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ tmp_result = SUBDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_prod;
+ DI tmp_result;
+ tmp_prod = MULSI (EXTSISI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2)));
+ tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CUST1) : /* l.cust1 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CUST2) : /* l.cust2 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CUST3) : /* l.cust3 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CUST4) : /* l.cust4 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CUST5) : /* l.cust5 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CUST6) : /* l.cust6 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CUST7) : /* l.cust7 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CUST8) : /* l.cust8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_ADD_S) : /* lf.add.s $rDSF,$rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SUB_S) : /* lf.sub.s $rDSF,$rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_MUL_S) : /* lf.mul.s $rDSF,$rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_DIV_S) : /* lf.div.s $rDSF,$rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_REM_S) : /* lf.rem.s $rDSF,$rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_ITOF_S) : /* lf.itof.s $rDSF,$rA */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCSISI (GET_H_GPR (FLD (f_r2))));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_FTOI_S) : /* lf.ftoi.s $rD,$rASF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTSISI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_EQ_S) : /* lf.sfeq.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_NE_S) : /* lf.sfne.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_GE_S) : /* lf.sfge.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_GT_S) : /* lf.sfgt.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_LT_S) : /* lf.sflt.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_LE_S) : /* lf.sfle.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_MADD_S) : /* lf.madd.s $rDSF,$rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_CUST1_S) : /* lf.cust1.s $rASF,$rBSF */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
--- /dev/null
+/* Simulator instruction semantics for or1k32bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU or1k32bf
+#define WANT_CPU_OR1K32BF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+/* This is used so that we can compile two copies of the semantic code,
+ one with full feature support and one without that runs fast(er).
+ FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
+/* x-invalid: --invalid-- */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+ or1k32bf_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+ or1k32bf_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+#ifdef DEFINE_SWITCH
+ vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = or1k32bf_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+ vpc = or1k32bf_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_OR1K32BF
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = or1k32bf_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = or1k32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = or1k32bf_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-j: l.j ${disp26} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_j) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ USI opval = FLD (i_disp26);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* l-jal: l.jal ${disp26} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_jal) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
+ SET_H_GPR (((UINT) 9), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+{
+{
+ {
+ USI opval = FLD (i_disp26);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* l-jr: l.jr $rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_jr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ USI opval = GET_H_GPR (FLD (f_r3));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* l-jalr: l.jalr $rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_jalr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
+ SET_H_GPR (((UINT) 9), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+{
+{
+ {
+ USI opval = GET_H_GPR (FLD (f_r3));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* l-bnf: l.bnf ${disp26} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_bnf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (NOTSI (GET_H_SYS_SR_F ())) {
+{
+ {
+ USI opval = FLD (i_disp26);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+} else {
+if (GET_H_SYS_CPUCFGR_ND ()) {
+{
+ {
+ USI opval = ADDSI (pc, 4);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* l-bf: l.bf ${disp26} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_bf) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_j.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (GET_H_SYS_SR_F ()) {
+{
+ {
+ USI opval = FLD (i_disp26);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+} else {
+if (GET_H_SYS_CPUCFGR_ND ()) {
+{
+ {
+ USI opval = ADDSI (pc, 4);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+if (GET_H_SYS_CPUCFGR_ND ()) {
+if (1)
+ SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* l-trap: l.trap ${uimm16} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_exception (current_cpu, pc, EXCEPT_TRAP);
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sys: l.sys ${uimm16} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sys) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
+
+ return vpc;
+#undef FLD
+}
+
+/* l-msync: l.msync */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_msync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-psync: l.psync */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_psync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-csync: l.csync */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_csync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-rfe: l.rfe */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_rfe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_rfe (current_cpu);
+
+ return vpc;
+#undef FLD
+}
+
+/* l-nop-imm: l.nop ${uimm16} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_nop_imm) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
+
+ return vpc;
+#undef FLD
+}
+
+/* l-movhi: l.movhi $rD,$uimm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_movhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16);
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-macrc: l.macrc $rD */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_macrc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = GET_H_MAC_MACLO ();
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+ {
+ USI opval = 0;
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+ {
+ USI opval = 0;
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-mfspr: l.mfspr $rD,$rA,${uimm16} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_mfspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-mtspr: l.mtspr $rA,$rB,${uimm16-split} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_mtspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mtspr.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
+
+ return vpc;
+#undef FLD
+}
+
+/* l-lwz: l.lwz $rD,${simm16}($rA) */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_lwz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-lws: l.lws $rD,${simm16}($rA) */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_lws) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-lwa: l.lwa $rD,${simm16}($rA) */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_lwa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+ {
+ SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4);
+ CPU (h_atomic_address) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-lbz: l.lbz $rD,${simm16}($rA) */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_lbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-lbs: l.lbs $rD,${simm16}($rA) */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_lbs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-lhz: l.lhz $rD,${simm16}($rA) */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_lhz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-lhs: l.lhs $rD,${simm16}($rA) */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_lhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sw: l.sw ${simm16-split}($rA),$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
+ {
+ USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* l-sb: l.sb ${simm16-split}($rA),$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1);
+ {
+ UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* l-sh: l.sh ${simm16-split}($rA),$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2);
+ {
+ UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUHI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* l-swa: l.swa ${simm16-split}($rA),$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_swa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ BI tmp_flag;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
+ {
+ USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+if (GET_H_SYS_SR_F ()) {
+ {
+ USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* l-sll: l.sll $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-slli: l.slli $rD,$rA,${uimm6} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-srl: l.srl $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-srli: l.srli $rD,$rA,${uimm6} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sra: l.sra $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SRASI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-srai: l.srai $rD,$rA,${uimm6} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = SRASI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-ror: l.ror $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_ror) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = RORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-rori: l.rori $rD,$rA,${uimm6} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_rori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = RORSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-and: l.and $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-or: l.or $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-xor: l.xor $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = XORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-add: l.add $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sub: l.sub $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = SUBCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = SUBOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = SUBSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-addc: l.addc $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ BI tmp_tmp_sys_sr_cy;
+ tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
+ {
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-mul: l.mul $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-mulu: l.mulu $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-div: l.div $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
+{
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_CY (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ written |= (1 << 5);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ SET_H_SYS_SR_CY (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* l-divu: l.divu $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
+{
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_CY (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_GPR (FLD (f_r1), opval);
+ written |= (1 << 5);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ SET_H_SYS_SR_CY (opval);
+ written |= (1 << 6);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* l-ff1: l.ff1 $rD,$rA */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_ff1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = or1k32bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-fl1: l.fl1 $rD,$rA */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_fl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = or1k32bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-andi: l.andi $rD,$rA,$uimm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-ori: l.ori $rD,$rA,$uimm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-xori: l.xori $rD,$rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = XORSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-addi: l.addi $rD,$rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-addic: l.addic $rD,$rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_addic) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ BI tmp_tmp_sys_sr_cy;
+ tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
+ {
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ SI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-muli: l.muli $rD,$rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_muli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ USI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_OV (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ }
+ {
+ USI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_CY (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ }
+ {
+ USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
+or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
+}
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-exths: l.exths $rD,$rA */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_exths) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-extbs: l.extbs $rD,$rA */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_extbs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-exthz: l.exthz $rD,$rA */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_exthz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-extbz: l.extbz $rD,$rA */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_extbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-extws: l.extws $rD,$rA */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_extws) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-extwz: l.extwz $rD,$rA */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_extwz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = ZEXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-cmov: l.cmov $rD,$rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_cmov) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GET_H_SYS_SR_F ()) {
+ {
+ USI opval = GET_H_GPR (FLD (f_r2));
+ SET_H_GPR (FLD (f_r1), opval);
+ written |= (1 << 3);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+} else {
+ {
+ USI opval = GET_H_GPR (FLD (f_r3));
+ SET_H_GPR (FLD (f_r1), opval);
+ written |= (1 << 3);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* l-sfgts: l.sfgts $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfgtsi: l.sfgtsi $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfgtu: l.sfgtu $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfgtui: l.sfgtui $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfges: l.sfges $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfgesi: l.sfgesi $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfgeu: l.sfgeu $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfgeui: l.sfgeui $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sflts: l.sflts $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfltsi: l.sfltsi $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfltu: l.sfltu $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfltui: l.sfltui $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfles: l.sfles $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sflesi: l.sflesi $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfleu: l.sfleu $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfleui: l.sfleui $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfeq: l.sfeq $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EQSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfeqi: l.sfeqi $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfeqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = EQSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfne: l.sfne $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = NESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-sfnei: l.sfnei $rA,$simm16 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_sfnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ USI opval = NESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-mac: l.mac $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_mac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_prod;
+ DI tmp_result;
+ tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-msb: l.msb $rA,$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_msb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_prod;
+ DI tmp_result;
+ tmp_prod = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ tmp_result = SUBDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-maci: l.maci $rA,${simm16} */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_prod;
+ DI tmp_result;
+ tmp_prod = MULSI (EXTSISI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2)));
+ tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MAC_MACHI (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MAC_MACLO (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* l-cust1: l.cust1 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_cust1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-cust2: l.cust2 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_cust2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-cust3: l.cust3 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_cust3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-cust4: l.cust4 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_cust4) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-cust5: l.cust5 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_cust5) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-cust6: l.cust6 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_cust6) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-cust7: l.cust7 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_cust7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-cust8: l.cust8 */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_cust8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-add-s: lf.add.s $rDSF,$rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_add_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-sub-s: lf.sub.s $rDSF,$rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sub_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-mul-s: lf.mul.s $rDSF,$rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_mul_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-div-s: lf.div.s $rDSF,$rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_div_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-rem-s: lf.rem.s $rDSF,$rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_rem_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-itof-s: lf.itof.s $rDSF,$rA */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_itof_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCSISI (GET_H_GPR (FLD (f_r2))));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-ftoi-s: lf.ftoi.s $rD,$rASF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_ftoi_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = EXTSISI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2))));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-eq-s: lf.sfeq.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_eq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-ne-s: lf.sfne.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_ne_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-ge-s: lf.sfge.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_ge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-gt-s: lf.sfgt.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_gt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-lt-s: lf.sflt.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_lt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-le-s: lf.sfle.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_le_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-madd-s: lf.madd.s $rDSF,$rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_madd_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1)));
+ SET_H_FSR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lf-cust1-s: lf.cust1.s $rASF,$rBSF */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_cust1_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns. */
+
+static const struct sem_fn_desc sem_fns[] = {
+ { OR1K32BF_INSN_X_INVALID, SEM_FN_NAME (or1k32bf,x_invalid) },
+ { OR1K32BF_INSN_X_AFTER, SEM_FN_NAME (or1k32bf,x_after) },
+ { OR1K32BF_INSN_X_BEFORE, SEM_FN_NAME (or1k32bf,x_before) },
+ { OR1K32BF_INSN_X_CTI_CHAIN, SEM_FN_NAME (or1k32bf,x_cti_chain) },
+ { OR1K32BF_INSN_X_CHAIN, SEM_FN_NAME (or1k32bf,x_chain) },
+ { OR1K32BF_INSN_X_BEGIN, SEM_FN_NAME (or1k32bf,x_begin) },
+ { OR1K32BF_INSN_L_J, SEM_FN_NAME (or1k32bf,l_j) },
+ { OR1K32BF_INSN_L_JAL, SEM_FN_NAME (or1k32bf,l_jal) },
+ { OR1K32BF_INSN_L_JR, SEM_FN_NAME (or1k32bf,l_jr) },
+ { OR1K32BF_INSN_L_JALR, SEM_FN_NAME (or1k32bf,l_jalr) },
+ { OR1K32BF_INSN_L_BNF, SEM_FN_NAME (or1k32bf,l_bnf) },
+ { OR1K32BF_INSN_L_BF, SEM_FN_NAME (or1k32bf,l_bf) },
+ { OR1K32BF_INSN_L_TRAP, SEM_FN_NAME (or1k32bf,l_trap) },
+ { OR1K32BF_INSN_L_SYS, SEM_FN_NAME (or1k32bf,l_sys) },
+ { OR1K32BF_INSN_L_MSYNC, SEM_FN_NAME (or1k32bf,l_msync) },
+ { OR1K32BF_INSN_L_PSYNC, SEM_FN_NAME (or1k32bf,l_psync) },
+ { OR1K32BF_INSN_L_CSYNC, SEM_FN_NAME (or1k32bf,l_csync) },
+ { OR1K32BF_INSN_L_RFE, SEM_FN_NAME (or1k32bf,l_rfe) },
+ { OR1K32BF_INSN_L_NOP_IMM, SEM_FN_NAME (or1k32bf,l_nop_imm) },
+ { OR1K32BF_INSN_L_MOVHI, SEM_FN_NAME (or1k32bf,l_movhi) },
+ { OR1K32BF_INSN_L_MACRC, SEM_FN_NAME (or1k32bf,l_macrc) },
+ { OR1K32BF_INSN_L_MFSPR, SEM_FN_NAME (or1k32bf,l_mfspr) },
+ { OR1K32BF_INSN_L_MTSPR, SEM_FN_NAME (or1k32bf,l_mtspr) },
+ { OR1K32BF_INSN_L_LWZ, SEM_FN_NAME (or1k32bf,l_lwz) },
+ { OR1K32BF_INSN_L_LWS, SEM_FN_NAME (or1k32bf,l_lws) },
+ { OR1K32BF_INSN_L_LWA, SEM_FN_NAME (or1k32bf,l_lwa) },
+ { OR1K32BF_INSN_L_LBZ, SEM_FN_NAME (or1k32bf,l_lbz) },
+ { OR1K32BF_INSN_L_LBS, SEM_FN_NAME (or1k32bf,l_lbs) },
+ { OR1K32BF_INSN_L_LHZ, SEM_FN_NAME (or1k32bf,l_lhz) },
+ { OR1K32BF_INSN_L_LHS, SEM_FN_NAME (or1k32bf,l_lhs) },
+ { OR1K32BF_INSN_L_SW, SEM_FN_NAME (or1k32bf,l_sw) },
+ { OR1K32BF_INSN_L_SB, SEM_FN_NAME (or1k32bf,l_sb) },
+ { OR1K32BF_INSN_L_SH, SEM_FN_NAME (or1k32bf,l_sh) },
+ { OR1K32BF_INSN_L_SWA, SEM_FN_NAME (or1k32bf,l_swa) },
+ { OR1K32BF_INSN_L_SLL, SEM_FN_NAME (or1k32bf,l_sll) },
+ { OR1K32BF_INSN_L_SLLI, SEM_FN_NAME (or1k32bf,l_slli) },
+ { OR1K32BF_INSN_L_SRL, SEM_FN_NAME (or1k32bf,l_srl) },
+ { OR1K32BF_INSN_L_SRLI, SEM_FN_NAME (or1k32bf,l_srli) },
+ { OR1K32BF_INSN_L_SRA, SEM_FN_NAME (or1k32bf,l_sra) },
+ { OR1K32BF_INSN_L_SRAI, SEM_FN_NAME (or1k32bf,l_srai) },
+ { OR1K32BF_INSN_L_ROR, SEM_FN_NAME (or1k32bf,l_ror) },
+ { OR1K32BF_INSN_L_RORI, SEM_FN_NAME (or1k32bf,l_rori) },
+ { OR1K32BF_INSN_L_AND, SEM_FN_NAME (or1k32bf,l_and) },
+ { OR1K32BF_INSN_L_OR, SEM_FN_NAME (or1k32bf,l_or) },
+ { OR1K32BF_INSN_L_XOR, SEM_FN_NAME (or1k32bf,l_xor) },
+ { OR1K32BF_INSN_L_ADD, SEM_FN_NAME (or1k32bf,l_add) },
+ { OR1K32BF_INSN_L_SUB, SEM_FN_NAME (or1k32bf,l_sub) },
+ { OR1K32BF_INSN_L_ADDC, SEM_FN_NAME (or1k32bf,l_addc) },
+ { OR1K32BF_INSN_L_MUL, SEM_FN_NAME (or1k32bf,l_mul) },
+ { OR1K32BF_INSN_L_MULU, SEM_FN_NAME (or1k32bf,l_mulu) },
+ { OR1K32BF_INSN_L_DIV, SEM_FN_NAME (or1k32bf,l_div) },
+ { OR1K32BF_INSN_L_DIVU, SEM_FN_NAME (or1k32bf,l_divu) },
+ { OR1K32BF_INSN_L_FF1, SEM_FN_NAME (or1k32bf,l_ff1) },
+ { OR1K32BF_INSN_L_FL1, SEM_FN_NAME (or1k32bf,l_fl1) },
+ { OR1K32BF_INSN_L_ANDI, SEM_FN_NAME (or1k32bf,l_andi) },
+ { OR1K32BF_INSN_L_ORI, SEM_FN_NAME (or1k32bf,l_ori) },
+ { OR1K32BF_INSN_L_XORI, SEM_FN_NAME (or1k32bf,l_xori) },
+ { OR1K32BF_INSN_L_ADDI, SEM_FN_NAME (or1k32bf,l_addi) },
+ { OR1K32BF_INSN_L_ADDIC, SEM_FN_NAME (or1k32bf,l_addic) },
+ { OR1K32BF_INSN_L_MULI, SEM_FN_NAME (or1k32bf,l_muli) },
+ { OR1K32BF_INSN_L_EXTHS, SEM_FN_NAME (or1k32bf,l_exths) },
+ { OR1K32BF_INSN_L_EXTBS, SEM_FN_NAME (or1k32bf,l_extbs) },
+ { OR1K32BF_INSN_L_EXTHZ, SEM_FN_NAME (or1k32bf,l_exthz) },
+ { OR1K32BF_INSN_L_EXTBZ, SEM_FN_NAME (or1k32bf,l_extbz) },
+ { OR1K32BF_INSN_L_EXTWS, SEM_FN_NAME (or1k32bf,l_extws) },
+ { OR1K32BF_INSN_L_EXTWZ, SEM_FN_NAME (or1k32bf,l_extwz) },
+ { OR1K32BF_INSN_L_CMOV, SEM_FN_NAME (or1k32bf,l_cmov) },
+ { OR1K32BF_INSN_L_SFGTS, SEM_FN_NAME (or1k32bf,l_sfgts) },
+ { OR1K32BF_INSN_L_SFGTSI, SEM_FN_NAME (or1k32bf,l_sfgtsi) },
+ { OR1K32BF_INSN_L_SFGTU, SEM_FN_NAME (or1k32bf,l_sfgtu) },
+ { OR1K32BF_INSN_L_SFGTUI, SEM_FN_NAME (or1k32bf,l_sfgtui) },
+ { OR1K32BF_INSN_L_SFGES, SEM_FN_NAME (or1k32bf,l_sfges) },
+ { OR1K32BF_INSN_L_SFGESI, SEM_FN_NAME (or1k32bf,l_sfgesi) },
+ { OR1K32BF_INSN_L_SFGEU, SEM_FN_NAME (or1k32bf,l_sfgeu) },
+ { OR1K32BF_INSN_L_SFGEUI, SEM_FN_NAME (or1k32bf,l_sfgeui) },
+ { OR1K32BF_INSN_L_SFLTS, SEM_FN_NAME (or1k32bf,l_sflts) },
+ { OR1K32BF_INSN_L_SFLTSI, SEM_FN_NAME (or1k32bf,l_sfltsi) },
+ { OR1K32BF_INSN_L_SFLTU, SEM_FN_NAME (or1k32bf,l_sfltu) },
+ { OR1K32BF_INSN_L_SFLTUI, SEM_FN_NAME (or1k32bf,l_sfltui) },
+ { OR1K32BF_INSN_L_SFLES, SEM_FN_NAME (or1k32bf,l_sfles) },
+ { OR1K32BF_INSN_L_SFLESI, SEM_FN_NAME (or1k32bf,l_sflesi) },
+ { OR1K32BF_INSN_L_SFLEU, SEM_FN_NAME (or1k32bf,l_sfleu) },
+ { OR1K32BF_INSN_L_SFLEUI, SEM_FN_NAME (or1k32bf,l_sfleui) },
+ { OR1K32BF_INSN_L_SFEQ, SEM_FN_NAME (or1k32bf,l_sfeq) },
+ { OR1K32BF_INSN_L_SFEQI, SEM_FN_NAME (or1k32bf,l_sfeqi) },
+ { OR1K32BF_INSN_L_SFNE, SEM_FN_NAME (or1k32bf,l_sfne) },
+ { OR1K32BF_INSN_L_SFNEI, SEM_FN_NAME (or1k32bf,l_sfnei) },
+ { OR1K32BF_INSN_L_MAC, SEM_FN_NAME (or1k32bf,l_mac) },
+ { OR1K32BF_INSN_L_MSB, SEM_FN_NAME (or1k32bf,l_msb) },
+ { OR1K32BF_INSN_L_MACI, SEM_FN_NAME (or1k32bf,l_maci) },
+ { OR1K32BF_INSN_L_CUST1, SEM_FN_NAME (or1k32bf,l_cust1) },
+ { OR1K32BF_INSN_L_CUST2, SEM_FN_NAME (or1k32bf,l_cust2) },
+ { OR1K32BF_INSN_L_CUST3, SEM_FN_NAME (or1k32bf,l_cust3) },
+ { OR1K32BF_INSN_L_CUST4, SEM_FN_NAME (or1k32bf,l_cust4) },
+ { OR1K32BF_INSN_L_CUST5, SEM_FN_NAME (or1k32bf,l_cust5) },
+ { OR1K32BF_INSN_L_CUST6, SEM_FN_NAME (or1k32bf,l_cust6) },
+ { OR1K32BF_INSN_L_CUST7, SEM_FN_NAME (or1k32bf,l_cust7) },
+ { OR1K32BF_INSN_L_CUST8, SEM_FN_NAME (or1k32bf,l_cust8) },
+ { OR1K32BF_INSN_LF_ADD_S, SEM_FN_NAME (or1k32bf,lf_add_s) },
+ { OR1K32BF_INSN_LF_SUB_S, SEM_FN_NAME (or1k32bf,lf_sub_s) },
+ { OR1K32BF_INSN_LF_MUL_S, SEM_FN_NAME (or1k32bf,lf_mul_s) },
+ { OR1K32BF_INSN_LF_DIV_S, SEM_FN_NAME (or1k32bf,lf_div_s) },
+ { OR1K32BF_INSN_LF_REM_S, SEM_FN_NAME (or1k32bf,lf_rem_s) },
+ { OR1K32BF_INSN_LF_ITOF_S, SEM_FN_NAME (or1k32bf,lf_itof_s) },
+ { OR1K32BF_INSN_LF_FTOI_S, SEM_FN_NAME (or1k32bf,lf_ftoi_s) },
+ { OR1K32BF_INSN_LF_EQ_S, SEM_FN_NAME (or1k32bf,lf_eq_s) },
+ { OR1K32BF_INSN_LF_NE_S, SEM_FN_NAME (or1k32bf,lf_ne_s) },
+ { OR1K32BF_INSN_LF_GE_S, SEM_FN_NAME (or1k32bf,lf_ge_s) },
+ { OR1K32BF_INSN_LF_GT_S, SEM_FN_NAME (or1k32bf,lf_gt_s) },
+ { OR1K32BF_INSN_LF_LT_S, SEM_FN_NAME (or1k32bf,lf_lt_s) },
+ { OR1K32BF_INSN_LF_LE_S, SEM_FN_NAME (or1k32bf,lf_le_s) },
+ { OR1K32BF_INSN_LF_MADD_S, SEM_FN_NAME (or1k32bf,lf_madd_s) },
+ { OR1K32BF_INSN_LF_CUST1_S, SEM_FN_NAME (or1k32bf,lf_cust1_s) },
+ { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE. */
+
+void
+SEM_FN_NAME (or1k32bf,init_idesc_table) (SIM_CPU *current_cpu)
+{
+ IDESC *idesc_table = CPU_IDESC (current_cpu);
+ const struct sem_fn_desc *sf;
+ int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+ for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+ {
+ const CGEN_INSN *insn = idesc_table[sf->index].idata;
+ int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+ || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+ if (valid_p)
+ idesc_table[sf->index].sem_fast = sf->fn;
+ else
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (or1k32bf,x_invalid);
+#else
+ if (valid_p)
+ idesc_table[sf->index].sem_full = sf->fn;
+ else
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (or1k32bf,x_invalid);
+#endif
+ }
+}
+
projects / thirdparty / binutils-gdb.git / commitdiff
