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c5986054 | 1 | /* Save and restore call-clobbered registers which are live across a call. |
23a5b65a | 2 | Copyright (C) 1989-2014 Free Software Foundation, Inc. |
c5986054 | 3 | |
1322177d | 4 | This file is part of GCC. |
c5986054 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
c5986054 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
c5986054 RS |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
c5986054 RS |
19 | |
20 | #include "config.h" | |
670ee920 | 21 | #include "system.h" |
4977bab6 ZW |
22 | #include "coretypes.h" |
23 | #include "tm.h" | |
c5986054 | 24 | #include "rtl.h" |
7932a3db | 25 | #include "regs.h" |
c5986054 RS |
26 | #include "insn-config.h" |
27 | #include "flags.h" | |
c5986054 RS |
28 | #include "hard-reg-set.h" |
29 | #include "recog.h" | |
30 | #include "basic-block.h" | |
7a8cba34 | 31 | #include "df.h" |
c5986054 | 32 | #include "reload.h" |
49ad7cfa | 33 | #include "function.h" |
c5986054 | 34 | #include "expr.h" |
718f9c0f | 35 | #include "diagnostic-core.h" |
63290521 | 36 | #include "tm_p.h" |
f6c4ed08 | 37 | #include "addresses.h" |
78187f5a | 38 | #include "ggc.h" |
7ee2468b | 39 | #include "dumpfile.h" |
c5986054 | 40 | |
7609e720 BS |
41 | #define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD) |
42 | ||
bcbaaba1 RS |
43 | #define regno_save_mode \ |
44 | (this_target_reload->x_regno_save_mode) | |
cc14227f RS |
45 | #define cached_reg_save_code \ |
46 | (this_target_reload->x_cached_reg_save_code) | |
47 | #define cached_reg_restore_code \ | |
48 | (this_target_reload->x_cached_reg_restore_code) | |
c5986054 RS |
49 | |
50 | /* For each hard register, a place on the stack where it can be saved, | |
51 | if needed. */ | |
52 | ||
d329e058 | 53 | static rtx |
ef0e53ce | 54 | regno_save_mem[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1]; |
c5986054 | 55 | |
058e97ec VM |
56 | /* The number of elements in the subsequent array. */ |
57 | static int save_slots_num; | |
58 | ||
59 | /* Allocated slots so far. */ | |
60 | static rtx save_slots[FIRST_PSEUDO_REGISTER]; | |
61 | ||
c5986054 RS |
62 | /* Set of hard regs currently residing in save area (during insn scan). */ |
63 | ||
64 | static HARD_REG_SET hard_regs_saved; | |
65 | ||
7609e720 | 66 | /* Number of registers currently in hard_regs_saved. */ |
f95361c8 | 67 | |
7609e720 | 68 | static int n_regs_saved; |
f95361c8 | 69 | |
7609e720 BS |
70 | /* Computed by mark_referenced_regs, all regs referenced in a given |
71 | insn. */ | |
72 | static HARD_REG_SET referenced_regs; | |
c5986054 | 73 | |
7609e720 | 74 | |
b5b8b0ac AO |
75 | typedef void refmarker_fn (rtx *loc, enum machine_mode mode, int hardregno, |
76 | void *mark_arg); | |
77 | ||
058e97ec VM |
78 | static int reg_save_code (int, enum machine_mode); |
79 | static int reg_restore_code (int, enum machine_mode); | |
80 | ||
81 | struct saved_hard_reg; | |
82 | static void initiate_saved_hard_regs (void); | |
e16b6fd0 | 83 | static void new_saved_hard_reg (int, int); |
058e97ec VM |
84 | static void finish_saved_hard_regs (void); |
85 | static int saved_hard_reg_compare_func (const void *, const void *); | |
86 | ||
7bc980e1 | 87 | static void mark_set_regs (rtx, const_rtx, void *); |
b5b8b0ac AO |
88 | static void mark_referenced_regs (rtx *, refmarker_fn *mark, void *mark_arg); |
89 | static refmarker_fn mark_reg_as_referenced; | |
90 | static refmarker_fn replace_reg_with_saved_mem; | |
d329e058 AJ |
91 | static int insert_save (struct insn_chain *, int, int, HARD_REG_SET *, |
92 | enum machine_mode *); | |
93 | static int insert_restore (struct insn_chain *, int, int, int, | |
94 | enum machine_mode *); | |
95 | static struct insn_chain *insert_one_insn (struct insn_chain *, int, int, | |
96 | rtx); | |
7bc980e1 | 97 | static void add_stored_regs (rtx, const_rtx, void *); |
058e97ec | 98 | |
c5986054 | 99 | \f |
058e97ec | 100 | |
78187f5a JH |
101 | static GTY(()) rtx savepat; |
102 | static GTY(()) rtx restpat; | |
103 | static GTY(()) rtx test_reg; | |
104 | static GTY(()) rtx test_mem; | |
105 | static GTY(()) rtx saveinsn; | |
106 | static GTY(()) rtx restinsn; | |
107 | ||
108 | /* Return the INSN_CODE used to save register REG in mode MODE. */ | |
109 | static int | |
110 | reg_save_code (int reg, enum machine_mode mode) | |
111 | { | |
112 | bool ok; | |
113 | if (cached_reg_save_code[reg][mode]) | |
114 | return cached_reg_save_code[reg][mode]; | |
115 | if (!HARD_REGNO_MODE_OK (reg, mode)) | |
f57e2756 JR |
116 | { |
117 | /* Depending on how HARD_REGNO_MODE_OK is defined, range propagation | |
118 | might deduce here that reg >= FIRST_PSEUDO_REGISTER. So the assert | |
119 | below silences a warning. */ | |
120 | gcc_assert (reg < FIRST_PSEUDO_REGISTER); | |
121 | cached_reg_save_code[reg][mode] = -1; | |
122 | cached_reg_restore_code[reg][mode] = -1; | |
123 | return -1; | |
124 | } | |
78187f5a JH |
125 | |
126 | /* Update the register number and modes of the register | |
127 | and memory operand. */ | |
5444da31 | 128 | SET_REGNO_RAW (test_reg, reg); |
78187f5a JH |
129 | PUT_MODE (test_reg, mode); |
130 | PUT_MODE (test_mem, mode); | |
131 | ||
132 | /* Force re-recognition of the modified insns. */ | |
133 | INSN_CODE (saveinsn) = -1; | |
f81e79b5 | 134 | INSN_CODE (restinsn) = -1; |
78187f5a JH |
135 | |
136 | cached_reg_save_code[reg][mode] = recog_memoized (saveinsn); | |
137 | cached_reg_restore_code[reg][mode] = recog_memoized (restinsn); | |
138 | ||
139 | /* Now extract both insns and see if we can meet their | |
140 | constraints. */ | |
141 | ok = (cached_reg_save_code[reg][mode] != -1 | |
142 | && cached_reg_restore_code[reg][mode] != -1); | |
143 | if (ok) | |
144 | { | |
145 | extract_insn (saveinsn); | |
146 | ok = constrain_operands (1); | |
147 | extract_insn (restinsn); | |
148 | ok &= constrain_operands (1); | |
149 | } | |
150 | ||
151 | if (! ok) | |
152 | { | |
153 | cached_reg_save_code[reg][mode] = -1; | |
154 | cached_reg_restore_code[reg][mode] = -1; | |
155 | } | |
156 | gcc_assert (cached_reg_save_code[reg][mode]); | |
157 | return cached_reg_save_code[reg][mode]; | |
158 | } | |
159 | ||
160 | /* Return the INSN_CODE used to restore register REG in mode MODE. */ | |
161 | static int | |
162 | reg_restore_code (int reg, enum machine_mode mode) | |
163 | { | |
164 | if (cached_reg_restore_code[reg][mode]) | |
165 | return cached_reg_restore_code[reg][mode]; | |
166 | /* Populate our cache. */ | |
167 | reg_save_code (reg, mode); | |
168 | return cached_reg_restore_code[reg][mode]; | |
169 | } | |
170 | \f | |
c5986054 RS |
171 | /* Initialize for caller-save. |
172 | ||
173 | Look at all the hard registers that are used by a call and for which | |
328e13b7 | 174 | reginfo.c has not already excluded from being used across a call. |
c5986054 | 175 | |
d329e058 | 176 | Ensure that we can find a mode to save the register and that there is a |
c5986054 RS |
177 | simple insn to save and restore the register. This latter check avoids |
178 | problems that would occur if we tried to save the MQ register of some | |
179 | machines directly into memory. */ | |
180 | ||
181 | void | |
d329e058 | 182 | init_caller_save (void) |
c5986054 | 183 | { |
c5986054 RS |
184 | rtx addr_reg; |
185 | int offset; | |
186 | rtx address; | |
f95361c8 | 187 | int i, j; |
c5986054 | 188 | |
dc12b70e JZ |
189 | if (caller_save_initialized_p) |
190 | return; | |
191 | ||
192 | caller_save_initialized_p = true; | |
193 | ||
058e97ec | 194 | CLEAR_HARD_REG_SET (no_caller_save_reg_set); |
c5986054 RS |
195 | /* First find all the registers that we need to deal with and all |
196 | the modes that they can have. If we can't find a mode to use, | |
197 | we can't have the register live over calls. */ | |
198 | ||
199 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
200 | { | |
adee59ae AS |
201 | if (call_used_regs[i] |
202 | && !TEST_HARD_REG_BIT (call_fixed_reg_set, i)) | |
c5986054 | 203 | { |
7609e720 | 204 | for (j = 1; j <= MOVE_MAX_WORDS; j++) |
c5986054 | 205 | { |
787dc842 JH |
206 | regno_save_mode[i][j] = HARD_REGNO_CALLER_SAVE_MODE (i, j, |
207 | VOIDmode); | |
f95361c8 JL |
208 | if (regno_save_mode[i][j] == VOIDmode && j == 1) |
209 | { | |
f95361c8 JL |
210 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
211 | } | |
c5986054 RS |
212 | } |
213 | } | |
214 | else | |
f95361c8 | 215 | regno_save_mode[i][1] = VOIDmode; |
c5986054 RS |
216 | } |
217 | ||
218 | /* The following code tries to approximate the conditions under which | |
219 | we can easily save and restore a register without scratch registers or | |
220 | other complexities. It will usually work, except under conditions where | |
221 | the validity of an insn operand is dependent on the address offset. | |
222 | No such cases are currently known. | |
223 | ||
224 | We first find a typical offset from some BASE_REG_CLASS register. | |
225 | This address is chosen by finding the first register in the class | |
226 | and by finding the smallest power of two that is a valid offset from | |
227 | that register in every mode we will use to save registers. */ | |
228 | ||
229 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3dcc68a4 NC |
230 | if (TEST_HARD_REG_BIT |
231 | (reg_class_contents | |
86fc3d06 UW |
232 | [(int) base_reg_class (regno_save_mode[i][1], ADDR_SPACE_GENERIC, |
233 | PLUS, CONST_INT)], i)) | |
c5986054 RS |
234 | break; |
235 | ||
366de0ce | 236 | gcc_assert (i < FIRST_PSEUDO_REGISTER); |
c5986054 | 237 | |
38a448ca | 238 | addr_reg = gen_rtx_REG (Pmode, i); |
c5986054 RS |
239 | |
240 | for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1) | |
241 | { | |
4789c0ce | 242 | address = gen_rtx_PLUS (Pmode, addr_reg, gen_int_mode (offset, Pmode)); |
c5986054 RS |
243 | |
244 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
f95361c8 JL |
245 | if (regno_save_mode[i][1] != VOIDmode |
246 | && ! strict_memory_address_p (regno_save_mode[i][1], address)) | |
c5986054 RS |
247 | break; |
248 | ||
249 | if (i == FIRST_PSEUDO_REGISTER) | |
250 | break; | |
251 | } | |
252 | ||
253 | /* If we didn't find a valid address, we must use register indirect. */ | |
254 | if (offset == 0) | |
255 | address = addr_reg; | |
256 | ||
257 | /* Next we try to form an insn to save and restore the register. We | |
d329e058 | 258 | see if such an insn is recognized and meets its constraints. |
bf1660a6 JL |
259 | |
260 | To avoid lots of unnecessary RTL allocation, we construct all the RTL | |
261 | once, then modify the memory and register operands in-place. */ | |
262 | ||
263 | test_reg = gen_rtx_REG (VOIDmode, 0); | |
264 | test_mem = gen_rtx_MEM (VOIDmode, address); | |
265 | savepat = gen_rtx_SET (VOIDmode, test_mem, test_reg); | |
266 | restpat = gen_rtx_SET (VOIDmode, test_reg, test_mem); | |
c5986054 | 267 | |
ed8921dc RS |
268 | saveinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, savepat, 0, -1, 0); |
269 | restinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, restpat, 0, -1, 0); | |
0db79a6b | 270 | |
787dc842 JH |
271 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
272 | for (j = 1; j <= MOVE_MAX_WORDS; j++) | |
78187f5a | 273 | if (reg_save_code (i,regno_save_mode[i][j]) == -1) |
787dc842 JH |
274 | { |
275 | regno_save_mode[i][j] = VOIDmode; | |
276 | if (j == 1) | |
277 | { | |
787dc842 | 278 | SET_HARD_REG_BIT (call_fixed_reg_set, i); |
058e97ec VM |
279 | if (call_used_regs[i]) |
280 | SET_HARD_REG_BIT (no_caller_save_reg_set, i); | |
787dc842 JH |
281 | } |
282 | } | |
c5986054 | 283 | } |
058e97ec | 284 | |
c5986054 | 285 | \f |
058e97ec | 286 | |
c5986054 RS |
287 | /* Initialize save areas by showing that we haven't allocated any yet. */ |
288 | ||
289 | void | |
d329e058 | 290 | init_save_areas (void) |
c5986054 | 291 | { |
f95361c8 | 292 | int i, j; |
c5986054 RS |
293 | |
294 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7609e720 | 295 | for (j = 1; j <= MOVE_MAX_WORDS; j++) |
f95361c8 | 296 | regno_save_mem[i][j] = 0; |
058e97ec | 297 | save_slots_num = 0; |
b8698a0f | 298 | |
058e97ec VM |
299 | } |
300 | ||
301 | /* The structure represents a hard register which should be saved | |
302 | through the call. It is used when the integrated register | |
303 | allocator (IRA) is used and sharing save slots is on. */ | |
304 | struct saved_hard_reg | |
305 | { | |
306 | /* Order number starting with 0. */ | |
307 | int num; | |
308 | /* The hard regno. */ | |
309 | int hard_regno; | |
310 | /* Execution frequency of all calls through which given hard | |
311 | register should be saved. */ | |
312 | int call_freq; | |
313 | /* Stack slot reserved to save the hard register through calls. */ | |
314 | rtx slot; | |
315 | /* True if it is first hard register in the chain of hard registers | |
316 | sharing the same stack slot. */ | |
317 | int first_p; | |
318 | /* Order number of the next hard register structure with the same | |
319 | slot in the chain. -1 represents end of the chain. */ | |
320 | int next; | |
321 | }; | |
322 | ||
323 | /* Map: hard register number to the corresponding structure. */ | |
324 | static struct saved_hard_reg *hard_reg_map[FIRST_PSEUDO_REGISTER]; | |
325 | ||
326 | /* The number of all structures representing hard registers should be | |
327 | saved, in order words, the number of used elements in the following | |
328 | array. */ | |
329 | static int saved_regs_num; | |
330 | ||
331 | /* Pointers to all the structures. Index is the order number of the | |
332 | corresponding structure. */ | |
333 | static struct saved_hard_reg *all_saved_regs[FIRST_PSEUDO_REGISTER]; | |
334 | ||
335 | /* First called function for work with saved hard registers. */ | |
336 | static void | |
337 | initiate_saved_hard_regs (void) | |
338 | { | |
339 | int i; | |
340 | ||
341 | saved_regs_num = 0; | |
342 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
343 | hard_reg_map[i] = NULL; | |
344 | } | |
345 | ||
346 | /* Allocate and return new saved hard register with given REGNO and | |
347 | CALL_FREQ. */ | |
e16b6fd0 | 348 | static void |
058e97ec VM |
349 | new_saved_hard_reg (int regno, int call_freq) |
350 | { | |
351 | struct saved_hard_reg *saved_reg; | |
352 | ||
353 | saved_reg | |
354 | = (struct saved_hard_reg *) xmalloc (sizeof (struct saved_hard_reg)); | |
355 | hard_reg_map[regno] = all_saved_regs[saved_regs_num] = saved_reg; | |
356 | saved_reg->num = saved_regs_num++; | |
357 | saved_reg->hard_regno = regno; | |
358 | saved_reg->call_freq = call_freq; | |
359 | saved_reg->first_p = FALSE; | |
360 | saved_reg->next = -1; | |
058e97ec VM |
361 | } |
362 | ||
363 | /* Free memory allocated for the saved hard registers. */ | |
364 | static void | |
365 | finish_saved_hard_regs (void) | |
366 | { | |
367 | int i; | |
368 | ||
369 | for (i = 0; i < saved_regs_num; i++) | |
370 | free (all_saved_regs[i]); | |
371 | } | |
372 | ||
373 | /* The function is used to sort the saved hard register structures | |
374 | according their frequency. */ | |
375 | static int | |
376 | saved_hard_reg_compare_func (const void *v1p, const void *v2p) | |
377 | { | |
378 | const struct saved_hard_reg *p1 = *(struct saved_hard_reg * const *) v1p; | |
379 | const struct saved_hard_reg *p2 = *(struct saved_hard_reg * const *) v2p; | |
b8698a0f | 380 | |
058e97ec VM |
381 | if (flag_omit_frame_pointer) |
382 | { | |
383 | if (p1->call_freq - p2->call_freq != 0) | |
384 | return p1->call_freq - p2->call_freq; | |
385 | } | |
386 | else if (p2->call_freq - p1->call_freq != 0) | |
387 | return p2->call_freq - p1->call_freq; | |
388 | ||
389 | return p1->num - p2->num; | |
c5986054 RS |
390 | } |
391 | ||
392 | /* Allocate save areas for any hard registers that might need saving. | |
393 | We take a conservative approach here and look for call-clobbered hard | |
394 | registers that are assigned to pseudos that cross calls. This may | |
395 | overestimate slightly (especially if some of these registers are later | |
396 | used as spill registers), but it should not be significant. | |
397 | ||
058e97ec VM |
398 | For IRA we use priority coloring to decrease stack slots needed for |
399 | saving hard registers through calls. We build conflicts for them | |
400 | to do coloring. | |
401 | ||
f95361c8 JL |
402 | Future work: |
403 | ||
404 | In the fallback case we should iterate backwards across all possible | |
d329e058 | 405 | modes for the save, choosing the largest available one instead of |
f95361c8 JL |
406 | falling back to the smallest mode immediately. (eg TF -> DF -> SF). |
407 | ||
408 | We do not try to use "move multiple" instructions that exist | |
d329e058 | 409 | on some machines (such as the 68k moveml). It could be a win to try |
f95361c8 | 410 | and use them when possible. The hard part is doing it in a way that is |
d329e058 | 411 | machine independent since they might be saving non-consecutive |
f95361c8 | 412 | registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */ |
c5986054 | 413 | |
437a710d | 414 | void |
d329e058 | 415 | setup_save_areas (void) |
c5986054 | 416 | { |
e90b336f | 417 | int i, j, k, freq; |
f95361c8 | 418 | HARD_REG_SET hard_regs_used; |
e90b336f JL |
419 | struct saved_hard_reg *saved_reg; |
420 | rtx insn; | |
421 | struct insn_chain *chain, *next; | |
422 | unsigned int regno; | |
423 | HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets; | |
424 | reg_set_iterator rsi; | |
f95361c8 | 425 | |
f95361c8 | 426 | CLEAR_HARD_REG_SET (hard_regs_used); |
f95361c8 | 427 | |
e90b336f JL |
428 | /* Find every CALL_INSN and record which hard regs are live across the |
429 | call into HARD_REG_MAP and HARD_REGS_USED. */ | |
430 | initiate_saved_hard_regs (); | |
431 | /* Create hard reg saved regs. */ | |
432 | for (chain = reload_insn_chain; chain != 0; chain = next) | |
058e97ec | 433 | { |
e384e6b5 BS |
434 | rtx cheap; |
435 | ||
e90b336f JL |
436 | insn = chain->insn; |
437 | next = chain->next; | |
438 | if (!CALL_P (insn) | |
439 | || find_reg_note (insn, REG_NORETURN, NULL)) | |
440 | continue; | |
441 | freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)); | |
442 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, | |
443 | &chain->live_throughout); | |
c2ba7e7a | 444 | get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); |
e90b336f JL |
445 | |
446 | /* Record all registers set in this call insn. These don't | |
447 | need to be saved. N.B. the call insn might set a subreg | |
448 | of a multi-hard-reg pseudo; then the pseudo is considered | |
449 | live during the call, but the subreg that is set | |
450 | isn't. */ | |
451 | CLEAR_HARD_REG_SET (this_insn_sets); | |
452 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
453 | /* Sibcalls are considered to set the return value. */ | |
454 | if (SIBLING_CALL_P (insn) && crtl->return_rtx) | |
455 | mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); | |
456 | ||
457 | AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); | |
458 | AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); | |
459 | AND_HARD_REG_SET (hard_regs_to_save, used_regs); | |
460 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
461 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
462 | { | |
463 | if (hard_reg_map[regno] != NULL) | |
464 | hard_reg_map[regno]->call_freq += freq; | |
465 | else | |
e16b6fd0 | 466 | new_saved_hard_reg (regno, freq); |
e90b336f JL |
467 | SET_HARD_REG_BIT (hard_regs_used, regno); |
468 | } | |
e384e6b5 BS |
469 | cheap = find_reg_note (insn, REG_RETURNED, NULL); |
470 | if (cheap) | |
471 | cheap = XEXP (cheap, 0); | |
e90b336f JL |
472 | /* Look through all live pseudos, mark their hard registers. */ |
473 | EXECUTE_IF_SET_IN_REG_SET | |
474 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
058e97ec | 475 | { |
e90b336f JL |
476 | int r = reg_renumber[regno]; |
477 | int bound; | |
058e97ec | 478 | |
e384e6b5 | 479 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
e90b336f | 480 | continue; |
058e97ec | 481 | |
e90b336f JL |
482 | bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; |
483 | for (; r < bound; r++) | |
484 | if (TEST_HARD_REG_BIT (used_regs, r)) | |
058e97ec | 485 | { |
e90b336f JL |
486 | if (hard_reg_map[r] != NULL) |
487 | hard_reg_map[r]->call_freq += freq; | |
058e97ec | 488 | else |
e16b6fd0 | 489 | new_saved_hard_reg (r, freq); |
e90b336f JL |
490 | SET_HARD_REG_BIT (hard_regs_to_save, r); |
491 | SET_HARD_REG_BIT (hard_regs_used, r); | |
058e97ec | 492 | } |
e90b336f JL |
493 | } |
494 | } | |
b8698a0f | 495 | |
e90b336f JL |
496 | /* If requested, figure out which hard regs can share save slots. */ |
497 | if (optimize && flag_ira_share_save_slots) | |
498 | { | |
499 | rtx slot; | |
500 | char *saved_reg_conflicts; | |
501 | int next_k; | |
502 | struct saved_hard_reg *saved_reg2, *saved_reg3; | |
503 | int call_saved_regs_num; | |
504 | struct saved_hard_reg *call_saved_regs[FIRST_PSEUDO_REGISTER]; | |
505 | int best_slot_num; | |
506 | int prev_save_slots_num; | |
507 | rtx prev_save_slots[FIRST_PSEUDO_REGISTER]; | |
b8698a0f | 508 | |
058e97ec VM |
509 | /* Find saved hard register conflicts. */ |
510 | saved_reg_conflicts = (char *) xmalloc (saved_regs_num * saved_regs_num); | |
511 | memset (saved_reg_conflicts, 0, saved_regs_num * saved_regs_num); | |
512 | for (chain = reload_insn_chain; chain != 0; chain = next) | |
513 | { | |
e384e6b5 | 514 | rtx cheap; |
058e97ec VM |
515 | call_saved_regs_num = 0; |
516 | insn = chain->insn; | |
517 | next = chain->next; | |
481683e1 | 518 | if (!CALL_P (insn) |
058e97ec VM |
519 | || find_reg_note (insn, REG_NORETURN, NULL)) |
520 | continue; | |
e384e6b5 BS |
521 | |
522 | cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
523 | if (cheap) | |
524 | cheap = XEXP (cheap, 0); | |
525 | ||
058e97ec VM |
526 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, |
527 | &chain->live_throughout); | |
c2ba7e7a | 528 | get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); |
058e97ec VM |
529 | |
530 | /* Record all registers set in this call insn. These don't | |
531 | need to be saved. N.B. the call insn might set a subreg | |
532 | of a multi-hard-reg pseudo; then the pseudo is considered | |
533 | live during the call, but the subreg that is set | |
534 | isn't. */ | |
535 | CLEAR_HARD_REG_SET (this_insn_sets); | |
536 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
537 | /* Sibcalls are considered to set the return value, | |
912eb5a4 | 538 | compare df-scan.c:df_get_call_refs. */ |
058e97ec VM |
539 | if (SIBLING_CALL_P (insn) && crtl->return_rtx) |
540 | mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets); | |
541 | ||
542 | AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set); | |
543 | AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets); | |
544 | AND_HARD_REG_SET (hard_regs_to_save, used_regs); | |
545 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
546 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
547 | { | |
548 | gcc_assert (hard_reg_map[regno] != NULL); | |
549 | call_saved_regs[call_saved_regs_num++] = hard_reg_map[regno]; | |
550 | } | |
551 | /* Look through all live pseudos, mark their hard registers. */ | |
552 | EXECUTE_IF_SET_IN_REG_SET | |
553 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) | |
c5986054 | 554 | { |
058e97ec VM |
555 | int r = reg_renumber[regno]; |
556 | int bound; | |
b8698a0f | 557 | |
e384e6b5 | 558 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
058e97ec VM |
559 | continue; |
560 | ||
561 | bound = r + hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; | |
562 | for (; r < bound; r++) | |
563 | if (TEST_HARD_REG_BIT (used_regs, r)) | |
564 | call_saved_regs[call_saved_regs_num++] = hard_reg_map[r]; | |
c5986054 | 565 | } |
058e97ec VM |
566 | for (i = 0; i < call_saved_regs_num; i++) |
567 | { | |
568 | saved_reg = call_saved_regs[i]; | |
569 | for (j = 0; j < call_saved_regs_num; j++) | |
570 | if (i != j) | |
571 | { | |
572 | saved_reg2 = call_saved_regs[j]; | |
573 | saved_reg_conflicts[saved_reg->num * saved_regs_num | |
574 | + saved_reg2->num] | |
575 | = saved_reg_conflicts[saved_reg2->num * saved_regs_num | |
576 | + saved_reg->num] | |
577 | = TRUE; | |
578 | } | |
579 | } | |
580 | } | |
581 | /* Sort saved hard regs. */ | |
582 | qsort (all_saved_regs, saved_regs_num, sizeof (struct saved_hard_reg *), | |
583 | saved_hard_reg_compare_func); | |
584 | /* Initiate slots available from the previous reload | |
585 | iteration. */ | |
586 | prev_save_slots_num = save_slots_num; | |
587 | memcpy (prev_save_slots, save_slots, save_slots_num * sizeof (rtx)); | |
588 | save_slots_num = 0; | |
589 | /* Allocate stack slots for the saved hard registers. */ | |
590 | for (i = 0; i < saved_regs_num; i++) | |
591 | { | |
592 | saved_reg = all_saved_regs[i]; | |
593 | regno = saved_reg->hard_regno; | |
594 | for (j = 0; j < i; j++) | |
595 | { | |
596 | saved_reg2 = all_saved_regs[j]; | |
597 | if (! saved_reg2->first_p) | |
598 | continue; | |
599 | slot = saved_reg2->slot; | |
600 | for (k = j; k >= 0; k = next_k) | |
601 | { | |
602 | saved_reg3 = all_saved_regs[k]; | |
603 | next_k = saved_reg3->next; | |
604 | if (saved_reg_conflicts[saved_reg->num * saved_regs_num | |
605 | + saved_reg3->num]) | |
606 | break; | |
607 | } | |
608 | if (k < 0 | |
609 | && (GET_MODE_SIZE (regno_save_mode[regno][1]) | |
610 | <= GET_MODE_SIZE (regno_save_mode | |
611 | [saved_reg2->hard_regno][1]))) | |
612 | { | |
613 | saved_reg->slot | |
614 | = adjust_address_nv | |
615 | (slot, regno_save_mode[saved_reg->hard_regno][1], 0); | |
616 | regno_save_mem[regno][1] = saved_reg->slot; | |
617 | saved_reg->next = saved_reg2->next; | |
618 | saved_reg2->next = i; | |
619 | if (dump_file != NULL) | |
620 | fprintf (dump_file, "%d uses slot of %d\n", | |
621 | regno, saved_reg2->hard_regno); | |
622 | break; | |
623 | } | |
624 | } | |
625 | if (j == i) | |
626 | { | |
627 | saved_reg->first_p = TRUE; | |
628 | for (best_slot_num = -1, j = 0; j < prev_save_slots_num; j++) | |
629 | { | |
630 | slot = prev_save_slots[j]; | |
631 | if (slot == NULL_RTX) | |
632 | continue; | |
633 | if (GET_MODE_SIZE (regno_save_mode[regno][1]) | |
634 | <= GET_MODE_SIZE (GET_MODE (slot)) | |
635 | && best_slot_num < 0) | |
636 | best_slot_num = j; | |
637 | if (GET_MODE (slot) == regno_save_mode[regno][1]) | |
638 | break; | |
639 | } | |
640 | if (best_slot_num >= 0) | |
641 | { | |
642 | saved_reg->slot = prev_save_slots[best_slot_num]; | |
643 | saved_reg->slot | |
644 | = adjust_address_nv | |
645 | (saved_reg->slot, | |
646 | regno_save_mode[saved_reg->hard_regno][1], 0); | |
647 | if (dump_file != NULL) | |
648 | fprintf (dump_file, | |
649 | "%d uses a slot from prev iteration\n", regno); | |
650 | prev_save_slots[best_slot_num] = NULL_RTX; | |
651 | if (best_slot_num + 1 == prev_save_slots_num) | |
652 | prev_save_slots_num--; | |
653 | } | |
654 | else | |
655 | { | |
656 | saved_reg->slot | |
657 | = assign_stack_local_1 | |
658 | (regno_save_mode[regno][1], | |
80a832cd JJ |
659 | GET_MODE_SIZE (regno_save_mode[regno][1]), 0, |
660 | ASLK_REDUCE_ALIGN); | |
058e97ec VM |
661 | if (dump_file != NULL) |
662 | fprintf (dump_file, "%d uses a new slot\n", regno); | |
663 | } | |
664 | regno_save_mem[regno][1] = saved_reg->slot; | |
665 | save_slots[save_slots_num++] = saved_reg->slot; | |
666 | } | |
667 | } | |
668 | free (saved_reg_conflicts); | |
669 | finish_saved_hard_regs (); | |
670 | } | |
671 | else | |
672 | { | |
e90b336f JL |
673 | /* We are not sharing slots. |
674 | ||
675 | Run through all the call-used hard-registers and allocate | |
676 | space for each in the caller-save area. Try to allocate space | |
058e97ec | 677 | in a manner which allows multi-register saves/restores to be done. */ |
b8698a0f | 678 | |
058e97ec VM |
679 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
680 | for (j = MOVE_MAX_WORDS; j > 0; j--) | |
681 | { | |
682 | int do_save = 1; | |
b8698a0f | 683 | |
058e97ec VM |
684 | /* If no mode exists for this size, try another. Also break out |
685 | if we have already saved this hard register. */ | |
686 | if (regno_save_mode[i][j] == VOIDmode || regno_save_mem[i][1] != 0) | |
687 | continue; | |
b8698a0f | 688 | |
058e97ec VM |
689 | /* See if any register in this group has been saved. */ |
690 | for (k = 0; k < j; k++) | |
691 | if (regno_save_mem[i + k][1]) | |
692 | { | |
693 | do_save = 0; | |
694 | break; | |
695 | } | |
696 | if (! do_save) | |
697 | continue; | |
b8698a0f | 698 | |
058e97ec VM |
699 | for (k = 0; k < j; k++) |
700 | if (! TEST_HARD_REG_BIT (hard_regs_used, i + k)) | |
701 | { | |
702 | do_save = 0; | |
703 | break; | |
704 | } | |
705 | if (! do_save) | |
706 | continue; | |
b8698a0f | 707 | |
058e97ec VM |
708 | /* We have found an acceptable mode to store in. Since |
709 | hard register is always saved in the widest mode | |
710 | available, the mode may be wider than necessary, it is | |
711 | OK to reduce the alignment of spill space. We will | |
712 | verify that it is equal to or greater than required | |
713 | when we restore and save the hard register in | |
714 | insert_restore and insert_save. */ | |
715 | regno_save_mem[i][j] | |
716 | = assign_stack_local_1 (regno_save_mode[i][j], | |
717 | GET_MODE_SIZE (regno_save_mode[i][j]), | |
80a832cd | 718 | 0, ASLK_REDUCE_ALIGN); |
b8698a0f | 719 | |
058e97ec VM |
720 | /* Setup single word save area just in case... */ |
721 | for (k = 0; k < j; k++) | |
722 | /* This should not depend on WORDS_BIG_ENDIAN. | |
723 | The order of words in regs is the same as in memory. */ | |
724 | regno_save_mem[i + k][1] | |
725 | = adjust_address_nv (regno_save_mem[i][j], | |
726 | regno_save_mode[i + k][1], | |
727 | k * UNITS_PER_WORD); | |
728 | } | |
729 | } | |
3bdf5ad1 RK |
730 | |
731 | /* Now loop again and set the alias set of any save areas we made to | |
732 | the alias set used to represent frame objects. */ | |
733 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
734 | for (j = MOVE_MAX_WORDS; j > 0; j--) | |
735 | if (regno_save_mem[i][j] != 0) | |
ba4828e0 | 736 | set_mem_alias_set (regno_save_mem[i][j], get_frame_alias_set ()); |
c5986054 | 737 | } |
058e97ec | 738 | |
c5986054 | 739 | \f |
058e97ec | 740 | |
437a710d | 741 | /* Find the places where hard regs are live across calls and save them. */ |
3bdf5ad1 | 742 | |
c5986054 | 743 | void |
d329e058 | 744 | save_call_clobbered_regs (void) |
c5986054 | 745 | { |
169e464e | 746 | struct insn_chain *chain, *next, *last = NULL; |
787dc842 | 747 | enum machine_mode save_mode [FIRST_PSEUDO_REGISTER]; |
7609e720 | 748 | |
e30edd6c R |
749 | /* Computed in mark_set_regs, holds all registers set by the current |
750 | instruction. */ | |
751 | HARD_REG_SET this_insn_sets; | |
752 | ||
7609e720 BS |
753 | CLEAR_HARD_REG_SET (hard_regs_saved); |
754 | n_regs_saved = 0; | |
c5986054 | 755 | |
7609e720 | 756 | for (chain = reload_insn_chain; chain != 0; chain = next) |
c5986054 | 757 | { |
5d86f5f9 | 758 | rtx_insn *insn = chain->insn; |
7609e720 BS |
759 | enum rtx_code code = GET_CODE (insn); |
760 | ||
761 | next = chain->next; | |
762 | ||
366de0ce | 763 | gcc_assert (!chain->is_caller_save_insn); |
7609e720 | 764 | |
b5b8b0ac | 765 | if (NONDEBUG_INSN_P (insn)) |
c5986054 | 766 | { |
7609e720 BS |
767 | /* If some registers have been saved, see if INSN references |
768 | any of them. We must restore them before the insn if so. */ | |
c5986054 | 769 | |
7609e720 | 770 | if (n_regs_saved) |
c5986054 | 771 | { |
7609e720 | 772 | int regno; |
14292418 | 773 | HARD_REG_SET this_insn_sets; |
7609e720 BS |
774 | |
775 | if (code == JUMP_INSN) | |
776 | /* Restore all registers if this is a JUMP_INSN. */ | |
777 | COPY_HARD_REG_SET (referenced_regs, hard_regs_saved); | |
0e6362d9 | 778 | else |
0887bd4b | 779 | { |
7609e720 | 780 | CLEAR_HARD_REG_SET (referenced_regs); |
b5b8b0ac AO |
781 | mark_referenced_regs (&PATTERN (insn), |
782 | mark_reg_as_referenced, NULL); | |
7609e720 | 783 | AND_HARD_REG_SET (referenced_regs, hard_regs_saved); |
0887bd4b | 784 | } |
c5986054 | 785 | |
7609e720 BS |
786 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
787 | if (TEST_HARD_REG_BIT (referenced_regs, regno)) | |
14292418 BS |
788 | regno += insert_restore (chain, 1, regno, MOVE_MAX_WORDS, |
789 | save_mode); | |
790 | /* If a saved register is set after the call, this means we no | |
791 | longer should restore it. This can happen when parts of a | |
792 | multi-word pseudo do not conflict with other pseudos, so | |
793 | IRA may allocate the same hard register for both. One may | |
794 | be live across the call, while the other is set | |
795 | afterwards. */ | |
796 | CLEAR_HARD_REG_SET (this_insn_sets); | |
797 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); | |
798 | AND_COMPL_HARD_REG_SET (hard_regs_saved, this_insn_sets); | |
c5986054 RS |
799 | } |
800 | ||
ed765125 PB |
801 | if (code == CALL_INSN |
802 | && ! SIBLING_CALL_P (insn) | |
803 | && ! find_reg_note (insn, REG_NORETURN, NULL)) | |
7609e720 | 804 | { |
3cd8c58a | 805 | unsigned regno; |
7609e720 | 806 | HARD_REG_SET hard_regs_to_save; |
c2ba7e7a | 807 | HARD_REG_SET call_def_reg_set; |
a2041967 | 808 | reg_set_iterator rsi; |
e384e6b5 BS |
809 | rtx cheap; |
810 | ||
811 | cheap = find_reg_note (insn, REG_RETURNED, NULL); | |
812 | if (cheap) | |
813 | cheap = XEXP (cheap, 0); | |
7609e720 BS |
814 | |
815 | /* Use the register life information in CHAIN to compute which | |
285f3cf0 R |
816 | regs are live during the call. */ |
817 | REG_SET_TO_HARD_REG_SET (hard_regs_to_save, | |
239a0f5b | 818 | &chain->live_throughout); |
f63d1bf7 | 819 | /* Save hard registers always in the widest mode available. */ |
787dc842 JH |
820 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
821 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
822 | save_mode [regno] = regno_save_mode [regno][1]; | |
823 | else | |
824 | save_mode [regno] = VOIDmode; | |
825 | ||
f5143c46 | 826 | /* Look through all live pseudos, mark their hard registers |
787dc842 JH |
827 | and choose proper mode for saving. */ |
828 | EXECUTE_IF_SET_IN_REG_SET | |
a2041967 KH |
829 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi) |
830 | { | |
831 | int r = reg_renumber[regno]; | |
832 | int nregs; | |
833 | enum machine_mode mode; | |
834 | ||
e384e6b5 | 835 | if (r < 0 || regno_reg_rtx[regno] == cheap) |
058e97ec | 836 | continue; |
a2041967 KH |
837 | nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)]; |
838 | mode = HARD_REGNO_CALLER_SAVE_MODE | |
839 | (r, nregs, PSEUDO_REGNO_MODE (regno)); | |
840 | if (GET_MODE_BITSIZE (mode) | |
841 | > GET_MODE_BITSIZE (save_mode[r])) | |
842 | save_mode[r] = mode; | |
843 | while (nregs-- > 0) | |
844 | SET_HARD_REG_BIT (hard_regs_to_save, r + nregs); | |
845 | } | |
7609e720 BS |
846 | |
847 | /* Record all registers set in this call insn. These don't need | |
285f3cf0 R |
848 | to be saved. N.B. the call insn might set a subreg of a |
849 | multi-hard-reg pseudo; then the pseudo is considered live | |
850 | during the call, but the subreg that is set isn't. */ | |
7609e720 | 851 | CLEAR_HARD_REG_SET (this_insn_sets); |
e30edd6c | 852 | note_stores (PATTERN (insn), mark_set_regs, &this_insn_sets); |
7609e720 BS |
853 | |
854 | /* Compute which hard regs must be saved before this call. */ | |
855 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, call_fixed_reg_set); | |
856 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, this_insn_sets); | |
857 | AND_COMPL_HARD_REG_SET (hard_regs_to_save, hard_regs_saved); | |
c2ba7e7a RO |
858 | get_call_reg_set_usage (insn, &call_def_reg_set, |
859 | call_used_reg_set); | |
860 | AND_HARD_REG_SET (hard_regs_to_save, call_def_reg_set); | |
7609e720 | 861 | |
7609e720 BS |
862 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
863 | if (TEST_HARD_REG_BIT (hard_regs_to_save, regno)) | |
787dc842 | 864 | regno += insert_save (chain, 1, regno, &hard_regs_to_save, save_mode); |
7609e720 BS |
865 | |
866 | /* Must recompute n_regs_saved. */ | |
867 | n_regs_saved = 0; | |
868 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
869 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
870 | n_regs_saved++; | |
e384e6b5 BS |
871 | |
872 | if (cheap | |
873 | && HARD_REGISTER_P (cheap) | |
874 | && TEST_HARD_REG_BIT (call_used_reg_set, REGNO (cheap))) | |
875 | { | |
1d2944a3 BS |
876 | rtx dest, newpat; |
877 | rtx pat = PATTERN (insn); | |
878 | if (GET_CODE (pat) == PARALLEL) | |
879 | pat = XVECEXP (pat, 0, 0); | |
880 | dest = SET_DEST (pat); | |
881 | newpat = gen_rtx_SET (VOIDmode, cheap, copy_rtx (dest)); | |
882 | chain = insert_one_insn (chain, 0, -1, newpat); | |
e384e6b5 | 883 | } |
7609e720 | 884 | } |
169e464e | 885 | last = chain; |
7609e720 | 886 | } |
b5b8b0ac AO |
887 | else if (DEBUG_INSN_P (insn) && n_regs_saved) |
888 | mark_referenced_regs (&PATTERN (insn), | |
889 | replace_reg_with_saved_mem, | |
890 | save_mode); | |
c5986054 | 891 | |
058e97ec | 892 | if (chain->next == 0 || chain->next->block != chain->block) |
7609e720 BS |
893 | { |
894 | int regno; | |
895 | /* At the end of the basic block, we must restore any registers that | |
896 | remain saved. If the last insn in the block is a JUMP_INSN, put | |
897 | the restore before the insn, otherwise, put it after the insn. */ | |
898 | ||
49b48605 JJ |
899 | if (n_regs_saved |
900 | && DEBUG_INSN_P (insn) | |
901 | && last | |
902 | && last->block == chain->block) | |
169e464e | 903 | { |
44b9179f | 904 | rtx_insn *ins, *prev; |
169e464e JJ |
905 | basic_block bb = BLOCK_FOR_INSN (insn); |
906 | ||
907 | /* When adding hard reg restores after a DEBUG_INSN, move | |
908 | all notes between last real insn and this DEBUG_INSN after | |
909 | the DEBUG_INSN, otherwise we could get code | |
910 | -g/-g0 differences. */ | |
911 | for (ins = PREV_INSN (insn); ins != last->insn; ins = prev) | |
912 | { | |
913 | prev = PREV_INSN (ins); | |
914 | if (NOTE_P (ins)) | |
915 | { | |
0f82e5c9 DM |
916 | SET_NEXT_INSN (prev) = NEXT_INSN (ins); |
917 | SET_PREV_INSN (NEXT_INSN (ins)) = prev; | |
918 | SET_PREV_INSN (ins) = insn; | |
919 | SET_NEXT_INSN (ins) = NEXT_INSN (insn); | |
920 | SET_NEXT_INSN (insn) = ins; | |
169e464e | 921 | if (NEXT_INSN (ins)) |
0f82e5c9 | 922 | SET_PREV_INSN (NEXT_INSN (ins)) = ins; |
169e464e | 923 | if (BB_END (bb) == insn) |
1130d5e3 | 924 | BB_END (bb) = ins; |
169e464e JJ |
925 | } |
926 | else | |
927 | gcc_assert (DEBUG_INSN_P (ins)); | |
928 | } | |
929 | } | |
930 | last = NULL; | |
931 | ||
7609e720 BS |
932 | if (n_regs_saved) |
933 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
934 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno)) | |
4b4bf941 | 935 | regno += insert_restore (chain, JUMP_P (insn), |
787dc842 | 936 | regno, MOVE_MAX_WORDS, save_mode); |
7609e720 | 937 | } |
d329e058 | 938 | } |
c5986054 RS |
939 | } |
940 | ||
e30edd6c R |
941 | /* Here from note_stores, or directly from save_call_clobbered_regs, when |
942 | an insn stores a value in a register. | |
7609e720 | 943 | Set the proper bit or bits in this_insn_sets. All pseudos that have |
c5986054 RS |
944 | been assigned hard regs have had their register number changed already, |
945 | so we can ignore pseudos. */ | |
c5986054 | 946 | static void |
7bc980e1 | 947 | mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data) |
c5986054 | 948 | { |
b3694847 | 949 | int regno, endregno, i; |
f883e0a7 | 950 | HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data; |
c5986054 RS |
951 | |
952 | if (GET_CODE (reg) == SUBREG) | |
953 | { | |
ddef6bc7 | 954 | rtx inner = SUBREG_REG (reg); |
f8cfc6aa | 955 | if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 956 | return; |
6f9e3578 | 957 | regno = subreg_regno (reg); |
f1f4e530 | 958 | endregno = regno + subreg_nregs (reg); |
ddef6bc7 | 959 | } |
f8cfc6aa | 960 | else if (REG_P (reg) |
ddef6bc7 | 961 | && REGNO (reg) < FIRST_PSEUDO_REGISTER) |
f1f4e530 JM |
962 | { |
963 | regno = REGNO (reg); | |
09e18274 | 964 | endregno = END_HARD_REGNO (reg); |
f1f4e530 | 965 | } |
ddef6bc7 | 966 | else |
c5986054 RS |
967 | return; |
968 | ||
c5986054 | 969 | for (i = regno; i < endregno; i++) |
e30edd6c | 970 | SET_HARD_REG_BIT (*this_insn_sets, i); |
c5986054 RS |
971 | } |
972 | ||
285f3cf0 R |
973 | /* Here from note_stores when an insn stores a value in a register. |
974 | Set the proper bit or bits in the passed regset. All pseudos that have | |
975 | been assigned hard regs have had their register number changed already, | |
976 | so we can ignore pseudos. */ | |
977 | static void | |
7bc980e1 | 978 | add_stored_regs (rtx reg, const_rtx setter, void *data) |
285f3cf0 | 979 | { |
b3694847 | 980 | int regno, endregno, i; |
285f3cf0 | 981 | enum machine_mode mode = GET_MODE (reg); |
ddef6bc7 | 982 | int offset = 0; |
285f3cf0 R |
983 | |
984 | if (GET_CODE (setter) == CLOBBER) | |
985 | return; | |
986 | ||
a446b4e8 JM |
987 | if (GET_CODE (reg) == SUBREG |
988 | && REG_P (SUBREG_REG (reg)) | |
989 | && REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER) | |
285f3cf0 | 990 | { |
ddef6bc7 JJ |
991 | offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)), |
992 | GET_MODE (SUBREG_REG (reg)), | |
993 | SUBREG_BYTE (reg), | |
994 | GET_MODE (reg)); | |
a446b4e8 | 995 | regno = REGNO (SUBREG_REG (reg)) + offset; |
f1f4e530 | 996 | endregno = regno + subreg_nregs (reg); |
285f3cf0 | 997 | } |
f1f4e530 JM |
998 | else |
999 | { | |
1000 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
1001 | return; | |
285f3cf0 | 1002 | |
f1f4e530 | 1003 | regno = REGNO (reg) + offset; |
09e18274 | 1004 | endregno = end_hard_regno (mode, regno); |
f1f4e530 | 1005 | } |
285f3cf0 R |
1006 | |
1007 | for (i = regno; i < endregno; i++) | |
1008 | SET_REGNO_REG_SET ((regset) data, i); | |
1009 | } | |
1010 | ||
7609e720 | 1011 | /* Walk X and record all referenced registers in REFERENCED_REGS. */ |
c5986054 | 1012 | static void |
b5b8b0ac | 1013 | mark_referenced_regs (rtx *loc, refmarker_fn *mark, void *arg) |
c5986054 | 1014 | { |
b5b8b0ac | 1015 | enum rtx_code code = GET_CODE (*loc); |
6f7d635c | 1016 | const char *fmt; |
c5986054 RS |
1017 | int i, j; |
1018 | ||
7609e720 | 1019 | if (code == SET) |
b5b8b0ac | 1020 | mark_referenced_regs (&SET_SRC (*loc), mark, arg); |
7609e720 BS |
1021 | if (code == SET || code == CLOBBER) |
1022 | { | |
b5b8b0ac AO |
1023 | loc = &SET_DEST (*loc); |
1024 | code = GET_CODE (*loc); | |
1025 | if ((code == REG && REGNO (*loc) < FIRST_PSEUDO_REGISTER) | |
4d450e9a | 1026 | || code == PC || code == CC0 |
b5b8b0ac AO |
1027 | || (code == SUBREG && REG_P (SUBREG_REG (*loc)) |
1028 | && REGNO (SUBREG_REG (*loc)) < FIRST_PSEUDO_REGISTER | |
2696f6a4 AO |
1029 | /* If we're setting only part of a multi-word register, |
1030 | we shall mark it as referenced, because the words | |
1031 | that are not being set should be restored. */ | |
b5b8b0ac AO |
1032 | && ((GET_MODE_SIZE (GET_MODE (*loc)) |
1033 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc)))) | |
1034 | || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (*loc))) | |
2696f6a4 | 1035 | <= UNITS_PER_WORD)))) |
7609e720 BS |
1036 | return; |
1037 | } | |
1038 | if (code == MEM || code == SUBREG) | |
1039 | { | |
b5b8b0ac AO |
1040 | loc = &XEXP (*loc, 0); |
1041 | code = GET_CODE (*loc); | |
7609e720 | 1042 | } |
f95361c8 | 1043 | |
c5986054 RS |
1044 | if (code == REG) |
1045 | { | |
b5b8b0ac | 1046 | int regno = REGNO (*loc); |
7609e720 BS |
1047 | int hardregno = (regno < FIRST_PSEUDO_REGISTER ? regno |
1048 | : reg_renumber[regno]); | |
c5986054 | 1049 | |
7609e720 | 1050 | if (hardregno >= 0) |
b5b8b0ac AO |
1051 | mark (loc, GET_MODE (*loc), hardregno, arg); |
1052 | else if (arg) | |
1053 | /* ??? Will we ever end up with an equiv expression in a debug | |
1054 | insn, that would have required restoring a reg, or will | |
1055 | reload take care of it for us? */ | |
1056 | return; | |
7609e720 BS |
1057 | /* If this is a pseudo that did not get a hard register, scan its |
1058 | memory location, since it might involve the use of another | |
1059 | register, which might be saved. */ | |
f2034d06 JL |
1060 | else if (reg_equiv_mem (regno) != 0) |
1061 | mark_referenced_regs (&XEXP (reg_equiv_mem (regno), 0), mark, arg); | |
1062 | else if (reg_equiv_address (regno) != 0) | |
1063 | mark_referenced_regs (®_equiv_address (regno), mark, arg); | |
c5986054 RS |
1064 | return; |
1065 | } | |
7609e720 | 1066 | |
c5986054 RS |
1067 | fmt = GET_RTX_FORMAT (code); |
1068 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1069 | { | |
1070 | if (fmt[i] == 'e') | |
b5b8b0ac | 1071 | mark_referenced_regs (&XEXP (*loc, i), mark, arg); |
c5986054 | 1072 | else if (fmt[i] == 'E') |
b5b8b0ac AO |
1073 | for (j = XVECLEN (*loc, i) - 1; j >= 0; j--) |
1074 | mark_referenced_regs (&XVECEXP (*loc, i, j), mark, arg); | |
1075 | } | |
1076 | } | |
1077 | ||
1078 | /* Parameter function for mark_referenced_regs() that adds registers | |
1079 | present in the insn and in equivalent mems and addresses to | |
1080 | referenced_regs. */ | |
1081 | ||
1082 | static void | |
1083 | mark_reg_as_referenced (rtx *loc ATTRIBUTE_UNUSED, | |
1084 | enum machine_mode mode, | |
1085 | int hardregno, | |
1086 | void *arg ATTRIBUTE_UNUSED) | |
1087 | { | |
1088 | add_to_hard_reg_set (&referenced_regs, mode, hardregno); | |
1089 | } | |
1090 | ||
1091 | /* Parameter function for mark_referenced_regs() that replaces | |
1092 | registers referenced in a debug_insn that would have been restored, | |
1093 | should it be a non-debug_insn, with their save locations. */ | |
1094 | ||
1095 | static void | |
1096 | replace_reg_with_saved_mem (rtx *loc, | |
1097 | enum machine_mode mode, | |
1098 | int regno, | |
1099 | void *arg) | |
1100 | { | |
1101 | unsigned int i, nregs = hard_regno_nregs [regno][mode]; | |
1102 | rtx mem; | |
1103 | enum machine_mode *save_mode = (enum machine_mode *)arg; | |
1104 | ||
1105 | for (i = 0; i < nregs; i++) | |
1106 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1107 | break; | |
1108 | ||
1109 | /* If none of the registers in the range would need restoring, we're | |
1110 | all set. */ | |
1111 | if (i == nregs) | |
1112 | return; | |
1113 | ||
1114 | while (++i < nregs) | |
1115 | if (!TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1116 | break; | |
1117 | ||
1118 | if (i == nregs | |
1119 | && regno_save_mem[regno][nregs]) | |
1120 | { | |
1121 | mem = copy_rtx (regno_save_mem[regno][nregs]); | |
1122 | ||
1123 | if (nregs == (unsigned int) hard_regno_nregs[regno][save_mode[regno]]) | |
1124 | mem = adjust_address_nv (mem, save_mode[regno], 0); | |
1125 | ||
1126 | if (GET_MODE (mem) != mode) | |
1127 | { | |
1128 | /* This is gen_lowpart_if_possible(), but without validating | |
1129 | the newly-formed address. */ | |
1130 | int offset = 0; | |
1131 | ||
1132 | if (WORDS_BIG_ENDIAN) | |
1133 | offset = (MAX (GET_MODE_SIZE (GET_MODE (mem)), UNITS_PER_WORD) | |
1134 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1135 | if (BYTES_BIG_ENDIAN) | |
1136 | /* Adjust the address so that the address-after-the-data is | |
1137 | unchanged. */ | |
1138 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1139 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (mem)))); | |
1140 | ||
1141 | mem = adjust_address_nv (mem, mode, offset); | |
1142 | } | |
c5986054 | 1143 | } |
b5b8b0ac AO |
1144 | else |
1145 | { | |
1146 | mem = gen_rtx_CONCATN (mode, rtvec_alloc (nregs)); | |
1147 | for (i = 0; i < nregs; i++) | |
1148 | if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i)) | |
1149 | { | |
1150 | gcc_assert (regno_save_mem[regno + i][1]); | |
1151 | XVECEXP (mem, 0, i) = copy_rtx (regno_save_mem[regno + i][1]); | |
1152 | } | |
1153 | else | |
1154 | { | |
1155 | gcc_assert (save_mode[regno] != VOIDmode); | |
1156 | XVECEXP (mem, 0, i) = gen_rtx_REG (save_mode [regno], | |
1157 | regno + i); | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | gcc_assert (GET_MODE (mem) == mode); | |
1162 | *loc = mem; | |
c5986054 | 1163 | } |
b5b8b0ac | 1164 | |
c5986054 | 1165 | \f |
7609e720 BS |
1166 | /* Insert a sequence of insns to restore. Place these insns in front of |
1167 | CHAIN if BEFORE_P is nonzero, behind the insn otherwise. MAXRESTORE is | |
1168 | the maximum number of registers which should be restored during this call. | |
1169 | It should never be less than 1 since we only work with entire registers. | |
c5986054 RS |
1170 | |
1171 | Note that we have verified in init_caller_save that we can do this | |
1172 | with a simple SET, so use it. Set INSN_CODE to what we save there | |
1173 | since the address might not be valid so the insn might not be recognized. | |
1174 | These insns will be reloaded and have register elimination done by | |
f95361c8 | 1175 | find_reload, so we need not worry about that here. |
c5986054 | 1176 | |
f95361c8 JL |
1177 | Return the extra number of registers saved. */ |
1178 | ||
1179 | static int | |
d329e058 AJ |
1180 | insert_restore (struct insn_chain *chain, int before_p, int regno, |
1181 | int maxrestore, enum machine_mode *save_mode) | |
c5986054 | 1182 | { |
285f3cf0 | 1183 | int i, k; |
aefdd5ab | 1184 | rtx pat = NULL_RTX; |
830a47ec | 1185 | int code; |
787dc842 | 1186 | unsigned int numregs = 0; |
32e9fa48 | 1187 | struct insn_chain *new_chain; |
787dc842 | 1188 | rtx mem; |
c5986054 | 1189 | |
41806d92 NS |
1190 | /* A common failure mode if register status is not correct in the |
1191 | RTL is for this routine to be called with a REGNO we didn't | |
1192 | expect to save. That will cause us to write an insn with a (nil) | |
1193 | SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
1194 | later, check for this common case here instead. This will remove | |
1195 | one step in debugging such problems. */ | |
366de0ce | 1196 | gcc_assert (regno_save_mem[regno][1]); |
09835ed2 | 1197 | |
7609e720 | 1198 | /* Get the pattern to emit and update our status. |
4554e20d | 1199 | |
7609e720 | 1200 | See if we can restore `maxrestore' registers at once. Work |
4554e20d JL |
1201 | backwards to the single register case. */ |
1202 | for (i = maxrestore; i > 0; i--) | |
c5986054 | 1203 | { |
285f3cf0 | 1204 | int j; |
7609e720 BS |
1205 | int ok = 1; |
1206 | ||
1207 | if (regno_save_mem[regno][i] == 0) | |
4554e20d JL |
1208 | continue; |
1209 | ||
7609e720 BS |
1210 | for (j = 0; j < i; j++) |
1211 | if (! TEST_HARD_REG_BIT (hard_regs_saved, regno + j)) | |
1212 | { | |
1213 | ok = 0; | |
1214 | break; | |
1215 | } | |
f9da5064 | 1216 | /* Must do this one restore at a time. */ |
4554e20d JL |
1217 | if (! ok) |
1218 | continue; | |
7609e720 | 1219 | |
4554e20d JL |
1220 | numregs = i; |
1221 | break; | |
1222 | } | |
f95361c8 | 1223 | |
787dc842 JH |
1224 | mem = regno_save_mem [regno][numregs]; |
1225 | if (save_mode [regno] != VOIDmode | |
1226 | && save_mode [regno] != GET_MODE (mem) | |
c3c96e68 L |
1227 | && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] |
1228 | /* Check that insn to restore REGNO in save_mode[regno] is | |
1229 | correct. */ | |
1230 | && reg_save_code (regno, save_mode[regno]) >= 0) | |
8d2547f2 | 1231 | mem = adjust_address_nv (mem, save_mode[regno], 0); |
ce7b36a4 JW |
1232 | else |
1233 | mem = copy_rtx (mem); | |
76fe54f0 L |
1234 | |
1235 | /* Verify that the alignment of spill space is equal to or greater | |
1236 | than required. */ | |
058e97ec VM |
1237 | gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, |
1238 | GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
76fe54f0 | 1239 | |
285f3cf0 | 1240 | pat = gen_rtx_SET (VOIDmode, |
d329e058 | 1241 | gen_rtx_REG (GET_MODE (mem), |
787dc842 | 1242 | regno), mem); |
78187f5a | 1243 | code = reg_restore_code (regno, GET_MODE (mem)); |
32e9fa48 | 1244 | new_chain = insert_one_insn (chain, before_p, code, pat); |
285f3cf0 R |
1245 | |
1246 | /* Clear status for all registers we restored. */ | |
1247 | for (k = 0; k < i; k++) | |
1248 | { | |
1249 | CLEAR_HARD_REG_BIT (hard_regs_saved, regno + k); | |
32e9fa48 | 1250 | SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); |
285f3cf0 R |
1251 | n_regs_saved--; |
1252 | } | |
1253 | ||
6614fd40 | 1254 | /* Tell our callers how many extra registers we saved/restored. */ |
4554e20d JL |
1255 | return numregs - 1; |
1256 | } | |
f95361c8 | 1257 | |
7609e720 | 1258 | /* Like insert_restore above, but save registers instead. */ |
2cc2d4bb | 1259 | |
4554e20d | 1260 | static int |
d329e058 AJ |
1261 | insert_save (struct insn_chain *chain, int before_p, int regno, |
1262 | HARD_REG_SET (*to_save), enum machine_mode *save_mode) | |
4554e20d | 1263 | { |
787dc842 JH |
1264 | int i; |
1265 | unsigned int k; | |
4554e20d | 1266 | rtx pat = NULL_RTX; |
830a47ec | 1267 | int code; |
787dc842 | 1268 | unsigned int numregs = 0; |
32e9fa48 | 1269 | struct insn_chain *new_chain; |
787dc842 | 1270 | rtx mem; |
f95361c8 | 1271 | |
41806d92 NS |
1272 | /* A common failure mode if register status is not correct in the |
1273 | RTL is for this routine to be called with a REGNO we didn't | |
1274 | expect to save. That will cause us to write an insn with a (nil) | |
1275 | SET_DEST or SET_SRC. Instead of doing so and causing a crash | |
1276 | later, check for this common case here. This will remove one | |
4554e20d | 1277 | step in debugging such problems. */ |
366de0ce | 1278 | gcc_assert (regno_save_mem[regno][1]); |
c5986054 | 1279 | |
7609e720 | 1280 | /* Get the pattern to emit and update our status. |
f95361c8 | 1281 | |
d329e058 | 1282 | See if we can save several registers with a single instruction. |
4554e20d | 1283 | Work backwards to the single register case. */ |
7609e720 | 1284 | for (i = MOVE_MAX_WORDS; i > 0; i--) |
4554e20d | 1285 | { |
285f3cf0 | 1286 | int j; |
7609e720 BS |
1287 | int ok = 1; |
1288 | if (regno_save_mem[regno][i] == 0) | |
4554e20d | 1289 | continue; |
f95361c8 | 1290 | |
7609e720 BS |
1291 | for (j = 0; j < i; j++) |
1292 | if (! TEST_HARD_REG_BIT (*to_save, regno + j)) | |
1293 | { | |
1294 | ok = 0; | |
1295 | break; | |
1296 | } | |
f9da5064 | 1297 | /* Must do this one save at a time. */ |
4554e20d JL |
1298 | if (! ok) |
1299 | continue; | |
1300 | ||
4554e20d JL |
1301 | numregs = i; |
1302 | break; | |
f95361c8 | 1303 | } |
c5986054 | 1304 | |
787dc842 JH |
1305 | mem = regno_save_mem [regno][numregs]; |
1306 | if (save_mode [regno] != VOIDmode | |
1307 | && save_mode [regno] != GET_MODE (mem) | |
c3c96e68 L |
1308 | && numregs == (unsigned int) hard_regno_nregs[regno][save_mode [regno]] |
1309 | /* Check that insn to save REGNO in save_mode[regno] is | |
1310 | correct. */ | |
1311 | && reg_save_code (regno, save_mode[regno]) >= 0) | |
8d2547f2 | 1312 | mem = adjust_address_nv (mem, save_mode[regno], 0); |
ce7b36a4 JW |
1313 | else |
1314 | mem = copy_rtx (mem); | |
76fe54f0 L |
1315 | |
1316 | /* Verify that the alignment of spill space is equal to or greater | |
1317 | than required. */ | |
058e97ec VM |
1318 | gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT, |
1319 | GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem)); | |
76fe54f0 | 1320 | |
787dc842 JH |
1321 | pat = gen_rtx_SET (VOIDmode, mem, |
1322 | gen_rtx_REG (GET_MODE (mem), | |
285f3cf0 | 1323 | regno)); |
78187f5a | 1324 | code = reg_save_code (regno, GET_MODE (mem)); |
32e9fa48 | 1325 | new_chain = insert_one_insn (chain, before_p, code, pat); |
285f3cf0 R |
1326 | |
1327 | /* Set hard_regs_saved and dead_or_set for all the registers we saved. */ | |
1328 | for (k = 0; k < numregs; k++) | |
1329 | { | |
1330 | SET_HARD_REG_BIT (hard_regs_saved, regno + k); | |
32e9fa48 | 1331 | SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k); |
285f3cf0 R |
1332 | n_regs_saved++; |
1333 | } | |
f95361c8 | 1334 | |
6614fd40 | 1335 | /* Tell our callers how many extra registers we saved/restored. */ |
f95361c8 | 1336 | return numregs - 1; |
c5986054 | 1337 | } |
4554e20d | 1338 | |
574af2d6 RS |
1339 | /* A for_each_rtx callback used by add_used_regs. Add the hard-register |
1340 | equivalent of each REG to regset DATA. */ | |
1341 | ||
1342 | static int | |
1343 | add_used_regs_1 (rtx *loc, void *data) | |
1344 | { | |
f773c2bd | 1345 | unsigned int regno; |
574af2d6 RS |
1346 | regset live; |
1347 | rtx x; | |
1348 | ||
1349 | x = *loc; | |
1350 | live = (regset) data; | |
1351 | if (REG_P (x)) | |
1352 | { | |
1353 | regno = REGNO (x); | |
f773c2bd AS |
1354 | if (HARD_REGISTER_NUM_P (regno)) |
1355 | bitmap_set_range (live, regno, hard_regno_nregs[regno][GET_MODE (x)]); | |
1356 | else | |
574af2d6 | 1357 | regno = reg_renumber[regno]; |
574af2d6 RS |
1358 | } |
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | /* A note_uses callback used by insert_one_insn. Add the hard-register | |
1363 | equivalent of each REG to regset DATA. */ | |
1364 | ||
1365 | static void | |
1366 | add_used_regs (rtx *loc, void *data) | |
1367 | { | |
1368 | for_each_rtx (loc, add_used_regs_1, data); | |
1369 | } | |
1370 | ||
7609e720 | 1371 | /* Emit a new caller-save insn and set the code. */ |
285f3cf0 | 1372 | static struct insn_chain * |
d329e058 | 1373 | insert_one_insn (struct insn_chain *chain, int before_p, int code, rtx pat) |
4554e20d | 1374 | { |
5d86f5f9 | 1375 | rtx_insn *insn = chain->insn; |
32e9fa48 | 1376 | struct insn_chain *new_chain; |
d329e058 | 1377 | |
4554e20d JL |
1378 | #ifdef HAVE_cc0 |
1379 | /* If INSN references CC0, put our insns in front of the insn that sets | |
1380 | CC0. This is always safe, since the only way we could be passed an | |
1381 | insn that references CC0 is for a restore, and doing a restore earlier | |
1382 | isn't a problem. We do, however, assume here that CALL_INSNs don't | |
1383 | reference CC0. Guard against non-INSN's like CODE_LABEL. */ | |
1384 | ||
4b4bf941 | 1385 | if ((NONJUMP_INSN_P (insn) || JUMP_P (insn)) |
4554e20d JL |
1386 | && before_p |
1387 | && reg_referenced_p (cc0_rtx, PATTERN (insn))) | |
7609e720 | 1388 | chain = chain->prev, insn = chain->insn; |
4554e20d JL |
1389 | #endif |
1390 | ||
32e9fa48 | 1391 | new_chain = new_insn_chain (); |
4554e20d JL |
1392 | if (before_p) |
1393 | { | |
285f3cf0 R |
1394 | rtx link; |
1395 | ||
32e9fa48 KG |
1396 | new_chain->prev = chain->prev; |
1397 | if (new_chain->prev != 0) | |
1398 | new_chain->prev->next = new_chain; | |
7609e720 | 1399 | else |
32e9fa48 | 1400 | reload_insn_chain = new_chain; |
7609e720 | 1401 | |
32e9fa48 KG |
1402 | chain->prev = new_chain; |
1403 | new_chain->next = chain; | |
1404 | new_chain->insn = emit_insn_before (pat, insn); | |
92691d7d JL |
1405 | /* ??? It would be nice if we could exclude the already / still saved |
1406 | registers from the live sets. */ | |
32e9fa48 | 1407 | COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); |
574af2d6 RS |
1408 | note_uses (&PATTERN (chain->insn), add_used_regs, |
1409 | &new_chain->live_throughout); | |
ac8bc93e PB |
1410 | /* If CHAIN->INSN is a call, then the registers which contain |
1411 | the arguments to the function are live in the new insn. */ | |
1412 | if (CALL_P (chain->insn)) | |
574af2d6 RS |
1413 | for (link = CALL_INSN_FUNCTION_USAGE (chain->insn); |
1414 | link != NULL_RTX; | |
1415 | link = XEXP (link, 1)) | |
1416 | note_uses (&XEXP (link, 0), add_used_regs, | |
1417 | &new_chain->live_throughout); | |
ac8bc93e | 1418 | |
32e9fa48 | 1419 | CLEAR_REG_SET (&new_chain->dead_or_set); |
06e28de2 | 1420 | if (chain->insn == BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block))) |
1130d5e3 | 1421 | BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; |
4554e20d JL |
1422 | } |
1423 | else | |
1424 | { | |
32e9fa48 KG |
1425 | new_chain->next = chain->next; |
1426 | if (new_chain->next != 0) | |
1427 | new_chain->next->prev = new_chain; | |
1428 | chain->next = new_chain; | |
1429 | new_chain->prev = chain; | |
1430 | new_chain->insn = emit_insn_after (pat, insn); | |
92691d7d JL |
1431 | /* ??? It would be nice if we could exclude the already / still saved |
1432 | registers from the live sets, and observe REG_UNUSED notes. */ | |
32e9fa48 | 1433 | COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout); |
285f3cf0 | 1434 | /* Registers that are set in CHAIN->INSN live in the new insn. |
c22cacf3 | 1435 | (Unless there is a REG_UNUSED note for them, but we don't |
285f3cf0 R |
1436 | look for them here.) */ |
1437 | note_stores (PATTERN (chain->insn), add_stored_regs, | |
32e9fa48 KG |
1438 | &new_chain->live_throughout); |
1439 | CLEAR_REG_SET (&new_chain->dead_or_set); | |
06e28de2 | 1440 | if (chain->insn == BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block))) |
1130d5e3 | 1441 | BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn; |
4554e20d | 1442 | } |
32e9fa48 KG |
1443 | new_chain->block = chain->block; |
1444 | new_chain->is_caller_save_insn = 1; | |
437a710d | 1445 | |
32e9fa48 KG |
1446 | INSN_CODE (new_chain->insn) = code; |
1447 | return new_chain; | |
4554e20d | 1448 | } |
78187f5a | 1449 | #include "gt-caller-save.h" |